busdma - Remove filter functionality - Remove filtfunc and filtarg arguments from bus_dma_tag_create() and fix all callers. All callers use NULL today for both filterfunc and filterarg with one exception: if_jme. - Remove filter functionality internally and parent tag tracking. Without filter functions, we do not need to keep track of tag ancestry. All inheritance of the parent tag's parameters occurs when creating the new child tag. - rename run_filter() to addr_needs_bounce(). - FreeBSD keeps the filtfunc and filtarg arguments but requires them to be NULL. - Drop filterfunc usage from if_jme. In case of "JMC260 chip full mask revision 2", which has a hardware bug when it comes to DMA transfers crossing the 4 GB bounday, the parent buffer tag already limits DMA memory to 32bit address space. As such it should be safe to drop the filterfunc. The filterfunc was checking if the lower 32bits of the physical address used for DMA are all 0. In case of a 32bit address space, the only address where all lower 32-bits are all zero is 0 itself and I am here assuming that the physical address 0 is not used for DMA transfers! Mainly obtained from: FreeBSD (commits 7cb028de, 900907f4, 1228b93b, 3933ff56)
ahci - Add quirk for MCP73 AHCI Controller - The AHCI chip for the MCP73 motherboard, which is identified as below, does not properly handle certain handshake operations. ahci0@pci0:0:14:0: class=0x010601 card=0xe03a1631 chip=0x07f410de rev=0xa2 hdr=0x00 vendor = 'NVIDIA Corporation' device = 'GeForce 7100/nForce 630i SATA' class = mass storage subclass = SATA cap 01[44] = powerspec 2 supports D0 D3 current D0 cap 12[8c] = SATA Index-Data Pair cap 05[b0] = MSI supports 8 messages, 64 bit enabled with 1 message Pointed-out-by: dillon
ahci - Reduce livelock warnings with ahci * Mark the ahci (sata) interrupt as HIFREQ to avoid triggering livelock warnings. * Very high interrupt rates are possible with modern SSDs. We don't use the AHCI chipset's interrupt rate moderation features because they are a bit problematic (often implemented via an unconditional delay even for single commands, for example). By flagging the interrupt as HIFREQ, the livelock code will trigger at kern.livelock_limit_hi instead of kern.livelock_limit.
AHCI - Misc fixes * Reduce chip reset time from 500ms to 250ms to speed up booting on machines with multiple AHCI controllers. * Fix a bug in a piece of the error recovery code that was waiting forever. * Implement the hw.ahci.synchronous_boot TUNABLE. Setting this variable to 0 in loader.conf causes the ahci device probe to be fully asynchronous during booting. This is HIGHLY experimental and not recommended on systems with only one controller as the kernel may boot too quickly for the boot drive to probe before the kernel gets to init. * Do a pass on the ahci.4 manual page.
ahci - Add workarounds for Marvell 88SE9215 * This Marvell chip also needs some quirks. Probably most of the older Marvell chips need the same quirks, and the newer probably needs the FR cycling quirk, but for now I'm adding them only specifically as they are tested. Reported-by: Edward Berger
ahci - Implement FBS for port-multipliers * Implement FBS (FIS-Based Switching) for port-multipliers. If the chipset supports it, the ahci driver now turns on FBS mode which allows us to queue concurrent requests to different targets. Most AHCI chipsets do not support FBS resulting in poor port-multiplier performance. - FBS is enabled in the PM probe. - FBS must be disabled when doing a hard reset. - In FBS mode commands must be queued to PREG_CI one at a time, and the target must be written to AHCI_PREG_FBS prior to activation via CI. - RFIS area is larger, and RFIS responses are copied from the appropriate target index instead of index 0. - Issue a COMRESET during the PM probe if a BSY status is recognized, which helps on chipsets which do not implement the SCLO cap. * Clean-up a little logic in ahci_port_stop(). * Use the saved sc_cap to check for the SCLO capability instead of re-reading AHCI_REG_CAP in a few places. * Dump the RFIS data to the console on error. * Fixup sc_cap to directly incorporate quirks.
ahci - Add quirks for Marvell devices * Add some quirks for badly broken Marvell devices. * 88SE9172 - This badly broken AHCI chipset does not support FR *or* CR responses. * 88SE9230 - This badly broken AHCI chipset supports FR and CR, but cannot maintain FR across a disconnect. FRE must be cycled on the insertion detect in order to re-assert FR and be able to detect the new device. This chipset also seems to have other problems, sometimes generating an error (TFES error) on SET_FEATURES, which does not happen when the drive is connected to the Intel AHCI chipset. * Implement quirks for these devices. Also, don't enable FRE with POD and SUD (do it separately), and sequence CMD_ICC_ACTIVE a bit differently than before.
ahci - Adjust a few things * These changes have no effect on known AHCI devices but are a good idea. * As suggested in the AHCI spec 10.1.2, zero out the memory pointed to by the FB and CL port dma addresses. * Write to FB before FBU, and to CLB before CLBU, just in case hardware clears the upper bits on a write to the lower bits (no known AHCI hardware does this but its something that is commonly implemented in other hw so...). * Improved I/O error reporting.
ahci: Add and use AHCI_PREG_SCTL_IPM_NODEVSLP definition from ahci-1.3.1. * The DevSleep interface power saving state was introduced with the ahci-1.3.1 specification. However actual DevSleep support needs to be recognized via the AHCI_REG_CAP2_SDS bit, since many controllers identifying as ahci-1.3 already support DevSleep. * Since the correct bitmask to use in the AHCI_PREG_SCTL_IPM field for disabling all power-management features depends on DevSleep support, store that precomputed value in sc->sc_ipm_disable. * Make some operations on the AHCI_PREG_SCTL_IPM_* bitfield a bit clearer. * While there add AHCI_PREG_CMD_ICC_DEVSLEEP definition.
kernel - Flesh out AHCI 1.3 regs / detection (FBSS not yet supported) * Detect the CAP2 register. Add definitions for new CAP and CAP2 bits. * Detect and report FBSS support when a PM is attached. Note that the driver does not yet support FBSS (I'm still tring to find a mobo whos AHCI has it).