Add more magic numbers for the token code.
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
38787eef 39 * $DragonFly: src/sys/platform/pc32/i386/machdep.c,v 1.74 2005/06/16 21:12:44 dillon Exp $
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40 */
41
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42#include "use_apm.h"
43#include "use_ether.h"
44#include "use_npx.h"
45#include "use_isa.h"
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46#include "opt_atalk.h"
47#include "opt_compat.h"
48#include "opt_cpu.h"
49#include "opt_ddb.h"
50#include "opt_directio.h"
51#include "opt_inet.h"
52#include "opt_ipx.h"
53#include "opt_maxmem.h"
54#include "opt_msgbuf.h"
55#include "opt_perfmon.h"
56#include "opt_swap.h"
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57#include "opt_userconfig.h"
58
59#include <sys/param.h>
60#include <sys/systm.h>
61#include <sys/sysproto.h>
62#include <sys/signalvar.h>
63#include <sys/kernel.h>
64#include <sys/linker.h>
65#include <sys/malloc.h>
66#include <sys/proc.h>
67#include <sys/buf.h>
68#include <sys/reboot.h>
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69#include <sys/mbuf.h>
70#include <sys/msgbuf.h>
71#include <sys/sysent.h>
72#include <sys/sysctl.h>
73#include <sys/vmmeter.h>
74#include <sys/bus.h>
a722be49 75#include <sys/upcall.h>
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76
77#include <vm/vm.h>
78#include <vm/vm_param.h>
79#include <sys/lock.h>
80#include <vm/vm_kern.h>
81#include <vm/vm_object.h>
82#include <vm/vm_page.h>
83#include <vm/vm_map.h>
84#include <vm/vm_pager.h>
85#include <vm/vm_extern.h>
86
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87#include <sys/thread2.h>
88
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89#include <sys/user.h>
90#include <sys/exec.h>
91#include <sys/cons.h>
92
93#include <ddb/ddb.h>
94
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95#include <machine/cpu.h>
96#include <machine/reg.h>
97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#include <machine/bootinfo.h>
100#include <machine/ipl.h>
101#include <machine/md_var.h>
102#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 103#include <machine/globaldata.h> /* CPU_prvspace */
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104#ifdef SMP
105#include <machine/smp.h>
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106#endif
107#ifdef PERFMON
108#include <machine/perfmon.h>
109#endif
110#include <machine/cputypes.h>
111
112#ifdef OLD_BUS_ARCH
1f2de5d4 113#include <bus/isa/i386/isa_device.h>
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114#endif
115#include <i386/isa/intr_machdep.h>
1f2de5d4 116#include <bus/isa/rtc.h>
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117#include <machine/vm86.h>
118#include <sys/random.h>
119#include <sys/ptrace.h>
120#include <machine/sigframe.h>
121
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122extern void init386 (int first);
123extern void dblfault_handler (void);
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124
125extern void printcpuinfo(void); /* XXX header file */
126extern void finishidentcpu(void);
127extern void panicifcpuunsupported(void);
128extern void initializecpu(void);
129
3ae0cd58 130static void cpu_startup (void *);
642a6e88 131#ifndef CPU_DISABLE_SSE
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132static void set_fpregs_xmm (struct save87 *, struct savexmm *);
133static void fill_fpregs_xmm (struct savexmm *, struct save87 *);
642a6e88 134#endif /* CPU_DISABLE_SSE */
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135#ifdef DIRECTIO
136extern void ffs_rawread_setup(void);
137#endif /* DIRECTIO */
8a8d5d85 138static void init_locks(void);
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139
140SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
141
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142int _udatasel, _ucodesel;
143u_int atdevbase;
144
145#if defined(SWTCH_OPTIM_STATS)
146extern int swtch_optim_stats;
147SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
148 CTLFLAG_RD, &swtch_optim_stats, 0, "");
149SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
150 CTLFLAG_RD, &tlb_flush_count, 0, "");
151#endif
152
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153int physmem = 0;
154int cold = 1;
155
156static int
157sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
158{
159 int error = sysctl_handle_int(oidp, 0, ctob(physmem), req);
160 return (error);
161}
162
163SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_INT|CTLFLAG_RD,
164 0, 0, sysctl_hw_physmem, "IU", "");
165
166static int
167sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
168{
169 int error = sysctl_handle_int(oidp, 0,
12e4aaff 170 ctob(physmem - vmstats.v_wire_count), req);
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171 return (error);
172}
173
174SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
175 0, 0, sysctl_hw_usermem, "IU", "");
176
177static int
178sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
179{
180 int error = sysctl_handle_int(oidp, 0,
181 i386_btop(avail_end - avail_start), req);
182 return (error);
183}
184
185SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
186 0, 0, sysctl_hw_availpages, "I", "");
187
188static int
189sysctl_machdep_msgbuf(SYSCTL_HANDLER_ARGS)
190{
191 int error;
192
193 /* Unwind the buffer, so that it's linear (possibly starting with
194 * some initial nulls).
195 */
196 error=sysctl_handle_opaque(oidp,msgbufp->msg_ptr+msgbufp->msg_bufr,
197 msgbufp->msg_size-msgbufp->msg_bufr,req);
198 if(error) return(error);
199 if(msgbufp->msg_bufr>0) {
200 error=sysctl_handle_opaque(oidp,msgbufp->msg_ptr,
201 msgbufp->msg_bufr,req);
202 }
203 return(error);
204}
205
206SYSCTL_PROC(_machdep, OID_AUTO, msgbuf, CTLTYPE_STRING|CTLFLAG_RD,
207 0, 0, sysctl_machdep_msgbuf, "A","Contents of kernel message buffer");
208
209static int msgbuf_clear;
210
211static int
212sysctl_machdep_msgbuf_clear(SYSCTL_HANDLER_ARGS)
213{
214 int error;
215 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
216 req);
217 if (!error && req->newptr) {
218 /* Clear the buffer and reset write pointer */
219 bzero(msgbufp->msg_ptr,msgbufp->msg_size);
220 msgbufp->msg_bufr=msgbufp->msg_bufx=0;
221 msgbuf_clear=0;
222 }
223 return (error);
224}
225
226SYSCTL_PROC(_machdep, OID_AUTO, msgbuf_clear, CTLTYPE_INT|CTLFLAG_RW,
227 &msgbuf_clear, 0, sysctl_machdep_msgbuf_clear, "I",
228 "Clear kernel message buffer");
229
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230int bootverbose = 0;
231vm_paddr_t Maxmem = 0;
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232long dumplo;
233
6ef943a3 234vm_paddr_t phys_avail[10];
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235
236/* must be 2 less so 0 0 can signal end of chunks */
237#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(vm_offset_t)) - 2)
238
239static vm_offset_t buffer_sva, buffer_eva;
240vm_offset_t clean_sva, clean_eva;
241static vm_offset_t pager_sva, pager_eva;
242static struct trapframe proc0_tf;
243
244static void
245cpu_startup(dummy)
246 void *dummy;
247{
c9faf524 248 caddr_t v;
cb840899 249 vm_offset_t minaddr;
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250 vm_offset_t maxaddr;
251 vm_size_t size = 0;
252 int firstaddr;
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253
254 if (boothowto & RB_VERBOSE)
255 bootverbose++;
256
257 /*
258 * Good {morning,afternoon,evening,night}.
259 */
260 printf("%s", version);
261 startrtclock();
262 printcpuinfo();
263 panicifcpuunsupported();
264#ifdef PERFMON
265 perfmon_init();
266#endif
6ef943a3 267 printf("real memory = %llu (%lluK bytes)\n", ptoa(Maxmem), ptoa(Maxmem) / 1024);
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268 /*
269 * Display any holes after the first chunk of extended memory.
270 */
271 if (bootverbose) {
272 int indx;
273
274 printf("Physical memory chunk(s):\n");
275 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 276 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 277
6ef943a3 278 printf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
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279 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
280 size1 / PAGE_SIZE);
281 }
282 }
283
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284 /*
285 * Allocate space for system data structures.
286 * The first available kernel virtual address is in "v".
287 * As pages of kernel virtual memory are allocated, "v" is incremented.
288 * As pages of memory are allocated and cleared,
289 * "firstaddr" is incremented.
290 * An index into the kernel page table corresponding to the
291 * virtual memory address maintained in "v" is kept in "mapaddr".
292 */
293
294 /*
295 * Make two passes. The first pass calculates how much memory is
296 * needed and allocates it. The second pass assigns virtual
297 * addresses to the various data structures.
298 */
299 firstaddr = 0;
300again:
301 v = (caddr_t)firstaddr;
302
303#define valloc(name, type, num) \
304 (name) = (type *)v; v = (caddr_t)((name)+(num))
305#define valloclim(name, type, num, lim) \
306 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
307
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308 /*
309 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
310 * For the first 64MB of ram nominally allocate sufficient buffers to
311 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
312 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
313 * the buffer cache we limit the eventual kva reservation to
314 * maxbcache bytes.
315 *
316 * factor represents the 1/4 x ram conversion.
317 */
318 if (nbuf == 0) {
319 int factor = 4 * BKVASIZE / 1024;
320 int kbytes = physmem * (PAGE_SIZE / 1024);
321
322 nbuf = 50;
323 if (kbytes > 4096)
324 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
325 if (kbytes > 65536)
326 nbuf += (kbytes - 65536) * 2 / (factor * 5);
327 if (maxbcache && nbuf > maxbcache / BKVASIZE)
328 nbuf = maxbcache / BKVASIZE;
329 }
330
331 /*
332 * Do not allow the buffer_map to be more then 1/2 the size of the
333 * kernel_map.
334 */
335 if (nbuf > (kernel_map->max_offset - kernel_map->min_offset) /
336 (BKVASIZE * 2)) {
337 nbuf = (kernel_map->max_offset - kernel_map->min_offset) /
338 (BKVASIZE * 2);
339 printf("Warning: nbufs capped at %d\n", nbuf);
340 }
341
342 nswbuf = max(min(nbuf/4, 256), 16);
343#ifdef NSWBUF_MIN
344 if (nswbuf < NSWBUF_MIN)
345 nswbuf = NSWBUF_MIN;
346#endif
347#ifdef DIRECTIO
348 ffs_rawread_setup();
349#endif
350
351 valloc(swbuf, struct buf, nswbuf);
352 valloc(buf, struct buf, nbuf);
353 v = bufhashinit(v);
354
355 /*
356 * End of first pass, size has been calculated so allocate memory
357 */
358 if (firstaddr == 0) {
359 size = (vm_size_t)(v - firstaddr);
360 firstaddr = (int)kmem_alloc(kernel_map, round_page(size));
361 if (firstaddr == 0)
362 panic("startup: no room for tables");
363 goto again;
364 }
365
366 /*
367 * End of second pass, addresses have been assigned
368 */
369 if ((vm_size_t)(v - firstaddr) != size)
370 panic("startup: table size inconsistency");
371
372 clean_map = kmem_suballoc(kernel_map, &clean_sva, &clean_eva,
373 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
374 buffer_map = kmem_suballoc(clean_map, &buffer_sva, &buffer_eva,
375 (nbuf*BKVASIZE));
376 buffer_map->system_map = 1;
377 pager_map = kmem_suballoc(clean_map, &pager_sva, &pager_eva,
378 (nswbuf*MAXPHYS) + pager_map_size);
379 pager_map->system_map = 1;
380 exec_map = kmem_suballoc(kernel_map, &minaddr, &maxaddr,
381 (16*(ARG_MAX+(PAGE_SIZE*3))));
382
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383#if defined(USERCONFIG)
384 userconfig();
385 cninit(); /* the preferred console may have changed */
386#endif
387
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388 printf("avail memory = %u (%uK bytes)\n", ptoa(vmstats.v_free_count),
389 ptoa(vmstats.v_free_count) / 1024);
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390
391 /*
392 * Set up buffers, so they can be used to read disk labels.
393 */
394 bufinit();
395 vm_pager_bufferinit();
396
397#ifdef SMP
398 /*
399 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
400 */
401 mp_start(); /* fire up the APs and APICs */
402 mp_announce();
403#endif /* SMP */
404 cpu_setregs();
405}
406
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407/*
408 * Send an interrupt to process.
409 *
410 * Stack is set up to allow sigcode stored
411 * at top to call routine, followed by kcall
412 * to sigreturn routine below. After sigreturn
413 * resets the signal mask, the stack, and the
414 * frame pointer, it returns to the user
415 * specified pc, psl.
416 */
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417void
418sendsig(catcher, sig, mask, code)
419 sig_t catcher;
420 int sig;
421 sigset_t *mask;
422 u_long code;
423{
424 struct proc *p = curproc;
425 struct trapframe *regs;
426 struct sigacts *psp = p->p_sigacts;
427 struct sigframe sf, *sfp;
428 int oonstack;
429
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430 regs = p->p_md.md_regs;
431 oonstack = (p->p_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
432
433 /* save user context */
434 bzero(&sf, sizeof(struct sigframe));
435 sf.sf_uc.uc_sigmask = *mask;
436 sf.sf_uc.uc_stack = p->p_sigstk;
437 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
438 sf.sf_uc.uc_mcontext.mc_gs = rgs();
439 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_fs, sizeof(struct trapframe));
440
441 /* Allocate and validate space for the signal handler context. */
442 if ((p->p_flag & P_ALTSTACK) != 0 && !oonstack &&
443 SIGISMEMBER(psp->ps_sigonstack, sig)) {
444 sfp = (struct sigframe *)(p->p_sigstk.ss_sp +
445 p->p_sigstk.ss_size - sizeof(struct sigframe));
446 p->p_sigstk.ss_flags |= SS_ONSTACK;
447 }
448 else
449 sfp = (struct sigframe *)regs->tf_esp - 1;
450
451 /* Translate the signal is appropriate */
452 if (p->p_sysent->sv_sigtbl) {
453 if (sig <= p->p_sysent->sv_sigsize)
454 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
455 }
456
457 /* Build the argument list for the signal handler. */
458 sf.sf_signum = sig;
459 sf.sf_ucontext = (register_t)&sfp->sf_uc;
460 if (SIGISMEMBER(p->p_sigacts->ps_siginfo, sig)) {
461 /* Signal handler installed with SA_SIGINFO. */
462 sf.sf_siginfo = (register_t)&sfp->sf_si;
463 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
464
465 /* fill siginfo structure */
466 sf.sf_si.si_signo = sig;
467 sf.sf_si.si_code = code;
468 sf.sf_si.si_addr = (void*)regs->tf_err;
469 }
470 else {
471 /* Old FreeBSD-style arguments. */
472 sf.sf_siginfo = code;
473 sf.sf_addr = regs->tf_err;
474 sf.sf_ahu.sf_handler = catcher;
475 }
476
477 /*
478 * If we're a vm86 process, we want to save the segment registers.
479 * We also change eflags to be our emulated eflags, not the actual
480 * eflags.
481 */
482 if (regs->tf_eflags & PSL_VM) {
483 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
b7c628e4 484 struct vm86_kernel *vm86 = &p->p_thread->td_pcb->pcb_ext->ext_vm86;
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485
486 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
487 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
488 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
489 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
490
491 if (vm86->vm86_has_vme == 0)
492 sf.sf_uc.uc_mcontext.mc_eflags =
493 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
494 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
495
496 /*
497 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
498 * syscalls made by the signal handler. This just avoids
499 * wasting time for our lazy fixup of such faults. PSL_NT
500 * does nothing in vm86 mode, but vm86 programs can set it
501 * almost legitimately in probes for old cpu types.
502 */
503 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
504 }
505
506 /*
507 * Copy the sigframe out to the user's stack.
508 */
509 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
510 /*
511 * Something is wrong with the stack pointer.
512 * ...Kill the process.
513 */
514 sigexit(p, SIGILL);
515 }
516
517 regs->tf_esp = (int)sfp;
518 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
519 regs->tf_eflags &= ~PSL_T;
520 regs->tf_cs = _ucodesel;
521 regs->tf_ds = _udatasel;
522 regs->tf_es = _udatasel;
523 regs->tf_fs = _udatasel;
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524 regs->tf_ss = _udatasel;
525}
526
527/*
65957d54 528 * sigreturn(ucontext_t *sigcntxp)
41c20dac 529 *
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530 * System call to cleanup state after a signal
531 * has been taken. Reset signal mask and
532 * stack state from context left by sendsig (above).
533 * Return to previous pc and psl as specified by
534 * context left by sendsig. Check carefully to
535 * make sure that the user has not modified the
536 * state to gain improper privileges.
537 */
538#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
539#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
540
984263bc 541int
41c20dac 542sigreturn(struct sigreturn_args *uap)
984263bc 543{
41c20dac 544 struct proc *p = curproc;
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545 struct trapframe *regs;
546 ucontext_t *ucp;
547 int cs, eflags;
548
549 ucp = uap->sigcntxp;
550
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551 if (!useracc((caddr_t)ucp, sizeof(ucontext_t), VM_PROT_READ))
552 return (EFAULT);
553
554 regs = p->p_md.md_regs;
555 eflags = ucp->uc_mcontext.mc_eflags;
556
557 if (eflags & PSL_VM) {
558 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
559 struct vm86_kernel *vm86;
560
561 /*
562 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
563 * set up the vm86 area, and we can't enter vm86 mode.
564 */
b7c628e4 565 if (p->p_thread->td_pcb->pcb_ext == 0)
984263bc 566 return (EINVAL);
b7c628e4 567 vm86 = &p->p_thread->td_pcb->pcb_ext->ext_vm86;
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568 if (vm86->vm86_inited == 0)
569 return (EINVAL);
570
571 /* go back to user mode if both flags are set */
572 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
573 trapsignal(p, SIGBUS, 0);
574
575 if (vm86->vm86_has_vme) {
576 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
577 (eflags & VME_USERCHANGE) | PSL_VM;
578 } else {
579 vm86->vm86_eflags = eflags; /* save VIF, VIP */
580 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | (eflags & VM_USERCHANGE) | PSL_VM;
581 }
582 bcopy(&ucp->uc_mcontext.mc_fs, tf, sizeof(struct trapframe));
583 tf->tf_eflags = eflags;
584 tf->tf_vm86_ds = tf->tf_ds;
585 tf->tf_vm86_es = tf->tf_es;
586 tf->tf_vm86_fs = tf->tf_fs;
587 tf->tf_vm86_gs = ucp->uc_mcontext.mc_gs;
588 tf->tf_ds = _udatasel;
589 tf->tf_es = _udatasel;
590 tf->tf_fs = _udatasel;
591 } else {
592 /*
593 * Don't allow users to change privileged or reserved flags.
594 */
595 /*
596 * XXX do allow users to change the privileged flag PSL_RF.
597 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
598 * should sometimes set it there too. tf_eflags is kept in
599 * the signal context during signal handling and there is no
600 * other place to remember it, so the PSL_RF bit may be
601 * corrupted by the signal handler without us knowing.
602 * Corruption of the PSL_RF bit at worst causes one more or
603 * one less debugger trap, so allowing it is fairly harmless.
604 */
605 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
606 printf("sigreturn: eflags = 0x%x\n", eflags);
607 return(EINVAL);
608 }
609
610 /*
611 * Don't allow users to load a valid privileged %cs. Let the
612 * hardware check for invalid selectors, excess privilege in
613 * other selectors, invalid %eip's and invalid %esp's.
614 */
615 cs = ucp->uc_mcontext.mc_cs;
616 if (!CS_SECURE(cs)) {
617 printf("sigreturn: cs = 0x%x\n", cs);
618 trapsignal(p, SIGBUS, T_PROTFLT);
619 return(EINVAL);
620 }
621 bcopy(&ucp->uc_mcontext.mc_fs, regs, sizeof(struct trapframe));
622 }
623
624 if (ucp->uc_mcontext.mc_onstack & 1)
625 p->p_sigstk.ss_flags |= SS_ONSTACK;
626 else
627 p->p_sigstk.ss_flags &= ~SS_ONSTACK;
628
629 p->p_sigmask = ucp->uc_sigmask;
630 SIG_CANTMASK(p->p_sigmask);
631 return(EJUSTRETURN);
632}
633
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634/*
635 * Stack frame on entry to function. %eax will contain the function vector,
636 * %ecx will contain the function data. flags, ecx, and eax will have
637 * already been pushed on the stack.
638 */
639struct upc_frame {
640 register_t eax;
641 register_t ecx;
0a455ac5 642 register_t edx;
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643 register_t flags;
644 register_t oldip;
645};
646
647void
648sendupcall(struct vmupcall *vu, int morepending)
649{
650 struct proc *p = curproc;
651 struct trapframe *regs;
652 struct upcall upcall;
653 struct upc_frame upc_frame;
6e58b5df 654 int crit_count = 0;
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655
656 /*
657 * Get the upcall data structure
658 */
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659 if (copyin(p->p_upcall, &upcall, sizeof(upcall)) ||
660 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
661 ) {
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662 vu->vu_pending = 0;
663 printf("bad upcall address\n");
664 return;
665 }
666
667 /*
668 * If the data structure is already marked pending or has a critical
669 * section count, mark the data structure as pending and return
670 * without doing an upcall. vu_pending is left set.
671 */
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672 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
673 if (upcall.upc_pending < vu->vu_pending) {
674 upcall.upc_pending = vu->vu_pending;
675 copyout(&upcall.upc_pending, &p->p_upcall->upc_pending,
676 sizeof(upcall.upc_pending));
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677 }
678 return;
679 }
680
681 /*
682 * We can run this upcall now, clear vu_pending.
683 *
684 * Bump our critical section count and set or clear the
685 * user pending flag depending on whether more upcalls are
686 * pending. The user will be responsible for calling
687 * upc_dispatch(-1) to process remaining upcalls.
688 */
689 vu->vu_pending = 0;
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690 upcall.upc_pending = morepending;
691 crit_count += TDPRI_CRIT;
692 copyout(&upcall.upc_pending, &p->p_upcall->upc_pending,
693 sizeof(upcall.upc_pending));
694 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
695 sizeof(int));
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696
697 /*
698 * Construct a stack frame and issue the upcall
699 */
700 regs = p->p_md.md_regs;
701 upc_frame.eax = regs->tf_eax;
702 upc_frame.ecx = regs->tf_ecx;
0a455ac5 703 upc_frame.edx = regs->tf_edx;
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704 upc_frame.flags = regs->tf_eflags;
705 upc_frame.oldip = regs->tf_eip;
706 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
707 sizeof(upc_frame)) != 0) {
708 printf("bad stack on upcall\n");
709 } else {
710 regs->tf_eax = (register_t)vu->vu_func;
711 regs->tf_ecx = (register_t)vu->vu_data;
0a455ac5 712 regs->tf_edx = (register_t)p->p_upcall;
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713 regs->tf_eip = (register_t)vu->vu_ctx;
714 regs->tf_esp -= sizeof(upc_frame);
715 }
716}
717
718/*
719 * fetchupcall occurs in the context of a system call, which means that
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720 * we have to return EJUSTRETURN in order to prevent eax and edx from
721 * being overwritten by the syscall return value.
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722 *
723 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
724 * and the function pointer in %eax.
725 */
726int
0a455ac5 727fetchupcall (struct vmupcall *vu, int morepending, void *rsp)
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728{
729 struct upc_frame upc_frame;
730 struct proc *p;
731 struct trapframe *regs;
732 int error;
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733 struct upcall upcall;
734 int crit_count;
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735
736 p = curproc;
737 regs = p->p_md.md_regs;
738
6e58b5df 739 error = copyout(&morepending, &p->p_upcall->upc_pending, sizeof(int));
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740 if (error == 0) {
741 if (vu) {
742 /*
743 * This jumps us to the next ready context.
744 */
745 vu->vu_pending = 0;
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746 error = copyin(p->p_upcall, &upcall, sizeof(upcall));
747 crit_count = 0;
748 if (error == 0)
749 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
750 crit_count += TDPRI_CRIT;
a722be49 751 if (error == 0)
6e58b5df 752 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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753 regs->tf_eax = (register_t)vu->vu_func;
754 regs->tf_ecx = (register_t)vu->vu_data;
0a455ac5 755 regs->tf_edx = (register_t)p->p_upcall;
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756 regs->tf_eip = (register_t)vu->vu_ctx;
757 regs->tf_esp = (register_t)rsp;
758 } else {
759 /*
760 * This returns us to the originally interrupted code.
761 */
762 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
763 regs->tf_eax = upc_frame.eax;
764 regs->tf_ecx = upc_frame.ecx;
0a455ac5 765 regs->tf_edx = upc_frame.edx;
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766 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
767 (upc_frame.flags & PSL_USERCHANGE);
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768 regs->tf_eip = upc_frame.oldip;
769 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
770 }
771 }
772 if (error == 0)
773 error = EJUSTRETURN;
774 return(error);
775}
776
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777/*
778 * Machine dependent boot() routine
779 *
780 * I haven't seen anything to put here yet
781 * Possibly some stuff might be grafted back here from boot()
782 */
783void
784cpu_boot(int howto)
785{
786}
787
788/*
789 * Shutdown the CPU as much as possible
790 */
791void
792cpu_halt(void)
793{
794 for (;;)
795 __asm__ ("hlt");
796}
797
798/*
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799 * cpu_idle() represents the idle LWKT. You cannot return from this function
800 * (unless you want to blow things up!). Instead we look for runnable threads
801 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 802 *
26a0694b 803 * The main loop is entered with a critical section held, we must release
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804 * the critical section before doing anything else. lwkt_switch() will
805 * check for pending interrupts due to entering and exiting its own
806 * critical section.
26a0694b 807 *
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808 * Note on cpu_idle_hlt: On an SMP system we rely on a scheduler IPI
809 * to wake a HLTed cpu up. However, there are cases where the idlethread
810 * will be entered with the possibility that no IPI will occur and in such
811 * cases lwkt_switch() sets TDF_IDLE_NOHLT.
984263bc 812 */
96728c05 813static int cpu_idle_hlt = 1;
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814static int cpu_idle_hltcnt;
815static int cpu_idle_spincnt;
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816SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
817 &cpu_idle_hlt, 0, "Idle loop HLT enable");
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818SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
819 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
820SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
821 &cpu_idle_spincnt, 0, "Idle loop entry spins");
984263bc 822
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823static void
824cpu_idle_default_hook(void)
825{
826 /*
827 * We must guarentee that hlt is exactly the instruction
828 * following the sti.
829 */
830 __asm __volatile("sti; hlt");
831}
832
833/* Other subsystems (e.g., ACPI) can hook this later. */
834void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
835
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836void
837cpu_idle(void)
838{
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839 struct thread *td = curthread;
840
26a0694b 841 crit_exit();
a2a5ad0d 842 KKASSERT(td->td_pri < TDPRI_CRIT);
8ad65e08 843 for (;;) {
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844 /*
845 * See if there are any LWKTs ready to go.
846 */
8ad65e08 847 lwkt_switch();
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848
849 /*
850 * If we are going to halt call splz unconditionally after
851 * CLIing to catch any interrupt races. Note that we are
852 * at SPL0 and interrupts are enabled.
853 */
854 if (cpu_idle_hlt && !lwkt_runnable() &&
855 (td->td_flags & TDF_IDLE_NOHLT) == 0) {
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856 __asm __volatile("cli");
857 splz();
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858 if (!lwkt_runnable())
859 cpu_idle_hook();
860#ifdef SMP
861 else
862 __asm __volatile("pause");
863#endif
60f945af 864 ++cpu_idle_hltcnt;
8ad65e08 865 } else {
a2a5ad0d 866 td->td_flags &= ~TDF_IDLE_NOHLT;
60f945af 867 splz();
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868#ifdef SMP
869 __asm __volatile("sti; pause");
870#else
8ad65e08 871 __asm __volatile("sti");
8b6d0f3f 872#endif
60f945af 873 ++cpu_idle_spincnt;
8ad65e08 874 }
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875 }
876}
877
878/*
879 * Clear registers on exec
880 */
881void
882setregs(p, entry, stack, ps_strings)
883 struct proc *p;
884 u_long entry;
885 u_long stack;
886 u_long ps_strings;
887{
888 struct trapframe *regs = p->p_md.md_regs;
b7c628e4 889 struct pcb *pcb = p->p_thread->td_pcb;
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890
891 /* Reset pc->pcb_gs and %gs before possibly invalidating it. */
892 pcb->pcb_gs = _udatasel;
893 load_gs(_udatasel);
894
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895 /* was i386_user_cleanup() in NetBSD */
896 user_ldt_free(pcb);
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897
898 bzero((char *)regs, sizeof(struct trapframe));
899 regs->tf_eip = entry;
900 regs->tf_esp = stack;
901 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
902 regs->tf_ss = _udatasel;
903 regs->tf_ds = _udatasel;
904 regs->tf_es = _udatasel;
905 regs->tf_fs = _udatasel;
906 regs->tf_cs = _ucodesel;
907
908 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
909 regs->tf_ebx = ps_strings;
910
911 /*
912 * Reset the hardware debug registers if they were in use.
913 * They won't have any meaning for the newly exec'd process.
914 */
915 if (pcb->pcb_flags & PCB_DBREGS) {
916 pcb->pcb_dr0 = 0;
917 pcb->pcb_dr1 = 0;
918 pcb->pcb_dr2 = 0;
919 pcb->pcb_dr3 = 0;
920 pcb->pcb_dr6 = 0;
921 pcb->pcb_dr7 = 0;
b7c628e4 922 if (pcb == curthread->td_pcb) {
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923 /*
924 * Clear the debug registers on the running
925 * CPU, otherwise they will end up affecting
926 * the next process we switch to.
927 */
928 reset_dbregs();
929 }
930 pcb->pcb_flags &= ~PCB_DBREGS;
931 }
932
933 /*
934 * Initialize the math emulator (if any) for the current process.
935 * Actually, just clear the bit that says that the emulator has
936 * been initialized. Initialization is delayed until the process
937 * traps to the emulator (if it is done at all) mainly because
938 * emulators don't provide an entry point for initialization.
939 */
b7c628e4 940 p->p_thread->td_pcb->pcb_flags &= ~FP_SOFTFP;
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941
942 /*
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943 * note: do not set CR0_TS here. npxinit() must do it after clearing
944 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
945 * in npxdna().
984263bc 946 */
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947 crit_enter();
948 load_cr0(rcr0() | CR0_MP);
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949
950#if NNPX > 0
951 /* Initialize the npx (if any) for the current process. */
952 npxinit(__INITIAL_NPXCW__);
953#endif
a02705a9 954 crit_exit();
984263bc 955
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956 /*
957 * note: linux emulator needs edx to be 0x0 on entry, which is
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958 * handled in execve simply by setting the 64 bit syscall
959 * return value to 0.
90b9818c 960 */
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961}
962
963void
964cpu_setregs(void)
965{
966 unsigned int cr0;
967
968 cr0 = rcr0();
969 cr0 |= CR0_NE; /* Done by npxinit() */
970 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
971#ifdef I386_CPU
972 if (cpu_class != CPUCLASS_386)
973#endif
974 cr0 |= CR0_WP | CR0_AM;
975 load_cr0(cr0);
976 load_gs(_udatasel);
977}
978
979static int
980sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
981{
982 int error;
983 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
984 req);
985 if (!error && req->newptr)
986 resettodr();
987 return (error);
988}
989
990SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
991 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
992
993SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
994 CTLFLAG_RW, &disable_rtc_set, 0, "");
995
996SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
997 CTLFLAG_RD, &bootinfo, bootinfo, "");
998
999SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1000 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1001
1002extern u_long bootdev; /* not a dev_t - encoding is different */
1003SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1004 CTLFLAG_RD, &bootdev, 0, "Boot device (not in dev_t format)");
1005
1006/*
1007 * Initialize 386 and configure to run kernel
1008 */
1009
1010/*
1011 * Initialize segments & interrupt table
1012 */
1013
1014int _default_ldt;
1015union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1016static struct gate_descriptor idt0[NIDT];
1017struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1018union descriptor ldt[NLDT]; /* local descriptor table */
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MD
1019
1020/* table descriptors - used to load tables by cpu */
984263bc 1021struct region_descriptor r_gdt, r_idt;
984263bc 1022
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MD
1023#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1024extern int has_f00f_bug;
1025#endif
1026
1027static struct i386tss dblfault_tss;
1028static char dblfault_stack[PAGE_SIZE];
1029
1030extern struct user *proc0paddr;
1031
1032
1033/* software prototypes -- in more palatable form */
1034struct soft_segment_descriptor gdt_segs[] = {
1035/* GNULL_SEL 0 Null Descriptor */
1036{ 0x0, /* segment base address */
1037 0x0, /* length */
1038 0, /* segment type */
1039 0, /* segment descriptor priority level */
1040 0, /* segment descriptor present */
1041 0, 0,
1042 0, /* default 32 vs 16 bit size */
1043 0 /* limit granularity (byte/page units)*/ },
1044/* GCODE_SEL 1 Code Descriptor for kernel */
1045{ 0x0, /* segment base address */
1046 0xfffff, /* length - all address space */
1047 SDT_MEMERA, /* segment type */
1048 0, /* segment descriptor priority level */
1049 1, /* segment descriptor present */
1050 0, 0,
1051 1, /* default 32 vs 16 bit size */
1052 1 /* limit granularity (byte/page units)*/ },
1053/* GDATA_SEL 2 Data Descriptor for kernel */
1054{ 0x0, /* segment base address */
1055 0xfffff, /* length - all address space */
1056 SDT_MEMRWA, /* segment type */
1057 0, /* segment descriptor priority level */
1058 1, /* segment descriptor present */
1059 0, 0,
1060 1, /* default 32 vs 16 bit size */
1061 1 /* limit granularity (byte/page units)*/ },
1062/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1063{ 0x0, /* segment base address */
1064 0xfffff, /* length - all address space */
1065 SDT_MEMRWA, /* segment type */
1066 0, /* segment descriptor priority level */
1067 1, /* segment descriptor present */
1068 0, 0,
1069 1, /* default 32 vs 16 bit size */
1070 1 /* limit granularity (byte/page units)*/ },
1071/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1072{
1073 0x0, /* segment base address */
1074 sizeof(struct i386tss)-1,/* length - all address space */
1075 SDT_SYS386TSS, /* segment type */
1076 0, /* segment descriptor priority level */
1077 1, /* segment descriptor present */
1078 0, 0,
1079 0, /* unused - default 32 vs 16 bit size */
1080 0 /* limit granularity (byte/page units)*/ },
1081/* GLDT_SEL 5 LDT Descriptor */
1082{ (int) ldt, /* segment base address */
1083 sizeof(ldt)-1, /* length - all address space */
1084 SDT_SYSLDT, /* segment type */
1085 SEL_UPL, /* segment descriptor priority level */
1086 1, /* segment descriptor present */
1087 0, 0,
1088 0, /* unused - default 32 vs 16 bit size */
1089 0 /* limit granularity (byte/page units)*/ },
1090/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1091{ (int) ldt, /* segment base address */
1092 (512 * sizeof(union descriptor)-1), /* length */
1093 SDT_SYSLDT, /* segment type */
1094 0, /* segment descriptor priority level */
1095 1, /* segment descriptor present */
1096 0, 0,
1097 0, /* unused - default 32 vs 16 bit size */
1098 0 /* limit granularity (byte/page units)*/ },
1099/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1100{ 0x0, /* segment base address */
1101 0x0, /* length - all address space */
1102 0, /* segment type */
1103 0, /* segment descriptor priority level */
1104 0, /* segment descriptor present */
1105 0, 0,
1106 0, /* default 32 vs 16 bit size */
1107 0 /* limit granularity (byte/page units)*/ },
1108/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1109{ 0x400, /* segment base address */
1110 0xfffff, /* length */
1111 SDT_MEMRWA, /* segment type */
1112 0, /* segment descriptor priority level */
1113 1, /* segment descriptor present */
1114 0, 0,
1115 1, /* default 32 vs 16 bit size */
1116 1 /* limit granularity (byte/page units)*/ },
1117/* GPANIC_SEL 9 Panic Tss Descriptor */
1118{ (int) &dblfault_tss, /* segment base address */
1119 sizeof(struct i386tss)-1,/* length - all address space */
1120 SDT_SYS386TSS, /* segment type */
1121 0, /* segment descriptor priority level */
1122 1, /* segment descriptor present */
1123 0, 0,
1124 0, /* unused - default 32 vs 16 bit size */
1125 0 /* limit granularity (byte/page units)*/ },
1126/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1127{ 0, /* segment base address (overwritten) */
1128 0xfffff, /* length */
1129 SDT_MEMERA, /* segment type */
1130 0, /* segment descriptor priority level */
1131 1, /* segment descriptor present */
1132 0, 0,
1133 0, /* default 32 vs 16 bit size */
1134 1 /* limit granularity (byte/page units)*/ },
1135/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1136{ 0, /* segment base address (overwritten) */
1137 0xfffff, /* length */
1138 SDT_MEMERA, /* segment type */
1139 0, /* segment descriptor priority level */
1140 1, /* segment descriptor present */
1141 0, 0,
1142 0, /* default 32 vs 16 bit size */
1143 1 /* limit granularity (byte/page units)*/ },
1144/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1145{ 0, /* segment base address (overwritten) */
1146 0xfffff, /* length */
1147 SDT_MEMRWA, /* segment type */
1148 0, /* segment descriptor priority level */
1149 1, /* segment descriptor present */
1150 0, 0,
1151 1, /* default 32 vs 16 bit size */
1152 1 /* limit granularity (byte/page units)*/ },
1153/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1154{ 0, /* segment base address (overwritten) */
1155 0xfffff, /* length */
1156 SDT_MEMRWA, /* segment type */
1157 0, /* segment descriptor priority level */
1158 1, /* segment descriptor present */
1159 0, 0,
1160 0, /* default 32 vs 16 bit size */
1161 1 /* limit granularity (byte/page units)*/ },
1162/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1163{ 0, /* segment base address (overwritten) */
1164 0xfffff, /* length */
1165 SDT_MEMRWA, /* segment type */
1166 0, /* segment descriptor priority level */
1167 1, /* segment descriptor present */
1168 0, 0,
1169 0, /* default 32 vs 16 bit size */
1170 1 /* limit granularity (byte/page units)*/ },
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MD
1171/* GTLS_START 15 TLS */
1172{ 0x0, /* segment base address */
1173 0x0, /* length */
1174 0, /* segment type */
1175 0, /* segment descriptor priority level */
1176 0, /* segment descriptor present */
1177 0, 0,
1178 0, /* default 32 vs 16 bit size */
1179 0 /* limit granularity (byte/page units)*/ },
1180/* GTLS_START+1 16 TLS */
1181{ 0x0, /* segment base address */
1182 0x0, /* length */
1183 0, /* segment type */
1184 0, /* segment descriptor priority level */
1185 0, /* segment descriptor present */
1186 0, 0,
1187 0, /* default 32 vs 16 bit size */
1188 0 /* limit granularity (byte/page units)*/ },
1189/* GTLS_END 17 TLS */
1190{ 0x0, /* segment base address */
1191 0x0, /* length */
1192 0, /* segment type */
1193 0, /* segment descriptor priority level */
1194 0, /* segment descriptor present */
1195 0, 0,
1196 0, /* default 32 vs 16 bit size */
1197 0 /* limit granularity (byte/page units)*/ },
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MD
1198};
1199
1200static struct soft_segment_descriptor ldt_segs[] = {
1201 /* Null Descriptor - overwritten by call gate */
1202{ 0x0, /* segment base address */
1203 0x0, /* length - all address space */
1204 0, /* segment type */
1205 0, /* segment descriptor priority level */
1206 0, /* segment descriptor present */
1207 0, 0,
1208 0, /* default 32 vs 16 bit size */
1209 0 /* limit granularity (byte/page units)*/ },
1210 /* Null Descriptor - overwritten by call gate */
1211{ 0x0, /* segment base address */
1212 0x0, /* length - all address space */
1213 0, /* segment type */
1214 0, /* segment descriptor priority level */
1215 0, /* segment descriptor present */
1216 0, 0,
1217 0, /* default 32 vs 16 bit size */
1218 0 /* limit granularity (byte/page units)*/ },
1219 /* Null Descriptor - overwritten by call gate */
1220{ 0x0, /* segment base address */
1221 0x0, /* length - all address space */
1222 0, /* segment type */
1223 0, /* segment descriptor priority level */
1224 0, /* segment descriptor present */
1225 0, 0,
1226 0, /* default 32 vs 16 bit size */
1227 0 /* limit granularity (byte/page units)*/ },
1228 /* Code Descriptor for user */
1229{ 0x0, /* segment base address */
1230 0xfffff, /* length - all address space */
1231 SDT_MEMERA, /* segment type */
1232 SEL_UPL, /* segment descriptor priority level */
1233 1, /* segment descriptor present */
1234 0, 0,
1235 1, /* default 32 vs 16 bit size */
1236 1 /* limit granularity (byte/page units)*/ },
1237 /* Null Descriptor - overwritten by call gate */
1238{ 0x0, /* segment base address */
1239 0x0, /* length - all address space */
1240 0, /* segment type */
1241 0, /* segment descriptor priority level */
1242 0, /* segment descriptor present */
1243 0, 0,
1244 0, /* default 32 vs 16 bit size */
1245 0 /* limit granularity (byte/page units)*/ },
1246 /* Data Descriptor for user */
1247{ 0x0, /* segment base address */
1248 0xfffff, /* length - all address space */
1249 SDT_MEMRWA, /* segment type */
1250 SEL_UPL, /* segment descriptor priority level */
1251 1, /* segment descriptor present */
1252 0, 0,
1253 1, /* default 32 vs 16 bit size */
1254 1 /* limit granularity (byte/page units)*/ },
1255};
1256
1257void
1258setidt(idx, func, typ, dpl, selec)
1259 int idx;
1260 inthand_t *func;
1261 int typ;
1262 int dpl;
1263 int selec;
1264{
1265 struct gate_descriptor *ip;
1266
1267 ip = idt + idx;
1268 ip->gd_looffset = (int)func;
1269 ip->gd_selector = selec;
1270 ip->gd_stkcpy = 0;
1271 ip->gd_xx = 0;
1272 ip->gd_type = typ;
1273 ip->gd_dpl = dpl;
1274 ip->gd_p = 1;
1275 ip->gd_hioffset = ((int)func)>>16 ;
1276}
1277
1278#define IDTVEC(name) __CONCAT(X,name)
1279
1280extern inthand_t
1281 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1282 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1283 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1284 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1285 IDTVEC(xmm), IDTVEC(syscall),
1286 IDTVEC(rsvd0);
a64ba182 1287extern inthand_t
7062f5b4
EN
1288 IDTVEC(int0x80_syscall), IDTVEC(int0x81_syscall),
1289 IDTVEC(int0x82_syscall);
984263bc 1290
f7bc9806
MD
1291#ifdef DEBUG_INTERRUPTS
1292extern inthand_t *Xrsvdary[256];
1293#endif
1294
984263bc
MD
1295void
1296sdtossd(sd, ssd)
1297 struct segment_descriptor *sd;
1298 struct soft_segment_descriptor *ssd;
1299{
1300 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1301 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1302 ssd->ssd_type = sd->sd_type;
1303 ssd->ssd_dpl = sd->sd_dpl;
1304 ssd->ssd_p = sd->sd_p;
1305 ssd->ssd_def32 = sd->sd_def32;
1306 ssd->ssd_gran = sd->sd_gran;
1307}
1308
1309#define PHYSMAP_SIZE (2 * 8)
1310
1311/*
1312 * Populate the (physmap) array with base/bound pairs describing the
1313 * available physical memory in the system, then test this memory and
1314 * build the phys_avail array describing the actually-available memory.
1315 *
1316 * If we cannot accurately determine the physical memory map, then use
1317 * value from the 0xE801 call, and failing that, the RTC.
1318 *
1319 * Total memory size may be set by the kernel environment variable
1320 * hw.physmem or the compile-time define MAXMEM.
1321 */
1322static void
1323getmemsize(int first)
1324{
1325 int i, physmap_idx, pa_indx;
1326 int hasbrokenint12;
1327 u_int basemem, extmem;
1328 struct vm86frame vmf;
1329 struct vm86context vmc;
1330 vm_offset_t pa, physmap[PHYSMAP_SIZE];
b5b32410 1331 pt_entry_t *pte;
984263bc
MD
1332 const char *cp;
1333 struct {
1334 u_int64_t base;
1335 u_int64_t length;
1336 u_int32_t type;
1337 } *smap;
28abdbbb 1338 quad_t dcons_addr, dcons_size;
984263bc
MD
1339
1340 hasbrokenint12 = 0;
1341 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
1342 bzero(&vmf, sizeof(struct vm86frame));
1343 bzero(physmap, sizeof(physmap));
1344 basemem = 0;
1345
1346 /*
1347 * Some newer BIOSes has broken INT 12H implementation which cause
1348 * kernel panic immediately. In this case, we need to scan SMAP
1349 * with INT 15:E820 first, then determine base memory size.
1350 */
1351 if (hasbrokenint12) {
1352 goto int15e820;
1353 }
1354
1355 /*
7febcc6e
MD
1356 * Perform "base memory" related probes & setup. If we get a crazy
1357 * value give the bios some scribble space just in case.
984263bc
MD
1358 */
1359 vm86_intcall(0x12, &vmf);
1360 basemem = vmf.vmf_ax;
1361 if (basemem > 640) {
7febcc6e
MD
1362 printf("Preposterous BIOS basemem of %uK, "
1363 "truncating to < 640K\n", basemem);
1364 basemem = 636;
984263bc
MD
1365 }
1366
1367 /*
1368 * XXX if biosbasemem is now < 640, there is a `hole'
1369 * between the end of base memory and the start of
1370 * ISA memory. The hole may be empty or it may
1371 * contain BIOS code or data. Map it read/write so
1372 * that the BIOS can write to it. (Memory from 0 to
1373 * the physical end of the kernel is mapped read-only
1374 * to begin with and then parts of it are remapped.
1375 * The parts that aren't remapped form holes that
1376 * remain read-only and are unused by the kernel.
1377 * The base memory area is below the physical end of
1378 * the kernel and right now forms a read-only hole.
1379 * The part of it from PAGE_SIZE to
1380 * (trunc_page(biosbasemem * 1024) - 1) will be
1381 * remapped and used by the kernel later.)
1382 *
1383 * This code is similar to the code used in
1384 * pmap_mapdev, but since no memory needs to be
1385 * allocated we simply change the mapping.
1386 */
1387 for (pa = trunc_page(basemem * 1024);
1388 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1389 pte = vtopte(pa + KERNBASE);
984263bc
MD
1390 *pte = pa | PG_RW | PG_V;
1391 }
1392
1393 /*
1394 * if basemem != 640, map pages r/w into vm86 page table so
1395 * that the bios can scribble on it.
1396 */
b5b32410 1397 pte = vm86paddr;
984263bc
MD
1398 for (i = basemem / 4; i < 160; i++)
1399 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1400
1401int15e820:
1402 /*
1403 * map page 1 R/W into the kernel page table so we can use it
1404 * as a buffer. The kernel will unmap this page later.
1405 */
b5b32410 1406 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1407 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1408
1409 /*
1410 * get memory map with INT 15:E820
1411 */
1412#define SMAPSIZ sizeof(*smap)
1413#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1414
1415 vmc.npages = 0;
1416 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1417 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1418
1419 physmap_idx = 0;
1420 vmf.vmf_ebx = 0;
1421 do {
1422 vmf.vmf_eax = 0xE820;
1423 vmf.vmf_edx = SMAP_SIG;
1424 vmf.vmf_ecx = SMAPSIZ;
1425 i = vm86_datacall(0x15, &vmf, &vmc);
1426 if (i || vmf.vmf_eax != SMAP_SIG)
1427 break;
1428 if (boothowto & RB_VERBOSE)
1429 printf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
1430 smap->type,
1431 *(u_int32_t *)((char *)&smap->base + 4),
1432 (u_int32_t)smap->base,
1433 *(u_int32_t *)((char *)&smap->length + 4),
1434 (u_int32_t)smap->length);
1435
1436 if (smap->type != 0x01)
1437 goto next_run;
1438
1439 if (smap->length == 0)
1440 goto next_run;
1441
1442 if (smap->base >= 0xffffffff) {
1443 printf("%uK of memory above 4GB ignored\n",
1444 (u_int)(smap->length / 1024));
1445 goto next_run;
1446 }
1447
1448 for (i = 0; i <= physmap_idx; i += 2) {
1449 if (smap->base < physmap[i + 1]) {
1450 if (boothowto & RB_VERBOSE)
1451 printf(
1452 "Overlapping or non-montonic memory region, ignoring second region\n");
1453 goto next_run;
1454 }
1455 }
1456
1457 if (smap->base == physmap[physmap_idx + 1]) {
1458 physmap[physmap_idx + 1] += smap->length;
1459 goto next_run;
1460 }
1461
1462 physmap_idx += 2;
1463 if (physmap_idx == PHYSMAP_SIZE) {
1464 printf(
1465 "Too many segments in the physical address map, giving up\n");
1466 break;
1467 }
1468 physmap[physmap_idx] = smap->base;
1469 physmap[physmap_idx + 1] = smap->base + smap->length;
1470next_run:
6b08710e 1471 ; /* fix GCC3.x warning */
984263bc
MD
1472 } while (vmf.vmf_ebx != 0);
1473
1474 /*
1475 * Perform "base memory" related probes & setup based on SMAP
1476 */
1477 if (basemem == 0) {
1478 for (i = 0; i <= physmap_idx; i += 2) {
1479 if (physmap[i] == 0x00000000) {
1480 basemem = physmap[i + 1] / 1024;
1481 break;
1482 }
1483 }
1484
1485 if (basemem == 0) {
1486 basemem = 640;
1487 }
1488
1489 if (basemem > 640) {
1490 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
1491 basemem);
1492 basemem = 640;
1493 }
1494
1495 for (pa = trunc_page(basemem * 1024);
1496 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1497 pte = vtopte(pa + KERNBASE);
984263bc
MD
1498 *pte = pa | PG_RW | PG_V;
1499 }
1500
b5b32410 1501 pte = vm86paddr;
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MD
1502 for (i = basemem / 4; i < 160; i++)
1503 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1504 }
1505
1506 if (physmap[1] != 0)
1507 goto physmap_done;
1508
1509 /*
1510 * If we failed above, try memory map with INT 15:E801
1511 */
1512 vmf.vmf_ax = 0xE801;
1513 if (vm86_intcall(0x15, &vmf) == 0) {
1514 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1515 } else {
1516#if 0
1517 vmf.vmf_ah = 0x88;
1518 vm86_intcall(0x15, &vmf);
1519 extmem = vmf.vmf_ax;
1520#else
1521 /*
1522 * Prefer the RTC value for extended memory.
1523 */
1524 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1525#endif
1526 }
1527
1528 /*
1529 * Special hack for chipsets that still remap the 384k hole when
1530 * there's 16MB of memory - this really confuses people that
1531 * are trying to use bus mastering ISA controllers with the
1532 * "16MB limit"; they only have 16MB, but the remapping puts
1533 * them beyond the limit.
1534 *
1535 * If extended memory is between 15-16MB (16-17MB phys address range),
1536 * chop it to 15MB.
1537 */
1538 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1539 extmem = 15 * 1024;
1540
1541 physmap[0] = 0;
1542 physmap[1] = basemem * 1024;
1543 physmap_idx = 2;
1544 physmap[physmap_idx] = 0x100000;
1545 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1546
1547physmap_done:
1548 /*
1549 * Now, physmap contains a map of physical memory.
1550 */
1551
1552#ifdef SMP
17a9f566 1553 /* make hole for AP bootstrap code YYY */
984263bc
MD
1554 physmap[1] = mp_bootaddress(physmap[1] / 1024);
1555
1556 /* look for the MP hardware - needed for apic addresses */
1557 mp_probe();
1558#endif
1559
1560 /*
1561 * Maxmem isn't the "maximum memory", it's one larger than the
1562 * highest page of the physical address space. It should be
1563 * called something like "Maxphyspage". We may adjust this
1564 * based on ``hw.physmem'' and the results of the memory test.
1565 */
1566 Maxmem = atop(physmap[physmap_idx + 1]);
1567
1568#ifdef MAXMEM
1569 Maxmem = MAXMEM / 4;
1570#endif
1571
1572 /*
eb7d35b8 1573 * hw.physmem is a size in bytes; we also allow k, m, and g suffixes
984263bc
MD
1574 * for the appropriate modifiers. This overrides MAXMEM.
1575 */
1576 if ((cp = getenv("hw.physmem")) != NULL) {
1577 u_int64_t AllowMem, sanity;
1578 char *ep;
1579
1580 sanity = AllowMem = strtouq(cp, &ep, 0);
1581 if ((ep != cp) && (*ep != 0)) {
1582 switch(*ep) {
1583 case 'g':
1584 case 'G':
1585 AllowMem <<= 10;
1586 case 'm':
1587 case 'M':
1588 AllowMem <<= 10;
1589 case 'k':
1590 case 'K':
1591 AllowMem <<= 10;
1592 break;
1593 default:
1594 AllowMem = sanity = 0;
1595 }
1596 if (AllowMem < sanity)
1597 AllowMem = 0;
1598 }
1599 if (AllowMem == 0)
1600 printf("Ignoring invalid memory size of '%s'\n", cp);
1601 else
1602 Maxmem = atop(AllowMem);
1603 }
1604
1605 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1606 (boothowto & RB_VERBOSE))
6ef943a3 1607 printf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1608
1609 /*
1610 * If Maxmem has been increased beyond what the system has detected,
1611 * extend the last memory segment to the new limit.
1612 */
1613 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1614 physmap[physmap_idx + 1] = ptoa(Maxmem);
1615
1616 /* call pmap initialization to make new kernel address space */
1617 pmap_bootstrap(first, 0);
1618
1619 /*
1620 * Size up each available chunk of physical memory.
1621 */
1622 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1623 pa_indx = 0;
1624 phys_avail[pa_indx++] = physmap[0];
1625 phys_avail[pa_indx] = physmap[0];
b5b32410 1626 pte = CMAP1;
984263bc 1627
28abdbbb
HS
1628 /*
1629 * Get dcons buffer address
1630 */
1631 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1632 getenv_quad("dcons.size", &dcons_size) == 0)
1633 dcons_addr = 0;
1634
984263bc
MD
1635 /*
1636 * physmap is in bytes, so when converting to page boundaries,
1637 * round up the start address and round down the end address.
1638 */
1639 for (i = 0; i <= physmap_idx; i += 2) {
1640 vm_offset_t end;
1641
1642 end = ptoa(Maxmem);
1643 if (physmap[i + 1] < end)
1644 end = trunc_page(physmap[i + 1]);
1645 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1646 int tmp, page_bad;
1647#if 0
1648 int *ptr = 0;
1649#else
1650 int *ptr = (int *)CADDR1;
1651#endif
1652
1653 /*
1654 * block out kernel memory as not available.
1655 */
1656 if (pa >= 0x100000 && pa < first)
1657 continue;
1658
28abdbbb
HS
1659 /*
1660 * block out dcons buffer
1661 */
1662 if (dcons_addr > 0
1663 && pa >= trunc_page(dcons_addr)
1664 && pa < dcons_addr + dcons_size)
1665 continue;
1666
984263bc
MD
1667 page_bad = FALSE;
1668
1669 /*
1670 * map page into kernel: valid, read/write,non-cacheable
1671 */
1672 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1673 cpu_invltlb();
984263bc
MD
1674
1675 tmp = *(int *)ptr;
1676 /*
1677 * Test for alternating 1's and 0's
1678 */
1679 *(volatile int *)ptr = 0xaaaaaaaa;
1680 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1681 page_bad = TRUE;
1682 }
1683 /*
1684 * Test for alternating 0's and 1's
1685 */
1686 *(volatile int *)ptr = 0x55555555;
1687 if (*(volatile int *)ptr != 0x55555555) {
1688 page_bad = TRUE;
1689 }
1690 /*
1691 * Test for all 1's
1692 */
1693 *(volatile int *)ptr = 0xffffffff;
1694 if (*(volatile int *)ptr != 0xffffffff) {
1695 page_bad = TRUE;
1696 }
1697 /*
1698 * Test for all 0's
1699 */
1700 *(volatile int *)ptr = 0x0;
1701 if (*(volatile int *)ptr != 0x0) {
1702 page_bad = TRUE;
1703 }
1704 /*
1705 * Restore original value.
1706 */
1707 *(int *)ptr = tmp;
1708
1709 /*
1710 * Adjust array of valid/good pages.
1711 */
1712 if (page_bad == TRUE) {
1713 continue;
1714 }
1715 /*
1716 * If this good page is a continuation of the
1717 * previous set of good pages, then just increase
1718 * the end pointer. Otherwise start a new chunk.
1719 * Note that "end" points one higher than end,
1720 * making the range >= start and < end.
1721 * If we're also doing a speculative memory
1722 * test and we at or past the end, bump up Maxmem
1723 * so that we keep going. The first bad page
1724 * will terminate the loop.
1725 */
1726 if (phys_avail[pa_indx] == pa) {
1727 phys_avail[pa_indx] += PAGE_SIZE;
1728 } else {
1729 pa_indx++;
1730 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1731 printf("Too many holes in the physical address space, giving up\n");
1732 pa_indx--;
1733 break;
1734 }
1735 phys_avail[pa_indx++] = pa; /* start */
1736 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1737 }
1738 physmem++;
1739 }
1740 }
1741 *pte = 0;
0f7a3396 1742 cpu_invltlb();
984263bc
MD
1743
1744 /*
1745 * XXX
1746 * The last chunk must contain at least one page plus the message
1747 * buffer to avoid complicating other code (message buffer address
1748 * calculation, etc.).
1749 */
1750 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1751 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1752 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1753 phys_avail[pa_indx--] = 0;
1754 phys_avail[pa_indx--] = 0;
1755 }
1756
1757 Maxmem = atop(phys_avail[pa_indx]);
1758
1759 /* Trim off space for the message buffer. */
1760 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1761
1762 avail_end = phys_avail[pa_indx];
1763}
1764
f7bc9806
MD
1765/*
1766 * IDT VECTORS:
1767 * 0 Divide by zero
1768 * 1 Debug
1769 * 2 NMI
1770 * 3 BreakPoint
1771 * 4 OverFlow
1772 * 5 Bound-Range
1773 * 6 Invalid OpCode
1774 * 7 Device Not Available (x87)
1775 * 8 Double-Fault
1776 * 9 Coprocessor Segment overrun (unsupported, reserved)
1777 * 10 Invalid-TSS
1778 * 11 Segment not present
1779 * 12 Stack
1780 * 13 General Protection
1781 * 14 Page Fault
1782 * 15 Reserved
1783 * 16 x87 FP Exception pending
1784 * 17 Alignment Check
1785 * 18 Machine Check
1786 * 19 SIMD floating point
1787 * 20-31 reserved
1788 * 32-255 INTn/external sources
1789 */
984263bc 1790void
17a9f566 1791init386(int first)
984263bc
MD
1792{
1793 struct gate_descriptor *gdp;
1794 int gsel_tss, metadata_missing, off, x;
85100692 1795 struct mdglobaldata *gd;
984263bc
MD
1796
1797 /*
1798 * Prevent lowering of the ipl if we call tsleep() early.
1799 */
85100692 1800 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1801 bzero(gd, sizeof(*gd));
984263bc 1802
85100692 1803 gd->mi.gd_curthread = &thread0;
984263bc
MD
1804
1805 atdevbase = ISA_HOLE_START + KERNBASE;
1806
1807 metadata_missing = 0;
1808 if (bootinfo.bi_modulep) {
1809 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1810 preload_bootstrap_relocate(KERNBASE);
1811 } else {
1812 metadata_missing = 1;
1813 }
1814 if (bootinfo.bi_envp)
1815 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1816
c5cc06e3
MD
1817 /*
1818 * start with one cpu. Note: ncpus2_shift and ncpus2_mask are left
1819 * at 0.
1820 */
4e8e646b 1821 ncpus = 1;
c5cc06e3 1822 ncpus2 = 1;
984263bc
MD
1823 /* Init basic tunables, hz etc */
1824 init_param1();
1825
1826 /*
1827 * make gdt memory segments, the code segment goes up to end of the
1828 * page with etext in it, the data segment goes to the end of
1829 * the address space
1830 */
1831 /*
1832 * XXX text protection is temporarily (?) disabled. The limit was
1833 * i386_btop(round_page(etext)) - 1.
1834 */
1835 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1836 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1837
984263bc
MD
1838 gdt_segs[GPRIV_SEL].ssd_limit =
1839 atop(sizeof(struct privatespace) - 1);
8ad65e08 1840 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1841 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1842 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1843
85100692 1844 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1845
84b592ba
MD
1846 /*
1847 * Note: on both UP and SMP curthread must be set non-NULL
1848 * early in the boot sequence because the system assumes
1849 * that 'curthread' is never NULL.
1850 */
984263bc
MD
1851
1852 for (x = 0; x < NGDT; x++) {
1853#ifdef BDE_DEBUGGER
1854 /* avoid overwriting db entries with APM ones */
1855 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1856 continue;
1857#endif
1858 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1859 }
1860
1861 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1862 r_gdt.rd_base = (int) gdt;
1863 lgdt(&r_gdt);
1864
73e4f7b9
MD
1865 mi_gdinit(&gd->mi, 0);
1866 cpu_gdinit(gd, 0);
f470d0c8 1867 lwkt_init_thread(&thread0, proc0paddr, LWKT_THREAD_STACK, 0, &gd->mi);
73e4f7b9
MD
1868 lwkt_set_comm(&thread0, "thread0");
1869 proc0.p_addr = (void *)thread0.td_kstack;
1870 proc0.p_thread = &thread0;
98a7f915 1871 varsymset_init(&proc0.p_varsymset, NULL);
d9eea1a5 1872 thread0.td_flags |= TDF_RUNNING;
73e4f7b9
MD
1873 thread0.td_proc = &proc0;
1874 thread0.td_switch = cpu_heavy_switch; /* YYY eventually LWKT */
e43a034f 1875 safepri = TDPRI_MAX;
73e4f7b9 1876
984263bc
MD
1877 /* make ldt memory segments */
1878 /*
1879 * XXX - VM_MAXUSER_ADDRESS is an end address, not a max. And it
1880 * should be spelled ...MAX_USER...
1881 */
1882 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAXUSER_ADDRESS - 1);
1883 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAXUSER_ADDRESS - 1);
1884 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
1885 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1886
1887 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1888 lldt(_default_ldt);
17a9f566 1889 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
1890 /* spinlocks and the BGL */
1891 init_locks();
984263bc
MD
1892
1893 /* exceptions */
f7bc9806
MD
1894 for (x = 0; x < NIDT; x++) {
1895#ifdef DEBUG_INTERRUPTS
1896 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1897#else
1898 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1899#endif
1900 }
984263bc
MD
1901 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1902 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1903 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1904 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1905 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1906 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1907 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1908 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1909 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
1910 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1911 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1912 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1913 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1914 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1915 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 1916 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
1917 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1918 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1919 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1920 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1921 setidt(0x80, &IDTVEC(int0x80_syscall),
1922 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
a64ba182
MD
1923 setidt(0x81, &IDTVEC(int0x81_syscall),
1924 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
7062f5b4
EN
1925 setidt(0x82, &IDTVEC(int0x82_syscall),
1926 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
1927
1928 r_idt.rd_limit = sizeof(idt0) - 1;
1929 r_idt.rd_base = (int) idt;
1930 lidt(&r_idt);
1931
1932 /*
1933 * Initialize the console before we print anything out.
1934 */
1935 cninit();
1936
1937 if (metadata_missing)
1938 printf("WARNING: loader(8) metadata is missing!\n");
1939
984263bc
MD
1940#if NISA >0
1941 isa_defaultirq();
1942#endif
1943 rand_initialize();
1944
1945#ifdef DDB
1946 kdb_init();
1947 if (boothowto & RB_KDB)
1948 Debugger("Boot flags requested debugger");
1949#endif
1950
1951 finishidentcpu(); /* Final stage of CPU initialization */
1952 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1953 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1954 initializecpu(); /* Initialize CPU registers */
1955
b7c628e4
MD
1956 /*
1957 * make an initial tss so cpu can get interrupt stack on syscall!
1958 * The 16 bytes is to save room for a VM86 context.
1959 */
17a9f566
MD
1960 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
1961 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 1962 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
1963 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
1964 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 1965 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
1966 ltr(gsel_tss);
1967
1968 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
1969 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
1970 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
1971 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
1972 dblfault_tss.tss_cr3 = (int)IdlePTD;
1973 dblfault_tss.tss_eip = (int) dblfault_handler;
1974 dblfault_tss.tss_eflags = PSL_KERNEL;
1975 dblfault_tss.tss_ds = dblfault_tss.tss_es =
1976 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
1977 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
1978 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
1979 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
1980
1981 vm86_initialize();
1982 getmemsize(first);
1983 init_param2(physmem);
1984
1985 /* now running on new page tables, configured,and u/iom is accessible */
1986
1987 /* Map the message buffer. */
1988 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1989 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1990
1991 msgbufinit(msgbufp, MSGBUF_SIZE);
1992
1993 /* make a call gate to reenter kernel with */
1994 gdp = &ldt[LSYS5CALLS_SEL].gd;
1995
1996 x = (int) &IDTVEC(syscall);
1997 gdp->gd_looffset = x++;
1998 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
1999 gdp->gd_stkcpy = 1;
2000 gdp->gd_type = SDT_SYS386CGT;
2001 gdp->gd_dpl = SEL_UPL;
2002 gdp->gd_p = 1;
2003 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2004
2005 /* XXX does this work? */
2006 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2007 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2008
2009 /* transfer to user mode */
2010
2011 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2012 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2013
2014 /* setup proc 0's pcb */
b7c628e4
MD
2015 thread0.td_pcb->pcb_flags = 0;
2016 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2017 thread0.td_pcb->pcb_ext = 0;
984263bc
MD
2018 proc0.p_md.md_regs = &proc0_tf;
2019}
2020
8ad65e08 2021/*
17a9f566
MD
2022 * Initialize machine-dependant portions of the global data structure.
2023 * Note that the global data area and cpu0's idlestack in the private
2024 * data space were allocated in locore.
ef0fdad1
MD
2025 *
2026 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2027 *
2028 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2029 */
2030void
85100692 2031cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2032{
7d0bac62 2033 if (cpu)
a2a5ad0d 2034 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2035
f470d0c8
MD
2036 lwkt_init_thread(&gd->mi.gd_idlethread,
2037 gd->mi.gd_prvspace->idlestack,
2038 sizeof(gd->mi.gd_prvspace->idlestack), 0, &gd->mi);
a2a5ad0d
MD
2039 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2040 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2041 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2042 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2043}
2044
0cd275af
MD
2045int
2046is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2047{
2048 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2049 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2050 return (TRUE);
2051 }
2052 return (FALSE);
2053}
2054
12e4aaff
MD
2055struct globaldata *
2056globaldata_find(int cpu)
2057{
2058 KKASSERT(cpu >= 0 && cpu < ncpus);
2059 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2060}
2061
984263bc
MD
2062#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2063static void f00f_hack(void *unused);
2064SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
2065
2066static void
17a9f566
MD
2067f00f_hack(void *unused)
2068{
984263bc 2069 struct gate_descriptor *new_idt;
984263bc
MD
2070 vm_offset_t tmp;
2071
2072 if (!has_f00f_bug)
2073 return;
2074
2075 printf("Intel Pentium detected, installing workaround for F00F bug\n");
2076
2077 r_idt.rd_limit = sizeof(idt0) - 1;
2078
2079 tmp = kmem_alloc(kernel_map, PAGE_SIZE * 2);
2080 if (tmp == 0)
2081 panic("kmem_alloc returned 0");
2082 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2083 panic("kmem_alloc returned non-page-aligned memory");
2084 /* Put the first seven entries in the lower page */
2085 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2086 bcopy(idt, new_idt, sizeof(idt0));
2087 r_idt.rd_base = (int)new_idt;
2088 lidt(&r_idt);
2089 idt = new_idt;
2090 if (vm_map_protect(kernel_map, tmp, tmp + PAGE_SIZE,
2091 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2092 panic("vm_map_protect failed");
2093 return;
2094}
2095#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2096
2097int
2098ptrace_set_pc(p, addr)
2099 struct proc *p;
2100 unsigned long addr;
2101{
2102 p->p_md.md_regs->tf_eip = addr;
2103 return (0);
2104}
2105
2106int
2107ptrace_single_step(p)
2108 struct proc *p;
2109{
2110 p->p_md.md_regs->tf_eflags |= PSL_T;
2111 return (0);
2112}
2113
2114int ptrace_read_u_check(p, addr, len)
2115 struct proc *p;
2116 vm_offset_t addr;
2117 size_t len;
2118{
2119 vm_offset_t gap;
2120
2121 if ((vm_offset_t) (addr + len) < addr)
2122 return EPERM;
2123 if ((vm_offset_t) (addr + len) <= sizeof(struct user))
2124 return 0;
2125
2126 gap = (char *) p->p_md.md_regs - (char *) p->p_addr;
2127
2128 if ((vm_offset_t) addr < gap)
2129 return EPERM;
2130 if ((vm_offset_t) (addr + len) <=
2131 (vm_offset_t) (gap + sizeof(struct trapframe)))
2132 return 0;
2133 return EPERM;
2134}
2135
2136int ptrace_write_u(p, off, data)
2137 struct proc *p;
2138 vm_offset_t off;
2139 long data;
2140{
2141 struct trapframe frame_copy;
2142 vm_offset_t min;
2143 struct trapframe *tp;
2144
2145 /*
2146 * Privileged kernel state is scattered all over the user area.
2147 * Only allow write access to parts of regs and to fpregs.
2148 */
2149 min = (char *)p->p_md.md_regs - (char *)p->p_addr;
2150 if (off >= min && off <= min + sizeof(struct trapframe) - sizeof(int)) {
2151 tp = p->p_md.md_regs;
2152 frame_copy = *tp;
2153 *(int *)((char *)&frame_copy + (off - min)) = data;
2154 if (!EFL_SECURE(frame_copy.tf_eflags, tp->tf_eflags) ||
2155 !CS_SECURE(frame_copy.tf_cs))
2156 return (EINVAL);
2157 *(int*)((char *)p->p_addr + off) = data;
2158 return (0);
2159 }
b7c628e4
MD
2160
2161 /*
2162 * The PCB is at the end of the user area YYY
2163 */
2164 min = (char *)p->p_thread->td_pcb - (char *)p->p_addr;
2165 min += offsetof(struct pcb, pcb_save);
984263bc
MD
2166 if (off >= min && off <= min + sizeof(union savefpu) - sizeof(int)) {
2167 *(int*)((char *)p->p_addr + off) = data;
2168 return (0);
2169 }
2170 return (EFAULT);
2171}
2172
2173int
2174fill_regs(p, regs)
2175 struct proc *p;
2176 struct reg *regs;
2177{
2178 struct pcb *pcb;
2179 struct trapframe *tp;
2180
2181 tp = p->p_md.md_regs;
2182 regs->r_fs = tp->tf_fs;
2183 regs->r_es = tp->tf_es;
2184 regs->r_ds = tp->tf_ds;
2185 regs->r_edi = tp->tf_edi;
2186 regs->r_esi = tp->tf_esi;
2187 regs->r_ebp = tp->tf_ebp;
2188 regs->r_ebx = tp->tf_ebx;
2189 regs->r_edx = tp->tf_edx;
2190 regs->r_ecx = tp->tf_ecx;
2191 regs->r_eax = tp->tf_eax;
2192 regs->r_eip = tp->tf_eip;
2193 regs->r_cs = tp->tf_cs;
2194 regs->r_eflags = tp->tf_eflags;
2195 regs->r_esp = tp->tf_esp;
2196 regs->r_ss = tp->tf_ss;
b7c628e4 2197 pcb = p->p_thread->td_pcb;
984263bc
MD
2198 regs->r_gs = pcb->pcb_gs;
2199 return (0);
2200}
2201
2202int
2203set_regs(p, regs)
2204 struct proc *p;
2205 struct reg *regs;
2206{
2207 struct pcb *pcb;
2208 struct trapframe *tp;
2209
2210 tp = p->p_md.md_regs;
2211 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2212 !CS_SECURE(regs->r_cs))
2213 return (EINVAL);
2214 tp->tf_fs = regs->r_fs;
2215 tp->tf_es = regs->r_es;
2216 tp->tf_ds = regs->r_ds;
2217 tp->tf_edi = regs->r_edi;
2218 tp->tf_esi = regs->r_esi;
2219 tp->tf_ebp = regs->r_ebp;
2220 tp->tf_ebx = regs->r_ebx;
2221 tp->tf_edx = regs->r_edx;
2222 tp->tf_ecx = regs->r_ecx;
2223 tp->tf_eax = regs->r_eax;
2224 tp->tf_eip = regs->r_eip;
2225 tp->tf_cs = regs->r_cs;
2226 tp->tf_eflags = regs->r_eflags;
2227 tp->tf_esp = regs->r_esp;
2228 tp->tf_ss = regs->r_ss;
b7c628e4 2229 pcb = p->p_thread->td_pcb;
984263bc
MD
2230 pcb->pcb_gs = regs->r_gs;
2231 return (0);
2232}
2233
642a6e88 2234#ifndef CPU_DISABLE_SSE
984263bc
MD
2235static void
2236fill_fpregs_xmm(sv_xmm, sv_87)
2237 struct savexmm *sv_xmm;
2238 struct save87 *sv_87;
2239{
c9faf524
RG
2240 struct env87 *penv_87 = &sv_87->sv_env;
2241 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2242 int i;
2243
2244 /* FPU control/status */
2245 penv_87->en_cw = penv_xmm->en_cw;
2246 penv_87->en_sw = penv_xmm->en_sw;
2247 penv_87->en_tw = penv_xmm->en_tw;
2248 penv_87->en_fip = penv_xmm->en_fip;
2249 penv_87->en_fcs = penv_xmm->en_fcs;
2250 penv_87->en_opcode = penv_xmm->en_opcode;
2251 penv_87->en_foo = penv_xmm->en_foo;
2252 penv_87->en_fos = penv_xmm->en_fos;
2253
2254 /* FPU registers */
2255 for (i = 0; i < 8; ++i)
2256 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2257
2258 sv_87->sv_ex_sw = sv_xmm->sv_ex_sw;
2259}
2260
2261static void
2262set_fpregs_xmm(sv_87, sv_xmm)
2263 struct save87 *sv_87;
2264 struct savexmm *sv_xmm;
2265{
c9faf524
RG
2266 struct env87 *penv_87 = &sv_87->sv_env;
2267 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2268 int i;
2269
2270 /* FPU control/status */
2271 penv_xmm->en_cw = penv_87->en_cw;
2272 penv_xmm->en_sw = penv_87->en_sw;
2273 penv_xmm->en_tw = penv_87->en_tw;
2274 penv_xmm->en_fip = penv_87->en_fip;
2275 penv_xmm->en_fcs = penv_87->en_fcs;
2276 penv_xmm->en_opcode = penv_87->en_opcode;
2277 penv_xmm->en_foo = penv_87->en_foo;
2278 penv_xmm->en_fos = penv_87->en_fos;
2279
2280 /* FPU registers */
2281 for (i = 0; i < 8; ++i)
2282 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2283
2284 sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
2285}
642a6e88 2286#endif /* CPU_DISABLE_SSE */
984263bc
MD
2287
2288int
2289fill_fpregs(p, fpregs)
2290 struct proc *p;
2291 struct fpreg *fpregs;
2292{
642a6e88 2293#ifndef CPU_DISABLE_SSE
984263bc 2294 if (cpu_fxsr) {
b7c628e4 2295 fill_fpregs_xmm(&p->p_thread->td_pcb->pcb_save.sv_xmm,
984263bc
MD
2296 (struct save87 *)fpregs);
2297 return (0);
2298 }
642a6e88 2299#endif /* CPU_DISABLE_SSE */
b7c628e4 2300 bcopy(&p->p_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2301 return (0);
2302}
2303
2304int
2305set_fpregs(p, fpregs)
2306 struct proc *p;
2307 struct fpreg *fpregs;
2308{
642a6e88 2309#ifndef CPU_DISABLE_SSE
984263bc
MD
2310 if (cpu_fxsr) {
2311 set_fpregs_xmm((struct save87 *)fpregs,
b7c628e4 2312 &p->p_thread->td_pcb->pcb_save.sv_xmm);
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MD
2313 return (0);
2314 }
642a6e88 2315#endif /* CPU_DISABLE_SSE */
b7c628e4 2316 bcopy(fpregs, &p->p_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2317 return (0);
2318}
2319
2320int
2321fill_dbregs(p, dbregs)
2322 struct proc *p;
2323 struct dbreg *dbregs;
2324{
2325 struct pcb *pcb;
2326
2327 if (p == NULL) {
2328 dbregs->dr0 = rdr0();
2329 dbregs->dr1 = rdr1();
2330 dbregs->dr2 = rdr2();
2331 dbregs->dr3 = rdr3();
2332 dbregs->dr4 = rdr4();
2333 dbregs->dr5 = rdr5();
2334 dbregs->dr6 = rdr6();
2335 dbregs->dr7 = rdr7();
2336 }
2337 else {
b7c628e4 2338 pcb = p->p_thread->td_pcb;
984263bc
MD
2339 dbregs->dr0 = pcb->pcb_dr0;
2340 dbregs->dr1 = pcb->pcb_dr1;
2341 dbregs->dr2 = pcb->pcb_dr2;
2342 dbregs->dr3 = pcb->pcb_dr3;
2343 dbregs->dr4 = 0;
2344 dbregs->dr5 = 0;
2345 dbregs->dr6 = pcb->pcb_dr6;
2346 dbregs->dr7 = pcb->pcb_dr7;
2347 }
2348 return (0);
2349}
2350
2351int
2352set_dbregs(p, dbregs)
2353 struct proc *p;
2354 struct dbreg *dbregs;
2355{
2356 struct pcb *pcb;
2357 int i;
2358 u_int32_t mask1, mask2;
2359
2360 if (p == NULL) {
2361 load_dr0(dbregs->dr0);
2362 load_dr1(dbregs->dr1);
2363 load_dr2(dbregs->dr2);
2364 load_dr3(dbregs->dr3);
2365 load_dr4(dbregs->dr4);
2366 load_dr5(dbregs->dr5);
2367 load_dr6(dbregs->dr6);
2368 load_dr7(dbregs->dr7);
2369 }
2370 else {
2371 /*
2372 * Don't let an illegal value for dr7 get set. Specifically,
2373 * check for undefined settings. Setting these bit patterns
2374 * result in undefined behaviour and can lead to an unexpected
2375 * TRCTRAP.
2376 */
2377 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2378 i++, mask1 <<= 2, mask2 <<= 2)
2379 if ((dbregs->dr7 & mask1) == mask2)
2380 return (EINVAL);
2381
b7c628e4 2382 pcb = p->p_thread->td_pcb;
984263bc
MD
2383
2384 /*
2385 * Don't let a process set a breakpoint that is not within the
2386 * process's address space. If a process could do this, it
2387 * could halt the system by setting a breakpoint in the kernel
2388 * (if ddb was enabled). Thus, we need to check to make sure
2389 * that no breakpoints are being enabled for addresses outside
2390 * process's address space, unless, perhaps, we were called by
2391 * uid 0.
2392 *
2393 * XXX - what about when the watched area of the user's
2394 * address space is written into from within the kernel
2395 * ... wouldn't that still cause a breakpoint to be generated
2396 * from within kernel mode?
2397 */
2398
dadab5e9 2399 if (suser_cred(p->p_ucred, 0) != 0) {
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MD
2400 if (dbregs->dr7 & 0x3) {
2401 /* dr0 is enabled */
2402 if (dbregs->dr0 >= VM_MAXUSER_ADDRESS)
2403 return (EINVAL);
2404 }
2405
2406 if (dbregs->dr7 & (0x3<<2)) {
2407 /* dr1 is enabled */
2408 if (dbregs->dr1 >= VM_MAXUSER_ADDRESS)
2409 return (EINVAL);
2410 }
2411
2412 if (dbregs->dr7 & (0x3<<4)) {
2413 /* dr2 is enabled */
2414 if (dbregs->dr2 >= VM_MAXUSER_ADDRESS)
2415 return (EINVAL);
2416 }
2417
2418 if (dbregs->dr7 & (0x3<<6)) {
2419 /* dr3 is enabled */
2420 if (dbregs->dr3 >= VM_MAXUSER_ADDRESS)
2421 return (EINVAL);
2422 }
2423 }
2424
2425 pcb->pcb_dr0 = dbregs->dr0;
2426 pcb->pcb_dr1 = dbregs->dr1;
2427 pcb->pcb_dr2 = dbregs->dr2;
2428 pcb->pcb_dr3 = dbregs->dr3;
2429 pcb->pcb_dr6 = dbregs->dr6;
2430 pcb->pcb_dr7 = dbregs->dr7;
2431
2432 pcb->pcb_flags |= PCB_DBREGS;
2433 }
2434
2435 return (0);
2436}
2437
2438/*
2439 * Return > 0 if a hardware breakpoint has been hit, and the
2440 * breakpoint was in user space. Return 0, otherwise.
2441 */
2442int
2443user_dbreg_trap(void)
2444{
2445 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2446 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2447 int nbp; /* number of breakpoints that triggered */
2448 caddr_t addr[4]; /* breakpoint addresses */
2449 int i;
2450
2451 dr7 = rdr7();
2452 if ((dr7 & 0x000000ff) == 0) {
2453 /*
2454 * all GE and LE bits in the dr7 register are zero,
2455 * thus the trap couldn't have been caused by the
2456 * hardware debug registers
2457 */
2458 return 0;
2459 }
2460
2461 nbp = 0;
2462 dr6 = rdr6();
2463 bp = dr6 & 0x0000000f;
2464
2465 if (!bp) {
2466 /*
2467 * None of the breakpoint bits are set meaning this
2468 * trap was not caused by any of the debug registers
2469 */
2470 return 0;
2471 }
2472
2473 /*
2474 * at least one of the breakpoints were hit, check to see
2475 * which ones and if any of them are user space addresses
2476 */
2477
2478 if (bp & 0x01) {
2479 addr[nbp++] = (caddr_t)rdr0();
2480 }
2481 if (bp & 0x02) {
2482 addr[nbp++] = (caddr_t)rdr1();
2483 }
2484 if (bp & 0x04) {
2485 addr[nbp++] = (caddr_t)rdr2();
2486 }
2487 if (bp & 0x08) {
2488 addr[nbp++] = (caddr_t)rdr3();
2489 }
2490
2491 for (i=0; i<nbp; i++) {
2492 if (addr[i] <
2493 (caddr_t)VM_MAXUSER_ADDRESS) {
2494 /*
2495 * addr[i] is in user space
2496 */
2497 return nbp;
2498 }
2499 }
2500
2501 /*
2502 * None of the breakpoints are in user space.
2503 */
2504 return 0;
2505}
2506
2507
2508#ifndef DDB
2509void
2510Debugger(const char *msg)
2511{
2512 printf("Debugger(\"%s\") called.\n", msg);
2513}
2514#endif /* no DDB */
2515
f9d8cd12
MD
2516#include <machine/apicvar.h>
2517
2518/*
2519 * Provide stub functions so that the MADT APIC enumerator in the acpi
2520 * kernel module will link against a kernel without 'option APIC_IO'.
2521 *
2522 * XXX - This is a gross hack.
2523 */
2524void
2525apic_register_enumerator(struct apic_enumerator *enumerator)
2526{
2527}
2528
2529void *
2530ioapic_create(uintptr_t addr, int32_t id, int intbase)
2531{
2532 return (NULL);
2533}
2534
2535int
2536ioapic_disable_pin(void *cookie, u_int pin)
2537{
2538 return (ENXIO);
2539}
2540
2541void
2542ioapic_enable_mixed_mode(void)
2543{
2544}
2545
2546int
2547ioapic_get_vector(void *cookie, u_int pin)
2548{
2549 return (-1);
2550}
2551
2552void
2553ioapic_register(void *cookie)
2554{
2555}
2556
2557int
2558ioapic_remap_vector(void *cookie, u_int pin, int vector)
2559{
2560 return (ENXIO);
2561}
2562
2563int
2564ioapic_set_extint(void *cookie, u_int pin)
2565{
2566 return (ENXIO);
2567}
2568
2569int
2570ioapic_set_nmi(void *cookie, u_int pin)
2571{
2572 return (ENXIO);
2573}
2574
2575int
2576ioapic_set_polarity(void *cookie, u_int pin, char activehi)
2577{
2578 return (ENXIO);
2579}
2580
2581int
2582ioapic_set_triggermode(void *cookie, u_int pin, char edgetrigger)
2583{
2584 return (ENXIO);
2585}
2586
2587void
2588lapic_create(u_int apic_id, int boot_cpu)
2589{
2590}
2591
2592void
2593lapic_init(uintptr_t addr)
2594{
2595}
2596
2597int
2598lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
2599{
2600 return (ENXIO);
2601}
2602
2603int
2604lapic_set_lvt_polarity(u_int apic_id, u_int lvt, u_char activehi)
2605{
2606 return (ENXIO);
2607}
2608
2609int
2610lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, u_char edgetrigger)
2611{
2612 return (ENXIO);
2613}
f9d8cd12 2614
984263bc
MD
2615#include <sys/disklabel.h>
2616
2617/*
2618 * Determine the size of the transfer, and make sure it is
2619 * within the boundaries of the partition. Adjust transfer
2620 * if needed, and signal errors or early completion.
2621 */
2622int
2623bounds_check_with_label(struct buf *bp, struct disklabel *lp, int wlabel)
2624{
2625 struct partition *p = lp->d_partitions + dkpart(bp->b_dev);
2626 int labelsect = lp->d_partitions[0].p_offset;
2627 int maxsz = p->p_size,
2628 sz = (bp->b_bcount + DEV_BSIZE - 1) >> DEV_BSHIFT;
2629
2630 /* overwriting disk label ? */
2631 /* XXX should also protect bootstrap in first 8K */
2632 if (bp->b_blkno + p->p_offset <= LABELSECTOR + labelsect &&
2633#if LABELSECTOR != 0
2634 bp->b_blkno + p->p_offset + sz > LABELSECTOR + labelsect &&
2635#endif
2636 (bp->b_flags & B_READ) == 0 && wlabel == 0) {
2637 bp->b_error = EROFS;
2638 goto bad;
2639 }
2640
2641#if defined(DOSBBSECTOR) && defined(notyet)
2642 /* overwriting master boot record? */
2643 if (bp->b_blkno + p->p_offset <= DOSBBSECTOR &&
2644 (bp->b_flags & B_READ) == 0 && wlabel == 0) {
2645 bp->b_error = EROFS;
2646 goto bad;
2647 }
2648#endif
2649
2650 /* beyond partition? */
2651 if (bp->b_blkno < 0 || bp->b_blkno + sz > maxsz) {
2652 /* if exactly at end of disk, return an EOF */
2653 if (bp->b_blkno == maxsz) {
2654 bp->b_resid = bp->b_bcount;
2655 return(0);
2656 }
2657 /* or truncate if part of it fits */
2658 sz = maxsz - bp->b_blkno;
2659 if (sz <= 0) {
2660 bp->b_error = EINVAL;
2661 goto bad;
2662 }
2663 bp->b_bcount = sz << DEV_BSHIFT;
2664 }
2665
2666 bp->b_pblkno = bp->b_blkno + p->p_offset;
2667 return(1);
2668
2669bad:
2670 bp->b_flags |= B_ERROR;
2671 return(-1);
2672}
2673
2674#ifdef DDB
2675
2676/*
2677 * Provide inb() and outb() as functions. They are normally only
2678 * available as macros calling inlined functions, thus cannot be
2679 * called inside DDB.
2680 *
2681 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2682 */
2683
2684#undef inb
2685#undef outb
2686
2687/* silence compiler warnings */
2688u_char inb(u_int);
2689void outb(u_int, u_char);
2690
2691u_char
2692inb(u_int port)
2693{
2694 u_char data;
2695 /*
2696 * We use %%dx and not %1 here because i/o is done at %dx and not at
2697 * %edx, while gcc generates inferior code (movw instead of movl)
2698 * if we tell it to load (u_short) port.
2699 */
2700 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2701 return (data);
2702}
2703
2704void
2705outb(u_int port, u_char data)
2706{
2707 u_char al;
2708 /*
2709 * Use an unnecessary assignment to help gcc's register allocator.
2710 * This make a large difference for gcc-1.40 and a tiny difference
2711 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2712 * best results. gcc-2.6.0 can't handle this.
2713 */
2714 al = data;
2715 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2716}
2717
2718#endif /* DDB */
8a8d5d85
MD
2719
2720
2721
2722#include "opt_cpu.h"
8a8d5d85
MD
2723
2724
2725/*
2726 * initialize all the SMP locks
2727 */
2728
2729/* critical region around IO APIC, apic_imen */
2730struct spinlock imen_spinlock;
2731
2732/* Make FAST_INTR() routines sequential */
2733struct spinlock fast_intr_spinlock;
2734
2735/* critical region for old style disable_intr/enable_intr */
2736struct spinlock mpintr_spinlock;
2737
2738/* critical region around INTR() routines */
2739struct spinlock intr_spinlock;
2740
2741/* lock region used by kernel profiling */
2742struct spinlock mcount_spinlock;
2743
2744/* locks com (tty) data/hardware accesses: a FASTINTR() */
2745struct spinlock com_spinlock;
2746
2747/* locks kernel printfs */
2748struct spinlock cons_spinlock;
2749
2750/* lock regions around the clock hardware */
2751struct spinlock clock_spinlock;
2752
2753/* lock around the MP rendezvous */
2754struct spinlock smp_rv_spinlock;
2755
2756static void
2757init_locks(void)
2758{
2759 /*
2760 * mp_lock = 0; BSP already owns the MP lock
2761 */
2762 /*
2763 * Get the initial mp_lock with a count of 1 for the BSP.
2764 * This uses a LOGICAL cpu ID, ie BSP == 0.
2765 */
2766#ifdef SMP
2767 cpu_get_initial_mplock();
2768#endif
41a01a4d 2769 /* DEPRECATED */
8a8d5d85
MD
2770 spin_lock_init(&mcount_spinlock);
2771 spin_lock_init(&fast_intr_spinlock);
2772 spin_lock_init(&intr_spinlock);
2773 spin_lock_init(&mpintr_spinlock);
2774 spin_lock_init(&imen_spinlock);
2775 spin_lock_init(&smp_rv_spinlock);
2776 spin_lock_init(&com_spinlock);
2777 spin_lock_init(&clock_spinlock);
2778 spin_lock_init(&cons_spinlock);
41a01a4d
MD
2779
2780 /* our token pool needs to work early */
2781 lwkt_token_pool_init();
8a8d5d85
MD
2782}
2783