ioapic_abi: More consistent function name w/ legacy interrupt
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
CommitLineData
c8fe38ae
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1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
47#include <sys/interrupt.h>
48#include <sys/bus.h>
981239a7 49#include <sys/rman.h>
95874ffd 50#include <sys/thread2.h>
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51
52#include <machine/smp.h>
53#include <machine/segments.h>
54#include <machine/md_var.h>
57a9c56b 55#include <machine/intr_machdep.h>
c8fe38ae 56#include <machine/globaldata.h>
4234567c 57#include <machine/msi_var.h>
c8fe38ae 58
104463f2 59#include <machine_base/isa/isa_intr.h>
61452645 60#include <machine_base/icu/icu.h>
6b809ec7 61#include <machine_base/icu/icu_var.h>
61452645 62#include <machine_base/apic/ioapic.h>
929c940f 63#include <machine_base/apic/ioapic_abi.h>
77f86d14 64#include <machine_base/apic/ioapic_ipl.h>
9a4bd8f3 65#include <machine_base/apic/apicreg.h>
c8fe38ae 66
95874ffd
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67#include <dev/acpica5/acpi_sci_var.h>
68
451af8d9
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69#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
70
c8fe38ae 71extern inthand_t
9e0e3f85
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72 IDTVEC(ioapic_intr0),
73 IDTVEC(ioapic_intr1),
74 IDTVEC(ioapic_intr2),
75 IDTVEC(ioapic_intr3),
76 IDTVEC(ioapic_intr4),
77 IDTVEC(ioapic_intr5),
78 IDTVEC(ioapic_intr6),
79 IDTVEC(ioapic_intr7),
80 IDTVEC(ioapic_intr8),
81 IDTVEC(ioapic_intr9),
82 IDTVEC(ioapic_intr10),
83 IDTVEC(ioapic_intr11),
84 IDTVEC(ioapic_intr12),
85 IDTVEC(ioapic_intr13),
86 IDTVEC(ioapic_intr14),
87 IDTVEC(ioapic_intr15),
88 IDTVEC(ioapic_intr16),
89 IDTVEC(ioapic_intr17),
90 IDTVEC(ioapic_intr18),
91 IDTVEC(ioapic_intr19),
92 IDTVEC(ioapic_intr20),
93 IDTVEC(ioapic_intr21),
94 IDTVEC(ioapic_intr22),
95 IDTVEC(ioapic_intr23),
96 IDTVEC(ioapic_intr24),
97 IDTVEC(ioapic_intr25),
98 IDTVEC(ioapic_intr26),
99 IDTVEC(ioapic_intr27),
100 IDTVEC(ioapic_intr28),
101 IDTVEC(ioapic_intr29),
102 IDTVEC(ioapic_intr30),
103 IDTVEC(ioapic_intr31),
104 IDTVEC(ioapic_intr32),
105 IDTVEC(ioapic_intr33),
106 IDTVEC(ioapic_intr34),
107 IDTVEC(ioapic_intr35),
108 IDTVEC(ioapic_intr36),
109 IDTVEC(ioapic_intr37),
110 IDTVEC(ioapic_intr38),
111 IDTVEC(ioapic_intr39),
112 IDTVEC(ioapic_intr40),
113 IDTVEC(ioapic_intr41),
114 IDTVEC(ioapic_intr42),
115 IDTVEC(ioapic_intr43),
116 IDTVEC(ioapic_intr44),
117 IDTVEC(ioapic_intr45),
118 IDTVEC(ioapic_intr46),
119 IDTVEC(ioapic_intr47),
120 IDTVEC(ioapic_intr48),
121 IDTVEC(ioapic_intr49),
122 IDTVEC(ioapic_intr50),
123 IDTVEC(ioapic_intr51),
124 IDTVEC(ioapic_intr52),
125 IDTVEC(ioapic_intr53),
126 IDTVEC(ioapic_intr54),
127 IDTVEC(ioapic_intr55),
128 IDTVEC(ioapic_intr56),
129 IDTVEC(ioapic_intr57),
130 IDTVEC(ioapic_intr58),
131 IDTVEC(ioapic_intr59),
132 IDTVEC(ioapic_intr60),
133 IDTVEC(ioapic_intr61),
134 IDTVEC(ioapic_intr62),
135 IDTVEC(ioapic_intr63),
136 IDTVEC(ioapic_intr64),
137 IDTVEC(ioapic_intr65),
138 IDTVEC(ioapic_intr66),
139 IDTVEC(ioapic_intr67),
140 IDTVEC(ioapic_intr68),
141 IDTVEC(ioapic_intr69),
142 IDTVEC(ioapic_intr70),
143 IDTVEC(ioapic_intr71),
144 IDTVEC(ioapic_intr72),
145 IDTVEC(ioapic_intr73),
146 IDTVEC(ioapic_intr74),
147 IDTVEC(ioapic_intr75),
148 IDTVEC(ioapic_intr76),
149 IDTVEC(ioapic_intr77),
150 IDTVEC(ioapic_intr78),
151 IDTVEC(ioapic_intr79),
152 IDTVEC(ioapic_intr80),
153 IDTVEC(ioapic_intr81),
154 IDTVEC(ioapic_intr82),
155 IDTVEC(ioapic_intr83),
156 IDTVEC(ioapic_intr84),
157 IDTVEC(ioapic_intr85),
158 IDTVEC(ioapic_intr86),
159 IDTVEC(ioapic_intr87),
160 IDTVEC(ioapic_intr88),
161 IDTVEC(ioapic_intr89),
162 IDTVEC(ioapic_intr90),
163 IDTVEC(ioapic_intr91),
164 IDTVEC(ioapic_intr92),
165 IDTVEC(ioapic_intr93),
166 IDTVEC(ioapic_intr94),
167 IDTVEC(ioapic_intr95),
168 IDTVEC(ioapic_intr96),
169 IDTVEC(ioapic_intr97),
170 IDTVEC(ioapic_intr98),
171 IDTVEC(ioapic_intr99),
172 IDTVEC(ioapic_intr100),
173 IDTVEC(ioapic_intr101),
174 IDTVEC(ioapic_intr102),
175 IDTVEC(ioapic_intr103),
176 IDTVEC(ioapic_intr104),
177 IDTVEC(ioapic_intr105),
178 IDTVEC(ioapic_intr106),
179 IDTVEC(ioapic_intr107),
180 IDTVEC(ioapic_intr108),
181 IDTVEC(ioapic_intr109),
182 IDTVEC(ioapic_intr110),
183 IDTVEC(ioapic_intr111),
184 IDTVEC(ioapic_intr112),
185 IDTVEC(ioapic_intr113),
186 IDTVEC(ioapic_intr114),
187 IDTVEC(ioapic_intr115),
188 IDTVEC(ioapic_intr116),
189 IDTVEC(ioapic_intr117),
190 IDTVEC(ioapic_intr118),
191 IDTVEC(ioapic_intr119),
192 IDTVEC(ioapic_intr120),
193 IDTVEC(ioapic_intr121),
194 IDTVEC(ioapic_intr122),
195 IDTVEC(ioapic_intr123),
196 IDTVEC(ioapic_intr124),
197 IDTVEC(ioapic_intr125),
198 IDTVEC(ioapic_intr126),
199 IDTVEC(ioapic_intr127),
200 IDTVEC(ioapic_intr128),
201 IDTVEC(ioapic_intr129),
202 IDTVEC(ioapic_intr130),
203 IDTVEC(ioapic_intr131),
204 IDTVEC(ioapic_intr132),
205 IDTVEC(ioapic_intr133),
206 IDTVEC(ioapic_intr134),
207 IDTVEC(ioapic_intr135),
208 IDTVEC(ioapic_intr136),
209 IDTVEC(ioapic_intr137),
210 IDTVEC(ioapic_intr138),
211 IDTVEC(ioapic_intr139),
212 IDTVEC(ioapic_intr140),
213 IDTVEC(ioapic_intr141),
214 IDTVEC(ioapic_intr142),
215 IDTVEC(ioapic_intr143),
216 IDTVEC(ioapic_intr144),
217 IDTVEC(ioapic_intr145),
218 IDTVEC(ioapic_intr146),
219 IDTVEC(ioapic_intr147),
220 IDTVEC(ioapic_intr148),
221 IDTVEC(ioapic_intr149),
222 IDTVEC(ioapic_intr150),
223 IDTVEC(ioapic_intr151),
224 IDTVEC(ioapic_intr152),
225 IDTVEC(ioapic_intr153),
226 IDTVEC(ioapic_intr154),
227 IDTVEC(ioapic_intr155),
228 IDTVEC(ioapic_intr156),
229 IDTVEC(ioapic_intr157),
230 IDTVEC(ioapic_intr158),
231 IDTVEC(ioapic_intr159),
232 IDTVEC(ioapic_intr160),
233 IDTVEC(ioapic_intr161),
234 IDTVEC(ioapic_intr162),
235 IDTVEC(ioapic_intr163),
236 IDTVEC(ioapic_intr164),
237 IDTVEC(ioapic_intr165),
238 IDTVEC(ioapic_intr166),
239 IDTVEC(ioapic_intr167),
240 IDTVEC(ioapic_intr168),
241 IDTVEC(ioapic_intr169),
242 IDTVEC(ioapic_intr170),
243 IDTVEC(ioapic_intr171),
244 IDTVEC(ioapic_intr172),
245 IDTVEC(ioapic_intr173),
246 IDTVEC(ioapic_intr174),
247 IDTVEC(ioapic_intr175),
248 IDTVEC(ioapic_intr176),
249 IDTVEC(ioapic_intr177),
250 IDTVEC(ioapic_intr178),
251 IDTVEC(ioapic_intr179),
252 IDTVEC(ioapic_intr180),
253 IDTVEC(ioapic_intr181),
254 IDTVEC(ioapic_intr182),
255 IDTVEC(ioapic_intr183),
256 IDTVEC(ioapic_intr184),
257 IDTVEC(ioapic_intr185),
258 IDTVEC(ioapic_intr186),
259 IDTVEC(ioapic_intr187),
260 IDTVEC(ioapic_intr188),
261 IDTVEC(ioapic_intr189),
262 IDTVEC(ioapic_intr190),
263 IDTVEC(ioapic_intr191);
264
265static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
266 &IDTVEC(ioapic_intr0),
267 &IDTVEC(ioapic_intr1),
268 &IDTVEC(ioapic_intr2),
269 &IDTVEC(ioapic_intr3),
270 &IDTVEC(ioapic_intr4),
271 &IDTVEC(ioapic_intr5),
272 &IDTVEC(ioapic_intr6),
273 &IDTVEC(ioapic_intr7),
274 &IDTVEC(ioapic_intr8),
275 &IDTVEC(ioapic_intr9),
276 &IDTVEC(ioapic_intr10),
277 &IDTVEC(ioapic_intr11),
278 &IDTVEC(ioapic_intr12),
279 &IDTVEC(ioapic_intr13),
280 &IDTVEC(ioapic_intr14),
281 &IDTVEC(ioapic_intr15),
282 &IDTVEC(ioapic_intr16),
283 &IDTVEC(ioapic_intr17),
284 &IDTVEC(ioapic_intr18),
285 &IDTVEC(ioapic_intr19),
286 &IDTVEC(ioapic_intr20),
287 &IDTVEC(ioapic_intr21),
288 &IDTVEC(ioapic_intr22),
289 &IDTVEC(ioapic_intr23),
290 &IDTVEC(ioapic_intr24),
291 &IDTVEC(ioapic_intr25),
292 &IDTVEC(ioapic_intr26),
293 &IDTVEC(ioapic_intr27),
294 &IDTVEC(ioapic_intr28),
295 &IDTVEC(ioapic_intr29),
296 &IDTVEC(ioapic_intr30),
297 &IDTVEC(ioapic_intr31),
298 &IDTVEC(ioapic_intr32),
299 &IDTVEC(ioapic_intr33),
300 &IDTVEC(ioapic_intr34),
301 &IDTVEC(ioapic_intr35),
302 &IDTVEC(ioapic_intr36),
303 &IDTVEC(ioapic_intr37),
304 &IDTVEC(ioapic_intr38),
305 &IDTVEC(ioapic_intr39),
306 &IDTVEC(ioapic_intr40),
307 &IDTVEC(ioapic_intr41),
308 &IDTVEC(ioapic_intr42),
309 &IDTVEC(ioapic_intr43),
310 &IDTVEC(ioapic_intr44),
311 &IDTVEC(ioapic_intr45),
312 &IDTVEC(ioapic_intr46),
313 &IDTVEC(ioapic_intr47),
314 &IDTVEC(ioapic_intr48),
315 &IDTVEC(ioapic_intr49),
316 &IDTVEC(ioapic_intr50),
317 &IDTVEC(ioapic_intr51),
318 &IDTVEC(ioapic_intr52),
319 &IDTVEC(ioapic_intr53),
320 &IDTVEC(ioapic_intr54),
321 &IDTVEC(ioapic_intr55),
322 &IDTVEC(ioapic_intr56),
323 &IDTVEC(ioapic_intr57),
324 &IDTVEC(ioapic_intr58),
325 &IDTVEC(ioapic_intr59),
326 &IDTVEC(ioapic_intr60),
327 &IDTVEC(ioapic_intr61),
328 &IDTVEC(ioapic_intr62),
329 &IDTVEC(ioapic_intr63),
330 &IDTVEC(ioapic_intr64),
331 &IDTVEC(ioapic_intr65),
332 &IDTVEC(ioapic_intr66),
333 &IDTVEC(ioapic_intr67),
334 &IDTVEC(ioapic_intr68),
335 &IDTVEC(ioapic_intr69),
336 &IDTVEC(ioapic_intr70),
337 &IDTVEC(ioapic_intr71),
338 &IDTVEC(ioapic_intr72),
339 &IDTVEC(ioapic_intr73),
340 &IDTVEC(ioapic_intr74),
341 &IDTVEC(ioapic_intr75),
342 &IDTVEC(ioapic_intr76),
343 &IDTVEC(ioapic_intr77),
344 &IDTVEC(ioapic_intr78),
345 &IDTVEC(ioapic_intr79),
346 &IDTVEC(ioapic_intr80),
347 &IDTVEC(ioapic_intr81),
348 &IDTVEC(ioapic_intr82),
349 &IDTVEC(ioapic_intr83),
350 &IDTVEC(ioapic_intr84),
351 &IDTVEC(ioapic_intr85),
352 &IDTVEC(ioapic_intr86),
353 &IDTVEC(ioapic_intr87),
354 &IDTVEC(ioapic_intr88),
355 &IDTVEC(ioapic_intr89),
356 &IDTVEC(ioapic_intr90),
357 &IDTVEC(ioapic_intr91),
358 &IDTVEC(ioapic_intr92),
359 &IDTVEC(ioapic_intr93),
360 &IDTVEC(ioapic_intr94),
361 &IDTVEC(ioapic_intr95),
362 &IDTVEC(ioapic_intr96),
363 &IDTVEC(ioapic_intr97),
364 &IDTVEC(ioapic_intr98),
365 &IDTVEC(ioapic_intr99),
366 &IDTVEC(ioapic_intr100),
367 &IDTVEC(ioapic_intr101),
368 &IDTVEC(ioapic_intr102),
369 &IDTVEC(ioapic_intr103),
370 &IDTVEC(ioapic_intr104),
371 &IDTVEC(ioapic_intr105),
372 &IDTVEC(ioapic_intr106),
373 &IDTVEC(ioapic_intr107),
374 &IDTVEC(ioapic_intr108),
375 &IDTVEC(ioapic_intr109),
376 &IDTVEC(ioapic_intr110),
377 &IDTVEC(ioapic_intr111),
378 &IDTVEC(ioapic_intr112),
379 &IDTVEC(ioapic_intr113),
380 &IDTVEC(ioapic_intr114),
381 &IDTVEC(ioapic_intr115),
382 &IDTVEC(ioapic_intr116),
383 &IDTVEC(ioapic_intr117),
384 &IDTVEC(ioapic_intr118),
385 &IDTVEC(ioapic_intr119),
386 &IDTVEC(ioapic_intr120),
387 &IDTVEC(ioapic_intr121),
388 &IDTVEC(ioapic_intr122),
389 &IDTVEC(ioapic_intr123),
390 &IDTVEC(ioapic_intr124),
391 &IDTVEC(ioapic_intr125),
392 &IDTVEC(ioapic_intr126),
393 &IDTVEC(ioapic_intr127),
394 &IDTVEC(ioapic_intr128),
395 &IDTVEC(ioapic_intr129),
396 &IDTVEC(ioapic_intr130),
397 &IDTVEC(ioapic_intr131),
398 &IDTVEC(ioapic_intr132),
399 &IDTVEC(ioapic_intr133),
400 &IDTVEC(ioapic_intr134),
401 &IDTVEC(ioapic_intr135),
402 &IDTVEC(ioapic_intr136),
403 &IDTVEC(ioapic_intr137),
404 &IDTVEC(ioapic_intr138),
405 &IDTVEC(ioapic_intr139),
406 &IDTVEC(ioapic_intr140),
407 &IDTVEC(ioapic_intr141),
408 &IDTVEC(ioapic_intr142),
409 &IDTVEC(ioapic_intr143),
410 &IDTVEC(ioapic_intr144),
411 &IDTVEC(ioapic_intr145),
412 &IDTVEC(ioapic_intr146),
413 &IDTVEC(ioapic_intr147),
414 &IDTVEC(ioapic_intr148),
415 &IDTVEC(ioapic_intr149),
416 &IDTVEC(ioapic_intr150),
417 &IDTVEC(ioapic_intr151),
418 &IDTVEC(ioapic_intr152),
419 &IDTVEC(ioapic_intr153),
420 &IDTVEC(ioapic_intr154),
421 &IDTVEC(ioapic_intr155),
422 &IDTVEC(ioapic_intr156),
423 &IDTVEC(ioapic_intr157),
424 &IDTVEC(ioapic_intr158),
425 &IDTVEC(ioapic_intr159),
426 &IDTVEC(ioapic_intr160),
427 &IDTVEC(ioapic_intr161),
428 &IDTVEC(ioapic_intr162),
429 &IDTVEC(ioapic_intr163),
430 &IDTVEC(ioapic_intr164),
431 &IDTVEC(ioapic_intr165),
432 &IDTVEC(ioapic_intr166),
433 &IDTVEC(ioapic_intr167),
434 &IDTVEC(ioapic_intr168),
435 &IDTVEC(ioapic_intr169),
436 &IDTVEC(ioapic_intr170),
437 &IDTVEC(ioapic_intr171),
438 &IDTVEC(ioapic_intr172),
439 &IDTVEC(ioapic_intr173),
440 &IDTVEC(ioapic_intr174),
441 &IDTVEC(ioapic_intr175),
442 &IDTVEC(ioapic_intr176),
443 &IDTVEC(ioapic_intr177),
444 &IDTVEC(ioapic_intr178),
445 &IDTVEC(ioapic_intr179),
446 &IDTVEC(ioapic_intr180),
447 &IDTVEC(ioapic_intr181),
448 &IDTVEC(ioapic_intr182),
449 &IDTVEC(ioapic_intr183),
450 &IDTVEC(ioapic_intr184),
451 &IDTVEC(ioapic_intr185),
452 &IDTVEC(ioapic_intr186),
453 &IDTVEC(ioapic_intr187),
454 &IDTVEC(ioapic_intr188),
455 &IDTVEC(ioapic_intr189),
456 &IDTVEC(ioapic_intr190),
457 &IDTVEC(ioapic_intr191)
c571da4a 458};
c8fe38ae 459
474ba684
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460#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
461
a3dd9120
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462static struct ioapic_irqmap {
463 int im_type; /* IOAPIC_IMT_ */
464 enum intr_trigger im_trig;
f6915355 465 enum intr_polarity im_pola;
a3dd9120 466 int im_gsi;
4234567c 467 int im_msi_base;
d1ae7328 468 uint32_t im_flags; /* IOAPIC_IMF_ */
6f072945 469} ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
a3dd9120 470
4234567c
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471static struct lwkt_token ioapic_irqmap_tok =
472 LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token);
473
a3dd9120
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474#define IOAPIC_IMT_UNUSED 0
475#define IOAPIC_IMT_RESERVED 1
f9593a5d 476#define IOAPIC_IMT_LEGACY 2
474ba684 477#define IOAPIC_IMT_SYSCALL 3
4234567c 478#define IOAPIC_IMT_MSI 4
a3dd9120 479
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480#define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \
481 (map)->im_type != IOAPIC_IMT_SYSCALL)
482
d1ae7328
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483#define IOAPIC_IMF_CONF 0x1
484
9e0e3f85
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485extern void IOAPIC_INTREN(int);
486extern void IOAPIC_INTRDIS(int);
487
85bcaa51
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488extern int imcr_present;
489
35b2edcb
SZ
490static void ioapic_abi_intr_enable(int);
491static void ioapic_abi_intr_disable(int);
f416026e
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492static void ioapic_abi_intr_setup(int, int);
493static void ioapic_abi_intr_teardown(int);
aea76754
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494static void ioapic_abi_intr_config(int,
495 enum intr_trigger, enum intr_polarity);
a05c798c 496static int ioapic_abi_intr_cpuid(int);
35b2edcb 497
4234567c
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498static int ioapic_abi_msi_alloc(int [], int, int);
499static void ioapic_abi_msi_release(const int [], int, int);
500static void ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int);
501
aea76754
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502static void ioapic_abi_finalize(void);
503static void ioapic_abi_cleanup(void);
504static void ioapic_abi_setdefault(void);
505static void ioapic_abi_stabilize(void);
506static void ioapic_abi_initmap(void);
981239a7 507static void ioapic_abi_rman_setup(struct rman *);
9e0e3f85 508
95874ffd
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509static int ioapic_abi_gsi_cpuid(int, int);
510
9e0e3f85
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511struct machintr_abi MachIntrABI_IOAPIC = {
512 MACHINTR_IOAPIC,
35b2edcb
SZ
513 .intr_disable = ioapic_abi_intr_disable,
514 .intr_enable = ioapic_abi_intr_enable,
f416026e
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515 .intr_setup = ioapic_abi_intr_setup,
516 .intr_teardown = ioapic_abi_intr_teardown,
aea76754 517 .intr_config = ioapic_abi_intr_config,
a05c798c 518 .intr_cpuid = ioapic_abi_intr_cpuid,
35b2edcb 519
4234567c
SZ
520 .msi_alloc = ioapic_abi_msi_alloc,
521 .msi_release = ioapic_abi_msi_release,
522 .msi_map = ioapic_abi_msi_map,
523
aea76754
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524 .finalize = ioapic_abi_finalize,
525 .cleanup = ioapic_abi_cleanup,
526 .setdefault = ioapic_abi_setdefault,
527 .stabilize = ioapic_abi_stabilize,
981239a7
SZ
528 .initmap = ioapic_abi_initmap,
529 .rman_setup = ioapic_abi_rman_setup
c8fe38ae
MD
530};
531
6b809ec7 532static int ioapic_abi_extint_irq = -1;
f9593a5d 533static int ioapic_abi_legacy_irq_max;
2b195d6a 534static int ioapic_abi_gsi_balance;
7b87350b 535static int ioapic_abi_msi_start; /* NOTE: for testing only */
6b809ec7 536
5ac5ccd2 537struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
566d27d4
SZ
538
539static void
35b2edcb 540ioapic_abi_intr_enable(int irq)
566d27d4 541{
aef690c8
SZ
542 const struct ioapic_irqmap *map;
543
544 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
545 ("ioapic enable, invalid irq %d\n", irq));
546
547 map = &ioapic_irqmaps[mycpuid][irq];
548 KASSERT(IOAPIC_IMT_ISHWI(map),
549 ("ioapic enable, not hwi irq %d, type %d, cpu%d\n",
550 irq, map->im_type, mycpuid));
f9593a5d 551 if (map->im_type != IOAPIC_IMT_LEGACY)
566d27d4 552 return;
aef690c8 553
566d27d4
SZ
554 IOAPIC_INTREN(irq);
555}
556
557static void
35b2edcb 558ioapic_abi_intr_disable(int irq)
566d27d4 559{
aef690c8
SZ
560 const struct ioapic_irqmap *map;
561
562 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
563 ("ioapic disable, invalid irq %d\n", irq));
564
565 map = &ioapic_irqmaps[mycpuid][irq];
566 KASSERT(IOAPIC_IMT_ISHWI(map),
567 ("ioapic disable, not hwi irq %d, type %d, cpu%d\n",
568 irq, map->im_type, mycpuid));
f9593a5d 569 if (map->im_type != IOAPIC_IMT_LEGACY)
566d27d4 570 return;
aef690c8 571
566d27d4
SZ
572 IOAPIC_INTRDIS(irq);
573}
574
c8fe38ae 575static void
aea76754 576ioapic_abi_finalize(void)
c8fe38ae 577{
e0918665 578 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 579 KKASSERT(ioapic_enable);
10db3cc6 580
339478ac
SZ
581 /*
582 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 583 * from the BSP.
339478ac 584 */
9d758cc4 585 if (imcr_present) {
339478ac
SZ
586 outb(0x22, 0x70); /* select IMCR */
587 outb(0x23, 0x01); /* disconnect 8259 */
588 }
c8fe38ae
MD
589}
590
591/*
592 * This routine is called after physical interrupts are enabled but before
593 * the critical section is released. We need to clean out any interrupts
594 * that had already been posted to the cpu.
595 */
596static void
aea76754 597ioapic_abi_cleanup(void)
c8fe38ae 598{
9611ff20 599 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
c8fe38ae
MD
600}
601
7bf5fa56
SZ
602/* Must never be called */
603static void
aea76754 604ioapic_abi_stabilize(void)
7bf5fa56
SZ
605{
606 panic("ioapic_stabilize is called\n");
607}
608
f416026e
SZ
609static void
610ioapic_abi_intr_setup(int intr, int flags)
c8fe38ae 611{
88100cf6 612 const struct ioapic_irqmap *map;
f416026e 613 int vector, select;
339478ac 614 uint32_t value;
7bf5fa56 615 register_t ef;
c8fe38ae 616
88100cf6
SZ
617 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
618 ("ioapic setup, invalid irq %d\n", intr));
619
620 map = &ioapic_irqmaps[mycpuid][intr];
621 KASSERT(IOAPIC_IMT_ISHWI(map),
622 ("ioapic setup, not hwi irq %d, type %d, cpu%d",
623 intr, map->im_type, mycpuid));
f9593a5d 624 if (map->im_type != IOAPIC_IMT_LEGACY)
88100cf6 625 return;
88100cf6
SZ
626
627 KASSERT(ioapic_irqs[intr].io_addr != NULL,
628 ("ioapic setup, no GSI information, irq %d\n", intr));
f416026e
SZ
629
630 ef = read_rflags();
631 cpu_disable_intr();
632
633 vector = IDT_OFFSET + intr;
f416026e
SZ
634
635 /*
636 * Now reprogram the vector in the IO APIC. In order to avoid
637 * losing an EOI for a level interrupt, which is vector based,
638 * make sure that the IO APIC is programmed for edge-triggering
639 * first, then reprogrammed with the new vector. This should
640 * clear the IRR bit.
641 */
642 imen_lock();
643
644 select = ioapic_irqs[intr].io_idx;
645 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
646 value |= IOART_INTMSET;
647
648 ioapic_write(ioapic_irqs[intr].io_addr, select,
649 (value & ~APIC_TRIGMOD_MASK));
650 ioapic_write(ioapic_irqs[intr].io_addr, select,
651 (value & ~IOART_INTVEC) | vector);
652
653 imen_unlock();
654
26cf64b2 655 IOAPIC_INTREN(intr);
c8fe38ae 656
f416026e
SZ
657 write_rflags(ef);
658}
659
660static void
661ioapic_abi_intr_teardown(int intr)
662{
88100cf6 663 const struct ioapic_irqmap *map;
f416026e
SZ
664 int vector, select;
665 uint32_t value;
666 register_t ef;
667
88100cf6
SZ
668 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
669 ("ioapic teardown, invalid irq %d\n", intr));
670
671 map = &ioapic_irqmaps[mycpuid][intr];
672 KASSERT(IOAPIC_IMT_ISHWI(map),
673 ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
674 intr, map->im_type, mycpuid));
f9593a5d 675 if (map->im_type != IOAPIC_IMT_LEGACY)
88100cf6 676 return;
88100cf6
SZ
677
678 KASSERT(ioapic_irqs[intr].io_addr != NULL,
679 ("ioapic teardown, no GSI information, irq %d\n", intr));
5ac5ccd2 680
339478ac
SZ
681 ef = read_rflags();
682 cpu_disable_intr();
f416026e
SZ
683
684 /*
685 * Teardown an interrupt vector. The vector should already be
686 * installed in the cpu's IDT, but make sure.
687 */
26cf64b2 688 IOAPIC_INTRDIS(intr);
f416026e
SZ
689
690 vector = IDT_OFFSET + intr;
f416026e
SZ
691
692 /*
693 * In order to avoid losing an EOI for a level interrupt, which
694 * is vector based, make sure that the IO APIC is programmed for
695 * edge-triggering first, then reprogrammed with the new vector.
696 * This should clear the IRR bit.
697 */
698 imen_lock();
699
700 select = ioapic_irqs[intr].io_idx;
701 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
702
703 ioapic_write(ioapic_irqs[intr].io_addr, select,
704 (value & ~APIC_TRIGMOD_MASK));
705 ioapic_write(ioapic_irqs[intr].io_addr, select,
706 (value & ~IOART_INTVEC) | vector);
707
708 imen_unlock();
c8fe38ae 709
339478ac 710 write_rflags(ef);
339478ac 711}
c8fe38ae 712
10db3cc6 713static void
aea76754 714ioapic_abi_setdefault(void)
10db3cc6
SZ
715{
716 int intr;
717
9e0e3f85 718 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 719 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 720 continue;
8a06c6ee
SZ
721 setidt_global(IDT_OFFSET + intr, ioapic_intr[intr],
722 SDT_SYSIGT, SEL_KPL, 0);
10db3cc6
SZ
723 }
724}
725
a3dd9120 726static void
aea76754 727ioapic_abi_initmap(void)
a3dd9120 728{
6f072945 729 int cpu;
a3dd9120 730
2b195d6a
SZ
731 kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
732
7b87350b
SZ
733 kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start);
734 ioapic_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */
735
6f072945
SZ
736 /*
737 * NOTE: ncpus is not ready yet
738 */
739 for (cpu = 0; cpu < MAXCPU; ++cpu) {
740 int i;
741
4234567c 742 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
6f072945 743 ioapic_irqmaps[cpu][i].im_gsi = -1;
4234567c
SZ
744 ioapic_irqmaps[cpu][i].im_msi_base = -1;
745 }
6f072945
SZ
746 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
747 IOAPIC_IMT_SYSCALL;
748 }
a3dd9120
SZ
749}
750
929c940f 751void
027bbbfe 752ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
929c940f
SZ
753 enum intr_polarity pola)
754{
5ac5ccd2 755 struct ioapic_irqinfo *info;
929c940f
SZ
756 struct ioapic_irqmap *map;
757 void *ioaddr;
95874ffd 758 int pin, cpuid;
929c940f
SZ
759
760 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
761 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ
762
763 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
f9593a5d
SZ
764 if (irq > ioapic_abi_legacy_irq_max)
765 ioapic_abi_legacy_irq_max = irq;
bf2e6ffb 766
6f072945
SZ
767 cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
768
769 map = &ioapic_irqmaps[cpuid][irq];
929c940f
SZ
770
771 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
f9593a5d 772 map->im_type = IOAPIC_IMT_LEGACY;
929c940f
SZ
773
774 map->im_gsi = gsi;
775 map->im_trig = trig;
776 map->im_pola = pola;
777
778 if (bootverbose) {
4ecd5d4d
SZ
779 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
780 irq, map->im_gsi,
781 intr_str_trigger(map->im_trig),
782 intr_str_polarity(map->im_pola));
929c940f
SZ
783 }
784
d1ae7328
SZ
785 pin = ioapic_gsi_pin(map->im_gsi);
786 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 787
5ac5ccd2 788 info = &ioapic_irqs[irq];
929c940f 789
7bceaa10
SZ
790 imen_lock();
791
5ac5ccd2
SZ
792 info->io_addr = ioaddr;
793 info->io_idx = IOAPIC_REDTBL + (2 * pin);
794 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 795 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 796 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
SZ
797
798 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 799 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
800
801 imen_unlock();
d1ae7328
SZ
802}
803
4a913811 804void
027bbbfe 805ioapic_fixup_legacy_irqmaps(void)
4a913811 806{
6f072945
SZ
807 int cpu;
808
809 for (cpu = 0; cpu < ncpus; ++cpu) {
810 int i;
4a913811 811
6f072945
SZ
812 for (i = 0; i < ISA_IRQ_CNT; ++i) {
813 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
4a913811 814
6f072945
SZ
815 if (map->im_type == IOAPIC_IMT_UNUSED) {
816 map->im_type = IOAPIC_IMT_RESERVED;
817 if (bootverbose) {
818 kprintf("IOAPIC: "
819 "cpu%d irq %d reserved\n", cpu, i);
820 }
821 }
4a913811
SZ
822 }
823 }
6f072945 824
f9593a5d
SZ
825 ioapic_abi_legacy_irq_max += 1;
826 if (bootverbose) {
827 kprintf("IOAPIC: legacy irq max %d\n",
828 ioapic_abi_legacy_irq_max);
829 }
4a913811
SZ
830}
831
e90e7ac4 832int
027bbbfe
SZ
833ioapic_find_legacy_by_gsi(int gsi, enum intr_trigger trig,
834 enum intr_polarity pola)
e90e7ac4 835{
6f072945 836 int cpu;
e90e7ac4
SZ
837
838 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
839 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4 840
6f072945
SZ
841 for (cpu = 0; cpu < ncpus; ++cpu) {
842 int irq;
e90e7ac4 843
f9593a5d 844 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) {
6f072945
SZ
845 const struct ioapic_irqmap *map =
846 &ioapic_irqmaps[cpu][irq];
e90e7ac4 847
6f072945 848 if (map->im_gsi == gsi) {
f9593a5d 849 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY);
6f072945
SZ
850
851 if (map->im_flags & IOAPIC_IMF_CONF) {
852 if (map->im_trig != trig ||
853 map->im_pola != pola)
854 return -1;
855 }
856 return irq;
e90e7ac4 857 }
e90e7ac4
SZ
858 }
859 }
860 return -1;
861}
862
863int
027bbbfe
SZ
864ioapic_find_legacy_by_irq(int irq, enum intr_trigger trig,
865 enum intr_polarity pola)
e90e7ac4 866{
6f072945 867 int cpu;
e90e7ac4
SZ
868
869 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
870 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4 871
f9593a5d 872 if (irq < 0 || irq >= ioapic_abi_legacy_irq_max)
e90e7ac4 873 return -1;
e90e7ac4 874
6f072945
SZ
875 for (cpu = 0; cpu < ncpus; ++cpu) {
876 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
e90e7ac4 877
f9593a5d 878 if (map->im_type == IOAPIC_IMT_LEGACY) {
6f072945
SZ
879 if (map->im_flags & IOAPIC_IMF_CONF) {
880 if (map->im_trig != trig ||
881 map->im_pola != pola)
882 return -1;
883 }
884 return irq;
885 }
e90e7ac4 886 }
6f072945 887 return -1;
e90e7ac4
SZ
888}
889
d1ae7328 890static void
aea76754 891ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
d1ae7328 892{
5ac5ccd2 893 struct ioapic_irqinfo *info;
6f072945 894 struct ioapic_irqmap *map = NULL;
d1ae7328 895 void *ioaddr;
95874ffd 896 int pin, cpuid;
d1ae7328 897
d1ae7328
SZ
898 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
899 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328 900
f9593a5d 901 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
6f072945
SZ
902 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
903 map = &ioapic_irqmaps[cpuid][irq];
f9593a5d 904 if (map->im_type == IOAPIC_IMT_LEGACY)
6f072945
SZ
905 break;
906 }
907 KKASSERT(cpuid < ncpus);
d1ae7328 908
7962296e 909#ifdef notyet
d1ae7328
SZ
910 if (map->im_flags & IOAPIC_IMF_CONF) {
911 if (trig != map->im_trig) {
4ecd5d4d
SZ
912 panic("ioapic_intr_config: trig %s -> %s\n",
913 intr_str_trigger(map->im_trig),
914 intr_str_trigger(trig));
d1ae7328
SZ
915 }
916 if (pola != map->im_pola) {
917 panic("ioapic_intr_config: pola %s -> %s\n",
4ecd5d4d
SZ
918 intr_str_polarity(map->im_pola),
919 intr_str_polarity(pola));
d1ae7328
SZ
920 }
921 return;
922 }
7962296e 923#endif
d1ae7328
SZ
924 map->im_flags |= IOAPIC_IMF_CONF;
925
926 if (trig == map->im_trig && pola == map->im_pola)
927 return;
928
929 if (bootverbose) {
4ecd5d4d
SZ
930 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
931 irq, map->im_gsi,
932 intr_str_trigger(map->im_trig),
933 intr_str_polarity(map->im_pola),
934 intr_str_trigger(trig),
935 intr_str_polarity(pola));
d1ae7328 936 }
d1ae7328
SZ
937 map->im_trig = trig;
938 map->im_pola = pola;
939
940 pin = ioapic_gsi_pin(map->im_gsi);
941 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
942
5ac5ccd2 943 info = &ioapic_irqs[irq];
d1ae7328 944
7bceaa10
SZ
945 imen_lock();
946
5ac5ccd2 947 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 948 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 949 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 950
ecec8ddc 951 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 952 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
953
954 imen_unlock();
929c940f
SZ
955}
956
6b809ec7 957int
027bbbfe 958ioapic_conf_legacy_extint(int irq)
6b809ec7 959{
5ac5ccd2 960 struct ioapic_irqinfo *info;
6b809ec7
SZ
961 struct ioapic_irqmap *map;
962 void *ioaddr;
963 int pin, error, vec;
964
95874ffd
SZ
965 /* XXX only irq0 is allowed */
966 KKASSERT(irq == 0);
967
6b809ec7
SZ
968 vec = IDT_OFFSET + irq;
969
970 if (ioapic_abi_extint_irq == irq)
971 return 0;
972 else if (ioapic_abi_extint_irq >= 0)
973 return EEXIST;
974
975 error = icu_ioapic_extint(irq, vec);
976 if (error)
977 return error;
978
6f072945
SZ
979 /* ExtINT is always targeted to cpu0 */
980 map = &ioapic_irqmaps[0][irq];
6b809ec7
SZ
981
982 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
f9593a5d
SZ
983 map->im_type == IOAPIC_IMT_LEGACY);
984 if (map->im_type == IOAPIC_IMT_LEGACY) {
6b809ec7
SZ
985 if (map->im_flags & IOAPIC_IMF_CONF)
986 return EEXIST;
987 }
988 ioapic_abi_extint_irq = irq;
989
f9593a5d 990 map->im_type = IOAPIC_IMT_LEGACY;
6b809ec7
SZ
991 map->im_trig = INTR_TRIGGER_EDGE;
992 map->im_pola = INTR_POLARITY_HIGH;
993 map->im_flags = IOAPIC_IMF_CONF;
994
995 map->im_gsi = ioapic_extpin_gsi();
996 KKASSERT(map->im_gsi >= 0);
997
998 if (bootverbose) {
4ecd5d4d
SZ
999 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
1000 irq, map->im_gsi,
1001 intr_str_trigger(map->im_trig),
1002 intr_str_polarity(map->im_pola));
6b809ec7
SZ
1003 }
1004
1005 pin = ioapic_gsi_pin(map->im_gsi);
1006 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1007
5ac5ccd2 1008 info = &ioapic_irqs[irq];
6b809ec7
SZ
1009
1010 imen_lock();
1011
5ac5ccd2
SZ
1012 info->io_addr = ioaddr;
1013 info->io_idx = IOAPIC_REDTBL + (2 * pin);
1014 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ
1015
1016 ioapic_extpin_setup(ioaddr, pin, vec);
1017
1018 imen_unlock();
1019
1020 return 0;
1021}
a05c798c
SZ
1022
1023static int
95874ffd 1024ioapic_abi_intr_cpuid(int irq)
a05c798c 1025{
6f072945
SZ
1026 const struct ioapic_irqmap *map = NULL;
1027 int cpuid;
95874ffd 1028
f9593a5d 1029 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
95874ffd 1030
6f072945
SZ
1031 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1032 map = &ioapic_irqmaps[cpuid][irq];
f9593a5d 1033 if (map->im_type == IOAPIC_IMT_LEGACY)
6f072945 1034 return cpuid;
95874ffd
SZ
1035 }
1036
6f072945
SZ
1037 /* XXX some drivers tries to peek at reserved IRQs */
1038 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1039 map = &ioapic_irqmaps[cpuid][irq];
1040 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1041 }
1042 return 0;
95874ffd
SZ
1043}
1044
1045static int
1046ioapic_abi_gsi_cpuid(int irq, int gsi)
1047{
1048 char envpath[32];
1049 int cpuid = -1;
1050
1051 KKASSERT(gsi >= 0);
1052
1053 if (irq == 0 || gsi == 0) {
621d2ccf
SZ
1054 if (bootverbose) {
1055 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1056 irq, gsi);
1057 }
95874ffd
SZ
1058 return 0;
1059 }
1060
1061 if (irq == acpi_sci_irqno()) {
621d2ccf
SZ
1062 if (bootverbose) {
1063 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1064 irq, gsi);
1065 }
95874ffd
SZ
1066 return 0;
1067 }
1068
1069 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1070 kgetenv_int(envpath, &cpuid);
1071
1072 if (cpuid < 0) {
b8dfb6b1
SZ
1073 if (!ioapic_abi_gsi_balance) {
1074 if (bootverbose) {
1075 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1076 "(fixed)\n", irq, gsi);
1077 }
1078 return 0;
1079 }
1080
95874ffd 1081 cpuid = gsi % ncpus;
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1082 if (bootverbose) {
1083 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1084 irq, gsi, cpuid);
1085 }
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SZ
1086 } else if (cpuid >= ncpus) {
1087 cpuid = ncpus - 1;
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SZ
1088 if (bootverbose) {
1089 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1090 irq, gsi, cpuid);
1091 }
95874ffd 1092 } else {
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1093 if (bootverbose) {
1094 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1095 irq, gsi, cpuid);
1096 }
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1097 }
1098 return cpuid;
a05c798c 1099}
981239a7
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1100
1101static void
1102ioapic_abi_rman_setup(struct rman *rm)
1103{
1104 int start, end, i;
1105
1106 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1107 ("invalid rman cpuid %d", rm->rm_cpuid));
1108
1109 start = end = -1;
1110 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1111 const struct ioapic_irqmap *map =
1112 &ioapic_irqmaps[rm->rm_cpuid][i];
1113
1114 if (start < 0) {
1115 if (IOAPIC_IMT_ISHWI(map))
1116 start = end = i;
1117 } else {
1118 if (IOAPIC_IMT_ISHWI(map)) {
1119 end = i;
1120 } else {
1121 KKASSERT(end >= 0);
1122 if (bootverbose) {
1123 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1124 rm->rm_cpuid, start, end);
1125 }
1126 if (rman_manage_region(rm, start, end)) {
1127 panic("rman_manage_region"
1128 "(cpu%d %d - %d)", rm->rm_cpuid,
1129 start, end);
1130 }
1131 start = end = -1;
1132 }
1133 }
1134 }
1135 if (start >= 0) {
1136 KKASSERT(end >= 0);
1137 if (bootverbose) {
1138 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1139 rm->rm_cpuid, start, end);
1140 }
1141 if (rman_manage_region(rm, start, end)) {
1142 panic("rman_manage_region(cpu%d %d - %d)",
1143 rm->rm_cpuid, start, end);
1144 }
1145 }
1146}
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1147
1148static int
1149ioapic_abi_msi_alloc(int intrs[], int count, int cpuid)
1150{
1151 int i, error;
1152
1153 KASSERT(cpuid >= 0 && cpuid < ncpus,
1154 ("invalid cpuid %d", cpuid));
1155
1156 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
1157 KASSERT((count & (count - 1)) == 0,
1158 ("count %d is not power of 2\n", count));
1159
1160 lwkt_gettoken(&ioapic_irqmap_tok);
1161
1162 /*
1163 * NOTE:
1164 * Since IDT_OFFSET is 32, which is the maximum valid 'count',
1165 * we do not need to find out the first properly aligned
1166 * interrupt vector.
1167 */
1168
2c3d7ac8 1169 error = EMSGSIZE;
7b87350b 1170 for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) {
4234567c
SZ
1171 int j;
1172
1173 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED)
1174 continue;
1175
1176 for (j = 1; j < count; ++j) {
1177 if (ioapic_irqmaps[cpuid][i + j].im_type !=
1178 IOAPIC_IMT_UNUSED)
1179 break;
1180 }
1181 if (j != count)
1182 continue;
1183
1184 for (j = 0; j < count; ++j) {
1185 struct ioapic_irqmap *map;
1186 int intr = i + j;
1187
1188 map = &ioapic_irqmaps[cpuid][intr];
1189 KASSERT(map->im_msi_base < 0,
1190 ("intr %d, stale MSI-base %d\n",
1191 intr, map->im_msi_base));
1192
1193 map->im_type = IOAPIC_IMT_MSI;
1194 map->im_msi_base = i;
1195
1196 intrs[j] = intr;
1197 msi_setup(intr, cpuid);
1198
1199 if (bootverbose) {
1200 kprintf("alloc MSI intr %d on cpu%d\n",
1201 intr, cpuid);
1202 }
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1203 }
1204 error = 0;
1205 break;
1206 }
1207
1208 lwkt_reltoken(&ioapic_irqmap_tok);
1209
1210 return error;
1211}
1212
1213static void
1214ioapic_abi_msi_release(const int intrs[], int count, int cpuid)
1215{
1216 int i, msi_base = -1, intr_next = -1, mask;
1217
1218 KASSERT(cpuid >= 0 && cpuid < ncpus,
1219 ("invalid cpuid %d", cpuid));
1220
1221 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
1222
1223 mask = count - 1;
1224 KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count));
1225
1226 lwkt_gettoken(&ioapic_irqmap_tok);
1227
1228 for (i = 0; i < count; ++i) {
1229 struct ioapic_irqmap *map;
1230 int intr = intrs[i];
1231
1232 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1233 ("invalid intr %d\n", intr));
1234
1235 map = &ioapic_irqmaps[cpuid][intr];
1236 KASSERT(map->im_type == IOAPIC_IMT_MSI,
1237 ("try release non-MSI intr %d, type %d\n",
1238 intr, map->im_type));
1239 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
1240 ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base));
1241 KASSERT((map->im_msi_base & mask) == 0,
1242 ("intr %d, MSI-base %d is not proper aligned %d\n",
1243 intr, map->im_msi_base, count));
1244
1245 if (msi_base < 0) {
1246 msi_base = map->im_msi_base;
1247 } else {
1248 KASSERT(map->im_msi_base == msi_base,
1249 ("intr %d, inconsistent MSI-base, "
1250 "was %d, now %d\n",
1251 intr, msi_base, map->im_msi_base));
1252 }
1253
1254 if (intr_next < intr)
1255 intr_next = intr;
1256
1257 map->im_type = IOAPIC_IMT_UNUSED;
1258 map->im_msi_base = -1;
1259
1260 if (bootverbose)
1261 kprintf("release MSI intr %d on cpu%d\n", intr, cpuid);
1262 }
1263
1264 KKASSERT(intr_next > 0);
1265 KKASSERT(msi_base >= 0);
1266
1267 ++intr_next;
1268 if (intr_next < IOAPIC_HWI_VECTORS) {
1269 const struct ioapic_irqmap *map =
1270 &ioapic_irqmaps[cpuid][intr_next];
1271
1272 if (map->im_type == IOAPIC_IMT_MSI) {
1273 KASSERT(map->im_msi_base != msi_base,
1274 ("more than %d MSI was allocated\n", count));
1275 }
1276 }
1277
1278 lwkt_reltoken(&ioapic_irqmap_tok);
1279}
1280
1281static void
1282ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
1283{
1284 const struct ioapic_irqmap *map;
1285
1286 KASSERT(cpuid >= 0 && cpuid < ncpus,
1287 ("invalid cpuid %d", cpuid));
1288
1289 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1290 ("invalid intr %d\n", intr));
1291
1292 lwkt_gettoken(&ioapic_irqmap_tok);
1293
1294 map = &ioapic_irqmaps[cpuid][intr];
1295 KASSERT(map->im_type == IOAPIC_IMT_MSI,
1296 ("try map non-MSI intr %d, type %d\n", intr, map->im_type));
1297 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
1298 ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base));
1299
1300 msi_map(map->im_msi_base, addr, data, cpuid);
1301
1302 if (bootverbose)
1303 kprintf("map MSI intr %d on cpu%d\n", intr, cpuid);
1304
1305 lwkt_reltoken(&ioapic_irqmap_tok);
1306}