em: Use MSI, if device supports it
[dragonfly.git] / sys / dev / netif / em / if_em.c
CommitLineData
78195a76 1/*
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2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
9c80d176 4 * Copyright (c) 2001-2008, Intel Corporation
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5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9c80d176 9 *
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10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
9c80d176 12 *
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13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
9c80d176 16 *
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17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
9c80d176 20 *
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
9c80d176 35 *
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36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
9c80d176 38 *
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39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
9c80d176 42 *
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43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
9c80d176 52 *
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53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
9c80d176 65 *
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66 */
67/*
68 * SERIALIZATION API RULES:
69 *
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
9c80d176 72 * driver.
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73 *
74 * - ifmedia entry points will be serialized by the ifmedia code using the
75 * ifnet serializer.
76 *
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
79 *
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
82 *
83 * - The device driver typically holds the serializer at the time it wishes
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84 * to call if_input.
85 *
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
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90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
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95
96#include "opt_polling.h"
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97
98#include <sys/param.h>
99#include <sys/bus.h>
100#include <sys/endian.h>
9db4b353 101#include <sys/interrupt.h>
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102#include <sys/kernel.h>
103#include <sys/ktr.h>
104#include <sys/malloc.h>
105#include <sys/mbuf.h>
9c80d176 106#include <sys/proc.h>
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107#include <sys/rman.h>
108#include <sys/serialize.h>
109#include <sys/socket.h>
110#include <sys/sockio.h>
111#include <sys/sysctl.h>
9c80d176 112#include <sys/systm.h>
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113
114#include <net/bpf.h>
115#include <net/ethernet.h>
116#include <net/if.h>
117#include <net/if_arp.h>
118#include <net/if_dl.h>
119#include <net/if_media.h>
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120#include <net/ifq_var.h>
121#include <net/vlan/if_vlan_var.h>
b637f170 122#include <net/vlan/if_vlan_ether.h>
87307ba1 123
87307ba1 124#include <netinet/in_systm.h>
9c80d176 125#include <netinet/in.h>
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126#include <netinet/ip.h>
127#include <netinet/tcp.h>
128#include <netinet/udp.h>
984263bc 129
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130#include <bus/pci/pcivar.h>
131#include <bus/pci/pcireg.h>
984263bc 132
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133#include <dev/netif/ig_hal/e1000_api.h>
134#include <dev/netif/ig_hal/e1000_82571.h>
135#include <dev/netif/em/if_em.h>
984263bc 136
9c80d176 137#define EM_NAME "Intel(R) PRO/1000 Network Connection "
2d0e5700 138#define EM_VER " 7.1.7"
9c80d176 139
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140#define _EM_DEVICE(id, ret) \
141 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
142#define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
143#define EM_DEVICE(id) _EM_DEVICE(id, 0)
144#define EM_DEVICE_NULL { 0, 0, 0, NULL }
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145
146static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM),
148 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP),
150 EM_DEVICE(82540EP_LOM),
151 EM_DEVICE(82540EP_LP),
152
153 EM_DEVICE(82541EI),
154 EM_DEVICE(82541ER),
155 EM_DEVICE(82541ER_LOM),
156 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI),
158 EM_DEVICE(82541GI_LF),
159 EM_DEVICE(82541GI_MOBILE),
160
161 EM_DEVICE(82542),
162
163 EM_DEVICE(82543GC_FIBER),
164 EM_DEVICE(82543GC_COPPER),
165
166 EM_DEVICE(82544EI_COPPER),
167 EM_DEVICE(82544EI_FIBER),
168 EM_DEVICE(82544GC_COPPER),
169 EM_DEVICE(82544GC_LOM),
170
171 EM_DEVICE(82545EM_COPPER),
172 EM_DEVICE(82545EM_FIBER),
173 EM_DEVICE(82545GM_COPPER),
174 EM_DEVICE(82545GM_FIBER),
175 EM_DEVICE(82545GM_SERDES),
176
177 EM_DEVICE(82546EB_COPPER),
178 EM_DEVICE(82546EB_FIBER),
179 EM_DEVICE(82546EB_QUAD_COPPER),
180 EM_DEVICE(82546GB_COPPER),
181 EM_DEVICE(82546GB_FIBER),
182 EM_DEVICE(82546GB_SERDES),
183 EM_DEVICE(82546GB_PCIE),
184 EM_DEVICE(82546GB_QUAD_COPPER),
185 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
186
187 EM_DEVICE(82547EI),
188 EM_DEVICE(82547EI_MOBILE),
189 EM_DEVICE(82547GI),
190
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191 EM_EMX_DEVICE(82571EB_COPPER),
192 EM_EMX_DEVICE(82571EB_FIBER),
193 EM_EMX_DEVICE(82571EB_SERDES),
194 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
195 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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198 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
199 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
200 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201
202 EM_EMX_DEVICE(82572EI_COPPER),
203 EM_EMX_DEVICE(82572EI_FIBER),
204 EM_EMX_DEVICE(82572EI_SERDES),
205 EM_EMX_DEVICE(82572EI),
206
207 EM_EMX_DEVICE(82573E),
208 EM_EMX_DEVICE(82573E_IAMT),
209 EM_EMX_DEVICE(82573L),
210
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211 EM_DEVICE(82583V),
212
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213 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
215 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
216 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
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217
218 EM_DEVICE(ICH8_IGP_M_AMT),
219 EM_DEVICE(ICH8_IGP_AMT),
220 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE),
222 EM_DEVICE(ICH8_IFE_GT),
223 EM_DEVICE(ICH8_IFE_G),
224 EM_DEVICE(ICH8_IGP_M),
2d0e5700 225 EM_DEVICE(ICH8_82567V_3),
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226
227 EM_DEVICE(ICH9_IGP_M_AMT),
228 EM_DEVICE(ICH9_IGP_AMT),
229 EM_DEVICE(ICH9_IGP_C),
230 EM_DEVICE(ICH9_IGP_M),
231 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE),
233 EM_DEVICE(ICH9_IFE_GT),
234 EM_DEVICE(ICH9_IFE_G),
235 EM_DEVICE(ICH9_BM),
236
96ced48a 237 EM_EMX_DEVICE(82574L),
2d0e5700 238 EM_EMX_DEVICE(82574LA),
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239
240 EM_DEVICE(ICH10_R_BM_LM),
241 EM_DEVICE(ICH10_R_BM_LF),
242 EM_DEVICE(ICH10_R_BM_V),
243 EM_DEVICE(ICH10_D_BM_LM),
244 EM_DEVICE(ICH10_D_BM_LF),
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245 EM_DEVICE(ICH10_D_BM_V),
246
247 EM_DEVICE(PCH_M_HV_LM),
248 EM_DEVICE(PCH_M_HV_LC),
249 EM_DEVICE(PCH_D_HV_DM),
250 EM_DEVICE(PCH_D_HV_DC),
251
252 EM_DEVICE(PCH2_LV_LM),
253 EM_DEVICE(PCH2_LV_V),
984263bc 254
f647ad3d 255 /* required last entry */
9c80d176 256 EM_DEVICE_NULL
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257};
258
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259static int em_probe(device_t);
260static int em_attach(device_t);
261static int em_detach(device_t);
262static int em_shutdown(device_t);
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263static int em_suspend(device_t);
264static int em_resume(device_t);
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265
266static void em_init(void *);
267static void em_stop(struct adapter *);
f647ad3d 268static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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269static void em_start(struct ifnet *);
270#ifdef DEVICE_POLLING
271static void em_poll(struct ifnet *, enum poll_cmd, int);
272#endif
f647ad3d 273static void em_watchdog(struct ifnet *);
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274static void em_media_status(struct ifnet *, struct ifmediareq *);
275static int em_media_change(struct ifnet *);
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276static void em_timer(void *);
277
278static void em_intr(void *);
279static void em_rxeof(struct adapter *, int);
280static void em_txeof(struct adapter *);
9f60d74b 281static void em_tx_collect(struct adapter *);
9c80d176 282static void em_tx_purge(struct adapter *);
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283static void em_enable_intr(struct adapter *);
284static void em_disable_intr(struct adapter *);
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285
286static int em_dma_malloc(struct adapter *, bus_size_t,
287 struct em_dma_alloc *);
288static void em_dma_free(struct adapter *, struct em_dma_alloc *);
289static void em_init_tx_ring(struct adapter *);
290static int em_init_rx_ring(struct adapter *);
291static int em_create_tx_ring(struct adapter *);
292static int em_create_rx_ring(struct adapter *);
293static void em_destroy_tx_ring(struct adapter *, int);
294static void em_destroy_rx_ring(struct adapter *, int);
295static int em_newbuf(struct adapter *, int, int);
296static int em_encap(struct adapter *, struct mbuf **);
297static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
298 struct mbuf *);
002b3a05 299static int em_txcsum_pullup(struct adapter *, struct mbuf **);
9f60d74b 300static int em_txcsum(struct adapter *, struct mbuf *,
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301 uint32_t *, uint32_t *);
302
303static int em_get_hw_info(struct adapter *);
304static int em_is_valid_eaddr(const uint8_t *);
305static int em_alloc_pci_res(struct adapter *);
306static void em_free_pci_res(struct adapter *);
2d0e5700 307static int em_reset(struct adapter *);
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308static void em_setup_ifp(struct adapter *);
309static void em_init_tx_unit(struct adapter *);
310static void em_init_rx_unit(struct adapter *);
311static void em_update_stats(struct adapter *);
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312static void em_set_promisc(struct adapter *);
313static void em_disable_promisc(struct adapter *);
314static void em_set_multi(struct adapter *);
87307ba1 315static void em_update_link_status(struct adapter *);
f647ad3d 316static void em_smartspeed(struct adapter *);
2d0e5700 317static void em_set_itr(struct adapter *, uint32_t);
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318
319/* Hardware workarounds */
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320static int em_82547_fifo_workaround(struct adapter *, int);
321static void em_82547_update_fifo_head(struct adapter *, int);
322static int em_82547_tx_fifo_reset(struct adapter *);
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323static void em_82547_move_tail(void *);
324static void em_82547_move_tail_serialized(struct adapter *);
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325static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
326
f647ad3d 327static void em_print_debug_info(struct adapter *);
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328static void em_print_nvm_info(struct adapter *);
329static void em_print_hw_stats(struct adapter *);
330
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331static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
332static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
d0870c72 333static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
9f60d74b 334static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
9c80d176 335static void em_add_sysctl(struct adapter *adapter);
984263bc 336
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337/* Management and WOL Support */
338static void em_get_mgmt(struct adapter *);
339static void em_rel_mgmt(struct adapter *);
340static void em_get_hw_control(struct adapter *);
341static void em_rel_hw_control(struct adapter *);
342static void em_enable_wol(device_t);
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343
344static device_method_t em_methods[] = {
345 /* Device interface */
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346 DEVMETHOD(device_probe, em_probe),
347 DEVMETHOD(device_attach, em_attach),
348 DEVMETHOD(device_detach, em_detach),
349 DEVMETHOD(device_shutdown, em_shutdown),
350 DEVMETHOD(device_suspend, em_suspend),
351 DEVMETHOD(device_resume, em_resume),
352 { 0, 0 }
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353};
354
355static driver_t em_driver = {
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356 "em",
357 em_methods,
358 sizeof(struct adapter),
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359};
360
361static devclass_t em_devclass;
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362
363DECLARE_DUMMY_MODULE(if_em);
9c80d176 364MODULE_DEPEND(em, ig_hal, 1, 1, 1);
aa2b9d05 365DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
984263bc 366
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367/*
368 * Tunables
369 */
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370static int em_int_throttle_ceil = EM_DEFAULT_ITR;
371static int em_rxd = EM_DEFAULT_RXD;
372static int em_txd = EM_DEFAULT_TXD;
053f3ae6 373static int em_smart_pwr_down = 0;
0d366ee7 374
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375/* Controls whether promiscuous also shows bad packets */
376static int em_debug_sbp = FALSE;
0d366ee7 377
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378static int em_82573_workaround = 1;
379static int em_msi_enable = 1;
05580856 380
d0870c72 381TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
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382TUNABLE_INT("hw.em.rxd", &em_rxd);
383TUNABLE_INT("hw.em.txd", &em_txd);
384TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
9c80d176 385TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
05580856 386TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
053f3ae6 387TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
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388
389/* Global used in WOL setup with multiport cards */
390static int em_global_quad_port_a = 0;
391
392/* Set this to one to display debug statistics */
393static int em_display_debug_stats = 0;
0d366ee7 394
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395#if !defined(KTR_IF_EM)
396#define KTR_IF_EM KTR_ALL
397#endif
398KTR_INFO_MASTER(if_em);
399KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0);
400KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0);
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401KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0);
402KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0);
403KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0);
404#define logif(name) KTR_LOG(if_em_ ## name)
405
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406static int
407em_probe(device_t dev)
408{
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409 const struct em_vendor_info *ent;
410 uint16_t vid, did;
984263bc 411
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412 vid = pci_get_vendor(dev);
413 did = pci_get_device(dev);
984263bc 414
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415 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
416 if (vid == ent->vendor_id && did == ent->device_id) {
417 device_set_desc(dev, ent->desc);
dbcd0c9b 418 device_set_async_attach(dev, TRUE);
96ced48a 419 return (ent->ret);
984263bc 420 }
984263bc 421 }
87307ba1 422 return (ENXIO);
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423}
424
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425static int
426em_attach(device_t dev)
427{
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428 struct adapter *adapter = device_get_softc(dev);
429 struct ifnet *ifp = &adapter->arpcom.ac_if;
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430 int tsize, rsize;
431 int error = 0;
2d0e5700 432 uint16_t eeprom_data, device_id, apme_mask;
984263bc 433
9c80d176 434 adapter->dev = adapter->osdep.dev = dev;
f647ad3d 435
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436 callout_init_mp(&adapter->timer);
437 callout_init_mp(&adapter->tx_fifo_timer);
af82d4bb 438
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439 /* Determine hardware and mac info */
440 error = em_get_hw_info(adapter);
441 if (error) {
442 device_printf(dev, "Identify hardware failed\n");
443 goto fail;
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444 }
445
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446 /* Setup PCI resources */
447 error = em_alloc_pci_res(adapter);
448 if (error) {
449 device_printf(dev, "Allocation of PCI resources failed\n");
450 goto fail;
451 }
984263bc 452
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453 /*
454 * For ICH8 and family we need to map the flash memory,
455 * and this must happen after the MAC is identified.
456 */
457 if (adapter->hw.mac.type == e1000_ich8lan ||
2d0e5700 458 adapter->hw.mac.type == e1000_ich9lan ||
9c80d176 459 adapter->hw.mac.type == e1000_ich10lan ||
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460 adapter->hw.mac.type == e1000_pchlan ||
461 adapter->hw.mac.type == e1000_pch2lan) {
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462 adapter->flash_rid = EM_BAR_FLASH;
463
464 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
465 &adapter->flash_rid, RF_ACTIVE);
466 if (adapter->flash == NULL) {
467 device_printf(dev, "Mapping of Flash failed\n");
468 error = ENXIO;
469 goto fail;
470 }
471 adapter->osdep.flash_bus_space_tag =
472 rman_get_bustag(adapter->flash);
473 adapter->osdep.flash_bus_space_handle =
474 rman_get_bushandle(adapter->flash);
984263bc 475
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476 /*
477 * This is used in the shared code
478 * XXX this goof is actually not used.
479 */
480 adapter->hw.flash_address = (uint8_t *)adapter->flash;
481 }
0d366ee7 482
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483 /* Do Shared Code initialization */
484 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
485 device_printf(dev, "Setup of Shared code failed\n");
486 error = ENXIO;
487 goto fail;
f647ad3d 488 }
7ea52455 489
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490 e1000_get_bus_info(&adapter->hw);
491
1eca7b82 492 /*
9c80d176 493 * Validate number of transmit and receive descriptors. It
1eca7b82 494 * must not exceed hardware maximum, and must be multiple
9c80d176 495 * of E1000_DBA_ALIGN.
1eca7b82 496 */
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497 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
498 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
499 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
500 em_txd < EM_MIN_TXD) {
1eca7b82 501 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
9c80d176 502 EM_DEFAULT_TXD, em_txd);
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503 adapter->num_tx_desc = EM_DEFAULT_TXD;
504 } else {
505 adapter->num_tx_desc = em_txd;
506 }
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507 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
508 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
509 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
510 em_rxd < EM_MIN_RXD) {
1eca7b82 511 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
9c80d176 512 EM_DEFAULT_RXD, em_rxd);
1eca7b82
SZ
513 adapter->num_rx_desc = EM_DEFAULT_RXD;
514 } else {
515 adapter->num_rx_desc = em_rxd;
516 }
517
9c80d176
SZ
518 adapter->hw.mac.autoneg = DO_AUTO_NEG;
519 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
520 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
521 adapter->rx_buffer_len = MCLBYTES;
e94c2bf4 522
9c80d176
SZ
523 /*
524 * Interrupt throttle rate
525 */
526 if (em_int_throttle_ceil == 0) {
527 adapter->int_throttle_ceil = 0;
528 } else {
529 int throttle = em_int_throttle_ceil;
f647ad3d 530
9c80d176
SZ
531 if (throttle < 0)
532 throttle = EM_DEFAULT_ITR;
0d366ee7 533
9c80d176
SZ
534 /* Recalculate the tunable value to get the exact frequency. */
535 throttle = 1000000000 / 256 / throttle;
664c7645
SZ
536
537 /* Upper 16bits of ITR is reserved and should be zero */
538 if (throttle & 0xffff0000)
539 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
540
9c80d176
SZ
541 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
542 }
984263bc 543
9c80d176
SZ
544 e1000_init_script_state_82541(&adapter->hw, TRUE);
545 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
546
547 /* Copper options */
548 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
549 adapter->hw.phy.mdix = AUTO_ALL_MODES;
550 adapter->hw.phy.disable_polarity_correction = FALSE;
551 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
552 }
553
554 /* Set the frame limits assuming standard ethernet sized frames. */
555 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
556 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
984263bc 557
9c80d176
SZ
558 /* This controls when hardware reports transmit completion status. */
559 adapter->hw.mac.report_tx_early = 1;
984263bc 560
87307ba1 561 /*
9c80d176 562 * Create top level busdma tag
984263bc 563 */
9c80d176
SZ
564 error = bus_dma_tag_create(NULL, 1, 0,
565 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
566 NULL, NULL,
567 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
568 0, &adapter->parent_dtag);
569 if (error) {
570 device_printf(dev, "could not create top level DMA tag\n");
af82d4bb 571 goto fail;
9c80d176 572 }
af82d4bb 573
9c80d176
SZ
574 /*
575 * Allocate Transmit Descriptor ring
576 */
577 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
1eca7b82 578 EM_DBA_ALIGN);
87307ba1
SZ
579 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
580 if (error) {
9c80d176 581 device_printf(dev, "Unable to allocate tx_desc memory\n");
af82d4bb 582 goto fail;
984263bc 583 }
9c80d176 584 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
984263bc 585
9c80d176
SZ
586 /*
587 * Allocate Receive Descriptor ring
588 */
589 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
1eca7b82 590 EM_DBA_ALIGN);
87307ba1
SZ
591 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
592 if (error) {
9ccd8c1f 593 device_printf(dev, "Unable to allocate rx_desc memory\n");
af82d4bb 594 goto fail;
984263bc 595 }
9c80d176
SZ
596 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
597
2d0e5700
SZ
598 /* Allocate multicast array memory. */
599 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
600 M_DEVBUF, M_WAITOK);
601
602 /* Indicate SOL/IDER usage */
603 if (e1000_check_reset_block(&adapter->hw)) {
604 device_printf(dev,
605 "PHY reset is blocked due to SOL/IDER session.\n");
606 }
607
608 /*
609 * Start from a known state, this is important in reading the
610 * nvm and mac from that.
611 */
612 e1000_reset_hw(&adapter->hw);
613
9c80d176
SZ
614 /* Make sure we have a good EEPROM before we read from it */
615 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
616 /*
617 * Some PCI-E parts fail the first check due to
618 * the link being in sleep state, call it again,
619 * if it fails a second time its a real issue.
620 */
621 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
622 device_printf(dev,
623 "The EEPROM Checksum Is Not Valid\n");
624 error = EIO;
625 goto fail;
626 }
627 }
984263bc 628
984263bc 629 /* Copy the permanent MAC address out of the EEPROM */
9c80d176
SZ
630 if (e1000_read_mac_addr(&adapter->hw) < 0) {
631 device_printf(dev, "EEPROM read error while reading MAC"
632 " address\n");
984263bc 633 error = EIO;
af82d4bb 634 goto fail;
984263bc 635 }
9c80d176 636 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
87307ba1 637 device_printf(dev, "Invalid MAC address\n");
984263bc 638 error = EIO;
af82d4bb 639 goto fail;
984263bc
MD
640 }
641
9c80d176
SZ
642 /* Allocate transmit descriptors and buffers */
643 error = em_create_tx_ring(adapter);
644 if (error) {
645 device_printf(dev, "Could not setup transmit structures\n");
646 goto fail;
647 }
648
649 /* Allocate receive descriptors and buffers */
650 error = em_create_rx_ring(adapter);
651 if (error) {
652 device_printf(dev, "Could not setup receive structures\n");
653 goto fail;
654 }
655
656 /* Manually turn off all interrupts */
657 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
658
9c80d176
SZ
659 /* Determine if we have to control management hardware */
660 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
661
662 /*
663 * Setup Wake-on-Lan
664 */
2d0e5700
SZ
665 apme_mask = EM_EEPROM_APME;
666 eeprom_data = 0;
9c80d176
SZ
667 switch (adapter->hw.mac.type) {
668 case e1000_82542:
669 case e1000_82543:
670 break;
671
2d0e5700
SZ
672 case e1000_82573:
673 case e1000_82583:
674 adapter->has_amt = 1;
675 /* FALL THROUGH */
676
9c80d176
SZ
677 case e1000_82546:
678 case e1000_82546_rev_3:
679 case e1000_82571:
2d0e5700 680 case e1000_82572:
9c80d176
SZ
681 case e1000_80003es2lan:
682 if (adapter->hw.bus.func == 1) {
683 e1000_read_nvm(&adapter->hw,
684 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
685 } else {
686 e1000_read_nvm(&adapter->hw,
687 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
688 }
2d0e5700
SZ
689 break;
690
691 case e1000_ich8lan:
692 case e1000_ich9lan:
693 case e1000_ich10lan:
694 case e1000_pchlan:
695 case e1000_pch2lan:
696 apme_mask = E1000_WUC_APME;
697 adapter->has_amt = TRUE;
698 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
9c80d176
SZ
699 break;
700
701 default:
2d0e5700
SZ
702 e1000_read_nvm(&adapter->hw,
703 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9c80d176
SZ
704 break;
705 }
2d0e5700
SZ
706 if (eeprom_data & apme_mask)
707 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
708
9c80d176
SZ
709 /*
710 * We have the eeprom settings, now apply the special cases
711 * where the eeprom may be wrong or the board won't support
712 * wake on lan on a particular port
713 */
714 device_id = pci_get_device(dev);
715 switch (device_id) {
716 case E1000_DEV_ID_82546GB_PCIE:
717 adapter->wol = 0;
718 break;
719
720 case E1000_DEV_ID_82546EB_FIBER:
721 case E1000_DEV_ID_82546GB_FIBER:
722 case E1000_DEV_ID_82571EB_FIBER:
723 /*
724 * Wake events only supported on port A for dual fiber
725 * regardless of eeprom setting
726 */
727 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
728 E1000_STATUS_FUNC_1)
729 adapter->wol = 0;
730 break;
731
732 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
733 case E1000_DEV_ID_82571EB_QUAD_COPPER:
734 case E1000_DEV_ID_82571EB_QUAD_FIBER:
735 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
736 /* if quad port adapter, disable WoL on all but port A */
737 if (em_global_quad_port_a != 0)
738 adapter->wol = 0;
739 /* Reset for multiple quad port adapters */
740 if (++em_global_quad_port_a == 4)
741 em_global_quad_port_a = 0;
742 break;
743 }
744
745 /* XXX disable wol */
746 adapter->wol = 0;
747
2d0e5700
SZ
748 /* Setup OS specific network interface */
749 em_setup_ifp(adapter);
750
751 /* Add sysctl tree, must after em_setup_ifp() */
752 em_add_sysctl(adapter);
753
754 /* Reset the hardware */
755 error = em_reset(adapter);
756 if (error) {
757 device_printf(dev, "Unable to reset the hardware\n");
758 goto fail;
759 }
760
761 /* Initialize statistics */
762 em_update_stats(adapter);
763
764 adapter->hw.mac.get_link_status = 1;
765 em_update_link_status(adapter);
766
9c80d176
SZ
767 /* Do we need workaround for 82544 PCI-X adapter? */
768 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
769 adapter->hw.mac.type == e1000_82544)
f647ad3d 770 adapter->pcix_82544 = TRUE;
87307ba1 771 else
f647ad3d 772 adapter->pcix_82544 = FALSE;
af82d4bb 773
9c80d176
SZ
774 if (adapter->pcix_82544) {
775 /*
776 * 82544 on PCI-X may split one TX segment
777 * into two TX descs, so we double its number
778 * of spare TX desc here.
779 */
780 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
781 } else {
782 adapter->spare_tx_desc = EM_TX_SPARE;
783 }
784
9f60d74b
SZ
785 /*
786 * Keep following relationship between spare_tx_desc, oact_tx_desc
787 * and tx_int_nsegs:
788 * (spare_tx_desc + EM_TX_RESERVED) <=
789 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
790 */
791 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
792 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
793 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
794 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
795 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
796
797 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
798 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
799 adapter->tx_int_nsegs = adapter->oact_tx_desc;
800
2d0e5700
SZ
801 /* Non-AMT based hardware can now take control from firmware */
802 if (adapter->has_manage && !adapter->has_amt &&
803 adapter->hw.mac.type >= e1000_82571)
804 em_get_hw_control(adapter);
805
9c80d176
SZ
806 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
807 em_intr, adapter, &adapter->intr_tag,
808 ifp->if_serializer);
af82d4bb 809 if (error) {
9c80d176
SZ
810 device_printf(dev, "Failed to register interrupt handler");
811 ether_ifdetach(&adapter->arpcom.ac_if);
af82d4bb
JS
812 goto fail;
813 }
814
9c80d176 815 ifp->if_cpuid = ithread_cpuid(rman_get_start(adapter->intr_res));
9db4b353 816 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
9c80d176 817 return (0);
af82d4bb
JS
818fail:
819 em_detach(dev);
9c80d176 820 return (error);
984263bc
MD
821}
822
984263bc
MD
823static int
824em_detach(device_t dev)
825{
78195a76 826 struct adapter *adapter = device_get_softc(dev);
984263bc 827
af82d4bb 828 if (device_is_attached(dev)) {
9c80d176 829 struct ifnet *ifp = &adapter->arpcom.ac_if;
cdf89432
SZ
830
831 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 832
af82d4bb 833 em_stop(adapter);
9c80d176
SZ
834
835 e1000_phy_hw_reset(&adapter->hw);
836
837 em_rel_mgmt(adapter);
2d0e5700 838 em_rel_hw_control(adapter);
9c80d176
SZ
839
840 if (adapter->wol) {
841 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
842 E1000_WUC_PME_EN);
843 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
844 em_enable_wol(dev);
845 }
846
847 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
848
cdf89432
SZ
849 lwkt_serialize_exit(ifp->if_serializer);
850
851 ether_ifdetach(ifp);
2d0e5700
SZ
852 } else {
853 em_rel_hw_control(adapter);
7ea52455 854 }
cdf89432
SZ
855 bus_generic_detach(dev);
856
9c80d176
SZ
857 em_free_pci_res(adapter);
858
859 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
860 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
af82d4bb 861
984263bc 862 /* Free Transmit Descriptor ring */
9c80d176 863 if (adapter->tx_desc_base)
9ccd8c1f 864 em_dma_free(adapter, &adapter->txdma);
984263bc 865
984263bc 866 /* Free Receive Descriptor ring */
9c80d176 867 if (adapter->rx_desc_base)
9ccd8c1f 868 em_dma_free(adapter, &adapter->rxdma);
9c80d176
SZ
869
870 /* Free top level busdma tag */
871 if (adapter->parent_dtag != NULL)
872 bus_dma_tag_destroy(adapter->parent_dtag);
984263bc 873
1eca7b82 874 /* Free sysctl tree */
9c80d176 875 if (adapter->sysctl_tree != NULL)
1eca7b82 876 sysctl_ctx_free(&adapter->sysctl_ctx);
984263bc 877
87307ba1 878 return (0);
984263bc
MD
879}
880
984263bc
MD
881static int
882em_shutdown(device_t dev)
883{
9c80d176 884 return em_suspend(dev);
87307ba1
SZ
885}
886
87307ba1
SZ
887static int
888em_suspend(device_t dev)
889{
890 struct adapter *adapter = device_get_softc(dev);
9c80d176 891 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
892
893 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 894
87307ba1 895 em_stop(adapter);
9c80d176
SZ
896
897 em_rel_mgmt(adapter);
2d0e5700 898 em_rel_hw_control(adapter);
9c80d176 899
2d0e5700 900 if (adapter->wol) {
9c80d176
SZ
901 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
902 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
903 em_enable_wol(dev);
2d0e5700 904 }
9c80d176 905
87307ba1 906 lwkt_serialize_exit(ifp->if_serializer);
9c80d176
SZ
907
908 return bus_generic_suspend(dev);
87307ba1
SZ
909}
910
911static int
912em_resume(device_t dev)
913{
914 struct adapter *adapter = device_get_softc(dev);
9c80d176 915 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
916
917 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 918
87307ba1 919 em_init(adapter);
9c80d176 920 em_get_mgmt(adapter);
9db4b353 921 if_devstart(ifp);
9c80d176 922
87307ba1
SZ
923 lwkt_serialize_exit(ifp->if_serializer);
924
925 return bus_generic_resume(dev);
984263bc
MD
926}
927
984263bc
MD
928static void
929em_start(struct ifnet *ifp)
930{
f647ad3d 931 struct adapter *adapter = ifp->if_softc;
9c80d176 932 struct mbuf *m_head;
984263bc 933
1eca7b82 934 ASSERT_SERIALIZED(ifp->if_serializer);
78195a76 935
87307ba1
SZ
936 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
937 return;
9c80d176 938
9db4b353
SZ
939 if (!adapter->link_active) {
940 ifq_purge(&ifp->if_snd);
f647ad3d 941 return;
9db4b353 942 }
9c80d176 943
e26dc3e9 944 while (!ifq_is_empty(&ifp->if_snd)) {
9f60d74b
SZ
945 /* Now do we at least have a minimal? */
946 if (EM_IS_OACTIVE(adapter)) {
947 em_tx_collect(adapter);
9c80d176 948 if (EM_IS_OACTIVE(adapter)) {
9c80d176 949 ifp->if_flags |= IFF_OACTIVE;
9f60d74b 950 adapter->no_tx_desc_avail1++;
9c80d176
SZ
951 break;
952 }
953 }
954
955 logif(pkt_txqueue);
9db4b353 956 m_head = ifq_dequeue(&ifp->if_snd, NULL);
f647ad3d
JS
957 if (m_head == NULL)
958 break;
984263bc 959
9c80d176 960 if (em_encap(adapter, &m_head)) {
002b3a05 961 ifp->if_oerrors++;
9f60d74b
SZ
962 em_tx_collect(adapter);
963 continue;
f647ad3d 964 }
984263bc
MD
965
966 /* Send a copy of the frame to the BPF listener */
b637f170 967 ETHER_BPF_MTAP(ifp, m_head);
87307ba1
SZ
968
969 /* Set timeout in case hardware has problems transmitting. */
970 ifp->if_timer = EM_TX_TIMEOUT;
f647ad3d 971 }
984263bc
MD
972}
973
984263bc 974static int
bd4539cc 975em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 976{
f647ad3d 977 struct adapter *adapter = ifp->if_softc;
9c80d176 978 struct ifreq *ifr = (struct ifreq *)data;
1eca7b82 979 uint16_t eeprom_data = 0;
9c80d176
SZ
980 int max_frame_size, mask, reinit;
981 int error = 0;
0d366ee7 982
9c80d176 983 ASSERT_SERIALIZED(ifp->if_serializer);
0d366ee7 984
984263bc 985 switch (command) {
984263bc 986 case SIOCSIFMTU:
9c80d176
SZ
987 switch (adapter->hw.mac.type) {
988 case e1000_82573:
1eca7b82
SZ
989 /*
990 * 82573 only supports jumbo frames
991 * if ASPM is disabled.
992 */
9c80d176
SZ
993 e1000_read_nvm(&adapter->hw,
994 NVM_INIT_3GIO_3, 1, &eeprom_data);
995 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1eca7b82
SZ
996 max_frame_size = ETHER_MAX_LEN;
997 break;
998 }
9c80d176
SZ
999 /* FALL THROUGH */
1000
1001 /* Limit Jumbo Frame size */
1002 case e1000_82571:
1003 case e1000_82572:
1004 case e1000_ich9lan:
1005 case e1000_ich10lan:
2d0e5700 1006 case e1000_pch2lan:
9c80d176
SZ
1007 case e1000_82574:
1008 case e1000_80003es2lan:
1eca7b82 1009 max_frame_size = 9234;
7ea52455 1010 break;
9c80d176 1011
2d0e5700
SZ
1012 case e1000_pchlan:
1013 max_frame_size = 4096;
1014 break;
1015
9c80d176
SZ
1016 /* Adapters that do not support jumbo frames */
1017 case e1000_82542:
2d0e5700 1018 case e1000_82583:
9c80d176 1019 case e1000_ich8lan:
7ea52455
SZ
1020 max_frame_size = ETHER_MAX_LEN;
1021 break;
9c80d176 1022
7ea52455
SZ
1023 default:
1024 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1025 break;
1026 }
9c80d176
SZ
1027 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1028 ETHER_CRC_LEN) {
984263bc 1029 error = EINVAL;
9c80d176 1030 break;
984263bc 1031 }
9c80d176
SZ
1032
1033 ifp->if_mtu = ifr->ifr_mtu;
1034 adapter->max_frame_size =
1035 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1036
1037 if (ifp->if_flags & IFF_RUNNING)
1038 em_init(adapter);
984263bc 1039 break;
9c80d176 1040
984263bc 1041 case SIOCSIFFLAGS:
984263bc 1042 if (ifp->if_flags & IFF_UP) {
9c80d176
SZ
1043 if ((ifp->if_flags & IFF_RUNNING)) {
1044 if ((ifp->if_flags ^ adapter->if_flags) &
1045 (IFF_PROMISC | IFF_ALLMULTI)) {
1046 em_disable_promisc(adapter);
1047 em_set_promisc(adapter);
1048 }
1049 } else {
78195a76 1050 em_init(adapter);
87307ba1 1051 }
9c80d176
SZ
1052 } else if (ifp->if_flags & IFF_RUNNING) {
1053 em_stop(adapter);
984263bc 1054 }
87307ba1 1055 adapter->if_flags = ifp->if_flags;
984263bc 1056 break;
9c80d176 1057
984263bc
MD
1058 case SIOCADDMULTI:
1059 case SIOCDELMULTI:
984263bc
MD
1060 if (ifp->if_flags & IFF_RUNNING) {
1061 em_disable_intr(adapter);
1062 em_set_multi(adapter);
9c80d176
SZ
1063 if (adapter->hw.mac.type == e1000_82542 &&
1064 adapter->hw.revision_id == E1000_REVISION_2)
1065 em_init_rx_unit(adapter);
1eca7b82 1066#ifdef DEVICE_POLLING
9c80d176 1067 if (!(ifp->if_flags & IFF_POLLING))
1eca7b82 1068#endif
9c80d176 1069 em_enable_intr(adapter);
984263bc
MD
1070 }
1071 break;
9c80d176 1072
984263bc 1073 case SIOCSIFMEDIA:
87307ba1 1074 /* Check SOL/IDER usage */
9c80d176
SZ
1075 if (e1000_check_reset_block(&adapter->hw)) {
1076 device_printf(adapter->dev, "Media change is"
1077 " blocked due to SOL/IDER session.\n");
87307ba1
SZ
1078 break;
1079 }
9c80d176
SZ
1080 /* FALL THROUGH */
1081
984263bc 1082 case SIOCGIFMEDIA:
984263bc
MD
1083 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1084 break;
9c80d176 1085
984263bc 1086 case SIOCSIFCAP:
9c80d176 1087 reinit = 0;
984263bc
MD
1088 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1089 if (mask & IFCAP_HWCSUM) {
9c80d176 1090 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
1eca7b82 1091 reinit = 1;
984263bc 1092 }
1eca7b82
SZ
1093 if (mask & IFCAP_VLAN_HWTAGGING) {
1094 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1095 reinit = 1;
1096 }
9c80d176 1097 if (reinit && (ifp->if_flags & IFF_RUNNING))
1eca7b82 1098 em_init(adapter);
984263bc 1099 break;
9c80d176 1100
984263bc 1101 default:
1eca7b82
SZ
1102 error = ether_ioctl(ifp, command, data);
1103 break;
984263bc 1104 }
87307ba1 1105 return (error);
984263bc
MD
1106}
1107
984263bc
MD
1108static void
1109em_watchdog(struct ifnet *ifp)
1110{
1eca7b82 1111 struct adapter *adapter = ifp->if_softc;
984263bc 1112
9c80d176
SZ
1113 ASSERT_SERIALIZED(ifp->if_serializer);
1114
1115 /*
1116 * The timer is set to 5 every time start queues a packet.
1117 * Then txeof keeps resetting it as long as it cleans at
1118 * least one descriptor.
1119 * Finally, anytime all descriptors are clean the timer is
1120 * set to 0.
1121 */
1122
9f60d74b
SZ
1123 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1124 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1125 /*
1126 * If we reach here, all TX jobs are completed and
1127 * the TX engine should have been idled for some time.
1128 * We don't need to call if_devstart() here.
1129 */
1130 ifp->if_flags &= ~IFF_OACTIVE;
1131 ifp->if_timer = 0;
1132 return;
1133 }
1134
1eca7b82
SZ
1135 /*
1136 * If we are in this routine because of pause frames, then
984263bc
MD
1137 * don't reset the hardware.
1138 */
9c80d176
SZ
1139 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1140 E1000_STATUS_TXOFF) {
984263bc
MD
1141 ifp->if_timer = EM_TX_TIMEOUT;
1142 return;
1143 }
1144
9c80d176 1145 if (e1000_check_for_link(&adapter->hw) == 0)
f647ad3d 1146 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc 1147
9c80d176
SZ
1148 ifp->if_oerrors++;
1149 adapter->watchdog_events++;
1150
984263bc
MD
1151 em_init(adapter);
1152
9c80d176
SZ
1153 if (!ifq_is_empty(&ifp->if_snd))
1154 if_devstart(ifp);
984263bc
MD
1155}
1156
984263bc 1157static void
9c80d176 1158em_init(void *xsc)
984263bc 1159{
9c80d176
SZ
1160 struct adapter *adapter = xsc;
1161 struct ifnet *ifp = &adapter->arpcom.ac_if;
1162 device_t dev = adapter->dev;
eac00e59 1163 uint32_t pba;
984263bc 1164
87307ba1
SZ
1165 ASSERT_SERIALIZED(ifp->if_serializer);
1166
984263bc
MD
1167 em_stop(adapter);
1168
eac00e59
SZ
1169 /*
1170 * Packet Buffer Allocation (PBA)
1171 * Writing PBA sets the receive portion of the buffer
1172 * the remainder is used for the transmit buffer.
1eca7b82
SZ
1173 *
1174 * Devices before the 82547 had a Packet Buffer of 64K.
1175 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1176 * After the 82547 the buffer was reduced to 40K.
1177 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1178 * Note: default does not leave enough room for Jumbo Frame >10k.
eac00e59 1179 */
9c80d176
SZ
1180 switch (adapter->hw.mac.type) {
1181 case e1000_82547:
1182 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1183 if (adapter->max_frame_size > 8192)
eac00e59 1184 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
7ea52455
SZ
1185 else
1186 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
eac00e59
SZ
1187 adapter->tx_fifo_head = 0;
1188 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1189 adapter->tx_fifo_size =
9c80d176 1190 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
7ea52455 1191 break;
9c80d176 1192
87307ba1 1193 /* Total Packet Buffer on these is 48K */
9c80d176
SZ
1194 case e1000_82571:
1195 case e1000_82572:
1196 case e1000_80003es2lan:
7ea52455
SZ
1197 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1198 break;
9c80d176
SZ
1199
1200 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
7ea52455
SZ
1201 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1202 break;
9c80d176
SZ
1203
1204 case e1000_82574:
2d0e5700 1205 case e1000_82583:
9c80d176 1206 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1eca7b82 1207 break;
9c80d176 1208
2d0e5700
SZ
1209 case e1000_ich8lan:
1210 pba = E1000_PBA_8K;
1211 break;
1212
9c80d176
SZ
1213 case e1000_ich9lan:
1214 case e1000_ich10lan:
1215#define E1000_PBA_10K 0x000A
b0ff1d56
MS
1216 pba = E1000_PBA_10K;
1217 break;
9c80d176 1218
2d0e5700
SZ
1219 case e1000_pchlan:
1220 case e1000_pch2lan:
1221 pba = E1000_PBA_26K;
9c80d176
SZ
1222 break;
1223
7ea52455
SZ
1224 default:
1225 /* Devices before 82547 had a Packet Buffer of 64K. */
9c80d176 1226 if (adapter->max_frame_size > 8192)
7ea52455
SZ
1227 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1228 else
1229 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
eac00e59 1230 }
9c80d176 1231 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
a4a205fa 1232
0d366ee7 1233 /* Get the latest mac address, User can use a LAA */
9c80d176
SZ
1234 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1235
1236 /* Put the address into the Receive Address Array */
1237 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1238
1239 /*
1240 * With the 82571 adapter, RAR[0] may be overwritten
1241 * when the other port is reset, we make a duplicate
1242 * in RAR[14] for that eventuality, this assures
1243 * the interface continues to function.
1244 */
1245 if (adapter->hw.mac.type == e1000_82571) {
1246 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1247 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1248 E1000_RAR_ENTRIES - 1);
1249 }
0d366ee7 1250
2d0e5700
SZ
1251 /* Reset the hardware */
1252 if (em_reset(adapter)) {
1253 device_printf(dev, "Unable to reset the hardware\n");
9c80d176 1254 /* XXX em_stop()? */
984263bc
MD
1255 return;
1256 }
87307ba1 1257 em_update_link_status(adapter);
984263bc 1258
9c80d176
SZ
1259 /* Setup VLAN support, basic and offload if available */
1260 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
984263bc 1261
9c80d176
SZ
1262 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1263 uint32_t ctrl;
1264
1265 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1266 ctrl |= E1000_CTRL_VME;
1267 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
87307ba1
SZ
1268 }
1269
9c80d176
SZ
1270 /* Set hardware offload abilities */
1271 if (ifp->if_capenable & IFCAP_TXCSUM)
1272 ifp->if_hwassist = EM_CSUM_FEATURES;
1273 else
1274 ifp->if_hwassist = 0;
1275
1276 /* Configure for OS presence */
1277 em_get_mgmt(adapter);
1278
984263bc 1279 /* Prepare transmit descriptors and buffers */
9c80d176
SZ
1280 em_init_tx_ring(adapter);
1281 em_init_tx_unit(adapter);
984263bc
MD
1282
1283 /* Setup Multicast table */
1284 em_set_multi(adapter);
1285
1286 /* Prepare receive descriptors and buffers */
9c80d176
SZ
1287 if (em_init_rx_ring(adapter)) {
1288 device_printf(dev, "Could not setup receive structures\n");
984263bc 1289 em_stop(adapter);
984263bc
MD
1290 return;
1291 }
9c80d176 1292 em_init_rx_unit(adapter);
7ea52455 1293
87307ba1 1294 /* Don't lose promiscuous settings */
0d366ee7 1295 em_set_promisc(adapter);
984263bc 1296
984263bc
MD
1297 ifp->if_flags |= IFF_RUNNING;
1298 ifp->if_flags &= ~IFF_OACTIVE;
1299
9c80d176
SZ
1300 callout_reset(&adapter->timer, hz, em_timer, adapter);
1301 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1302
1303 /* MSI/X configuration for 82574 */
1304 if (adapter->hw.mac.type == e1000_82574) {
1305 int tmp;
1306
1307 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1308 tmp |= E1000_CTRL_EXT_PBA_CLR;
1309 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1310 /*
2d0e5700 1311 * XXX MSIX
9c80d176
SZ
1312 * Set the IVAR - interrupt vector routing.
1313 * Each nibble represents a vector, high bit
1314 * is enable, other 3 bits are the MSIX table
1315 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1316 * Link (other) to 2, hence the magic number.
1317 */
1318 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1319 }
1eca7b82
SZ
1320
1321#ifdef DEVICE_POLLING
9c80d176
SZ
1322 /*
1323 * Only enable interrupts if we are not polling, make sure
1324 * they are off otherwise.
1325 */
1eca7b82
SZ
1326 if (ifp->if_flags & IFF_POLLING)
1327 em_disable_intr(adapter);
1328 else
9c80d176
SZ
1329#endif /* DEVICE_POLLING */
1330 em_enable_intr(adapter);
0d366ee7 1331
2d0e5700
SZ
1332 /* AMT based hardware can now take control from firmware */
1333 if (adapter->has_manage && adapter->has_amt &&
1334 adapter->hw.mac.type >= e1000_82571)
1335 em_get_hw_control(adapter);
1336
0d366ee7 1337 /* Don't reset the phy next time init gets called */
9c80d176 1338 adapter->hw.phy.reset_disable = TRUE;
984263bc
MD
1339}
1340
984263bc 1341#ifdef DEVICE_POLLING
f647ad3d
JS
1342
1343static void
984263bc
MD
1344em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1345{
f647ad3d
JS
1346 struct adapter *adapter = ifp->if_softc;
1347 uint32_t reg_icr;
984263bc 1348
78195a76
MD
1349 ASSERT_SERIALIZED(ifp->if_serializer);
1350
9c80d176 1351 switch (cmd) {
9c095379
MD
1352 case POLL_REGISTER:
1353 em_disable_intr(adapter);
1354 break;
9c80d176 1355
9c095379 1356 case POLL_DEREGISTER:
f647ad3d 1357 em_enable_intr(adapter);
9c095379 1358 break;
9c80d176 1359
9c095379 1360 case POLL_AND_CHECK_STATUS:
9c80d176 1361 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
f647ad3d 1362 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
9ccd8c1f 1363 callout_stop(&adapter->timer);
9c80d176 1364 adapter->hw.mac.get_link_status = 1;
87307ba1 1365 em_update_link_status(adapter);
9c80d176 1366 callout_reset(&adapter->timer, hz, em_timer, adapter);
f647ad3d 1367 }
9c80d176 1368 /* FALL THROUGH */
9c095379
MD
1369 case POLL_ONLY:
1370 if (ifp->if_flags & IFF_RUNNING) {
87307ba1
SZ
1371 em_rxeof(adapter, count);
1372 em_txeof(adapter);
1eca7b82 1373
9c095379 1374 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1375 if_devstart(ifp);
9c095379
MD
1376 }
1377 break;
f647ad3d 1378 }
984263bc 1379}
9c095379 1380
984263bc
MD
1381#endif /* DEVICE_POLLING */
1382
984263bc 1383static void
9c80d176 1384em_intr(void *xsc)
984263bc 1385{
9c80d176
SZ
1386 struct adapter *adapter = xsc;
1387 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1388 uint32_t reg_icr;
984263bc 1389
07855a48 1390 logif(intr_beg);
78195a76
MD
1391 ASSERT_SERIALIZED(ifp->if_serializer);
1392
9c80d176
SZ
1393 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1394
1395 if ((adapter->hw.mac.type >= e1000_82571 &&
1eca7b82
SZ
1396 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1397 reg_icr == 0) {
07855a48 1398 logif(intr_end);
984263bc 1399 return;
07855a48 1400 }
984263bc 1401
87307ba1 1402 /*
9c80d176
SZ
1403 * XXX: some laptops trigger several spurious interrupts
1404 * on em(4) when in the resume cycle. The ICR register
1405 * reports all-ones value in this case. Processing such
1406 * interrupts would lead to a freeze. I don't know why.
87307ba1
SZ
1407 */
1408 if (reg_icr == 0xffffffff) {
1409 logif(intr_end);
1410 return;
984263bc
MD
1411 }
1412
79938e61 1413 if (ifp->if_flags & IFF_RUNNING) {
9f60d74b 1414 if (reg_icr &
6643d744 1415 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
9f60d74b 1416 em_rxeof(adapter, -1);
6643d744 1417 if (reg_icr & E1000_ICR_TXDW) {
9f60d74b
SZ
1418 em_txeof(adapter);
1419 if (!ifq_is_empty(&ifp->if_snd))
1420 if_devstart(ifp);
1421 }
f647ad3d 1422 }
984263bc 1423
87307ba1
SZ
1424 /* Link status change */
1425 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1426 callout_stop(&adapter->timer);
9c80d176 1427 adapter->hw.mac.get_link_status = 1;
87307ba1 1428 em_update_link_status(adapter);
9c80d176
SZ
1429
1430 /* Deal with TX cruft when link lost */
1431 em_tx_purge(adapter);
1432
1433 callout_reset(&adapter->timer, hz, em_timer, adapter);
87307ba1
SZ
1434 }
1435
1436 if (reg_icr & E1000_ICR_RXO)
1437 adapter->rx_overruns++;
1438
07855a48 1439 logif(intr_end);
984263bc
MD
1440}
1441
984263bc
MD
1442static void
1443em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1444{
87307ba1 1445 struct adapter *adapter = ifp->if_softc;
1eca7b82 1446 u_char fiber_type = IFM_1000_SX;
984263bc 1447
78195a76
MD
1448 ASSERT_SERIALIZED(ifp->if_serializer);
1449
87307ba1 1450 em_update_link_status(adapter);
984263bc
MD
1451
1452 ifmr->ifm_status = IFM_AVALID;
1453 ifmr->ifm_active = IFM_ETHER;
1454
1455 if (!adapter->link_active)
1456 return;
1457
1458 ifmr->ifm_status |= IFM_ACTIVE;
1459
9c80d176
SZ
1460 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1461 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1462 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
1463 fiber_type = IFM_1000_LX;
1464 ifmr->ifm_active |= fiber_type | IFM_FDX;
984263bc
MD
1465 } else {
1466 switch (adapter->link_speed) {
1467 case 10:
1468 ifmr->ifm_active |= IFM_10_T;
1469 break;
1470 case 100:
1471 ifmr->ifm_active |= IFM_100_TX;
1472 break;
9c80d176 1473
984263bc 1474 case 1000:
7f259627 1475 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD
1476 break;
1477 }
1478 if (adapter->link_duplex == FULL_DUPLEX)
1479 ifmr->ifm_active |= IFM_FDX;
1480 else
1481 ifmr->ifm_active |= IFM_HDX;
1482 }
984263bc
MD
1483}
1484
984263bc
MD
1485static int
1486em_media_change(struct ifnet *ifp)
1487{
87307ba1
SZ
1488 struct adapter *adapter = ifp->if_softc;
1489 struct ifmedia *ifm = &adapter->media;
984263bc 1490
78195a76 1491 ASSERT_SERIALIZED(ifp->if_serializer);
9c095379 1492
87307ba1
SZ
1493 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1494 return (EINVAL);
1495
984263bc
MD
1496 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1497 case IFM_AUTO:
9c80d176
SZ
1498 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1499 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
984263bc 1500 break;
9c80d176 1501
1eca7b82 1502 case IFM_1000_LX:
984263bc 1503 case IFM_1000_SX:
7f259627 1504 case IFM_1000_T:
9c80d176
SZ
1505 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1506 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
984263bc 1507 break;
9c80d176 1508
984263bc 1509 case IFM_100_TX:
9c80d176
SZ
1510 adapter->hw.mac.autoneg = FALSE;
1511 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1512 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1513 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
984263bc 1514 else
9c80d176 1515 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
984263bc 1516 break;
9c80d176 1517
984263bc 1518 case IFM_10_T:
9c80d176
SZ
1519 adapter->hw.mac.autoneg = FALSE;
1520 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1521 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1522 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
984263bc 1523 else
9c80d176 1524 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
984263bc 1525 break;
9c80d176 1526
984263bc 1527 default:
f647ad3d 1528 if_printf(ifp, "Unsupported media type\n");
9c80d176 1529 break;
984263bc 1530 }
9c80d176 1531
f647ad3d 1532 /*
9c80d176 1533 * As the speed/duplex settings my have changed we need to
f647ad3d
JS
1534 * reset the PHY.
1535 */
9c80d176 1536 adapter->hw.phy.reset_disable = FALSE;
984263bc 1537
78195a76 1538 em_init(adapter);
984263bc 1539
9c80d176 1540 return (0);
9ccd8c1f
JS
1541}
1542
984263bc 1543static int
9c80d176 1544em_encap(struct adapter *adapter, struct mbuf **m_headp)
9ccd8c1f 1545{
9c80d176 1546 bus_dma_segment_t segs[EM_MAX_SCATTER];
1eca7b82 1547 bus_dmamap_t map;
9c80d176
SZ
1548 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1549 struct e1000_tx_desc *ctxd = NULL;
002b3a05 1550 struct mbuf *m_head = *m_headp;
9f60d74b 1551 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
9c80d176 1552 int maxsegs, nsegs, i, j, first, last = 0, error;
984263bc 1553
3752657e 1554 if (m_head->m_len < EM_TXCSUM_MINHL &&
002b3a05
SZ
1555 (m_head->m_flags & EM_CSUM_FEATURES)) {
1556 /*
1557 * Make sure that ethernet header and ip.ip_hl are in
1558 * contiguous memory, since if TXCSUM is enabled, later
1559 * TX context descriptor's setup need to access ip.ip_hl.
1560 */
1561 error = em_txcsum_pullup(adapter, m_headp);
1562 if (error) {
1563 KKASSERT(*m_headp == NULL);
1564 return error;
1565 }
1566 m_head = *m_headp;
1567 }
1568
9c80d176
SZ
1569 txd_upper = txd_lower = 0;
1570 txd_used = 0;
87307ba1
SZ
1571
1572 /*
9c80d176
SZ
1573 * Capture the first descriptor index, this descriptor
1574 * will have the index of the EOP which is the only one
1575 * that now gets a DONE bit writeback.
87307ba1 1576 */
9c80d176
SZ
1577 first = adapter->next_avail_tx_desc;
1578 tx_buffer = &adapter->tx_buffer_area[first];
1579 tx_buffer_mapped = tx_buffer;
1580 map = tx_buffer->map;
87307ba1 1581
9c80d176
SZ
1582 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1583 KASSERT(maxsegs >= adapter->spare_tx_desc,
1584 ("not enough spare TX desc\n"));
1585 if (adapter->pcix_82544) {
1586 /* Half it; see the comment in em_attach() */
1587 maxsegs >>= 1;
9ccd8c1f 1588 }
9c80d176
SZ
1589 if (maxsegs > EM_MAX_SCATTER)
1590 maxsegs = EM_MAX_SCATTER;
984263bc 1591
9c80d176
SZ
1592 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1593 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1594 if (error) {
1595 if (error == ENOBUFS)
1596 adapter->mbuf_alloc_failed++;
1597 else
1598 adapter->no_tx_dma_setup++;
984263bc 1599
9c80d176
SZ
1600 m_freem(*m_headp);
1601 *m_headp = NULL;
1602 return error;
7ea52455 1603 }
9c80d176 1604 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
984263bc 1605
9c80d176 1606 m_head = *m_headp;
9f60d74b 1607 adapter->tx_nsegs += nsegs;
9c80d176 1608
002b3a05 1609 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
9c80d176 1610 /* TX csum offloading will consume one TX desc */
9f60d74b
SZ
1611 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1612 &txd_upper, &txd_lower);
9c80d176 1613 }
984263bc 1614 i = adapter->next_avail_tx_desc;
87307ba1
SZ
1615
1616 /* Set up our transmit descriptors */
9c80d176 1617 for (j = 0; j < nsegs; j++) {
9ccd8c1f
JS
1618 /* If adapter is 82544 and on PCIX bus */
1619 if(adapter->pcix_82544) {
87307ba1
SZ
1620 DESC_ARRAY desc_array;
1621 uint32_t array_elements, counter;
1622
9c80d176 1623 /*
f647ad3d
JS
1624 * Check the Address and Length combination and
1625 * split the data accordingly
9ccd8c1f 1626 */
9c80d176
SZ
1627 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1628 segs[j].ds_len, &desc_array);
9ccd8c1f 1629 for (counter = 0; counter < array_elements; counter++) {
9c80d176
SZ
1630 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1631
9ccd8c1f 1632 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176
SZ
1633 ctxd = &adapter->tx_desc_base[i];
1634
1635 ctxd->buffer_addr = htole64(
1636 desc_array.descriptor[counter].address);
1637 ctxd->lower.data = htole32(
2af74b85 1638 E1000_TXD_CMD_IFCS | txd_lower |
9c80d176
SZ
1639 desc_array.descriptor[counter].length);
1640 ctxd->upper.data = htole32(txd_upper);
87307ba1
SZ
1641
1642 last = i;
9ccd8c1f
JS
1643 if (++i == adapter->num_tx_desc)
1644 i = 0;
1645
9ccd8c1f 1646 txd_used++;
9c80d176 1647 }
9ccd8c1f 1648 } else {
0d366ee7 1649 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176 1650 ctxd = &adapter->tx_desc_base[i];
9ccd8c1f 1651
9c80d176 1652 ctxd->buffer_addr = htole64(segs[j].ds_addr);
2af74b85 1653 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
9c80d176
SZ
1654 txd_lower | segs[j].ds_len);
1655 ctxd->upper.data = htole32(txd_upper);
984263bc 1656
87307ba1 1657 last = i;
0d366ee7
MD
1658 if (++i == adapter->num_tx_desc)
1659 i = 0;
0d366ee7 1660 }
984263bc 1661 }
9ccd8c1f 1662
984263bc 1663 adapter->next_avail_tx_desc = i;
9c80d176
SZ
1664 if (adapter->pcix_82544) {
1665 KKASSERT(adapter->num_tx_desc_avail > txd_used);
9ccd8c1f 1666 adapter->num_tx_desc_avail -= txd_used;
9c80d176
SZ
1667 } else {
1668 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1669 adapter->num_tx_desc_avail -= nsegs;
1670 }
984263bc 1671
9c80d176 1672 /* Handle VLAN tag */
83790f85 1673 if (m_head->m_flags & M_VLANTAG) {
9c80d176
SZ
1674 /* Set the vlan id. */
1675 ctxd->upper.fields.special =
1676 htole16(m_head->m_pkthdr.ether_vlantag);
9ccd8c1f 1677
f647ad3d 1678 /* Tell hardware to add tag */
9c80d176 1679 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
f647ad3d 1680 }
984263bc
MD
1681
1682 tx_buffer->m_head = m_head;
9c80d176 1683 tx_buffer_mapped->map = tx_buffer->map;
1eca7b82 1684 tx_buffer->map = map;
9ccd8c1f 1685
9f60d74b
SZ
1686 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1687 adapter->tx_nsegs = 0;
4e4e8481
SZ
1688
1689 /*
1690 * Report Status (RS) is turned on
1691 * every tx_int_nsegs descriptors.
1692 */
9f60d74b
SZ
1693 cmd = E1000_TXD_CMD_RS;
1694
b4b0a2b4
SZ
1695 /*
1696 * Keep track of the descriptor, which will
1697 * be written back by hardware.
1698 */
9f60d74b
SZ
1699 adapter->tx_dd[adapter->tx_dd_tail] = last;
1700 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1701 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1702 }
1703
9ccd8c1f 1704 /*
984263bc 1705 * Last Descriptor of Packet needs End Of Packet (EOP)
87307ba1 1706 */
9f60d74b 1707 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
87307ba1
SZ
1708
1709 /*
9c80d176 1710 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
984263bc
MD
1711 * that this frame is available to transmit.
1712 */
9c80d176 1713 if (adapter->hw.mac.type == e1000_82547 &&
984263bc 1714 adapter->link_duplex == HALF_DUPLEX) {
cfefda96 1715 em_82547_move_tail_serialized(adapter);
9ccd8c1f 1716 } else {
9c80d176
SZ
1717 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1718 if (adapter->hw.mac.type == e1000_82547) {
cfefda96 1719 em_82547_update_fifo_head(adapter,
9c80d176 1720 m_head->m_pkthdr.len);
984263bc
MD
1721 }
1722 }
87307ba1 1723 return (0);
984263bc
MD
1724}
1725
9c80d176 1726/*
984263bc 1727 * 82547 workaround to avoid controller hang in half-duplex environment.
87307ba1 1728 * The workaround is to avoid queuing a large packet that would span
9c80d176
SZ
1729 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1730 * in this case. We do that only when FIFO is quiescent.
1731 */
9c095379 1732static void
1eca7b82 1733em_82547_move_tail_serialized(struct adapter *adapter)
9c095379 1734{
9c80d176
SZ
1735 struct e1000_tx_desc *tx_desc;
1736 uint16_t hw_tdt, sw_tdt, length = 0;
1737 bool eop = 0;
984263bc 1738
9c80d176
SZ
1739 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1740
1741 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
984263bc 1742 sw_tdt = adapter->next_avail_tx_desc;
f647ad3d 1743
984263bc
MD
1744 while (hw_tdt != sw_tdt) {
1745 tx_desc = &adapter->tx_desc_base[hw_tdt];
1746 length += tx_desc->lower.flags.length;
1747 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
87307ba1 1748 if (++hw_tdt == adapter->num_tx_desc)
984263bc
MD
1749 hw_tdt = 0;
1750
87307ba1 1751 if (eop) {
984263bc 1752 if (em_82547_fifo_workaround(adapter, length)) {
eac00e59 1753 adapter->tx_fifo_wrk_cnt++;
9ccd8c1f
JS
1754 callout_reset(&adapter->tx_fifo_timer, 1,
1755 em_82547_move_tail, adapter);
1756 break;
984263bc 1757 }
9c80d176 1758 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
9ccd8c1f
JS
1759 em_82547_update_fifo_head(adapter, length);
1760 length = 0;
984263bc 1761 }
9c80d176
SZ
1762 }
1763}
1764
1765static void
1766em_82547_move_tail(void *xsc)
1767{
1768 struct adapter *adapter = xsc;
1769 struct ifnet *ifp = &adapter->arpcom.ac_if;
1770
1771 lwkt_serialize_enter(ifp->if_serializer);
1772 em_82547_move_tail_serialized(adapter);
1773 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1774}
1775
1776static int
1777em_82547_fifo_workaround(struct adapter *adapter, int len)
1778{
1779 int fifo_space, fifo_pkt_len;
1780
1eca7b82 1781 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
984263bc
MD
1782
1783 if (adapter->link_duplex == HALF_DUPLEX) {
eac00e59 1784 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
984263bc
MD
1785
1786 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
f647ad3d 1787 if (em_82547_tx_fifo_reset(adapter))
87307ba1 1788 return (0);
f647ad3d 1789 else
87307ba1 1790 return (1);
984263bc
MD
1791 }
1792 }
87307ba1 1793 return (0);
984263bc
MD
1794}
1795
1796static void
1797em_82547_update_fifo_head(struct adapter *adapter, int len)
1798{
1eca7b82 1799 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
f647ad3d 1800
984263bc
MD
1801 /* tx_fifo_head is always 16 byte aligned */
1802 adapter->tx_fifo_head += fifo_pkt_len;
eac00e59
SZ
1803 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1804 adapter->tx_fifo_head -= adapter->tx_fifo_size;
984263bc
MD
1805}
1806
984263bc
MD
1807static int
1808em_82547_tx_fifo_reset(struct adapter *adapter)
7ea52455 1809{
984263bc
MD
1810 uint32_t tctl;
1811
9c80d176
SZ
1812 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1813 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1814 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1815 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1816 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1817 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1818 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
984263bc 1819 /* Disable TX unit */
9c80d176
SZ
1820 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1821 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1822 tctl & ~E1000_TCTL_EN);
984263bc
MD
1823
1824 /* Reset FIFO pointers */
9c80d176
SZ
1825 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1826 adapter->tx_head_addr);
1827 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1828 adapter->tx_head_addr);
1829 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1830 adapter->tx_head_addr);
1831 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1832 adapter->tx_head_addr);
984263bc
MD
1833
1834 /* Re-enable TX unit */
9c80d176 1835 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
1836 E1000_WRITE_FLUSH(&adapter->hw);
1837
1838 adapter->tx_fifo_head = 0;
eac00e59 1839 adapter->tx_fifo_reset_cnt++;
984263bc 1840
87307ba1 1841 return (TRUE);
eac00e59 1842 } else {
87307ba1 1843 return (FALSE);
984263bc
MD
1844 }
1845}
1846
1847static void
f647ad3d 1848em_set_promisc(struct adapter *adapter)
984263bc 1849{
9c80d176 1850 struct ifnet *ifp = &adapter->arpcom.ac_if;
1eca7b82 1851 uint32_t reg_rctl;
984263bc 1852
9c80d176 1853 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc
MD
1854
1855 if (ifp->if_flags & IFF_PROMISC) {
1856 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
9c80d176
SZ
1857 /* Turn this on if you want to see bad packets */
1858 if (em_debug_sbp)
1859 reg_rctl |= E1000_RCTL_SBP;
1860 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1861 } else if (ifp->if_flags & IFF_ALLMULTI) {
1862 reg_rctl |= E1000_RCTL_MPE;
1863 reg_rctl &= ~E1000_RCTL_UPE;
9c80d176 1864 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc 1865 }
984263bc
MD
1866}
1867
1868static void
f647ad3d 1869em_disable_promisc(struct adapter *adapter)
984263bc 1870{
f647ad3d 1871 uint32_t reg_rctl;
984263bc 1872
9c80d176 1873 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc 1874
9c80d176
SZ
1875 reg_rctl &= ~E1000_RCTL_UPE;
1876 reg_rctl &= ~E1000_RCTL_MPE;
1877 reg_rctl &= ~E1000_RCTL_SBP;
1878 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1879}
1880
984263bc 1881static void
f647ad3d 1882em_set_multi(struct adapter *adapter)
984263bc 1883{
9c80d176 1884 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1885 struct ifmultiaddr *ifma;
9c80d176 1886 uint32_t reg_rctl = 0;
2d0e5700 1887 uint8_t *mta;
f647ad3d 1888 int mcnt = 0;
f647ad3d 1889
2d0e5700
SZ
1890 mta = adapter->mta;
1891 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1892
9c80d176
SZ
1893 if (adapter->hw.mac.type == e1000_82542 &&
1894 adapter->hw.revision_id == E1000_REVISION_2) {
1895 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1896 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1897 e1000_pci_clear_mwi(&adapter->hw);
f647ad3d 1898 reg_rctl |= E1000_RCTL_RST;
9c80d176 1899 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d
JS
1900 msec_delay(5);
1901 }
984263bc 1902
441d34b2 1903 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
f647ad3d
JS
1904 if (ifma->ifma_addr->sa_family != AF_LINK)
1905 continue;
1906
1907 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1908 break;
984263bc 1909
f647ad3d 1910 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
9c80d176 1911 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
f647ad3d
JS
1912 mcnt++;
1913 }
1914
1915 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
9c80d176 1916 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1917 reg_rctl |= E1000_RCTL_MPE;
9c80d176 1918 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
7ea52455 1919 } else {
6a5a645e 1920 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
7ea52455 1921 }
f647ad3d 1922
9c80d176
SZ
1923 if (adapter->hw.mac.type == e1000_82542 &&
1924 adapter->hw.revision_id == E1000_REVISION_2) {
1925 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1926 reg_rctl &= ~E1000_RCTL_RST;
9c80d176 1927 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d 1928 msec_delay(5);
9c80d176
SZ
1929 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1930 e1000_pci_set_mwi(&adapter->hw);
f647ad3d
JS
1931 }
1932}
984263bc 1933
9c80d176
SZ
1934/*
1935 * This routine checks for link status and updates statistics.
1936 */
984263bc 1937static void
9c80d176 1938em_timer(void *xsc)
984263bc 1939{
9c80d176
SZ
1940 struct adapter *adapter = xsc;
1941 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 1942
78195a76 1943 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1944
87307ba1 1945 em_update_link_status(adapter);
9c80d176
SZ
1946 em_update_stats(adapter);
1947
1948 /* Reset LAA into RAR[0] on 82571 */
1949 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1950 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1951
1952 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
984263bc 1953 em_print_hw_stats(adapter);
9c80d176 1954
984263bc
MD
1955 em_smartspeed(adapter);
1956
9c80d176 1957 callout_reset(&adapter->timer, hz, em_timer, adapter);
984263bc 1958
78195a76 1959 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1960}
1961
1962static void
87307ba1 1963em_update_link_status(struct adapter *adapter)
984263bc 1964{
9c80d176
SZ
1965 struct e1000_hw *hw = &adapter->hw;
1966 struct ifnet *ifp = &adapter->arpcom.ac_if;
1967 device_t dev = adapter->dev;
1968 uint32_t link_check = 0;
1969
1970 /* Get the cached link value or read phy for real */
1971 switch (hw->phy.media_type) {
1972 case e1000_media_type_copper:
1973 if (hw->mac.get_link_status) {
1974 /* Do the work to read phy */
1975 e1000_check_for_link(hw);
1976 link_check = !hw->mac.get_link_status;
1977 if (link_check) /* ESB2 fix */
1978 e1000_cfg_on_link_up(hw);
1979 } else {
1980 link_check = TRUE;
984263bc 1981 }
9c80d176
SZ
1982 break;
1983
1984 case e1000_media_type_fiber:
1985 e1000_check_for_link(hw);
1986 link_check =
1987 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1988 break;
1989
1990 case e1000_media_type_internal_serdes:
1991 e1000_check_for_link(hw);
1992 link_check = adapter->hw.mac.serdes_has_link;
1993 break;
1994
1995 case e1000_media_type_unknown:
1996 default:
1997 break;
1998 }
1999
2000 /* Now check for a transition */
2001 if (link_check && adapter->link_active == 0) {
2002 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2003 &adapter->link_duplex);
cb5a6be6
SZ
2004
2005 /*
2006 * Check if we should enable/disable SPEED_MODE bit on
2007 * 82571/82572
2008 */
2d0e5700
SZ
2009 if (adapter->link_speed != SPEED_1000 &&
2010 (hw->mac.type == e1000_82571 ||
2011 hw->mac.type == e1000_82572)) {
9c80d176
SZ
2012 int tarc0;
2013
2014 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 2015 tarc0 &= ~SPEED_MODE_BIT;
9c80d176 2016 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
984263bc 2017 }
9c80d176
SZ
2018 if (bootverbose) {
2019 device_printf(dev, "Link is up %d Mbps %s\n",
2020 adapter->link_speed,
2021 ((adapter->link_duplex == FULL_DUPLEX) ?
2022 "Full Duplex" : "Half Duplex"));
2023 }
2024 adapter->link_active = 1;
2025 adapter->smartspeed = 0;
2026 ifp->if_baudrate = adapter->link_speed * 1000000;
2027 ifp->if_link_state = LINK_STATE_UP;
2028 if_link_state_change(ifp);
2029 } else if (!link_check && adapter->link_active == 1) {
2030 ifp->if_baudrate = adapter->link_speed = 0;
2031 adapter->link_duplex = 0;
2032 if (bootverbose)
2033 device_printf(dev, "Link is Down\n");
2034 adapter->link_active = 0;
2035#if 0
2036 /* Link down, disable watchdog */
2037 if->if_timer = 0;
2038#endif
2039 ifp->if_link_state = LINK_STATE_DOWN;
2040 if_link_state_change(ifp);
984263bc 2041 }
984263bc
MD
2042}
2043
984263bc 2044static void
9c80d176 2045em_stop(struct adapter *adapter)
984263bc 2046{
9c80d176
SZ
2047 struct ifnet *ifp = &adapter->arpcom.ac_if;
2048 int i;
984263bc 2049
1eca7b82
SZ
2050 ASSERT_SERIALIZED(ifp->if_serializer);
2051
984263bc 2052 em_disable_intr(adapter);
9c80d176 2053
9ccd8c1f
JS
2054 callout_stop(&adapter->timer);
2055 callout_stop(&adapter->tx_fifo_timer);
984263bc 2056
984263bc 2057 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
af82d4bb 2058 ifp->if_timer = 0;
9c80d176
SZ
2059
2060 e1000_reset_hw(&adapter->hw);
2061 if (adapter->hw.mac.type >= e1000_82544)
2062 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2063
2064 for (i = 0; i < adapter->num_tx_desc; i++) {
2065 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2066
2067 if (tx_buffer->m_head != NULL) {
2068 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2069 m_freem(tx_buffer->m_head);
2070 tx_buffer->m_head = NULL;
2071 }
9c80d176
SZ
2072 }
2073
2074 for (i = 0; i < adapter->num_rx_desc; i++) {
2075 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2076
2077 if (rx_buffer->m_head != NULL) {
2078 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2079 m_freem(rx_buffer->m_head);
2080 rx_buffer->m_head = NULL;
2081 }
2082 }
c9ff32cc
SZ
2083
2084 if (adapter->fmp != NULL)
2085 m_freem(adapter->fmp);
2086 adapter->fmp = NULL;
2087 adapter->lmp = NULL;
51e6819f
SZ
2088
2089 adapter->csum_flags = 0;
2090 adapter->csum_ehlen = 0;
2091 adapter->csum_iphlen = 0;
9f60d74b
SZ
2092
2093 adapter->tx_dd_head = 0;
2094 adapter->tx_dd_tail = 0;
2095 adapter->tx_nsegs = 0;
984263bc
MD
2096}
2097
9c80d176
SZ
2098static int
2099em_get_hw_info(struct adapter *adapter)
984263bc
MD
2100{
2101 device_t dev = adapter->dev;
2102
984263bc
MD
2103 /* Save off the information about this board */
2104 adapter->hw.vendor_id = pci_get_vendor(dev);
2105 adapter->hw.device_id = pci_get_device(dev);
f647ad3d
JS
2106 adapter->hw.revision_id = pci_get_revid(dev);
2107 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
9c80d176 2108 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
984263bc 2109
9c80d176
SZ
2110 /* Do Shared Code Init and Setup */
2111 if (e1000_set_mac_type(&adapter->hw))
2112 return ENXIO;
2113 return 0;
984263bc
MD
2114}
2115
1eca7b82 2116static int
9c80d176 2117em_alloc_pci_res(struct adapter *adapter)
1eca7b82 2118{
9c80d176 2119 device_t dev = adapter->dev;
053f3ae6 2120 u_int intr_flags;
a483bd34 2121 int val, rid;
9c80d176
SZ
2122
2123 /* Enable bus mastering */
2124 pci_enable_busmaster(dev);
1eca7b82 2125
9c80d176
SZ
2126 adapter->memory_rid = EM_BAR_MEM;
2127 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2128 &adapter->memory_rid, RF_ACTIVE);
2129 if (adapter->memory == NULL) {
1eca7b82 2130 device_printf(dev, "Unable to allocate bus resource: memory\n");
9c80d176 2131 return (ENXIO);
1eca7b82
SZ
2132 }
2133 adapter->osdep.mem_bus_space_tag =
9c80d176 2134 rman_get_bustag(adapter->memory);
1eca7b82 2135 adapter->osdep.mem_bus_space_handle =
9c80d176
SZ
2136 rman_get_bushandle(adapter->memory);
2137
2138 /* XXX This is quite goofy, it is not actually used */
1eca7b82
SZ
2139 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2140
9c80d176
SZ
2141 /* Only older adapters use IO mapping */
2142 if (adapter->hw.mac.type > e1000_82543 &&
2143 adapter->hw.mac.type < e1000_82571) {
1eca7b82 2144 /* Figure our where our IO BAR is ? */
9c80d176 2145 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
1eca7b82 2146 val = pci_read_config(dev, rid, 4);
87307ba1 2147 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1eca7b82
SZ
2148 adapter->io_rid = rid;
2149 break;
2150 }
2151 rid += 4;
87307ba1
SZ
2152 /* check for 64bit BAR */
2153 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2154 rid += 4;
1eca7b82 2155 }
9c80d176 2156 if (rid >= PCIR_CARDBUSCIS) {
87307ba1
SZ
2157 device_printf(dev, "Unable to locate IO BAR\n");
2158 return (ENXIO);
9c80d176
SZ
2159 }
2160 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2161 &adapter->io_rid, RF_ACTIVE);
2162 if (adapter->ioport == NULL) {
1eca7b82 2163 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2164 "ioport\n");
2165 return (ENXIO);
1eca7b82 2166 }
87307ba1
SZ
2167 adapter->hw.io_base = 0;
2168 adapter->osdep.io_bus_space_tag =
9c80d176 2169 rman_get_bustag(adapter->ioport);
87307ba1 2170 adapter->osdep.io_bus_space_handle =
9c80d176 2171 rman_get_bushandle(adapter->ioport);
1eca7b82
SZ
2172 }
2173
053f3ae6
SZ
2174 adapter->intr_type = pci_alloc_1intr(dev, em_msi_enable,
2175 &adapter->intr_rid, &intr_flags);
2176
9c80d176 2177 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
053f3ae6 2178 &adapter->intr_rid, intr_flags);
9c80d176 2179 if (adapter->intr_res == NULL) {
1eca7b82 2180 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2181 "interrupt\n");
2182 return (ENXIO);
1eca7b82
SZ
2183 }
2184
9c80d176 2185 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1eca7b82 2186 adapter->hw.back = &adapter->osdep;
a483bd34 2187 return (0);
1eca7b82
SZ
2188}
2189
2190static void
9c80d176 2191em_free_pci_res(struct adapter *adapter)
1eca7b82 2192{
9c80d176 2193 device_t dev = adapter->dev;
1eca7b82 2194
9c80d176
SZ
2195 if (adapter->intr_res != NULL) {
2196 bus_release_resource(dev, SYS_RES_IRQ,
2197 adapter->intr_rid, adapter->intr_res);
1eca7b82 2198 }
9c80d176 2199
053f3ae6
SZ
2200 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2201 pci_release_msi(dev);
2202
9c80d176
SZ
2203 if (adapter->memory != NULL) {
2204 bus_release_resource(dev, SYS_RES_MEMORY,
2205 adapter->memory_rid, adapter->memory);
1eca7b82
SZ
2206 }
2207
9c80d176
SZ
2208 if (adapter->flash != NULL) {
2209 bus_release_resource(dev, SYS_RES_MEMORY,
2210 adapter->flash_rid, adapter->flash);
1eca7b82
SZ
2211 }
2212
9c80d176
SZ
2213 if (adapter->ioport != NULL) {
2214 bus_release_resource(dev, SYS_RES_IOPORT,
2215 adapter->io_rid, adapter->ioport);
1eca7b82
SZ
2216 }
2217}
2218
984263bc 2219static int
2d0e5700 2220em_reset(struct adapter *adapter)
984263bc 2221{
9c80d176
SZ
2222 device_t dev = adapter->dev;
2223 uint16_t rx_buffer_size;
7ea52455 2224
984263bc
MD
2225 /* When hardware is reset, fifo_head is also reset */
2226 adapter->tx_fifo_head = 0;
2227
87307ba1 2228 /* Set up smart power down as default off on newer adapters. */
1eca7b82 2229 if (!em_smart_pwr_down &&
9c80d176
SZ
2230 (adapter->hw.mac.type == e1000_82571 ||
2231 adapter->hw.mac.type == e1000_82572)) {
1eca7b82
SZ
2232 uint16_t phy_tmp = 0;
2233
87307ba1 2234 /* Speed up time to link by disabling smart power down. */
9c80d176
SZ
2235 e1000_read_phy_reg(&adapter->hw,
2236 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1eca7b82 2237 phy_tmp &= ~IGP02E1000_PM_SPD;
9c80d176
SZ
2238 e1000_write_phy_reg(&adapter->hw,
2239 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1eca7b82
SZ
2240 }
2241
7ea52455 2242 /*
87307ba1
SZ
2243 * These parameters control the automatic generation (Tx) and
2244 * response (Rx) to Ethernet PAUSE frames.
7ea52455
SZ
2245 * - High water mark should allow for at least two frames to be
2246 * received after sending an XOFF.
2247 * - Low water mark works best when it is very near the high water mark.
2248 * This allows the receiver to restart by sending XON when it has
9c80d176
SZ
2249 * drained a bit. Here we use an arbitary value of 1500 which will
2250 * restart after one full frame is pulled from the buffer. There
7ea52455
SZ
2251 * could be several smaller frames in the buffer and if so they will
2252 * not trigger the XON until their total number reduces the buffer
2253 * by 1500.
2254 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2255 */
9c80d176
SZ
2256 rx_buffer_size =
2257 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
7ea52455 2258
9c80d176
SZ
2259 adapter->hw.fc.high_water = rx_buffer_size -
2260 roundup2(adapter->max_frame_size, 1024);
2261 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2262
2263 if (adapter->hw.mac.type == e1000_80003es2lan)
2264 adapter->hw.fc.pause_time = 0xFFFF;
1eca7b82 2265 else
9c80d176 2266 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2d0e5700 2267
9c80d176 2268 adapter->hw.fc.send_xon = TRUE;
2d0e5700 2269
9c80d176 2270 adapter->hw.fc.requested_mode = e1000_fc_full;
7ea52455 2271
2d0e5700
SZ
2272 /* Workaround: no TX flow ctrl for PCH */
2273 if (adapter->hw.mac.type == e1000_pchlan)
2274 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2275
2276 /* Override - settings for PCH2LAN, ya its magic :) */
2277 if (adapter->hw.mac.type == e1000_pch2lan) {
2278 adapter->hw.fc.high_water = 0x5C20;
2279 adapter->hw.fc.low_water = 0x5048;
2280 adapter->hw.fc.pause_time = 0x0650;
2281 adapter->hw.fc.refresh_time = 0x0400;
2282
2283 /* Jumbos need adjusted PBA */
2284 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2285 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2286 else
2287 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2288 }
2289
2290 /* Issue a global reset */
2291 e1000_reset_hw(&adapter->hw);
2292 if (adapter->hw.mac.type >= e1000_82544)
2293 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2294
9c80d176
SZ
2295 if (e1000_init_hw(&adapter->hw) < 0) {
2296 device_printf(dev, "Hardware Initialization Failed\n");
87307ba1 2297 return (EIO);
984263bc
MD
2298 }
2299
2d0e5700
SZ
2300 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2301 e1000_get_phy_info(&adapter->hw);
9c80d176 2302 e1000_check_for_link(&adapter->hw);
984263bc 2303
87307ba1 2304 return (0);
984263bc
MD
2305}
2306
984263bc 2307static void
9c80d176 2308em_setup_ifp(struct adapter *adapter)
984263bc 2309{
9c80d176 2310 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2311
9c80d176
SZ
2312 if_initname(ifp, device_get_name(adapter->dev),
2313 device_get_unit(adapter->dev));
984263bc
MD
2314 ifp->if_softc = adapter;
2315 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c80d176 2316 ifp->if_init = em_init;
984263bc
MD
2317 ifp->if_ioctl = em_ioctl;
2318 ifp->if_start = em_start;
9c095379
MD
2319#ifdef DEVICE_POLLING
2320 ifp->if_poll = em_poll;
2321#endif
984263bc 2322 ifp->if_watchdog = em_watchdog;
e26dc3e9 2323 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
19b1d5b8 2324 ifq_set_ready(&ifp->if_snd);
984263bc 2325
9c80d176 2326 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
984263bc 2327
9c80d176
SZ
2328 if (adapter->hw.mac.type >= e1000_82543)
2329 ifp->if_capabilities = IFCAP_HWCSUM;
e095c7aa 2330
9c80d176
SZ
2331 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2332 ifp->if_capenable = ifp->if_capabilities;
984263bc 2333
9c80d176
SZ
2334 if (ifp->if_capenable & IFCAP_TXCSUM)
2335 ifp->if_hwassist = EM_CSUM_FEATURES;
21fa6062 2336
f647ad3d
JS
2337 /*
2338 * Tell the upper layer(s) we support long frames.
2339 */
2340 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
984263bc 2341
87307ba1 2342 /*
984263bc
MD
2343 * Specify the media types supported by this adapter and register
2344 * callbacks to update media and link information
2345 */
9c80d176
SZ
2346 ifmedia_init(&adapter->media, IFM_IMASK,
2347 em_media_change, em_media_status);
2348 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2349 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2350 u_char fiber_type = IFM_1000_SX; /* default type */
2351
2352 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
2353 fiber_type = IFM_1000_LX;
2354 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
984263bc 2355 0, NULL);
87307ba1 2356 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
984263bc
MD
2357 } else {
2358 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
87307ba1 2359 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
984263bc 2360 0, NULL);
87307ba1 2361 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
984263bc 2362 0, NULL);
87307ba1 2363 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
984263bc 2364 0, NULL);
9c80d176
SZ
2365 if (adapter->hw.phy.type != e1000_phy_ife) {
2366 ifmedia_add(&adapter->media,
2367 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2368 ifmedia_add(&adapter->media,
2369 IFM_ETHER | IFM_1000_T, 0, NULL);
2370 }
984263bc
MD
2371 }
2372 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2373 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
984263bc
MD
2374}
2375
9c80d176
SZ
2376
2377/*
2378 * Workaround for SmartSpeed on 82541 and 82547 controllers
2379 */
984263bc
MD
2380static void
2381em_smartspeed(struct adapter *adapter)
2382{
f647ad3d
JS
2383 uint16_t phy_tmp;
2384
9c80d176
SZ
2385 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2386 adapter->hw.mac.autoneg == 0 ||
2387 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
984263bc
MD
2388 return;
2389
f647ad3d
JS
2390 if (adapter->smartspeed == 0) {
2391 /*
2392 * If Master/Slave config fault is asserted twice,
9c80d176 2393 * we assume back-to-back
f647ad3d 2394 */
9c80d176 2395 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d
JS
2396 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2397 return;
9c80d176 2398 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d 2399 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
9c80d176
SZ
2400 e1000_read_phy_reg(&adapter->hw,
2401 PHY_1000T_CTRL, &phy_tmp);
f647ad3d
JS
2402 if (phy_tmp & CR_1000T_MS_ENABLE) {
2403 phy_tmp &= ~CR_1000T_MS_ENABLE;
9c80d176
SZ
2404 e1000_write_phy_reg(&adapter->hw,
2405 PHY_1000T_CTRL, phy_tmp);
f647ad3d 2406 adapter->smartspeed++;
9c80d176
SZ
2407 if (adapter->hw.mac.autoneg &&
2408 !e1000_phy_setup_autoneg(&adapter->hw) &&
2409 !e1000_read_phy_reg(&adapter->hw,
2410 PHY_CONTROL, &phy_tmp)) {
2411 phy_tmp |= MII_CR_AUTO_NEG_EN |
2412 MII_CR_RESTART_AUTO_NEG;
2413 e1000_write_phy_reg(&adapter->hw,
2414 PHY_CONTROL, phy_tmp);
f647ad3d
JS
2415 }
2416 }
2417 }
87307ba1 2418 return;
f647ad3d
JS
2419 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2420 /* If still no link, perhaps using 2/3 pair cable */
9c80d176 2421 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
f647ad3d 2422 phy_tmp |= CR_1000T_MS_ENABLE;
9c80d176
SZ
2423 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2424 if (adapter->hw.mac.autoneg &&
2425 !e1000_phy_setup_autoneg(&adapter->hw) &&
2426 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2427 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2428 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
f647ad3d
JS
2429 }
2430 }
9c80d176 2431
f647ad3d
JS
2432 /* Restart process after EM_SMARTSPEED_MAX iterations */
2433 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2434 adapter->smartspeed = 0;
984263bc
MD
2435}
2436
9ccd8c1f
JS
2437static int
2438em_dma_malloc(struct adapter *adapter, bus_size_t size,
87307ba1 2439 struct em_dma_alloc *dma)
9ccd8c1f 2440{
9c80d176
SZ
2441 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2442 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2443 &dma->dma_tag, &dma->dma_map,
2444 &dma->dma_paddr);
2445 if (dma->dma_vaddr == NULL)
2446 return ENOMEM;
2447 else
2448 return 0;
9ccd8c1f
JS
2449}
2450
2451static void
2452em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2453{
9c80d176
SZ
2454 if (dma->dma_tag == NULL)
2455 return;
2456 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2457 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2458 bus_dma_tag_destroy(dma->dma_tag);
984263bc
MD
2459}
2460
984263bc 2461static int
9c80d176 2462em_create_tx_ring(struct adapter *adapter)
984263bc 2463{
9c80d176 2464 device_t dev = adapter->dev;
1eca7b82 2465 struct em_buffer *tx_buffer;
1eca7b82
SZ
2466 int error, i;
2467
87307ba1
SZ
2468 adapter->tx_buffer_area =
2469 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2470 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 2471
9c80d176
SZ
2472 /*
2473 * Create DMA tags for tx buffers
2474 */
2475 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2476 1, 0, /* alignment, bounds */
2477 BUS_SPACE_MAXADDR, /* lowaddr */
2478 BUS_SPACE_MAXADDR, /* highaddr */
2479 NULL, NULL, /* filter, filterarg */
2480 EM_TSO_SIZE, /* maxsize */
2481 EM_MAX_SCATTER, /* nsegments */
2482 EM_MAX_SEGSIZE, /* maxsegsize */
2483 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2484 BUS_DMA_ONEBPAGE, /* flags */
2485 &adapter->txtag);
2486 if (error) {
2487 device_printf(dev, "Unable to allocate TX DMA tag\n");
2488 kfree(adapter->tx_buffer_area, M_DEVBUF);
2489 adapter->tx_buffer_area = NULL;
2490 return error;
2491 }
2492
2493 /*
2494 * Create DMA maps for tx buffers
2495 */
1eca7b82 2496 for (i = 0; i < adapter->num_tx_desc; i++) {
9c80d176
SZ
2497 tx_buffer = &adapter->tx_buffer_area[i];
2498
2499 error = bus_dmamap_create(adapter->txtag,
2500 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2501 &tx_buffer->map);
1eca7b82 2502 if (error) {
9c80d176
SZ
2503 device_printf(dev, "Unable to create TX DMA map\n");
2504 em_destroy_tx_ring(adapter, i);
2505 return error;
1eca7b82 2506 }
1eca7b82 2507 }
9c80d176
SZ
2508 return (0);
2509}
9ccd8c1f 2510
9c80d176
SZ
2511static void
2512em_init_tx_ring(struct adapter *adapter)
2513{
2514 /* Clear the old ring contents */
2515 bzero(adapter->tx_desc_base,
2516 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2517
2518 /* Reset state */
87307ba1
SZ
2519 adapter->next_avail_tx_desc = 0;
2520 adapter->next_tx_to_clean = 0;
984263bc 2521 adapter->num_tx_desc_avail = adapter->num_tx_desc;
984263bc
MD
2522}
2523
984263bc 2524static void
9c80d176 2525em_init_tx_unit(struct adapter *adapter)
984263bc 2526{
9c80d176 2527 uint32_t tctl, tarc, tipg = 0;
9ccd8c1f
JS
2528 uint64_t bus_addr;
2529
984263bc 2530 /* Setup the Base and Length of the Tx Descriptor Ring */
9ccd8c1f 2531 bus_addr = adapter->txdma.dma_paddr;
9c80d176
SZ
2532 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2533 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2534 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2535 (uint32_t)(bus_addr >> 32));
2536 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2537 (uint32_t)bus_addr);
984263bc 2538 /* Setup the HW Tx Head and Tail descriptor pointers */
9c80d176
SZ
2539 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2540 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
984263bc 2541
984263bc 2542 /* Set the default values for the Tx Inter Packet Gap timer */
9c80d176
SZ
2543 switch (adapter->hw.mac.type) {
2544 case e1000_82542:
2545 tipg = DEFAULT_82542_TIPG_IPGT;
2546 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2547 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
984263bc 2548 break;
9c80d176
SZ
2549
2550 case e1000_80003es2lan:
2551 tipg = DEFAULT_82543_TIPG_IPGR1;
2552 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2553 E1000_TIPG_IPGR2_SHIFT;
1eca7b82 2554 break;
9c80d176 2555
984263bc 2556 default:
9c80d176
SZ
2557 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2558 adapter->hw.phy.media_type ==
2559 e1000_media_type_internal_serdes)
2560 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
984263bc 2561 else
9c80d176
SZ
2562 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2563 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2564 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2565 break;
2566 }
2567
2568 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
91e8debf
SZ
2569
2570 /* NOTE: 0 is not allowed for TIDV */
2571 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2572 if(adapter->hw.mac.type >= e1000_82540)
2573 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
984263bc 2574
9c80d176
SZ
2575 if (adapter->hw.mac.type == e1000_82571 ||
2576 adapter->hw.mac.type == e1000_82572) {
2577 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2578 tarc |= SPEED_MODE_BIT;
2579 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2580 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2581 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2582 tarc |= 1;
2583 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2584 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2585 tarc |= 1;
2586 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
1eca7b82
SZ
2587 }
2588
984263bc 2589 /* Program the Transmit Control Register */
9c80d176
SZ
2590 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2591 tctl &= ~E1000_TCTL_CT;
2592 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2593 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2594
2595 if (adapter->hw.mac.type >= e1000_82571)
2596 tctl |= E1000_TCTL_MULR;
1eca7b82 2597
87307ba1 2598 /* This write will effectively turn on the transmit unit. */
9c80d176 2599 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
2600}
2601
984263bc 2602static void
9c80d176 2603em_destroy_tx_ring(struct adapter *adapter, int ndesc)
984263bc 2604{
f647ad3d
JS
2605 struct em_buffer *tx_buffer;
2606 int i;
984263bc 2607
9c80d176
SZ
2608 if (adapter->tx_buffer_area == NULL)
2609 return;
984263bc 2610
9c80d176
SZ
2611 for (i = 0; i < ndesc; i++) {
2612 tx_buffer = &adapter->tx_buffer_area[i];
1eca7b82 2613
9c80d176
SZ
2614 KKASSERT(tx_buffer->m_head == NULL);
2615 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
9ccd8c1f 2616 }
9c80d176
SZ
2617 bus_dma_tag_destroy(adapter->txtag);
2618
2619 kfree(adapter->tx_buffer_area, M_DEVBUF);
2620 adapter->tx_buffer_area = NULL;
984263bc
MD
2621}
2622
9c80d176
SZ
2623/*
2624 * The offload context needs to be set when we transfer the first
2625 * packet of a particular protocol (TCP/UDP). This routine has been
002b3a05 2626 * enhanced to deal with inserted VLAN headers.
51e6819f
SZ
2627 *
2628 * If the new packet's ether header length, ip header length and
2629 * csum offloading type are same as the previous packet, we should
2630 * avoid allocating a new csum context descriptor; mainly to take
2631 * advantage of the pipeline effect of the TX data read request.
9f60d74b
SZ
2632 *
2633 * This function returns number of TX descrptors allocated for
2634 * csum context.
9c80d176 2635 */
9f60d74b 2636static int
9c80d176
SZ
2637em_txcsum(struct adapter *adapter, struct mbuf *mp,
2638 uint32_t *txd_upper, uint32_t *txd_lower)
984263bc 2639{
9c80d176 2640 struct e1000_context_desc *TXD;
984263bc 2641 struct em_buffer *tx_buffer;
9c80d176 2642 struct ether_vlan_header *eh;
51e6819f
SZ
2643 struct ip *ip;
2644 int curr_txd, ehdrlen, csum_flags;
9c80d176
SZ
2645 uint32_t cmd, hdr_len, ip_hlen;
2646 uint16_t etype;
9c80d176 2647
9c80d176
SZ
2648 /*
2649 * Determine where frame payload starts.
2650 * Jump over vlan headers if already present,
2651 * helpful for QinQ too.
2652 */
252dfd0d
SZ
2653 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2654 ("em_txcsum_pullup is not called (eh)?\n"));
9c80d176
SZ
2655 eh = mtod(mp, struct ether_vlan_header *);
2656 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
252dfd0d
SZ
2657 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2658 ("em_txcsum_pullup is not called (evh)?\n"));
9c80d176
SZ
2659 etype = ntohs(eh->evl_proto);
2660 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
984263bc 2661 } else {
9c80d176
SZ
2662 etype = ntohs(eh->evl_encap_proto);
2663 ehdrlen = ETHER_HDR_LEN;
984263bc
MD
2664 }
2665
1eca7b82 2666 /*
002b3a05 2667 * We only support TCP/UDP for IPv4 for the moment.
9c80d176 2668 * TODO: Support SCTP too when it hits the tree.
984263bc 2669 */
51e6819f 2670 if (etype != ETHERTYPE_IP)
9f60d74b 2671 return 0;
002b3a05 2672
51e6819f 2673 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE,
252dfd0d 2674 ("em_txcsum_pullup is not called (eh+ip_vhl)?\n"));
9c80d176 2675
51e6819f
SZ
2676 /* NOTE: We could only safely access ip.ip_vhl part */
2677 ip = (struct ip *)(mp->m_data + ehdrlen);
2678 ip_hlen = ip->ip_hl << 2;
984263bc 2679
51e6819f
SZ
2680 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2681
2682 if (adapter->csum_ehlen == ehdrlen &&
2683 adapter->csum_iphlen == ip_hlen &&
2684 adapter->csum_flags == csum_flags) {
2685 /*
2686 * Same csum offload context as the previous packets;
2687 * just return.
2688 */
2689 *txd_upper = adapter->csum_txd_upper;
2690 *txd_lower = adapter->csum_txd_lower;
9f60d74b 2691 return 0;
984263bc
MD
2692 }
2693
51e6819f
SZ
2694 /*
2695 * Setup a new csum offload context.
2696 */
2697
2698 curr_txd = adapter->next_avail_tx_desc;
2699 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2700 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2701
2702 cmd = 0;
2703
2704 /* Setup of IP header checksum. */
2705 if (csum_flags & CSUM_IP) {
2706 /*
2707 * Start offset for header checksum calculation.
2708 * End offset for header checksum calculation.
2709 * Offset of place to put the checksum.
2710 */
2711 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2712 TXD->lower_setup.ip_fields.ipcse =
2713 htole16(ehdrlen + ip_hlen - 1);
2714 TXD->lower_setup.ip_fields.ipcso =
2715 ehdrlen + offsetof(struct ip, ip_sum);
2716 cmd |= E1000_TXD_CMD_IP;
2717 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2718 }
2719 hdr_len = ehdrlen + ip_hlen;
2720
2721 if (csum_flags & CSUM_TCP) {
002b3a05
SZ
2722 /*
2723 * Start offset for payload checksum calculation.
2724 * End offset for payload checksum calculation.
2725 * Offset of place to put the checksum.
2726 */
2727 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2728 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2729 TXD->upper_setup.tcp_fields.tucso =
2730 hdr_len + offsetof(struct tcphdr, th_sum);
2731 cmd |= E1000_TXD_CMD_TCP;
2732 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
51e6819f 2733 } else if (csum_flags & CSUM_UDP) {
002b3a05
SZ
2734 /*
2735 * Start offset for header checksum calculation.
2736 * End offset for header checksum calculation.
2737 * Offset of place to put the checksum.
2738 */
2739 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2740 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2741 TXD->upper_setup.tcp_fields.tucso =
2742 hdr_len + offsetof(struct udphdr, uh_sum);
2743 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
9c80d176
SZ
2744 }
2745
2746 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2747 E1000_TXD_DTYP_D; /* Data descr */
51e6819f
SZ
2748
2749 /* Save the information for this csum offloading context */
2750 adapter->csum_ehlen = ehdrlen;
2751 adapter->csum_iphlen = ip_hlen;
2752 adapter->csum_flags = csum_flags;
2753 adapter->csum_txd_upper = *txd_upper;
2754 adapter->csum_txd_lower = *txd_lower;
2755
9c80d176
SZ
2756 TXD->tcp_seg_setup.data = htole32(0);
2757 TXD->cmd_and_length =
2af74b85 2758 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
984263bc
MD
2759
2760 if (++curr_txd == adapter->num_tx_desc)
2761 curr_txd = 0;
2762
9c80d176 2763 KKASSERT(adapter->num_tx_desc_avail > 0);
984263bc 2764 adapter->num_tx_desc_avail--;
9c80d176 2765
984263bc 2766 adapter->next_avail_tx_desc = curr_txd;
9f60d74b 2767 return 1;
984263bc
MD
2768}
2769
002b3a05
SZ
2770static int
2771em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0)
2772{
2773 struct mbuf *m = *m0;
2774 struct ether_header *eh;
2775 int len;
2776
2777 adapter->tx_csum_try_pullup++;
2778
2779 len = ETHER_HDR_LEN + EM_IPVHL_SIZE;
2780
2781 if (__predict_false(!M_WRITABLE(m))) {
2782 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2783 adapter->tx_csum_drop1++;
2784 m_freem(m);
2785 *m0 = NULL;
2786 return ENOBUFS;
2787 }
2788 eh = mtod(m, struct ether_header *);
2789
2790 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2791 len += EVL_ENCAPLEN;
2792
3752657e 2793 if (m->m_len < len) {
002b3a05
SZ
2794 adapter->tx_csum_drop2++;
2795 m_freem(m);
2796 *m0 = NULL;
2797 return ENOBUFS;
2798 }
2799 return 0;
2800 }
2801
2802 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2803 adapter->tx_csum_pullup1++;
2804 m = m_pullup(m, ETHER_HDR_LEN);
2805 if (m == NULL) {
2806 adapter->tx_csum_pullup1_failed++;
2807 *m0 = NULL;
2808 return ENOBUFS;
2809 }
2810 *m0 = m;
2811 }
2812 eh = mtod(m, struct ether_header *);
2813
2814 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2815 len += EVL_ENCAPLEN;
2816
3752657e 2817 if (m->m_len < len) {
002b3a05
SZ
2818 adapter->tx_csum_pullup2++;
2819 m = m_pullup(m, len);
2820 if (m == NULL) {
2821 adapter->tx_csum_pullup2_failed++;
2822 *m0 = NULL;
2823 return ENOBUFS;
2824 }
2825 *m0 = m;
2826 }
2827 return 0;
2828}
2829
984263bc 2830static void
87307ba1 2831em_txeof(struct adapter *adapter)
984263bc 2832{
9c80d176 2833 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2834 struct em_buffer *tx_buffer;
2835 int first, num_avail;
2836
2837 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2838 return;
984263bc 2839
f647ad3d
JS
2840 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2841 return;
984263bc 2842
9c80d176 2843 num_avail = adapter->num_tx_desc_avail;
87307ba1 2844 first = adapter->next_tx_to_clean;
9c80d176 2845
9f60d74b 2846 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
4e499730 2847 struct e1000_tx_desc *tx_desc;
9f60d74b 2848 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
984263bc 2849
9f60d74b 2850 tx_desc = &adapter->tx_desc_base[dd_idx];
9f60d74b
SZ
2851 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2852 EM_INC_TXDD_IDX(adapter->tx_dd_head);
984263bc 2853
9f60d74b
SZ
2854 if (++dd_idx == adapter->num_tx_desc)
2855 dd_idx = 0;
9c80d176 2856
9f60d74b 2857 while (first != dd_idx) {
edbfa193
SZ
2858 logif(pkt_txclean);
2859
9f60d74b
SZ
2860 num_avail++;
2861
4e499730 2862 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
2863 if (tx_buffer->m_head) {
2864 ifp->if_opackets++;
2865 bus_dmamap_unload(adapter->txtag,
2866 tx_buffer->map);
2867 m_freem(tx_buffer->m_head);
2868 tx_buffer->m_head = NULL;
2869 }
2870
2871 if (++first == adapter->num_tx_desc)
2872 first = 0;
2873 }
87307ba1
SZ
2874 } else {
2875 break;
2876 }
f647ad3d 2877 }
9f60d74b
SZ
2878 adapter->next_tx_to_clean = first;
2879 adapter->num_tx_desc_avail = num_avail;
2880
2881 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2882 adapter->tx_dd_head = 0;
2883 adapter->tx_dd_tail = 0;
2884 }
2885
2886 if (!EM_IS_OACTIVE(adapter)) {
2887 ifp->if_flags &= ~IFF_OACTIVE;
2888
2889 /* All clean, turn off the timer */
2890 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2891 ifp->if_timer = 0;
2892 }
2893}
2894
2895static void
2896em_tx_collect(struct adapter *adapter)
2897{
2898 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2899 struct em_buffer *tx_buffer;
2900 int tdh, first, num_avail, dd_idx = -1;
2901
2902 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2903 return;
2904
2905 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2906 if (tdh == adapter->next_tx_to_clean)
2907 return;
2908
2909 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2910 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2911
2912 num_avail = adapter->num_tx_desc_avail;
2913 first = adapter->next_tx_to_clean;
2914
2915 while (first != tdh) {
edbfa193
SZ
2916 logif(pkt_txclean);
2917
9f60d74b
SZ
2918 num_avail++;
2919
4e499730 2920 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
2921 if (tx_buffer->m_head) {
2922 ifp->if_opackets++;
2923 bus_dmamap_unload(adapter->txtag,
2924 tx_buffer->map);
2925 m_freem(tx_buffer->m_head);
2926 tx_buffer->m_head = NULL;
2927 }
2928
2929 if (first == dd_idx) {
2930 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2931 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2932 adapter->tx_dd_head = 0;
2933 adapter->tx_dd_tail = 0;
2934 dd_idx = -1;
2935 } else {
2936 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2937 }
2938 }
2939
2940 if (++first == adapter->num_tx_desc)
2941 first = 0;
2942 }
2943 adapter->next_tx_to_clean = first;
9c80d176 2944 adapter->num_tx_desc_avail = num_avail;
984263bc 2945
9f60d74b 2946 if (!EM_IS_OACTIVE(adapter)) {
9c80d176 2947 ifp->if_flags &= ~IFF_OACTIVE;
afa68aa1 2948
9c80d176
SZ
2949 /* All clean, turn off the timer */
2950 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2951 ifp->if_timer = 0;
2952 }
2953}
984263bc 2954
9c80d176
SZ
2955/*
2956 * When Link is lost sometimes there is work still in the TX ring
2957 * which will result in a watchdog, rather than allow that do an
2958 * attempted cleanup and then reinit here. Note that this has been
2959 * seens mostly with fiber adapters.
2960 */
2961static void
2962em_tx_purge(struct adapter *adapter)
2963{
2964 struct ifnet *ifp = &adapter->arpcom.ac_if;
2965
2966 if (!adapter->link_active && ifp->if_timer) {
9f60d74b 2967 em_tx_collect(adapter);
9c80d176
SZ
2968 if (ifp->if_timer) {
2969 if_printf(ifp, "Link lost, TX pending, reinit\n");
f647ad3d 2970 ifp->if_timer = 0;
9c80d176
SZ
2971 em_init(adapter);
2972 }
f647ad3d 2973 }
984263bc
MD
2974}
2975
984263bc 2976static int
9c80d176 2977em_newbuf(struct adapter *adapter, int i, int init)
984263bc 2978{
9c80d176
SZ
2979 struct mbuf *m;
2980 bus_dma_segment_t seg;
2981 bus_dmamap_t map;
9ccd8c1f 2982 struct em_buffer *rx_buffer;
9c80d176
SZ
2983 int error, nseg;
2984
2985 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2986 if (m == NULL) {
2987 adapter->mbuf_cluster_failed++;
2988 if (init) {
2989 if_printf(&adapter->arpcom.ac_if,
2990 "Unable to allocate RX mbuf\n");
984263bc 2991 }
9c80d176 2992 return (ENOBUFS);
984263bc 2993 }
9c80d176 2994 m->m_len = m->m_pkthdr.len = MCLBYTES;
87307ba1 2995
9c80d176
SZ
2996 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2997 m_adj(m, ETHER_ALIGN);
9ccd8c1f 2998
9c80d176
SZ
2999 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3000 adapter->rx_sparemap, m,
3001 &seg, 1, &nseg, BUS_DMA_NOWAIT);
9ccd8c1f 3002 if (error) {
9c80d176
SZ
3003 m_freem(m);
3004 if (init) {
3005 if_printf(&adapter->arpcom.ac_if,
3006 "Unable to load RX mbuf\n");
3007 }
87307ba1 3008 return (error);
9ccd8c1f 3009 }
984263bc 3010
9c80d176
SZ
3011 rx_buffer = &adapter->rx_buffer_area[i];
3012 if (rx_buffer->m_head != NULL)
3013 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3014
3015 map = rx_buffer->map;
3016 rx_buffer->map = adapter->rx_sparemap;
3017 adapter->rx_sparemap = map;
3018
3019 rx_buffer->m_head = m;
3020
3021 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
87307ba1 3022 return (0);
984263bc
MD
3023}
3024
984263bc 3025static int
9c80d176 3026em_create_rx_ring(struct adapter *adapter)
984263bc 3027{
9c80d176 3028 device_t dev = adapter->dev;
9ccd8c1f 3029 struct em_buffer *rx_buffer;
9c80d176
SZ
3030 int i, error;
3031
3032 adapter->rx_buffer_area =
3033 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3034 M_DEVBUF, M_WAITOK | M_ZERO);
9ccd8c1f 3035
9c80d176
SZ
3036 /*
3037 * Create DMA tag for rx buffers
3038 */
3039 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3040 1, 0, /* alignment, bounds */
3041 BUS_SPACE_MAXADDR, /* lowaddr */
3042 BUS_SPACE_MAXADDR, /* highaddr */
3043 NULL, NULL, /* filter, filterarg */
3044 MCLBYTES, /* maxsize */
3045 1, /* nsegments */
3046 MCLBYTES, /* maxsegsize */
3047 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3048 &adapter->rxtag);
87307ba1 3049 if (error) {
9c80d176
SZ
3050 device_printf(dev, "Unable to allocate RX DMA tag\n");
3051 kfree(adapter->rx_buffer_area, M_DEVBUF);
3052 adapter->rx_buffer_area = NULL;
3053 return error;
3054 }
3055
3056 /*
3057 * Create spare DMA map for rx buffers
3058 */
3059 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3060 &adapter->rx_sparemap);
3061 if (error) {
3062 device_printf(dev, "Unable to create spare RX DMA map\n");
3063 bus_dma_tag_destroy(adapter->rxtag);
3064 kfree(adapter->rx_buffer_area, M_DEVBUF);
3065 adapter->rx_buffer_area = NULL;
3066 return error;
9ccd8c1f 3067 }
9c80d176
SZ
3068
3069 /*
3070 * Create DMA maps for rx buffers
3071 */
3072 for (i = 0; i < adapter->num_rx_desc; i++) {
3073 rx_buffer = &adapter->rx_buffer_area[i];
3074
3075 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
9ccd8c1f 3076 &rx_buffer->map);
87307ba1 3077 if (error) {
9c80d176
SZ
3078 device_printf(dev, "Unable to create RX DMA map\n");
3079 em_destroy_rx_ring(adapter, i);
3080 return error;
9ccd8c1f 3081 }
984263bc 3082 }
87307ba1 3083 return (0);
984263bc
MD
3084}
3085
984263bc 3086static int
9c80d176 3087em_init_rx_ring(struct adapter *adapter)
984263bc 3088{
9c80d176 3089 int i, error;
984263bc 3090
9c80d176 3091 /* Reset descriptor ring */
87307ba1 3092 bzero(adapter->rx_desc_base,
9c80d176 3093 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
87307ba1 3094
9c80d176
SZ
3095 /* Allocate new ones. */
3096 for (i = 0; i < adapter->num_rx_desc; i++) {
3097 error = em_newbuf(adapter, i, 1);
3098 if (error)
3099 return (error);
3100 }
984263bc
MD
3101
3102 /* Setup our descriptor pointers */
f647ad3d 3103 adapter->next_rx_desc_to_check = 0;
87307ba1
SZ
3104
3105 return (0);
984263bc
MD
3106}
3107
984263bc 3108static void
9c80d176 3109em_init_rx_unit(struct adapter *adapter)
984263bc 3110{
9c80d176 3111 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 3112 uint64_t bus_addr;
2d0e5700 3113 uint32_t rctl;
984263bc 3114
87307ba1
SZ
3115 /*
3116 * Make sure receives are disabled while setting
3117 * up the descriptor ring
3118 */
9c80d176
SZ
3119 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3120 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
984263bc 3121
9c80d176 3122 if (adapter->hw.mac.type >= e1000_82540) {
2d0e5700
SZ
3123 uint32_t itr;
3124
9c80d176
SZ
3125 /*
3126 * Set the interrupt throttling rate. Value is calculated
3127 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3128 */
2d0e5700
SZ
3129 if (adapter->int_throttle_ceil)
3130 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3131 else
3132 itr = 0;
3133 em_set_itr(adapter, itr);
f647ad3d 3134 }
984263bc 3135
9c80d176
SZ
3136 /* Disable accelerated ackknowledge */
3137 if (adapter->hw.mac.type == e1000_82574) {
3138 E1000_WRITE_REG(&adapter->hw,
3139 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3140 }
3141
2d0e5700
SZ
3142 /* Receive Checksum Offload for TCP and UDP */
3143 if (ifp->if_capenable & IFCAP_RXCSUM) {
3144 uint32_t rxcsum;
3145
3146 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3147 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3148 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3149 }
3150
3151 /*
3152 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3153 * long latencies are observed, like Lenovo X60. This
3154 * change eliminates the problem, but since having positive
3155 * values in RDTR is a known source of problems on other
3156 * platforms another solution is being sought.
3157 */
3158 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3159 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3160 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3161 }
3162
3163 /*
3164 * Setup the Base and Length of the Rx Descriptor Ring
3165 */
9ccd8c1f 3166 bus_addr = adapter->rxdma.dma_paddr;
9c80d176
SZ
3167 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3168 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3169 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3170 (uint32_t)(bus_addr >> 32));
3171 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3172 (uint32_t)bus_addr);
984263bc 3173
2d0e5700
SZ
3174 /*
3175 * Setup the HW Rx Head and Tail Descriptor Pointers
3176 */
3177 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3178 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3179
3180 /* Set early receive threshold on appropriate hw */
3181 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3182 (adapter->hw.mac.type == e1000_pch2lan) ||
3183 (adapter->hw.mac.type == e1000_ich10lan)) &&
3184 (ifp->if_mtu > ETHERMTU)) {
3185 uint32_t rxdctl;
3186
3187 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3188 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3189 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13));
3190 }
3191
3192 if (adapter->hw.mac.type == e1000_pch2lan) {
3193 if (ifp->if_mtu > ETHERMTU)
3194 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE);
3195 else
3196 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE);
3197 }
3198
984263bc 3199 /* Setup the Receive Control Register */
9c80d176
SZ
3200 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3201 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3202 E1000_RCTL_RDMTS_HALF |
3203 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
984263bc 3204
9c80d176
SZ
3205 /* Make sure VLAN Filters are off */
3206 rctl &= ~E1000_RCTL_VFE;
3207
3208 if (e1000_tbi_sbp_enabled_82543(&adapter->hw))
3209 rctl |= E1000_RCTL_SBP;
3210 else
3211 rctl &= ~E1000_RCTL_SBP;
984263bc 3212
984263bc
MD
3213 switch (adapter->rx_buffer_len) {
3214 default:
9c80d176
SZ
3215 case 2048:
3216 rctl |= E1000_RCTL_SZ_2048;
3217 break;
3218
3219 case 4096:
3220 rctl |= E1000_RCTL_SZ_4096 |
3221 E1000_RCTL_BSEX | E1000_RCTL_LPE;
984263bc 3222 break;
9c80d176
SZ
3223
3224 case 8192:
3225 rctl |= E1000_RCTL_SZ_8192 |
3226 E1000_RCTL_BSEX | E1000_RCTL_LPE;
984263bc 3227 break;
9c80d176
SZ
3228
3229 case 16384:
3230 rctl |= E1000_RCTL_SZ_16384 |
3231 E1000_RCTL_BSEX | E1000_RCTL_LPE;
984263bc
MD
3232 break;
3233 }
3234
3235 if (ifp->if_mtu > ETHERMTU)
9c80d176
SZ
3236 rctl |= E1000_RCTL_LPE;
3237 else
3238 rctl &= ~E1000_RCTL_LPE;
984263bc 3239
6b96e920
SZ
3240 /* Enable Receives */
3241 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
984263bc
MD
3242}
3243
984263bc 3244static void
9c80d176 3245em_destroy_rx_ring(struct adapter *adapter, int ndesc)
984263bc 3246{
f647ad3d
JS
3247 struct em_buffer *rx_buffer;
3248 int i;
984263bc 3249
9c80d176
SZ
3250 if (adapter->rx_buffer_area == NULL)
3251 return;
984263bc 3252
9c80d176
SZ
3253 for (i = 0; i < ndesc; i++) {
3254 rx_buffer = &adapter->rx_buffer_area[i];
3255
3256 KKASSERT(rx_buffer->m_head == NULL);
3257 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
9ccd8c1f 3258 }
9c80d176
SZ
3259 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap);
3260 bus_dma_tag_destroy(adapter->rxtag);
3261
3262 kfree(adapter->rx_buffer_area, M_DEVBUF);
3263 adapter->rx_buffer_area = NULL;
984263bc
MD
3264}