x86_64: Always set LINTEN for AMD CPUs if their family >= 0xF
[dragonfly.git] / sys / platform / pc64 / x86_64 / initcpu.c
CommitLineData
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1/*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 * Copyright (c) 2008 The DragonFly Project.
4 *
5 * All rights reserved. Unpublished rights reserved under the copyright
6 * laws of Japan.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer as
14 * the first lines of this file unmodified.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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29 */
30
31#include "opt_cpu.h"
32
33#include <sys/param.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/sysctl.h>
37
38#include <machine/cputypes.h>
39#include <machine/md_var.h>
40#include <machine/specialreg.h>
bfc09ba0 41#include <machine/smp.h>
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42
43#include <vm/vm.h>
44#include <vm/pmap.h>
45
46static int hw_instruction_sse;
47SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
48 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
49
50int cpu; /* Are we 386, 386sx, 486, etc? */
51u_int cpu_feature; /* Feature flags */
52u_int cpu_feature2; /* Feature flags */
53u_int amd_feature; /* AMD feature flags */
54u_int amd_feature2; /* AMD feature flags */
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55u_int via_feature_rng; /* VIA RNG features */
56u_int via_feature_xcrypt; /* VIA ACE features */
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57u_int cpu_high; /* Highest arg to CPUID */
58u_int cpu_exthigh; /* Highest arg to extended CPUID */
59u_int cpu_id; /* Stepping ID */
60u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
61u_int cpu_procinfo2; /* Multicore info */
62char cpu_vendor[20]; /* CPU Origin code */
a2a636cc 63u_int cpu_vendor_id; /* CPU vendor ID */
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64u_int cpu_fxsr; /* SSE enabled */
65u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
66
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67SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
68 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
69SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
70 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
71
72/*
73 * Initialize special VIA C3/C7 features
74 */
75static void
76init_via(void)
77{
78 u_int regs[4], val;
79 u_int64_t msreg;
80
81 do_cpuid(0xc0000000, regs);
82 val = regs[0];
83 if (val >= 0xc0000001) {
84 do_cpuid(0xc0000001, regs);
85 val = regs[3];
86 } else
87 val = 0;
88
89 /* Enable RNG if present and disabled */
90 if (val & VIA_CPUID_HAS_RNG) {
91 if (!(val & VIA_CPUID_DO_RNG)) {
92 msreg = rdmsr(0x110B);
93 msreg |= 0x40;
94 wrmsr(0x110B, msreg);
95 }
96 via_feature_rng = VIA_HAS_RNG;
97 }
98 /* Enable AES engine if present and disabled */
99 if (val & VIA_CPUID_HAS_ACE) {
100 if (!(val & VIA_CPUID_DO_ACE)) {
101 msreg = rdmsr(0x1107);
102 msreg |= (0x01 << 28);
103 wrmsr(0x1107, msreg);
104 }
105 via_feature_xcrypt |= VIA_HAS_AES;
106 }
107 /* Enable ACE2 engine if present and disabled */
108 if (val & VIA_CPUID_HAS_ACE2) {
109 if (!(val & VIA_CPUID_DO_ACE2)) {
110 msreg = rdmsr(0x1107);
111 msreg |= (0x01 << 28);
112 wrmsr(0x1107, msreg);
113 }
114 via_feature_xcrypt |= VIA_HAS_AESCTR;
115 }
116 /* Enable SHA engine if present and disabled */
117 if (val & VIA_CPUID_HAS_PHE) {
118 if (!(val & VIA_CPUID_DO_PHE)) {
119 msreg = rdmsr(0x1107);
120 msreg |= (0x01 << 28/**/);
121 wrmsr(0x1107, msreg);
122 }
123 via_feature_xcrypt |= VIA_HAS_SHA;
124 }
125 /* Enable MM engine if present and disabled */
126 if (val & VIA_CPUID_HAS_PMM) {
127 if (!(val & VIA_CPUID_DO_PMM)) {
128 msreg = rdmsr(0x1107);
129 msreg |= (0x01 << 28/**/);
130 wrmsr(0x1107, msreg);
131 }
132 via_feature_xcrypt |= VIA_HAS_MM;
133 }
134}
135
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136/*
137 * Initialize CPU control registers
138 */
139void
140initializecpu(void)
141{
142 uint64_t msr;
143
144 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
145 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
146 cpu_fxsr = hw_instruction_sse = 1;
147 }
e43754b8 148
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149 if ((amd_feature & AMDID_NX) != 0) {
150 msr = rdmsr(MSR_EFER) | EFER_NXE;
151 wrmsr(MSR_EFER, msr);
152#if JG
153 pg_nx = PG_NX;
154#endif
155 }
ca6dce84 156 if (cpu_vendor_id == CPU_VENDOR_CENTAUR &&
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157 CPUID_TO_FAMILY(cpu_id) == 0x6 &&
158 CPUID_TO_MODEL(cpu_id) >= 0xf)
ca6dce84 159 init_via();
c8fe38ae 160}