AMD64 - Fix trapframe, intrframe, and user mode cpu accounting.
[dragonfly.git] / sys / bus / pci / pcivar.h
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
22457186 26 * $FreeBSD: src/sys/pci/pcivar.h,v 1.48 2000/09/28 00:37:32 peter Exp $
01c9014b 27 * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.17 2008/10/19 09:13:58 sephe Exp $
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28 *
29 */
30
31#ifndef _PCIVAR_H_
32#define _PCIVAR_H_
33
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34#include <sys/queue.h>
35
36/* some PCI bus constants */
37
38#define PCI_BUSMAX 255 /* highest supported bus number */
39#define PCI_SLOTMAX 31 /* highest supported slot number */
40#define PCI_FUNCMAX 7 /* highest supported function number */
41#define PCI_REGMAX 255 /* highest supported config register addr. */
42
43#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
44#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
45#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
46
47/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
48
49#ifdef PCI_A64
50typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
51#else
52typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
53#endif
54
b4c0a845 55/* config values for PCI power management capability */
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56struct pcicfg_pmgt {
57 u_int16_t pp_cap; /* PCI power management capabilities */
58 u_int8_t pp_status; /* config space address of PCI power status reg */
59 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */
60 u_int8_t pp_data; /* config space address of PCI power data reg */
61};
62
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63/* config values for PCI Express capability */
64struct pcicfg_expr {
65 uint8_t expr_ptr; /* capability ptr */
66 uint16_t expr_cap; /* capabilities */
67 uint32_t expr_slotcap; /* slot capabilities */
68};
69
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70/* config header information common to all header types */
71
72typedef struct pcicfg {
73 struct device *dev; /* device which owns this */
74 void *hdrspec; /* pointer to header type specific data */
75
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76 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
77 uint32_t bios; /* BIOS mapping */
78
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79 u_int16_t subvendor; /* card vendor ID */
80 u_int16_t subdevice; /* card device ID, assigned by card vendor */
81 u_int16_t vendor; /* chip vendor ID */
82 u_int16_t device; /* chip device ID, assigned by chip vendor */
83
84 u_int16_t cmdreg; /* disable/enable chip and PCI options */
85 u_int16_t statreg; /* supported PCI features and error state */
86
87 u_int8_t baseclass; /* chip PCI class */
88 u_int8_t subclass; /* chip PCI subclass */
89 u_int8_t progif; /* chip PCI programming interface */
90 u_int8_t revid; /* chip revision ID */
91
92 u_int8_t hdrtype; /* chip config header type */
93 u_int8_t cachelnsz; /* cache line size in 4byte units */
94 u_int8_t intpin; /* PCI interrupt pin */
95 u_int8_t intline; /* interrupt line (IRQ for PC arch) */
96
97 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
98 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
99 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
100
101 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
102 u_int8_t nummaps; /* actual number of PCI maps used */
103
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104 u_int8_t bus; /* config space bus address */
105 u_int8_t slot; /* config space slot address */
106 u_int8_t func; /* config space function number */
107
108 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */
109 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */
110
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111 struct pcicfg_pmgt pmgt; /* power management capability */
112 struct pcicfg_expr expr; /* PCI Express capability */
c7e4e7eb 113 u_int8_t pcixcap_ptr; /* PCI-X capability PTR */
0254566f 114 u_int8_t vpdcap_ptr; /* Vital Product Data capability */
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115} pcicfgregs;
116
117/* additional type 1 device config header information (PCI to PCI bridge) */
118
119#ifdef PCI_A64
120#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
121#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
122#else
123#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
124#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
125#endif /* PCI_A64 */
126
127#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
128#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
129
130typedef struct {
131 pci_addr_t pmembase; /* base address of prefetchable memory */
132 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
133 u_int32_t membase; /* base address of memory window */
134 u_int32_t memlimit; /* topmost address of memory window */
135 u_int32_t iobase; /* base address of port window */
136 u_int32_t iolimit; /* topmost address of port window */
137 u_int16_t secstat; /* secondary bus status register */
138 u_int16_t bridgectl; /* bridge control register */
139 u_int8_t seclat; /* CardBus latency timer */
140} pcih1cfgregs;
141
142/* additional type 2 device config header information (CardBus bridge) */
143
144typedef struct {
145 u_int32_t membase0; /* base address of memory window */
146 u_int32_t memlimit0; /* topmost address of memory window */
147 u_int32_t membase1; /* base address of memory window */
148 u_int32_t memlimit1; /* topmost address of memory window */
149 u_int32_t iobase0; /* base address of port window */
150 u_int32_t iolimit0; /* topmost address of port window */
151 u_int32_t iobase1; /* base address of port window */
152 u_int32_t iolimit1; /* topmost address of port window */
153 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
154 u_int16_t secstat; /* secondary bus status register */
155 u_int16_t bridgectl; /* bridge control register */
156 u_int8_t seclat; /* CardBus latency timer */
157} pcih2cfgregs;
158
984263bc 159extern u_int32_t pci_numdevs;
2581072f 160extern const char *pcib_owner; /* arbitrate who owns the pci device arch */
984263bc 161
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162/* Only if the prerequisites are present */
163#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
164struct pci_devinfo {
165 STAILQ_ENTRY(pci_devinfo) pci_links;
166 struct resource_list resources;
167 pcicfgregs cfg;
168 struct pci_conf conf;
169};
170#endif
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171
172/* externally visible functions */
173
174const char *pci_ata_match(struct device *dev);
175const char *pci_usb_match(struct device *dev);
176const char *pci_vga_match(struct device *dev);
27c23c6b 177const char *pci_chip_match(struct device *dev);
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178
179/* low level PCI config register functions provided by pcibus.c */
180
181int pci_cfgread (pcicfgregs *cfg, int reg, int bytes);
182void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
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183
184/* low level devlist operations for the 2.2 compatibility code in pci.c */
185pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg);
186
187#ifdef _SYS_BUS_H_
188
189#include "pci_if.h"
190
191/*
192 * Define pci-specific resource flags for accessing memory via dense
193 * or bwx memory spaces. These flags are ignored on i386.
194 */
195#define PCI_RF_DENSE 0x10000
196#define PCI_RF_BWX 0x20000
197
198enum pci_device_ivars {
199 PCI_IVAR_SUBVENDOR,
200 PCI_IVAR_SUBDEVICE,
201 PCI_IVAR_VENDOR,
202 PCI_IVAR_DEVICE,
203 PCI_IVAR_DEVID,
204 PCI_IVAR_CLASS,
205 PCI_IVAR_SUBCLASS,
206 PCI_IVAR_PROGIF,
207 PCI_IVAR_REVID,
208 PCI_IVAR_INTPIN,
209 PCI_IVAR_IRQ,
210 PCI_IVAR_BUS,
211 PCI_IVAR_SLOT,
212 PCI_IVAR_FUNCTION,
213 PCI_IVAR_SECONDARYBUS,
214 PCI_IVAR_SUBORDINATEBUS,
22457186 215 PCI_IVAR_ETHADDR,
c7e4e7eb 216 PCI_IVAR_PCIXCAP_PTR,
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217 PCI_IVAR_PCIECAP_PTR,
218 PCI_IVAR_VPDCAP_PTR
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219};
220
221/*
222 * Simplified accessors for pci devices
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223 *
224 * The PCI device passed in actually represents a PCI function number
225 * for the current slot. The parent of dev is the "pci" slot device.
226 * Each function number has its own set of ivars.
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227 */
228#define PCI_ACCESSOR(A, B, T) \
229 \
230static __inline T pci_get_ ## A(device_t dev) \
231{ \
232 uintptr_t v; \
233 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \
234 return (T) v; \
235} \
236 \
237static __inline void pci_set_ ## A(device_t dev, T t) \
238{ \
27c23c6b 239 uintptr_t v = (uintptr_t) t; \
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240 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \
241}
242
243PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
244PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
245PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
246PCI_ACCESSOR(device, DEVICE, u_int16_t)
247PCI_ACCESSOR(devid, DEVID, u_int32_t)
248PCI_ACCESSOR(class, CLASS, u_int8_t)
249PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
250PCI_ACCESSOR(progif, PROGIF, u_int8_t)
251PCI_ACCESSOR(revid, REVID, u_int8_t)
252PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
253PCI_ACCESSOR(irq, IRQ, u_int8_t)
254PCI_ACCESSOR(bus, BUS, u_int8_t)
255PCI_ACCESSOR(slot, SLOT, u_int8_t)
256PCI_ACCESSOR(function, FUNCTION, u_int8_t)
257PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t)
258PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t)
f72d3d23 259PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
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260PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t)
261PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t)
0254566f 262PCI_ACCESSOR(vpdcap_ptr, VPDCAP_PTR, uint8_t)
984263bc 263
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264#undef PCI_ACCESSOR
265
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266static __inline u_int32_t
267pci_read_config(device_t dev, int reg, int width)
268{
269 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
270}
271
272static __inline void
273pci_write_config(device_t dev, int reg, u_int32_t val, int width)
274{
275 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
276}
277
278/*
279 * Convenience functions.
280 *
281 * These should be used in preference to manually manipulating
282 * configuration space.
283 */
284static __inline void
285pci_enable_busmaster(device_t dev)
286{
287 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev);
288}
289
290static __inline void
291pci_disable_busmaster(device_t dev)
292{
293 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev);
294}
295
296static __inline void
297pci_enable_io(device_t dev, int space)
298{
299 PCI_ENABLE_IO(device_get_parent(dev), dev, space);
300}
301
302static __inline void
303pci_disable_io(device_t dev, int space)
304{
305 PCI_DISABLE_IO(device_get_parent(dev), dev, space);
306}
307
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308static __inline int
309pci_is_pcie(device_t dev)
310{
311 return (pci_get_pciecap_ptr(dev) != 0);
312}
313
314static __inline int
315pci_is_pcix(device_t dev)
316{
317 return (pci_get_pcixcap_ptr(dev) != 0);
318}
319
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320/*
321 * PCI power states are as defined by ACPI:
322 *
323 * D0 State in which device is on and running. It is receiving full
324 * power from the system and delivering full functionality to the user.
325 * D1 Class-specific low-power state in which device context may or may not
326 * be lost. Buses in D1 cannot do anything to the bus that would force
327 * devices on that bus to loose context.
328 * D2 Class-specific low-power state in which device context may or may
329 * not be lost. Attains greater power savings than D1. Buses in D2
330 * can cause devices on that bus to loose some context. Devices in D2
331 * must be prepared for the bus to be in D2 or higher.
332 * D3 State in which the device is off and not running. Device context is
333 * lost. Power can be removed from the device.
334 */
335#define PCI_POWERSTATE_D0 0
336#define PCI_POWERSTATE_D1 1
337#define PCI_POWERSTATE_D2 2
338#define PCI_POWERSTATE_D3 3
339#define PCI_POWERSTATE_UNKNOWN -1
340
341static __inline int
342pci_set_powerstate(device_t dev, int state)
343{
344 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
345}
346
347static __inline int
348pci_get_powerstate(device_t dev)
349{
350 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
351}
352
353/*
354 * Ivars for pci bridges.
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355 *
356 * Whereas PCI devices are arranged [pciX]->[pciX.Y] with the pci driver
357 * functions in [pciX] but the individual ivars in [pciX.Y], PCI bridges
358 * are installed in [pciX.Y] and store their ivars in a softc. This
359 * is why the accessor functions for a bridge do not call device_get_parent().
984263bc 360 */
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361/*typedef enum pci_device_ivars pcib_device_ivars;*/
362enum pcib_device_ivars {
0beece56 363 PCIB_IVAR_BUS,
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364};
365
366#define PCIB_ACCESSOR(A, B, T) \
367 \
368static __inline T pcib_get_ ## A(device_t dev) \
369{ \
370 uintptr_t v; \
2581072f 371 BUS_READ_IVAR(dev, dev, PCIB_IVAR_ ## B, &v); \
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372 return (T) v; \
373} \
374 \
375static __inline void pcib_set_ ## A(device_t dev, T t) \
376{ \
27c23c6b 377 uintptr_t v = (uintptr_t) t; \
2581072f 378 BUS_WRITE_IVAR(dev, dev, PCIB_IVAR_ ## B, v); \
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379}
380
0beece56 381PCIB_ACCESSOR(bus, BUS, u_int32_t)
984263bc 382
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383#undef PCIB_ACCESSOR
384
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385device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
386device_t pci_find_device(u_int16_t, u_int16_t);
8c5b0f9a 387int pcie_slot_implemented(device_t);
01c9014b 388void pcie_set_max_readrq(device_t, uint16_t);
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389#endif
390
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391/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
392
393#if defined(_KERNEL) && !defined(KLD_MODULE)
394#include "opt_compat_oldpci.h"
395#endif
984263bc 396
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397#ifdef COMPAT_OLDPCI
398/* all this is going some day */
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399
400typedef pcicfgregs *pcici_t;
401typedef unsigned pcidi_t;
402typedef void pci_inthand_t(void *arg);
403
404#define pci_max_burst_len (3)
405
406/* just copied from old PCI code for now ... */
407
408struct pci_device {
409 char* pd_name;
410 const char* (*pd_probe ) (pcici_t tag, pcidi_t type);
411 void (*pd_attach) (pcici_t tag, int unit);
412 u_long *pd_count;
413 int (*pd_shutdown) (int, int);
414};
415
416#ifdef __i386__
417typedef u_short pci_port_t;
418#else
419typedef u_int pci_port_t;
420#endif
421
422u_long pci_conf_read (pcici_t tag, u_long reg);
423void pci_conf_write (pcici_t tag, u_long reg, u_long data);
424int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
425int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
38787eef 426int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg);
984263bc 427int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg,
38787eef 428 u_int flags);
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429int pci_unmap_int (pcici_t tag);
430
431pcici_t pci_get_parent_from_tag(pcici_t tag);
432int pci_get_bus_from_tag(pcici_t tag);
433
434struct module;
435int compat_pci_handler (struct module *, int, void *);
436#define COMPAT_PCI_DRIVER(name, pcidata) \
437static moduledata_t name##_mod = { \
438 #name, \
439 compat_pci_handler, \
440 &pcidata \
441}; \
442DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)
443
444
dc5a7bd2 445#endif /* COMPAT_OLDPCI */
984263bc 446#endif /* _PCIVAR_H_ */