wlan - Update wlan from Adrian / FreeBSD
[dragonfly.git] / sys / bus / u4b / wlan / if_urtwn.c
CommitLineData
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1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
2
3/*-
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3521a462 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
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6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
3521a462 19 * $FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 268487 2014-07-10 09:42:34Z kevlo $
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20 */
21
22/*
3521a462 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU.
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24 */
25
26#include <sys/param.h>
27#include <sys/sockio.h>
28#include <sys/sysctl.h>
29#include <sys/lock.h>
30#include <sys/mbuf.h>
31#include <sys/kernel.h>
32#include <sys/socket.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/module.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/linker.h>
39#include <sys/firmware.h>
40#include <net/ifq_var.h>
41
42#include <sys/rman.h>
43
44#include <net/bpf.h>
45#include <net/if.h>
3521a462 46#include <net/if_var.h>
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47#include <net/if_arp.h>
48#include <net/ethernet.h>
49#include <net/if_dl.h>
50#include <net/if_media.h>
51#include <net/if_types.h>
52
53#include <netinet/in.h>
54#include <netinet/in_systm.h>
55#include <netinet/in_var.h>
56#include <netinet/if_ether.h>
57#include <netinet/ip.h>
58
59#include <netproto/802_11/ieee80211_var.h>
60#include <netproto/802_11/ieee80211_regdomain.h>
61#include <netproto/802_11/ieee80211_radiotap.h>
62#include <netproto/802_11/ieee80211_ratectl.h>
63
64#include <bus/u4b/usb.h>
65#include <bus/u4b/usbdi.h>
ef4aa9ff 66#include "usbdevs.h"
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67
68#define USB_DEBUG_VAR urtwn_debug
69#include <bus/u4b/usb_debug.h>
70
71#include <bus/u4b/wlan/if_urtwnreg.h>
72
73#ifdef USB_DEBUG
74static int urtwn_debug = 0;
75
76SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn");
77SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0,
78 "Debug level");
79#endif
80
81#define URTWN_RSSI(r) (r) - 110
82#define IEEE80211_HAS_ADDR4(wh) \
83 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
84
85/* various supported device vendors/products */
86static const STRUCT_USB_HOST_ID urtwn_devs[] = {
87#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
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88#define URTWN_RTL8188E_DEV(v,p) \
89 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) }
90#define URTWN_RTL8188E 1
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91 URTWN_DEV(ABOCOM, RTL8188CU_1),
92 URTWN_DEV(ABOCOM, RTL8188CU_2),
93 URTWN_DEV(ABOCOM, RTL8192CU),
94 URTWN_DEV(ASUS, RTL8192CU),
3521a462 95 URTWN_DEV(ASUS, USBN10NANO),
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96 URTWN_DEV(AZUREWAVE, RTL8188CE_1),
97 URTWN_DEV(AZUREWAVE, RTL8188CE_2),
98 URTWN_DEV(AZUREWAVE, RTL8188CU),
99 URTWN_DEV(BELKIN, F7D2102),
100 URTWN_DEV(BELKIN, RTL8188CU),
101 URTWN_DEV(BELKIN, RTL8192CU),
102 URTWN_DEV(CHICONY, RTL8188CUS_1),
103 URTWN_DEV(CHICONY, RTL8188CUS_2),
104 URTWN_DEV(CHICONY, RTL8188CUS_3),
105 URTWN_DEV(CHICONY, RTL8188CUS_4),
106 URTWN_DEV(CHICONY, RTL8188CUS_5),
107 URTWN_DEV(COREGA, RTL8192CU),
108 URTWN_DEV(DLINK, RTL8188CU),
109 URTWN_DEV(DLINK, RTL8192CU_1),
110 URTWN_DEV(DLINK, RTL8192CU_2),
111 URTWN_DEV(DLINK, RTL8192CU_3),
112 URTWN_DEV(DLINK, DWA131B),
113 URTWN_DEV(EDIMAX, EW7811UN),
114 URTWN_DEV(EDIMAX, RTL8192CU),
115 URTWN_DEV(FEIXUN, RTL8188CU),
116 URTWN_DEV(FEIXUN, RTL8192CU),
117 URTWN_DEV(GUILLEMOT, HWNUP150),
118 URTWN_DEV(HAWKING, RTL8192CU),
119 URTWN_DEV(HP3, RTL8188CU),
120 URTWN_DEV(NETGEAR, WNA1000M),
121 URTWN_DEV(NETGEAR, RTL8192CU),
122 URTWN_DEV(NETGEAR4, RTL8188CU),
123 URTWN_DEV(NOVATECH, RTL8188CU),
124 URTWN_DEV(PLANEX2, RTL8188CU_1),
125 URTWN_DEV(PLANEX2, RTL8188CU_2),
126 URTWN_DEV(PLANEX2, RTL8188CU_3),
127 URTWN_DEV(PLANEX2, RTL8188CU_4),
128 URTWN_DEV(PLANEX2, RTL8188CUS),
129 URTWN_DEV(PLANEX2, RTL8192CU),
130 URTWN_DEV(REALTEK, RTL8188CE_0),
131 URTWN_DEV(REALTEK, RTL8188CE_1),
132 URTWN_DEV(REALTEK, RTL8188CTV),
133 URTWN_DEV(REALTEK, RTL8188CU_0),
134 URTWN_DEV(REALTEK, RTL8188CU_1),
135 URTWN_DEV(REALTEK, RTL8188CU_2),
136 URTWN_DEV(REALTEK, RTL8188CU_COMBO),
137 URTWN_DEV(REALTEK, RTL8188CUS),
138 URTWN_DEV(REALTEK, RTL8188RU_1),
139 URTWN_DEV(REALTEK, RTL8188RU_2),
140 URTWN_DEV(REALTEK, RTL8191CU),
141 URTWN_DEV(REALTEK, RTL8192CE),
142 URTWN_DEV(REALTEK, RTL8192CU),
143 URTWN_DEV(SITECOMEU, RTL8188CU_1),
144 URTWN_DEV(SITECOMEU, RTL8188CU_2),
145 URTWN_DEV(SITECOMEU, RTL8192CU),
146 URTWN_DEV(TRENDNET, RTL8188CU),
147 URTWN_DEV(TRENDNET, RTL8192CU),
148 URTWN_DEV(ZYXEL, RTL8192CU),
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149 /* URTWN_RTL8188E */
150 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV),
151 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU),
152#undef URTWN_RTL8188E_DEV
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153#undef URTWN_DEV
154};
155
156static device_probe_t urtwn_match;
157static device_attach_t urtwn_attach;
158static device_detach_t urtwn_detach;
159
160static usb_callback_t urtwn_bulk_tx_callback;
161static usb_callback_t urtwn_bulk_rx_callback;
162
163static usb_error_t urtwn_do_request(struct urtwn_softc *sc,
164 struct usb_device_request *req, void *data);
165static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *,
166 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
167 const uint8_t [IEEE80211_ADDR_LEN],
168 const uint8_t [IEEE80211_ADDR_LEN]);
169static void urtwn_vap_delete(struct ieee80211vap *);
170static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int,
171 int *);
172static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *,
173 int *, int8_t *);
174static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *);
175static int urtwn_alloc_list(struct urtwn_softc *,
176 struct urtwn_data[], int, int);
177static int urtwn_alloc_rx_list(struct urtwn_softc *);
178static int urtwn_alloc_tx_list(struct urtwn_softc *);
179static void urtwn_free_tx_list(struct urtwn_softc *);
180static void urtwn_free_rx_list(struct urtwn_softc *);
181static void urtwn_free_list(struct urtwn_softc *,
182 struct urtwn_data data[], int);
183static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *);
184static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *);
185static int urtwn_write_region_1(struct urtwn_softc *, uint16_t,
186 uint8_t *, int);
187static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t);
188static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
189static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
190static int urtwn_read_region_1(struct urtwn_softc *, uint16_t,
191 uint8_t *, int);
192static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t);
193static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t);
194static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
195static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t,
196 const void *, int);
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197static void urtwn_r92c_rf_write(struct urtwn_softc *, int,
198 uint8_t, uint32_t);
199static void urtwn_r88e_rf_write(struct urtwn_softc *, int,
200 uint8_t, uint32_t);
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201static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t);
202static int urtwn_llt_write(struct urtwn_softc *, uint32_t,
203 uint32_t);
204static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t);
205static void urtwn_efuse_read(struct urtwn_softc *);
3521a462 206static void urtwn_efuse_switch_power(struct urtwn_softc *);
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207static int urtwn_read_chipid(struct urtwn_softc *);
208static void urtwn_read_rom(struct urtwn_softc *);
3521a462 209static void urtwn_r88e_read_rom(struct urtwn_softc *);
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210static int urtwn_ra_init(struct urtwn_softc *);
211static void urtwn_tsf_sync_enable(struct urtwn_softc *);
212static void urtwn_set_led(struct urtwn_softc *, int, int);
213static int urtwn_newstate(struct ieee80211vap *,
214 enum ieee80211_state, int);
215static void urtwn_watchdog(void *);
216static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t);
217static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *);
3521a462 218static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *);
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219static int urtwn_tx_start(struct urtwn_softc *,
220 struct ieee80211_node *, struct mbuf *,
221 struct urtwn_data *);
790340ea 222static void urtwn_start(struct ifnet *, struct ifaltq_subque *);
3521a462 223static void urtwn_start_locked(struct ifnet *);
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224static int urtwn_ioctl(struct ifnet *, u_long, caddr_t,
225 struct ucred *);
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226static int urtwn_r92c_power_on(struct urtwn_softc *);
227static int urtwn_r88e_power_on(struct urtwn_softc *);
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228static int urtwn_llt_init(struct urtwn_softc *);
229static void urtwn_fw_reset(struct urtwn_softc *);
3521a462 230static void urtwn_r88e_fw_reset(struct urtwn_softc *);
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231static int urtwn_fw_loadpage(struct urtwn_softc *, int,
232 const uint8_t *, int);
233static int urtwn_load_firmware(struct urtwn_softc *);
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234static int urtwn_r92c_dma_init(struct urtwn_softc *);
235static int urtwn_r88e_dma_init(struct urtwn_softc *);
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236static void urtwn_mac_init(struct urtwn_softc *);
237static void urtwn_bb_init(struct urtwn_softc *);
238static void urtwn_rf_init(struct urtwn_softc *);
239static void urtwn_cam_init(struct urtwn_softc *);
240static void urtwn_pa_bias_init(struct urtwn_softc *);
241static void urtwn_rxfilter_init(struct urtwn_softc *);
242static void urtwn_edca_init(struct urtwn_softc *);
243static void urtwn_write_txpower(struct urtwn_softc *, int,
244 uint16_t[]);
245static void urtwn_get_txpower(struct urtwn_softc *, int,
246 struct ieee80211_channel *,
247 struct ieee80211_channel *, uint16_t[]);
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248static void urtwn_r88e_get_txpower(struct urtwn_softc *, int,
249 struct ieee80211_channel *,
250 struct ieee80211_channel *, uint16_t[]);
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251static void urtwn_set_txpower(struct urtwn_softc *,
252 struct ieee80211_channel *,
253 struct ieee80211_channel *);
254static void urtwn_scan_start(struct ieee80211com *);
255static void urtwn_scan_end(struct ieee80211com *);
256static void urtwn_set_channel(struct ieee80211com *);
257static void urtwn_set_chan(struct urtwn_softc *,
258 struct ieee80211_channel *,
259 struct ieee80211_channel *);
260static void urtwn_update_mcast(struct ifnet *);
261static void urtwn_iq_calib(struct urtwn_softc *);
262static void urtwn_lc_calib(struct urtwn_softc *);
263static void urtwn_init(void *);
264static void urtwn_init_locked(void *);
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265static void urtwn_stop(struct ifnet *);
266static void urtwn_stop_locked(struct ifnet *);
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267static void urtwn_abort_xfers(struct urtwn_softc *);
268static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
269 const struct ieee80211_bpf_params *);
3521a462 270static void urtwn_ms_delay(struct urtwn_softc *);
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271
272/* Aliases. */
273#define urtwn_bb_write urtwn_write_4
274#define urtwn_bb_read urtwn_read_4
275
276static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = {
277 [URTWN_BULK_RX] = {
278 .type = UE_BULK,
279 .endpoint = UE_ADDR_ANY,
280 .direction = UE_DIR_IN,
281 .bufsize = URTWN_RXBUFSZ,
282 .flags = {
283 .pipe_bof = 1,
284 .short_xfer_ok = 1
285 },
286 .callback = urtwn_bulk_rx_callback,
287 },
288 [URTWN_BULK_TX_BE] = {
289 .type = UE_BULK,
290 .endpoint = 0x03,
291 .direction = UE_DIR_OUT,
292 .bufsize = URTWN_TXBUFSZ,
293 .flags = {
294 .ext_buffer = 1,
295 .pipe_bof = 1,
296 .force_short_xfer = 1
297 },
298 .callback = urtwn_bulk_tx_callback,
299 .timeout = URTWN_TX_TIMEOUT, /* ms */
300 },
301 [URTWN_BULK_TX_BK] = {
302 .type = UE_BULK,
303 .endpoint = 0x03,
304 .direction = UE_DIR_OUT,
305 .bufsize = URTWN_TXBUFSZ,
306 .flags = {
307 .ext_buffer = 1,
308 .pipe_bof = 1,
309 .force_short_xfer = 1,
310 },
311 .callback = urtwn_bulk_tx_callback,
312 .timeout = URTWN_TX_TIMEOUT, /* ms */
313 },
314 [URTWN_BULK_TX_VI] = {
315 .type = UE_BULK,
316 .endpoint = 0x02,
317 .direction = UE_DIR_OUT,
318 .bufsize = URTWN_TXBUFSZ,
319 .flags = {
320 .ext_buffer = 1,
321 .pipe_bof = 1,
322 .force_short_xfer = 1
323 },
324 .callback = urtwn_bulk_tx_callback,
325 .timeout = URTWN_TX_TIMEOUT, /* ms */
326 },
327 [URTWN_BULK_TX_VO] = {
328 .type = UE_BULK,
329 .endpoint = 0x02,
330 .direction = UE_DIR_OUT,
331 .bufsize = URTWN_TXBUFSZ,
332 .flags = {
333 .ext_buffer = 1,
334 .pipe_bof = 1,
335 .force_short_xfer = 1
336 },
337 .callback = urtwn_bulk_tx_callback,
338 .timeout = URTWN_TX_TIMEOUT, /* ms */
339 },
340};
341
342static int
343urtwn_match(device_t self)
344{
345 struct usb_attach_arg *uaa = device_get_ivars(self);
346
347 if (uaa->usb_mode != USB_MODE_HOST)
348 return (ENXIO);
349 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX)
350 return (ENXIO);
351 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX)
352 return (ENXIO);
353
354 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa));
355}
356
357static int
358urtwn_attach(device_t self)
359{
360 struct usb_attach_arg *uaa = device_get_ivars(self);
361 struct urtwn_softc *sc = device_get_softc(self);
362 struct ifnet *ifp;
363 struct ieee80211com *ic;
364 uint8_t iface_index, bands;
365 int error;
366
367 wlan_serialize_enter();
368 device_set_usb_desc(self);
369 sc->sc_udev = uaa->device;
370 sc->sc_dev = self;
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371 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E)
372 sc->chip |= URTWN_CHIP_88E;
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373
374 lockinit(&sc->sc_lock, device_get_nameunit(self), 0, LK_CANRECURSE);
375 callout_init(&sc->sc_watchdog_ch);
376
377 iface_index = URTWN_IFACE_INDEX;
378 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
379 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_lock);
380 if (error) {
381 device_printf(self, "could not allocate USB transfers, "
382 "err=%s\n", usbd_errstr(error));
383 goto detach;
384 }
385
386 URTWN_LOCK(sc);
387
388 error = urtwn_read_chipid(sc);
389 if (error) {
390 device_printf(sc->sc_dev, "unsupported test chip\n");
391 URTWN_UNLOCK(sc);
392 goto detach;
393 }
394
395 /* Determine number of Tx/Rx chains. */
396 if (sc->chip & URTWN_CHIP_92C) {
397 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2;
398 sc->nrxchains = 2;
399 } else {
400 sc->ntxchains = 1;
401 sc->nrxchains = 1;
402 }
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403
404 if (sc->chip & URTWN_CHIP_88E)
405 urtwn_r88e_read_rom(sc);
406 else
407 urtwn_read_rom(sc);
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408
409 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n",
410 (sc->chip & URTWN_CHIP_92C) ? "8192CU" :
3521a462 411 (sc->chip & URTWN_CHIP_88E) ? "8188EU" :
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412 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" :
413 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" :
414 "8188CUS", sc->ntxchains, sc->nrxchains);
415
416 URTWN_UNLOCK(sc);
417
418 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
419 if (ifp == NULL) {
420 device_printf(sc->sc_dev, "can not if_alloc()\n");
421 goto detach;
422 }
423 ic = ifp->if_l2com;
424
425 ifp->if_softc = sc;
426 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev));
427 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
428 ifp->if_init = urtwn_init;
429 ifp->if_ioctl = urtwn_ioctl;
430 ifp->if_start = urtwn_start;
431 ifq_set_maxlen(&ifp->if_snd, ifqmaxlen);
432#if 0 /* XXX swildner: see c3d4131842e47b168d93a0650d58d425ebeef789 */
433 IFQ_SET_READY(&ifp->if_snd);
434#endif
435
436 ic->ic_ifp = ifp;
437 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
438 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
439
440 /* set device capabilities */
441 ic->ic_caps =
442 IEEE80211_C_STA /* station mode */
443 | IEEE80211_C_MONITOR /* monitor mode */
444 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
445 | IEEE80211_C_SHSLOT /* short slot time supported */
446 | IEEE80211_C_BGSCAN /* capable of bg scanning */
447 | IEEE80211_C_WPA /* 802.11i */
448 ;
449
450 bands = 0;
451 setbit(&bands, IEEE80211_MODE_11B);
452 setbit(&bands, IEEE80211_MODE_11G);
453 ieee80211_init_channels(ic, NULL, &bands);
454
455 ieee80211_ifattach(ic, sc->sc_bssid);
456 ic->ic_raw_xmit = urtwn_raw_xmit;
457 ic->ic_scan_start = urtwn_scan_start;
458 ic->ic_scan_end = urtwn_scan_end;
459 ic->ic_set_channel = urtwn_set_channel;
460
461 ic->ic_vap_create = urtwn_vap_create;
462 ic->ic_vap_delete = urtwn_vap_delete;
463 ic->ic_update_mcast = urtwn_update_mcast;
464
465 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
466 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT,
467 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
468 URTWN_RX_RADIOTAP_PRESENT);
469
470 if (bootverbose)
471 ieee80211_announce(ic);
472
473 wlan_serialize_exit();
474 return (0);
475
476detach:
477 wlan_serialize_exit();
478 urtwn_detach(self);
479 return (ENXIO); /* failure */
480}
481
482static int
483urtwn_detach(device_t self)
484{
485 struct urtwn_softc *sc = device_get_softc(self);
486 struct ifnet *ifp = sc->sc_ifp;
487 struct ieee80211com *ic = ifp->if_l2com;
3521a462 488 unsigned int x;
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489
490 wlan_serialize_enter();
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491
492 /* Prevent further ioctls. */
493 URTWN_LOCK(sc);
494 sc->sc_flags |= URTWN_DETACHED;
495 URTWN_UNLOCK(sc);
496
497 urtwn_stop(ifp);
790340ea
SW
498
499 callout_stop_sync(&sc->sc_watchdog_ch);
500
3521a462
SW
501 /* Prevent further allocations from RX/TX data lists. */
502 URTWN_LOCK(sc);
503 STAILQ_INIT(&sc->sc_tx_active);
504 STAILQ_INIT(&sc->sc_tx_inactive);
505 STAILQ_INIT(&sc->sc_tx_pending);
506
507 STAILQ_INIT(&sc->sc_rx_active);
508 STAILQ_INIT(&sc->sc_rx_inactive);
509 URTWN_UNLOCK(sc);
790340ea 510
3521a462
SW
511 /* drain USB transfers */
512 for (x = 0; x != URTWN_N_TRANSFER; x++)
513 usbd_transfer_drain(sc->sc_xfer[x]);
514
515 /* Free data buffers. */
516 URTWN_LOCK(sc);
790340ea
SW
517 urtwn_free_tx_list(sc);
518 urtwn_free_rx_list(sc);
3521a462
SW
519 URTWN_UNLOCK(sc);
520
521 /* stop all USB transfers */
522 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER);
523 ieee80211_ifdetach(ic);
790340ea
SW
524
525 if_free(ifp);
526 lockuninit(&sc->sc_lock);
527
528 wlan_serialize_exit();
529 return (0);
530}
531
532static void
533urtwn_free_tx_list(struct urtwn_softc *sc)
534{
535 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT);
536}
537
538static void
539urtwn_free_rx_list(struct urtwn_softc *sc)
540{
541 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT);
542}
543
544static void
545urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata)
546{
547 int i;
548
549 for (i = 0; i < ndata; i++) {
550 struct urtwn_data *dp = &data[i];
551
552 if (dp->buf != NULL) {
553 kfree(dp->buf, M_USBDEV);
554 dp->buf = NULL;
555 }
556 if (dp->ni != NULL) {
557 ieee80211_free_node(dp->ni);
558 dp->ni = NULL;
559 }
560 }
561}
562
563static usb_error_t
564urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req,
565 void *data)
566{
567 usb_error_t err;
568 int ntries = 10;
569
570 URTWN_ASSERT_LOCKED(sc);
571
572 while (ntries--) {
573 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_lock,
574 req, data, 0, NULL, 250 /* ms */);
575 if (err == 0)
576 break;
577
578 DPRINTFN(1, "Control request failed, %s (retrying)\n",
579 usbd_errstr(err));
580 usb_pause_mtx(&sc->sc_lock, hz / 100);
581 }
582 return (err);
583}
584
585static struct ieee80211vap *
586urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
587 enum ieee80211_opmode opmode, int flags,
588 const uint8_t bssid[IEEE80211_ADDR_LEN],
589 const uint8_t mac[IEEE80211_ADDR_LEN])
590{
591 struct urtwn_vap *uvp;
592 struct ieee80211vap *vap;
593
594 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
595 return (NULL);
596
597 uvp = (struct urtwn_vap *) kmalloc(sizeof(struct urtwn_vap),
598 M_80211_VAP, M_INTWAIT | M_ZERO);
599 vap = &uvp->vap;
600 /* enable s/w bmiss handling for sta mode */
3521a462
SW
601
602 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
603 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) {
604 /* out of memory */
605 kfree(uvp, M_80211_VAP);
606 return (NULL);
607 }
790340ea
SW
608
609 /* override state transition machine */
610 uvp->newstate = vap->iv_newstate;
611 vap->iv_newstate = urtwn_newstate;
612
613 /* complete setup */
614 ieee80211_vap_attach(vap, ieee80211_media_change,
615 ieee80211_media_status);
616 ic->ic_opmode = opmode;
617 return (vap);
618}
619
620static void
621urtwn_vap_delete(struct ieee80211vap *vap)
622{
623 struct urtwn_vap *uvp = URTWN_VAP(vap);
624
625 ieee80211_vap_detach(vap);
626 kfree(uvp, M_80211_VAP);
627}
628
629static struct mbuf *
630urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p)
631{
632 struct ifnet *ifp = sc->sc_ifp;
633 struct ieee80211com *ic = ifp->if_l2com;
634 struct ieee80211_frame *wh;
635 struct mbuf *m;
636 struct r92c_rx_stat *stat;
637 uint32_t rxdw0, rxdw3;
638 uint8_t rate;
639 int8_t rssi = 0;
640 int infosz;
641
642 /*
643 * don't pass packets to the ieee80211 framework if the driver isn't
644 * RUNNING.
645 */
646 if (!(ifp->if_flags & IFF_RUNNING))
647 return (NULL);
648
649 stat = (struct r92c_rx_stat *)buf;
650 rxdw0 = le32toh(stat->rxdw0);
651 rxdw3 = le32toh(stat->rxdw3);
652
653 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) {
654 /*
655 * This should not happen since we setup our Rx filter
656 * to not receive these frames.
657 */
658 ifp->if_ierrors++;
659 return (NULL);
660 }
661
662 rate = MS(rxdw3, R92C_RXDW3_RATE);
663 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
664
665 /* Get RSSI from PHY status descriptor if present. */
666 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
3521a462
SW
667 if (sc->chip & URTWN_CHIP_88E)
668 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]);
669 else
670 rssi = urtwn_get_rssi(sc, rate, &stat[1]);
790340ea
SW
671 /* Update our average RSSI. */
672 urtwn_update_avgrssi(sc, rate, rssi);
673 /*
674 * Convert the RSSI to a range that will be accepted
675 * by net80211.
676 */
677 rssi = URTWN_RSSI(rssi);
678 }
679
680 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
681 if (m == NULL) {
682 device_printf(sc->sc_dev, "could not create RX mbuf\n");
683 return (NULL);
684 }
685
686 /* Finalize mbuf. */
687 m->m_pkthdr.rcvif = ifp;
688 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz);
689 memcpy(mtod(m, uint8_t *), wh, pktlen);
690 m->m_pkthdr.len = m->m_len = pktlen;
691
692 if (ieee80211_radiotap_active(ic)) {
693 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
694
695 tap->wr_flags = 0;
696 /* Map HW rate index to 802.11 rate. */
697 if (!(rxdw3 & R92C_RXDW3_HT)) {
698 switch (rate) {
699 /* CCK. */
700 case 0: tap->wr_rate = 2; break;
701 case 1: tap->wr_rate = 4; break;
702 case 2: tap->wr_rate = 11; break;
703 case 3: tap->wr_rate = 22; break;
704 /* OFDM. */
705 case 4: tap->wr_rate = 12; break;
706 case 5: tap->wr_rate = 18; break;
707 case 6: tap->wr_rate = 24; break;
708 case 7: tap->wr_rate = 36; break;
709 case 8: tap->wr_rate = 48; break;
710 case 9: tap->wr_rate = 72; break;
711 case 10: tap->wr_rate = 96; break;
712 case 11: tap->wr_rate = 108; break;
713 }
714 } else if (rate >= 12) { /* MCS0~15. */
715 /* Bit 7 set means HT MCS instead of rate. */
716 tap->wr_rate = 0x80 | (rate - 12);
717 }
718 tap->wr_dbm_antsignal = rssi;
719 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
720 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
721 }
722
723 *rssi_p = rssi;
724
725 return (m);
726}
727
728static struct mbuf *
729urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi,
730 int8_t *nf)
731{
732 struct urtwn_softc *sc = data->sc;
733 struct ifnet *ifp = sc->sc_ifp;
734 struct r92c_rx_stat *stat;
735 struct mbuf *m, *m0 = NULL, *prevm = NULL;
736 uint32_t rxdw0;
737 uint8_t *buf;
738 int len, totlen, pktlen, infosz, npkts;
739
740 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
741
742 if (len < sizeof(*stat)) {
743 ifp->if_ierrors++;
744 return (NULL);
745 }
746
747 buf = data->buf;
748 /* Get the number of encapsulated frames. */
749 stat = (struct r92c_rx_stat *)buf;
750 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
751 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts);
752
753 /* Process all of them. */
754 while (npkts-- > 0) {
755 if (len < sizeof(*stat))
756 break;
757 stat = (struct r92c_rx_stat *)buf;
758 rxdw0 = le32toh(stat->rxdw0);
759
760 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
761 if (pktlen == 0)
762 break;
763
764 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
765
766 /* Make sure everything fits in xfer. */
767 totlen = sizeof(*stat) + infosz + pktlen;
768 if (totlen > len)
769 break;
770
771 m = urtwn_rx_frame(sc, buf, pktlen, rssi);
772 if (m0 == NULL)
773 m0 = m;
774 if (prevm == NULL)
775 prevm = m;
776 else {
777 prevm->m_next = m;
778 prevm = m;
779 }
780
781 /* Next chunk is 128-byte aligned. */
782 totlen = (totlen + 127) & ~127;
783 buf += totlen;
784 len -= totlen;
785 }
786
787 return (m0);
788}
789
790static void
791urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
792{
793 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
794 struct ifnet *ifp = sc->sc_ifp;
795 struct ieee80211com *ic = ifp->if_l2com;
796 struct ieee80211_frame *wh;
797 struct ieee80211_node *ni;
798 struct mbuf *m = NULL, *next;
799 struct urtwn_data *data;
800 int8_t nf;
801 int rssi = 1;
802
803 URTWN_ASSERT_LOCKED(sc);
804
805 switch (USB_GET_STATE(xfer)) {
806 case USB_ST_TRANSFERRED:
807 data = STAILQ_FIRST(&sc->sc_rx_active);
808 if (data == NULL)
809 goto tr_setup;
810 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
811 m = urtwn_rxeof(xfer, data, &rssi, &nf);
812 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
813 /* FALLTHROUGH */
814 case USB_ST_SETUP:
815tr_setup:
816 data = STAILQ_FIRST(&sc->sc_rx_inactive);
817 if (data == NULL) {
818 KASSERT(m == NULL, ("mbuf isn't NULL"));
819 return;
820 }
821 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
822 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
823 usbd_xfer_set_frame_data(xfer, 0, data->buf,
824 usbd_xfer_max_len(xfer));
825 usbd_transfer_submit(xfer);
826
827 /*
828 * To avoid LOR we should unlock our private mutex here to call
829 * ieee80211_input() because here is at the end of a USB
830 * callback and safe to unlock.
831 */
832 URTWN_UNLOCK(sc);
833 while (m != NULL) {
834 next = m->m_next;
835 m->m_next = NULL;
836 wh = mtod(m, struct ieee80211_frame *);
837 ni = ieee80211_find_rxnode(ic,
838 (struct ieee80211_frame_min *)wh);
839 nf = URTWN_NOISE_FLOOR;
840 if (ni != NULL) {
841 (void)ieee80211_input(ni, m, rssi, nf);
842 ieee80211_free_node(ni);
843 } else
844 (void)ieee80211_input_all(ic, m, rssi, nf);
845 m = next;
846 }
847 URTWN_LOCK(sc);
848 break;
849 default:
850 /* needs it to the inactive queue due to a error. */
851 data = STAILQ_FIRST(&sc->sc_rx_active);
852 if (data != NULL) {
853 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
854 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
855 }
856 if (error != USB_ERR_CANCELLED) {
857 usbd_xfer_set_stall(xfer);
858 ifp->if_ierrors++;
859 goto tr_setup;
860 }
861 break;
862 }
863}
864
865static void
866urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data)
867{
868 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
869 struct ifnet *ifp = sc->sc_ifp;
870 struct mbuf *m;
871
872 URTWN_ASSERT_LOCKED(sc);
873
874 /*
875 * Do any tx complete callback. Note this must be done before releasing
876 * the node reference.
877 */
878 if (data->m) {
879 m = data->m;
880 if (m->m_flags & M_TXCB) {
881 /* XXX status? */
882 ieee80211_process_callback(data->ni, m, 0);
883 }
884 m_freem(m);
885 data->m = NULL;
886 }
887 if (data->ni) {
888 ieee80211_free_node(data->ni);
889 data->ni = NULL;
890 }
891 sc->sc_txtimer = 0;
892 ifp->if_opackets++;
893 ifq_clr_oactive(&ifp->if_snd);
894}
895
896static void
897urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
898{
899 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
900 struct ifnet *ifp = sc->sc_ifp;
901 struct urtwn_data *data;
902
903 URTWN_ASSERT_LOCKED(sc);
904
905 switch (USB_GET_STATE(xfer)){
906 case USB_ST_TRANSFERRED:
907 data = STAILQ_FIRST(&sc->sc_tx_active);
908 if (data == NULL)
909 goto tr_setup;
910 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
911 urtwn_txeof(xfer, data);
912 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
913 /* FALLTHROUGH */
914 case USB_ST_SETUP:
915tr_setup:
916 data = STAILQ_FIRST(&sc->sc_tx_pending);
917 if (data == NULL) {
918 DPRINTF("%s: empty pending queue\n", __func__);
919 return;
920 }
921 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
922 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
790340ea
SW
923 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
924 usbd_transfer_submit(xfer);
925
926 urtwn_start_locked(ifp);
927 break;
928 default:
929 data = STAILQ_FIRST(&sc->sc_tx_active);
930 if (data == NULL)
931 goto tr_setup;
932 if (data->ni != NULL) {
933 ieee80211_free_node(data->ni);
934 data->ni = NULL;
935 ifp->if_oerrors++;
936 }
937 if (error != USB_ERR_CANCELLED) {
938 usbd_xfer_set_stall(xfer);
939 goto tr_setup;
940 }
941 break;
942 }
943}
944
945static struct urtwn_data *
946_urtwn_getbuf(struct urtwn_softc *sc)
947{
948 struct urtwn_data *bf;
949
950 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
951 if (bf != NULL)
952 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
953 else
954 bf = NULL;
955 if (bf == NULL)
956 DPRINTF("%s: %s\n", __func__, "out of xmit buffers");
957 return (bf);
958}
959
960static struct urtwn_data *
961urtwn_getbuf(struct urtwn_softc *sc)
962{
963 struct urtwn_data *bf;
964
965 URTWN_ASSERT_LOCKED(sc);
966
967 bf = _urtwn_getbuf(sc);
968 if (bf == NULL) {
969 struct ifnet *ifp = sc->sc_ifp;
970 DPRINTF("%s: stop queue\n", __func__);
971 ifq_set_oactive(&ifp->if_snd);
972 }
973 return (bf);
974}
975
976static int
977urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
978 int len)
979{
980 usb_device_request_t req;
981
982 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
983 req.bRequest = R92C_REQ_REGS;
984 USETW(req.wValue, addr);
985 USETW(req.wIndex, 0);
986 USETW(req.wLength, len);
987 return (urtwn_do_request(sc, &req, buf));
988}
989
990static void
991urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
992{
993 urtwn_write_region_1(sc, addr, &val, 1);
994}
995
996
997static void
998urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
999{
1000 val = htole16(val);
1001 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
1002}
1003
1004static void
1005urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
1006{
1007 val = htole32(val);
1008 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
1009}
1010
1011static int
1012urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
1013 int len)
1014{
1015 usb_device_request_t req;
1016
1017 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1018 req.bRequest = R92C_REQ_REGS;
1019 USETW(req.wValue, addr);
1020 USETW(req.wIndex, 0);
1021 USETW(req.wLength, len);
1022 return (urtwn_do_request(sc, &req, buf));
1023}
1024
1025static uint8_t
1026urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
1027{
1028 uint8_t val;
1029
1030 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
1031 return (0xff);
1032 return (val);
1033}
1034
1035static uint16_t
1036urtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
1037{
1038 uint16_t val;
1039
1040 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
1041 return (0xffff);
1042 return (le16toh(val));
1043}
1044
1045static uint32_t
1046urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
1047{
1048 uint32_t val;
1049
1050 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
1051 return (0xffffffff);
1052 return (le32toh(val));
1053}
1054
1055static int
1056urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1057{
1058 struct r92c_fw_cmd cmd;
1059 int ntries;
1060
1061 /* Wait for current FW box to be empty. */
1062 for (ntries = 0; ntries < 100; ntries++) {
1063 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1064 break;
3521a462 1065 urtwn_ms_delay(sc);
790340ea
SW
1066 }
1067 if (ntries == 100) {
1068 device_printf(sc->sc_dev,
1069 "could not send firmware command\n");
1070 return (ETIMEDOUT);
1071 }
1072 memset(&cmd, 0, sizeof(cmd));
1073 cmd.id = id;
1074 if (len > 3)
1075 cmd.id |= R92C_CMD_FLAG_EXT;
1076 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n"));
1077 memcpy(cmd.msg, buf, len);
1078
1079 /* Write the first word last since that will trigger the FW. */
1080 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur),
1081 (uint8_t *)&cmd + 4, 2);
1082 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur),
1083 (uint8_t *)&cmd + 0, 4);
1084
1085 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1086 return (0);
1087}
1088
3521a462 1089static __inline void
790340ea 1090urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
3521a462
SW
1091{
1092
1093 sc->sc_rf_write(sc, chain, addr, val);
1094}
1095
1096static void
1097urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1098 uint32_t val)
790340ea
SW
1099{
1100 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1101 SM(R92C_LSSI_PARAM_ADDR, addr) |
1102 SM(R92C_LSSI_PARAM_DATA, val));
1103}
1104
3521a462
SW
1105static void
1106urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1107uint32_t val)
1108{
1109 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1110 SM(R88E_LSSI_PARAM_ADDR, addr) |
1111 SM(R92C_LSSI_PARAM_DATA, val));
1112}
1113
790340ea
SW
1114static uint32_t
1115urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1116{
1117 uint32_t reg[R92C_MAX_CHAINS], val;
1118
1119 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1120 if (chain != 0)
1121 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1122
1123 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1124 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
3521a462 1125 urtwn_ms_delay(sc);
790340ea
SW
1126
1127 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1128 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1129 R92C_HSSI_PARAM2_READ_EDGE);
3521a462 1130 urtwn_ms_delay(sc);
790340ea
SW
1131
1132 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1133 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
3521a462 1134 urtwn_ms_delay(sc);
790340ea
SW
1135
1136 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
1137 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1138 else
1139 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1140 return (MS(val, R92C_LSSI_READBACK_DATA));
1141}
1142
1143static int
1144urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1145{
1146 int ntries;
1147
1148 urtwn_write_4(sc, R92C_LLT_INIT,
1149 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1150 SM(R92C_LLT_INIT_ADDR, addr) |
1151 SM(R92C_LLT_INIT_DATA, data));
1152 /* Wait for write operation to complete. */
1153 for (ntries = 0; ntries < 20; ntries++) {
1154 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1155 R92C_LLT_INIT_OP_NO_ACTIVE)
1156 return (0);
3521a462 1157 urtwn_ms_delay(sc);
790340ea
SW
1158 }
1159 return (ETIMEDOUT);
1160}
1161
1162static uint8_t
1163urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr)
1164{
1165 uint32_t reg;
1166 int ntries;
1167
1168 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1169 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
1170 reg &= ~R92C_EFUSE_CTRL_VALID;
1171 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1172 /* Wait for read operation to complete. */
1173 for (ntries = 0; ntries < 100; ntries++) {
1174 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1175 if (reg & R92C_EFUSE_CTRL_VALID)
1176 return (MS(reg, R92C_EFUSE_CTRL_DATA));
3521a462 1177 urtwn_ms_delay(sc);
790340ea
SW
1178 }
1179 device_printf(sc->sc_dev,
1180 "could not read efuse byte at address 0x%x\n", addr);
1181 return (0xff);
1182}
1183
1184static void
1185urtwn_efuse_read(struct urtwn_softc *sc)
1186{
1187 uint8_t *rom = (uint8_t *)&sc->rom;
1188 uint16_t addr = 0;
1189 uint32_t reg;
1190 uint8_t off, msk;
1191 int i;
1192
3521a462
SW
1193 urtwn_efuse_switch_power(sc);
1194
790340ea
SW
1195 memset(&sc->rom, 0xff, sizeof(sc->rom));
1196 while (addr < 512) {
1197 reg = urtwn_efuse_read_1(sc, addr);
1198 if (reg == 0xff)
1199 break;
1200 addr++;
1201 off = reg >> 4;
1202 msk = reg & 0xf;
1203 for (i = 0; i < 4; i++) {
1204 if (msk & (1 << i))
1205 continue;
1206 rom[off * 8 + i * 2 + 0] =
1207 urtwn_efuse_read_1(sc, addr);
1208 addr++;
1209 rom[off * 8 + i * 2 + 1] =
1210 urtwn_efuse_read_1(sc, addr);
1211 addr++;
1212 }
1213 }
1214#ifdef URTWN_DEBUG
1215 if (urtwn_debug >= 2) {
1216 /* Dump ROM content. */
1217 printf("\n");
1218 for (i = 0; i < sizeof(sc->rom); i++)
1219 printf("%02x:", rom[i]);
1220 printf("\n");
1221 }
1222#endif
1223}
3521a462
SW
1224static void
1225urtwn_efuse_switch_power(struct urtwn_softc *sc)
1226{
1227 uint32_t reg;
1228
1229 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1230 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1231 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1232 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1233 }
1234 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1235 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1236 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1237 reg | R92C_SYS_FUNC_EN_ELDR);
1238 }
1239 reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1240 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1241 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1242 urtwn_write_2(sc, R92C_SYS_CLKR,
1243 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1244 }
1245}
790340ea
SW
1246
1247static int
1248urtwn_read_chipid(struct urtwn_softc *sc)
1249{
1250 uint32_t reg;
1251
3521a462
SW
1252 if (sc->chip & URTWN_CHIP_88E)
1253 return (0);
1254
790340ea
SW
1255 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1256 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1257 return (EIO);
1258
1259 if (reg & R92C_SYS_CFG_TYPE_92C) {
1260 sc->chip |= URTWN_CHIP_92C;
1261 /* Check if it is a castrated 8192C. */
1262 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1263 R92C_HPON_FSM_CHIP_BONDING_ID) ==
1264 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1265 sc->chip |= URTWN_CHIP_92C_1T2R;
1266 }
1267 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1268 sc->chip |= URTWN_CHIP_UMC;
1269 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1270 sc->chip |= URTWN_CHIP_UMC_A_CUT;
1271 }
1272 return (0);
1273}
1274
1275static void
1276urtwn_read_rom(struct urtwn_softc *sc)
1277{
1278 struct r92c_rom *rom = &sc->rom;
1279
1280 /* Read full ROM image. */
1281 urtwn_efuse_read(sc);
1282
1283 /* XXX Weird but this is what the vendor driver does. */
1284 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa);
1285 DPRINTF("PA setting=0x%x\n", sc->pa_setting);
1286
1287 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1288
1289 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1290 DPRINTF("regulatory type=%d\n", sc->regulatory);
790340ea 1291 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr);
3521a462
SW
1292
1293 sc->sc_rf_write = urtwn_r92c_rf_write;
1294 sc->sc_power_on = urtwn_r92c_power_on;
1295 sc->sc_dma_init = urtwn_r92c_dma_init;
1296}
1297
1298static void
1299urtwn_r88e_read_rom(struct urtwn_softc *sc)
1300{
1301 uint8_t *rom = sc->r88e_rom;
1302 uint16_t addr = 0;
1303 uint32_t reg;
1304 uint8_t off, msk, tmp;
1305 int i;
1306
1307 off = 0;
1308 urtwn_efuse_switch_power(sc);
1309
1310 /* Read full ROM image. */
1311 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom));
1312 while (addr < 1024) {
1313 reg = urtwn_efuse_read_1(sc, addr);
1314 if (reg == 0xff)
1315 break;
1316 addr++;
1317 if ((reg & 0x1f) == 0x0f) {
1318 tmp = (reg & 0xe0) >> 5;
1319 reg = urtwn_efuse_read_1(sc, addr);
1320 if ((reg & 0x0f) != 0x0f)
1321 off = ((reg & 0xf0) >> 1) | tmp;
1322 addr++;
1323 } else
1324 off = reg >> 4;
1325 msk = reg & 0xf;
1326 for (i = 0; i < 4; i++) {
1327 if (msk & (1 << i))
1328 continue;
1329 rom[off * 8 + i * 2 + 0] =
1330 urtwn_efuse_read_1(sc, addr);
1331 addr++;
1332 rom[off * 8 + i * 2 + 1] =
1333 urtwn_efuse_read_1(sc, addr);
1334 addr++;
1335 }
1336 }
1337
1338 addr = 0x10;
1339 for (i = 0; i < 6; i++)
1340 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++];
1341 for (i = 0; i < 5; i++)
1342 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++];
1343 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4;
1344 if (sc->bw20_tx_pwr_diff & 0x08)
1345 sc->bw20_tx_pwr_diff |= 0xf0;
1346 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf);
1347 if (sc->ofdm_tx_pwr_diff & 0x08)
1348 sc->ofdm_tx_pwr_diff |= 0xf0;
1349 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY);
1350 IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]);
1351
1352 sc->sc_rf_write = urtwn_r88e_rf_write;
1353 sc->sc_power_on = urtwn_r88e_power_on;
1354 sc->sc_dma_init = urtwn_r88e_dma_init;
790340ea
SW
1355}
1356
1357/*
1358 * Initialize rate adaptation in firmware.
1359 */
1360static int
1361urtwn_ra_init(struct urtwn_softc *sc)
1362{
1363 static const uint8_t map[] =
1364 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
1365 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1366 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1367 struct ieee80211_node *ni;
1368 struct ieee80211_rateset *rs;
1369 struct r92c_fw_cmd_macid_cfg cmd;
1370 uint32_t rates, basicrates;
1371 uint8_t mode;
1372 int maxrate, maxbasicrate, error, i, j;
1373
1374 ni = ieee80211_ref_node(vap->iv_bss);
1375 rs = &ni->ni_rates;
1376
1377 /* Get normal and basic rates mask. */
1378 rates = basicrates = 0;
1379 maxrate = maxbasicrate = 0;
1380 for (i = 0; i < rs->rs_nrates; i++) {
1381 /* Convert 802.11 rate to HW rate index. */
1382 for (j = 0; j < NELEM(map); j++)
1383 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j])
1384 break;
1385 if (j == NELEM(map)) /* Unknown rate, skip. */
1386 continue;
1387 rates |= 1 << j;
1388 if (j > maxrate)
1389 maxrate = j;
1390 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1391 basicrates |= 1 << j;
1392 if (j > maxbasicrate)
1393 maxbasicrate = j;
1394 }
1395 }
1396 if (ic->ic_curmode == IEEE80211_MODE_11B)
1397 mode = R92C_RAID_11B;
1398 else
1399 mode = R92C_RAID_11BG;
1400 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1401 mode, rates, basicrates);
1402
1403 /* Set rates mask for group addressed frames. */
1404 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
1405 cmd.mask = htole32(mode << 28 | basicrates);
1406 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1407 if (error != 0) {
1408 ieee80211_free_node(ni);
1409 device_printf(sc->sc_dev,
1410 "could not add broadcast station\n");
1411 return (error);
1412 }
1413 /* Set initial MRR rate. */
1414 DPRINTF("maxbasicrate=%d\n", maxbasicrate);
1415 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC),
1416 maxbasicrate);
1417
1418 /* Set rates mask for unicast frames. */
1419 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
1420 cmd.mask = htole32(mode << 28 | rates);
1421 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1422 if (error != 0) {
1423 ieee80211_free_node(ni);
1424 device_printf(sc->sc_dev, "could not add BSS station\n");
1425 return (error);
1426 }
1427 /* Set initial MRR rate. */
1428 DPRINTF("maxrate=%d\n", maxrate);
1429 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS),
1430 maxrate);
1431
1432 /* Indicate highest supported rate. */
1433 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
1434 ieee80211_free_node(ni);
1435
1436 return (0);
1437}
1438
1439void
1440urtwn_tsf_sync_enable(struct urtwn_softc *sc)
1441{
1442 struct ifnet *ifp = sc->sc_ifp;
1443 struct ieee80211com *ic = ifp->if_l2com;
1444 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1445 struct ieee80211_node *ni = vap->iv_bss;
1446
1447 uint64_t tsf;
1448
1449 /* Enable TSF synchronization. */
1450 urtwn_write_1(sc, R92C_BCN_CTRL,
1451 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1452
1453 urtwn_write_1(sc, R92C_BCN_CTRL,
1454 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1455
1456 /* Set initial TSF. */
1457 memcpy(&tsf, ni->ni_tstamp.data, 8);
1458 tsf = le64toh(tsf);
1459 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU));
1460 tsf -= IEEE80211_DUR_TU;
1461 urtwn_write_4(sc, R92C_TSFTR + 0, tsf);
1462 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32);
1463
1464 urtwn_write_1(sc, R92C_BCN_CTRL,
1465 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1466}
1467
1468static void
1469urtwn_set_led(struct urtwn_softc *sc, int led, int on)
1470{
1471 uint8_t reg;
3521a462 1472
790340ea 1473 if (led == URTWN_LED_LINK) {
3521a462
SW
1474 if (sc->chip & URTWN_CHIP_88E) {
1475 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1476 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);
1477 if (!on) {
1478 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
1479 urtwn_write_1(sc, R92C_LEDCFG2,
1480 reg | R92C_LEDCFG0_DIS);
1481 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG,
1482 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) &
1483 0xfe);
1484 }
1485 } else {
1486 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
1487 if (!on)
1488 reg |= R92C_LEDCFG0_DIS;
1489 urtwn_write_1(sc, R92C_LEDCFG0, reg);
1490 }
1491 sc->ledlink = on; /* Save LED state. */
790340ea
SW
1492 }
1493}
1494
1495static int
1496urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1497{
1498 struct urtwn_vap *uvp = URTWN_VAP(vap);
1499 struct ieee80211com *ic = vap->iv_ic;
1500 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
1501 struct ieee80211_node *ni;
1502 enum ieee80211_state ostate;
1503 uint32_t reg;
1504
1505 ostate = vap->iv_state;
1506 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate],
1507 ieee80211_state_name[nstate]);
1508
1509 URTWN_LOCK(sc);
1510 callout_stop(&sc->sc_watchdog_ch);
1511
1512 if (ostate == IEEE80211_S_RUN) {
1513 /* Turn link LED off. */
1514 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1515
1516 /* Set media status to 'No Link'. */
1517 reg = urtwn_read_4(sc, R92C_CR);
1518 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK);
1519 urtwn_write_4(sc, R92C_CR, reg);
1520
1521 /* Stop Rx of data frames. */
1522 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1523
1524 /* Rest TSF. */
1525 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1526
1527 /* Disable TSF synchronization. */
1528 urtwn_write_1(sc, R92C_BCN_CTRL,
1529 urtwn_read_1(sc, R92C_BCN_CTRL) |
1530 R92C_BCN_CTRL_DIS_TSF_UDT0);
1531
1532 /* Reset EDCA parameters. */
1533 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1534 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1535 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1536 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1537 }
1538
1539 switch (nstate) {
1540 case IEEE80211_S_INIT:
1541 /* Turn link LED off. */
1542 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1543 break;
1544 case IEEE80211_S_SCAN:
1545 if (ostate != IEEE80211_S_SCAN) {
1546 /* Allow Rx from any BSSID. */
1547 urtwn_write_4(sc, R92C_RCR,
1548 urtwn_read_4(sc, R92C_RCR) &
1549 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1550
1551 /* Set gain for scanning. */
1552 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1553 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1554 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1555
3521a462
SW
1556 if (!(sc->chip & URTWN_CHIP_88E)) {
1557 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1558 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1559 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1560 }
790340ea 1561 }
790340ea
SW
1562 /* Make link LED blink during scan. */
1563 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
1564
1565 /* Pause AC Tx queues. */
1566 urtwn_write_1(sc, R92C_TXPAUSE,
1567 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1568
1569 urtwn_set_chan(sc, ic->ic_curchan, NULL);
1570 break;
1571 case IEEE80211_S_AUTH:
1572 /* Set initial gain under link. */
1573 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1574 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1575 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1576
3521a462
SW
1577 if (!(sc->chip & URTWN_CHIP_88E)) {
1578 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1579 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1580 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1581 }
790340ea
SW
1582 urtwn_set_chan(sc, ic->ic_curchan, NULL);
1583 break;
1584 case IEEE80211_S_RUN:
1585 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1586 /* Enable Rx of data frames. */
1587 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1588
1589 /* Turn link LED on. */
1590 urtwn_set_led(sc, URTWN_LED_LINK, 1);
1591 break;
1592 }
1593
1594 ni = ieee80211_ref_node(vap->iv_bss);
1595 /* Set media status to 'Associated'. */
1596 reg = urtwn_read_4(sc, R92C_CR);
1597 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
1598 urtwn_write_4(sc, R92C_CR, reg);
1599
1600 /* Set BSSID. */
1601 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
1602 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
1603
1604 if (ic->ic_curmode == IEEE80211_MODE_11B)
1605 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
1606 else /* 802.11b/g */
1607 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
1608
1609 /* Enable Rx of data frames. */
1610 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1611
1612 /* Flush all AC queues. */
1613 urtwn_write_1(sc, R92C_TXPAUSE, 0);
1614
1615 /* Set beacon interval. */
1616 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
1617
1618 /* Allow Rx from our BSSID only. */
1619 urtwn_write_4(sc, R92C_RCR,
1620 urtwn_read_4(sc, R92C_RCR) |
1621 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1622
1623 /* Enable TSF synchronization. */
1624 urtwn_tsf_sync_enable(sc);
1625
1626 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
1627 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
1628 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
1629 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
1630 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
1631 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
1632
1633 /* Intialize rate adaptation. */
3521a462
SW
1634 if (sc->chip & URTWN_CHIP_88E)
1635 ni->ni_txrate =
1636 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1];
1637 else
1638 urtwn_ra_init(sc);
790340ea
SW
1639 /* Turn link LED on. */
1640 urtwn_set_led(sc, URTWN_LED_LINK, 1);
1641
1642 sc->avg_pwdb = -1; /* Reset average RSSI. */
1643 /* Reset temperature calibration state machine. */
1644 sc->thcal_state = 0;
1645 sc->thcal_lctemp = 0;
1646 ieee80211_free_node(ni);
1647 break;
1648 default:
1649 break;
1650 }
1651 URTWN_UNLOCK(sc);
1652 return(uvp->newstate(vap, nstate, arg));
1653}
1654
1655static void
1656urtwn_watchdog(void *arg)
1657{
1658 struct urtwn_softc *sc = arg;
1659 struct ifnet *ifp = sc->sc_ifp;
1660
1661 if (sc->sc_txtimer > 0) {
1662 if (--sc->sc_txtimer == 0) {
1663 device_printf(sc->sc_dev, "device timeout\n");
1664 ifp->if_oerrors++;
1665 return;
1666 }
1667 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1668 }
1669}
1670
1671static void
1672urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
1673{
1674 int pwdb;
1675
1676 /* Convert antenna signal to percentage. */
1677 if (rssi <= -100 || rssi >= 20)
1678 pwdb = 0;
1679 else if (rssi >= 0)
1680 pwdb = 100;
1681 else
1682 pwdb = 100 + rssi;
3521a462
SW
1683 if (!(sc->chip & URTWN_CHIP_88E)) {
1684 if (rate <= 3) {
1685 /* CCK gain is smaller than OFDM/MCS gain. */
1686 pwdb += 6;
1687 if (pwdb > 100)
1688 pwdb = 100;
1689 if (pwdb <= 14)
1690 pwdb -= 4;
1691 else if (pwdb <= 26)
1692 pwdb -= 8;
1693 else if (pwdb <= 34)
1694 pwdb -= 6;
1695 else if (pwdb <= 42)
1696 pwdb -= 2;
1697 }
790340ea
SW
1698 }
1699 if (sc->avg_pwdb == -1) /* Init. */
1700 sc->avg_pwdb = pwdb;
1701 else if (sc->avg_pwdb < pwdb)
1702 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
1703 else
1704 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
1705 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb);
1706}
1707
1708static int8_t
1709urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
1710{
1711 static const int8_t cckoff[] = { 16, -12, -26, -46 };
1712 struct r92c_rx_phystat *phy;
1713 struct r92c_rx_cck *cck;
1714 uint8_t rpt;
1715 int8_t rssi;
1716
1717 if (rate <= 3) {
1718 cck = (struct r92c_rx_cck *)physt;
1719 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) {
1720 rpt = (cck->agc_rpt >> 5) & 0x3;
1721 rssi = (cck->agc_rpt & 0x1f) << 1;
1722 } else {
1723 rpt = (cck->agc_rpt >> 6) & 0x3;
1724 rssi = cck->agc_rpt & 0x3e;
1725 }
1726 rssi = cckoff[rpt] - rssi;
1727 } else { /* OFDM/HT. */
1728 phy = (struct r92c_rx_phystat *)physt;
1729 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1730 }
1731 return (rssi);
1732}
1733
3521a462
SW
1734static int8_t
1735urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
1736{
1737 struct r92c_rx_phystat *phy;
1738 struct r88e_rx_cck *cck;
1739 uint8_t cck_agc_rpt, lna_idx, vga_idx;
1740 int8_t rssi;
1741
1742 rssi = 0;
1743 if (rate <= 3) {
1744 cck = (struct r88e_rx_cck *)physt;
1745 cck_agc_rpt = cck->agc_rpt;
1746 lna_idx = (cck_agc_rpt & 0xe0) >> 5;
1747 vga_idx = cck_agc_rpt & 0x1f;
1748 switch (lna_idx) {
1749 case 7:
1750 if (vga_idx <= 27)
1751 rssi = -100 + 2* (27 - vga_idx);
1752 else
1753 rssi = -100;
1754 break;
1755 case 6:
1756 rssi = -48 + 2 * (2 - vga_idx);
1757 break;
1758 case 5:
1759 rssi = -42 + 2 * (7 - vga_idx);
1760 break;
1761 case 4:
1762 rssi = -36 + 2 * (7 - vga_idx);
1763 break;
1764 case 3:
1765 rssi = -24 + 2 * (7 - vga_idx);
1766 break;
1767 case 2:
1768 rssi = -12 + 2 * (5 - vga_idx);
1769 break;
1770 case 1:
1771 rssi = 8 - (2 * vga_idx);
1772 break;
1773 case 0:
1774 rssi = 14 - (2 * vga_idx);
1775 break;
1776 }
1777 rssi += 6;
1778 } else { /* OFDM/HT. */
1779 phy = (struct r92c_rx_phystat *)physt;
1780 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1781 }
1782 return (rssi);
1783}
1784
1785
790340ea
SW
1786static int
1787urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
1788 struct mbuf *m0, struct urtwn_data *data)
1789{
1790 struct ifnet *ifp = sc->sc_ifp;
1791 struct ieee80211_frame *wh;
1792 struct ieee80211_key *k;
1793 struct ieee80211com *ic = ifp->if_l2com;
1794 struct ieee80211vap *vap = ni->ni_vap;
1795 struct usb_xfer *xfer;
1796 struct r92c_tx_desc *txd;
1797 uint8_t raid, type;
1798 uint16_t sum;
1799 int i, hasqos, xferlen;
1800 struct usb_xfer *urtwn_pipes[4] = {
1801 sc->sc_xfer[URTWN_BULK_TX_BE],
1802 sc->sc_xfer[URTWN_BULK_TX_BK],
1803 sc->sc_xfer[URTWN_BULK_TX_VI],
1804 sc->sc_xfer[URTWN_BULK_TX_VO]
1805 };
1806
1807 URTWN_ASSERT_LOCKED(sc);
1808
1809 /*
1810 * Software crypto.
1811 */
1812 wh = mtod(m0, struct ieee80211_frame *);
3521a462
SW
1813 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1814
085ff963 1815 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
790340ea
SW
1816 k = ieee80211_crypto_encap(ni, m0);
1817 if (k == NULL) {
1818 device_printf(sc->sc_dev,
1819 "ieee80211_crypto_encap returns NULL.\n");
1820 /* XXX we don't expect the fragmented frames */
1821 m_freem(m0);
1822 return (ENOBUFS);
1823 }
1824
1825 /* in case packet header moved, reset pointer */
1826 wh = mtod(m0, struct ieee80211_frame *);
1827 }
1828
3521a462 1829 switch (type) {
790340ea
SW
1830 case IEEE80211_FC0_TYPE_CTL:
1831 case IEEE80211_FC0_TYPE_MGT:
1832 xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
1833 break;
1834 default:
1835 KASSERT(M_WME_GETAC(m0) < 4,
1836 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1837 xfer = urtwn_pipes[M_WME_GETAC(m0)];
1838 break;
1839 }
1840
1841 hasqos = 0;
1842
1843 /* Fill Tx descriptor. */
1844 txd = (struct r92c_tx_desc *)data->buf;
1845 memset(txd, 0, sizeof(*txd));
1846
1847 txd->txdw0 |= htole32(
1848 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) |
1849 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1850 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1851 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1852 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
790340ea
SW
1853 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1854 type == IEEE80211_FC0_TYPE_DATA) {
1855 if (ic->ic_curmode == IEEE80211_MODE_11B)
1856 raid = R92C_RAID_11B;
1857 else
1858 raid = R92C_RAID_11BG;
3521a462
SW
1859 if (sc->chip & URTWN_CHIP_88E) {
1860 txd->txdw1 |= htole32(
1861 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) |
1862 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1863 SM(R92C_TXDW1_RAID, raid));
1864 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK);
1865 } else {
1866 txd->txdw1 |= htole32(
1867 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
1868 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1869 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK);
1870 }
790340ea
SW
1871 if (ic->ic_flags & IEEE80211_F_USEPROT) {
1872 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1873 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1874 R92C_TXDW4_HWRTSEN);
1875 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1876 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1877 R92C_TXDW4_HWRTSEN);
1878 }
1879 }
1880 /* Send RTS at OFDM24. */
1881 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
1882 txd->txdw5 |= htole32(0x0001ff00);
1883 /* Send data at OFDM54. */
3521a462
SW
1884 if (sc->chip & URTWN_CHIP_88E)
1885 txd->txdw5 |= htole32(0x13 & 0x3f);
1886 else
1887 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
790340ea
SW
1888 } else {
1889 txd->txdw1 |= htole32(
1890 SM(R92C_TXDW1_MACID, 0) |
1891 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1892 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1893
1894 /* Force CCK1. */
1895 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1896 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1897 }
1898 /* Set sequence number (already little endian). */
1899 txd->txdseq |= *(uint16_t *)wh->i_seq;
1900
1901 if (!hasqos) {
1902 /* Use HW sequence numbering for non-QoS frames. */
1903 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
1904 txd->txdseq |= htole16(0x8000);
1905 } else
1906 txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1907
1908 /* Compute Tx descriptor checksum. */
1909 sum = 0;
1910 for (i = 0; i < sizeof(*txd) / 2; i++)
1911 sum ^= ((uint16_t *)txd)[i];
1912 txd->txdsum = sum; /* NB: already little endian. */
1913
1914 if (ieee80211_radiotap_active_vap(vap)) {
1915 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1916
1917 tap->wt_flags = 0;
1918 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1919 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1920 ieee80211_radiotap_tx(vap, m0);
1921 }
1922
1923 xferlen = sizeof(*txd) + m0->m_pkthdr.len;
1924 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]);
1925
1926 data->buflen = xferlen;
1927 data->ni = ni;
1928 data->m = m0;
1929
1930 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1931 usbd_transfer_start(xfer);
1932 return (0);
1933}
1934
3521a462
SW
1935static void
1936urtwn_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1937{
1938 if ((ifp->if_flags & IFF_RUNNING) == 0)
1939 return;
1940
1941 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1942 urtwn_start_locked(ifp);
1943}
1944
790340ea
SW
1945static void
1946urtwn_start_locked(struct ifnet *ifp)
1947{
1948 struct urtwn_softc *sc = ifp->if_softc;
1949 struct ieee80211_node *ni;
1950 struct mbuf *m;
1951 struct urtwn_data *bf;
1952
790340ea
SW
1953 URTWN_LOCK(sc);
1954 for (;;) {
1955 m = ifq_dequeue(&ifp->if_snd);
1956 if (m == NULL)
1957 break;
1958 bf = urtwn_getbuf(sc);
1959 if (bf == NULL) {
1960 ifq_prepend(&ifp->if_snd, m);
1961 break;
1962 }
1963 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1964 m->m_pkthdr.rcvif = NULL;
1965
1966 if (urtwn_tx_start(sc, ni, m, bf) != 0) {
1967 ifp->if_oerrors++;
1968 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1969 ieee80211_free_node(ni);
1970 break;
1971 }
1972
1973 sc->sc_txtimer = 5;
1974 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1975 }
1976 URTWN_UNLOCK(sc);
1977}
1978
790340ea
SW
1979static int
1980urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred)
1981{
3521a462 1982 struct urtwn_softc *sc = ifp->if_softc;
790340ea
SW
1983 struct ieee80211com *ic = ifp->if_l2com;
1984 struct ifreq *ifr = (struct ifreq *) data;
1985 int error = 0, startall = 0;
1986
3521a462
SW
1987 URTWN_LOCK(sc);
1988 error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0;
1989 URTWN_UNLOCK(sc);
1990 if (error != 0)
1991 return (error);
1992
790340ea
SW
1993 switch (cmd) {
1994 case SIOCSIFFLAGS:
1995 if (ifp->if_flags & IFF_UP) {
1996 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1997 urtwn_init(ifp->if_softc);
1998 startall = 1;
1999 }
2000 } else {
2001 if (ifp->if_flags & IFF_RUNNING)
3521a462 2002 urtwn_stop(ifp);
790340ea
SW
2003 }
2004 if (startall)
2005 ieee80211_start_all(ic);
2006 break;
2007 case SIOCGIFMEDIA:
2008 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
2009 break;
2010 case SIOCGIFADDR:
2011 error = ether_ioctl(ifp, cmd, data);
2012 break;
2013 default:
2014 error = EINVAL;
2015 break;
2016 }
2017 return (error);
2018}
2019
2020static int
2021urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[],
2022 int ndata, int maxsz)
2023{
2024 int i;
2025
2026 for (i = 0; i < ndata; i++) {
2027 struct urtwn_data *dp = &data[i];
2028 dp->sc = sc;
2029 dp->m = NULL;
2030 dp->buf = kmalloc(maxsz, M_USBDEV, M_WAITOK);
2031 dp->ni = NULL;
2032 }
2033
2034 return (0);
2035}
2036
2037static int
2038urtwn_alloc_rx_list(struct urtwn_softc *sc)
2039{
2040 int error, i;
2041
2042 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT,
2043 URTWN_RXBUFSZ);
2044 if (error != 0)
2045 return (error);
2046
2047 STAILQ_INIT(&sc->sc_rx_active);
2048 STAILQ_INIT(&sc->sc_rx_inactive);
2049
2050 for (i = 0; i < URTWN_RX_LIST_COUNT; i++)
2051 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
2052
2053 return (0);
2054}
2055
2056static int
2057urtwn_alloc_tx_list(struct urtwn_softc *sc)
2058{
2059 int error, i;
2060
2061 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT,
2062 URTWN_TXBUFSZ);
2063 if (error != 0)
2064 return (error);
2065
2066 STAILQ_INIT(&sc->sc_tx_active);
2067 STAILQ_INIT(&sc->sc_tx_inactive);
2068 STAILQ_INIT(&sc->sc_tx_pending);
2069
2070 for (i = 0; i < URTWN_TX_LIST_COUNT; i++)
2071 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next);
2072
2073 return (0);
2074}
2075
3521a462 2076static __inline int
790340ea 2077urtwn_power_on(struct urtwn_softc *sc)
3521a462
SW
2078{
2079
2080 return sc->sc_power_on(sc);
2081}
2082
2083static int
2084urtwn_r92c_power_on(struct urtwn_softc *sc)
790340ea
SW
2085{
2086 uint32_t reg;
2087 int ntries;
2088
2089 /* Wait for autoload done bit. */
2090 for (ntries = 0; ntries < 1000; ntries++) {
2091 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
2092 break;
3521a462 2093 urtwn_ms_delay(sc);
790340ea
SW
2094 }
2095 if (ntries == 1000) {
2096 device_printf(sc->sc_dev,
2097 "timeout waiting for chip autoload\n");
2098 return (ETIMEDOUT);
2099 }
2100
2101 /* Unlock ISO/CLK/Power control register. */
2102 urtwn_write_1(sc, R92C_RSV_CTRL, 0);
2103 /* Move SPS into PWM mode. */
2104 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
3521a462 2105 urtwn_ms_delay(sc);
790340ea
SW
2106
2107 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
2108 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
2109 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
2110 reg | R92C_LDOV12D_CTRL_LDV12_EN);
3521a462 2111 urtwn_ms_delay(sc);
790340ea
SW
2112 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
2113 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
2114 ~R92C_SYS_ISO_CTRL_MD2PP);
2115 }
2116
2117 /* Auto enable WLAN. */
2118 urtwn_write_2(sc, R92C_APS_FSMCO,
2119 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
2120 for (ntries = 0; ntries < 1000; ntries++) {
3521a462
SW
2121 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
2122 R92C_APS_FSMCO_APFM_ONMAC))
790340ea 2123 break;
3521a462 2124 urtwn_ms_delay(sc);
790340ea
SW
2125 }
2126 if (ntries == 1000) {
2127 device_printf(sc->sc_dev,
2128 "timeout waiting for MAC auto ON\n");
2129 return (ETIMEDOUT);
2130 }
2131
2132 /* Enable radio, GPIO and LED functions. */
2133 urtwn_write_2(sc, R92C_APS_FSMCO,
2134 R92C_APS_FSMCO_AFSM_HSUS |
2135 R92C_APS_FSMCO_PDN_EN |
2136 R92C_APS_FSMCO_PFM_ALDN);
2137 /* Release RF digital isolation. */
2138 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
2139 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
2140
2141 /* Initialize MAC. */
2142 urtwn_write_1(sc, R92C_APSD_CTRL,
2143 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
2144 for (ntries = 0; ntries < 200; ntries++) {
2145 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
2146 R92C_APSD_CTRL_OFF_STATUS))
2147 break;
3521a462 2148 urtwn_ms_delay(sc);
790340ea
SW
2149 }
2150 if (ntries == 200) {
2151 device_printf(sc->sc_dev,
2152 "timeout waiting for MAC initialization\n");
2153 return (ETIMEDOUT);
2154 }
2155
2156 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2157 reg = urtwn_read_2(sc, R92C_CR);
2158 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2159 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2160 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
2161 R92C_CR_ENSEC;
2162 urtwn_write_2(sc, R92C_CR, reg);
2163
2164 urtwn_write_1(sc, 0xfe10, 0x19);
2165 return (0);
2166}
2167
3521a462
SW
2168static int
2169urtwn_r88e_power_on(struct urtwn_softc *sc)
2170{
2171 uint8_t val;
2172 uint32_t reg;
2173 int ntries;
2174
2175 /* Wait for power ready bit. */
2176 for (ntries = 0; ntries < 5000; ntries++) {
2177 val = urtwn_read_1(sc, 0x6) & 0x2;
2178 if (val == 0x2)
2179 break;
2180 urtwn_ms_delay(sc);
2181 }
2182 if (ntries == 5000) {
2183 device_printf(sc->sc_dev,
2184 "timeout waiting for chip power up\n");
2185 return (ETIMEDOUT);
2186 }
2187
2188 /* Reset BB. */
2189 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2190 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
2191 R92C_SYS_FUNC_EN_BB_GLB_RST));
2192
2193 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
2194
2195 /* Disable HWPDN. */
2196 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
2197
2198 /* Disable WL suspend. */
2199 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
2200
2201 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
2202 for (ntries = 0; ntries < 5000; ntries++) {
2203 if (!(urtwn_read_1(sc, 0x5) & 0x1))
2204 break;
2205 urtwn_ms_delay(sc);
2206 }
2207 if (ntries == 5000)
2208 return (ETIMEDOUT);
2209
2210 /* Enable LDO normal mode. */
2211 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
2212
2213 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2214 urtwn_write_2(sc, R92C_CR, 0);
2215 reg = urtwn_read_2(sc, R92C_CR);
2216 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2217 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2218 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
2219 urtwn_write_2(sc, R92C_CR, reg);
2220
2221 return (0);
2222}
2223
790340ea
SW
2224static int
2225urtwn_llt_init(struct urtwn_softc *sc)
2226{
3521a462
SW
2227 int i, error, page_count, pktbuf_count;
2228
2229 page_count = (sc->chip & URTWN_CHIP_88E) ?
2230 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT;
2231 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ?
2232 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT;
790340ea 2233
3521a462
SW
2234 /* Reserve pages [0; page_count]. */
2235 for (i = 0; i < page_count; i++) {
790340ea
SW
2236 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
2237 return (error);
2238 }
2239 /* NB: 0xff indicates end-of-list. */
2240 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
2241 return (error);
2242 /*
3521a462 2243 * Use pages [page_count + 1; pktbuf_count - 1]
790340ea
SW
2244 * as ring buffer.
2245 */
3521a462 2246 for (++i; i < pktbuf_count - 1; i++) {
790340ea
SW
2247 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
2248 return (error);
2249 }
2250 /* Make the last page point to the beginning of the ring buffer. */
3521a462 2251 error = urtwn_llt_write(sc, i, page_count + 1);
790340ea
SW
2252 return (error);
2253}
2254
2255static void
2256urtwn_fw_reset(struct urtwn_softc *sc)
2257{
2258 uint16_t reg;
2259 int ntries;
2260
2261 /* Tell 8051 to reset itself. */
2262 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
2263
2264 /* Wait until 8051 resets by itself. */
2265 for (ntries = 0; ntries < 100; ntries++) {
2266 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
2267 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
2268 return;
3521a462 2269 urtwn_ms_delay(sc);
790340ea
SW
2270 }
2271 /* Force 8051 reset. */
2272 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
2273}
2274
3521a462
SW
2275static void
2276urtwn_r88e_fw_reset(struct urtwn_softc *sc)
2277{
2278 uint16_t reg;
2279
2280 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
2281 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
2282 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
2283}
2284
790340ea
SW
2285static int
2286urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len)
2287{
2288 uint32_t reg;
2289 int off, mlen, error = 0;
2290
2291 reg = urtwn_read_4(sc, R92C_MCUFWDL);
2292 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
2293 urtwn_write_4(sc, R92C_MCUFWDL, reg);
2294
2295 off = R92C_FW_START_ADDR;
2296 while (len > 0) {
2297 if (len > 196)
2298 mlen = 196;
2299 else if (len > 4)
2300 mlen = 4;
2301 else
2302 mlen = 1;
2303 /* XXX fix this deconst */
2304 error = urtwn_write_region_1(sc, off,
2305 __DECONST(uint8_t *, buf), mlen);
2306 if (error != 0)
2307 break;
2308 off += mlen;
2309 buf += mlen;
2310 len -= mlen;
2311 }
2312 return (error);
2313}
2314
2315static int
2316urtwn_load_firmware(struct urtwn_softc *sc)
2317{
2318 const struct firmware *fw;
2319 const struct r92c_fw_hdr *hdr;
2320 const char *imagename;
2321 const u_char *ptr;
2322 size_t len;
2323 uint32_t reg;
2324 int mlen, ntries, page, error;
2325
3521a462 2326 URTWN_UNLOCK(sc);
790340ea 2327 /* Read firmware image from the filesystem. */
3521a462
SW
2328 if (sc->chip & URTWN_CHIP_88E)
2329 imagename = "urtwn-rtl8188eufw";
2330 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2331 URTWN_CHIP_UMC_A_CUT)
790340ea
SW
2332 imagename = "urtwn-rtl8192cfwU";
2333 else
2334 imagename = "urtwn-rtl8192cfwT";
2335
2336 fw = firmware_get(imagename);
3521a462 2337 URTWN_LOCK(sc);
790340ea
SW
2338 if (fw == NULL) {
2339 device_printf(sc->sc_dev,
2340 "failed loadfirmware of file %s\n", imagename);
2341 return (ENOENT);
2342 }
2343
2344 len = fw->datasize;
2345
2346 if (len < sizeof(*hdr)) {
2347 device_printf(sc->sc_dev, "firmware too short\n");
2348 error = EINVAL;
2349 goto fail;
2350 }
2351 ptr = fw->data;
2352 hdr = (const struct r92c_fw_hdr *)ptr;
2353 /* Check if there is a valid FW header and skip it. */
2354 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
3521a462 2355 (le16toh(hdr->signature) >> 4) == 0x88e ||
790340ea
SW
2356 (le16toh(hdr->signature) >> 4) == 0x92c) {
2357 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n",
2358 le16toh(hdr->version), le16toh(hdr->subversion),
2359 hdr->month, hdr->date, hdr->hour, hdr->minute);
2360 ptr += sizeof(*hdr);
2361 len -= sizeof(*hdr);
2362 }
2363
3521a462
SW
2364 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
2365 if (sc->chip & URTWN_CHIP_88E)
2366 urtwn_r88e_fw_reset(sc);
2367 else
2368 urtwn_fw_reset(sc);
790340ea
SW
2369 urtwn_write_1(sc, R92C_MCUFWDL, 0);
2370 }
3521a462
SW
2371
2372 if (!(sc->chip & URTWN_CHIP_88E)) {
2373 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2374 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2375 R92C_SYS_FUNC_EN_CPUEN);
2376 }
790340ea
SW
2377 urtwn_write_1(sc, R92C_MCUFWDL,
2378 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2379 urtwn_write_1(sc, R92C_MCUFWDL + 2,
2380 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2381
3521a462
SW
2382 /* Reset the FWDL checksum. */
2383 urtwn_write_1(sc, R92C_MCUFWDL,
2384 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
2385
790340ea
SW
2386 for (page = 0; len > 0; page++) {
2387 mlen = min(len, R92C_FW_PAGE_SIZE);
2388 error = urtwn_fw_loadpage(sc, page, ptr, mlen);
2389 if (error != 0) {
2390 device_printf(sc->sc_dev,
2391 "could not load firmware page\n");
2392 goto fail;
2393 }
2394 ptr += mlen;
2395 len -= mlen;
2396 }
2397 urtwn_write_1(sc, R92C_MCUFWDL,
2398 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2399 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
2400
2401 /* Wait for checksum report. */
2402 for (ntries = 0; ntries < 1000; ntries++) {
2403 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
2404 break;
3521a462 2405 urtwn_ms_delay(sc);
790340ea
SW
2406 }
2407 if (ntries == 1000) {
2408 device_printf(sc->sc_dev,
2409 "timeout waiting for checksum report\n");
2410 error = ETIMEDOUT;
2411 goto fail;
2412 }
2413
2414 reg = urtwn_read_4(sc, R92C_MCUFWDL);
2415 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
2416 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3521a462
SW
2417 if (sc->chip & URTWN_CHIP_88E)
2418 urtwn_r88e_fw_reset(sc);
790340ea
SW
2419 /* Wait for firmware readiness. */
2420 for (ntries = 0; ntries < 1000; ntries++) {
2421 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
2422 break;
3521a462 2423 urtwn_ms_delay(sc);
790340ea
SW
2424 }
2425 if (ntries == 1000) {
2426 device_printf(sc->sc_dev,
2427 "timeout waiting for firmware readiness\n");
2428 error = ETIMEDOUT;
2429 goto fail;
2430 }
2431fail:
2432 firmware_put(fw, FIRMWARE_UNLOAD);
2433 return (error);
2434}
2435
3521a462 2436static __inline int
790340ea 2437urtwn_dma_init(struct urtwn_softc *sc)
3521a462
SW
2438{
2439
2440 return sc->sc_dma_init(sc);
2441}
2442
2443static int
2444urtwn_r92c_dma_init(struct urtwn_softc *sc)
790340ea
SW
2445{
2446 int hashq, hasnq, haslq, nqueues, nqpages, nrempages;
2447 uint32_t reg;
2448 int error;
2449
2450 /* Initialize LLT table. */
2451 error = urtwn_llt_init(sc);
2452 if (error != 0)
2453 return (error);
2454
2455 /* Get Tx queues to USB endpoints mapping. */
2456 hashq = hasnq = haslq = 0;
2457 reg = urtwn_read_2(sc, R92C_USB_EP + 1);
2458 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg);
2459 if (MS(reg, R92C_USB_EP_HQ) != 0)
2460 hashq = 1;
2461 if (MS(reg, R92C_USB_EP_NQ) != 0)
2462 hasnq = 1;
2463 if (MS(reg, R92C_USB_EP_LQ) != 0)
2464 haslq = 1;
2465 nqueues = hashq + hasnq + haslq;
2466 if (nqueues == 0)
2467 return (EIO);
2468 /* Get the number of pages for each queue. */
2469 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues;
2470 /* The remaining pages are assigned to the high priority queue. */
2471 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues;
2472
2473 /* Set number of pages for normal priority queue. */
2474 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
2475 urtwn_write_4(sc, R92C_RQPN,
2476 /* Set number of pages for public queue. */
2477 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
2478 /* Set number of pages for high priority queue. */
2479 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
2480 /* Set number of pages for low priority queue. */
2481 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
2482 /* Load values. */
2483 R92C_RQPN_LD);
2484
2485 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2486 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2487 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
2488 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
2489 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
2490
2491 /* Set queue to USB pipe mapping. */
2492 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2493 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2494 if (nqueues == 1) {
2495 if (hashq)
2496 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
2497 else if (hasnq)
2498 reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
2499 else
2500 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
2501 } else if (nqueues == 2) {
2502 /* All 2-endpoints configs have a high priority queue. */
2503 if (!hashq)
2504 return (EIO);
2505 if (hasnq)
2506 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2507 else
2508 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ;
2509 } else
2510 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2511 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2512
2513 /* Set Tx/Rx transfer page boundary. */
2514 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
2515
2516 /* Set Tx/Rx transfer page size. */
2517 urtwn_write_1(sc, R92C_PBP,
2518 SM(R92C_PBP_PSRX, R92C_PBP_128) |
2519 SM(R92C_PBP_PSTX, R92C_PBP_128));
2520 return (0);
2521}
2522
3521a462
SW
2523static int
2524urtwn_r88e_dma_init(struct urtwn_softc *sc)
2525{
2526 struct usb_interface *iface;
2527 uint32_t reg;
2528 int nqueues;
2529 int error;
2530
2531 /* Initialize LLT table. */
2532 error = urtwn_llt_init(sc);
2533 if (error != 0)
2534 return (error);
2535
2536 /* Get Tx queues to USB endpoints mapping. */
2537 iface = usbd_get_iface(sc->sc_udev, 0);
2538 nqueues = iface->idesc->bNumEndpoints - 1;
2539 if (nqueues == 0)
2540 return (EIO);
2541
2542 /* Set number of pages for normal priority queue. */
2543 urtwn_write_2(sc, R92C_RQPN_NPQ, 0);
2544 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d);
2545 urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
2546
2547 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY);
2548 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY);
2549 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY);
2550 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY);
2551 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY);
2552
2553 /* Set queue to USB pipe mapping. */
2554 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2555 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2556 if (nqueues == 1)
2557 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
2558 else if (nqueues == 2)
2559 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2560 else
2561 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2562 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2563
2564 /* Set Tx/Rx transfer page boundary. */
2565 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff);
2566
2567 /* Set Tx/Rx transfer page size. */
2568 urtwn_write_1(sc, R92C_PBP,
2569 SM(R92C_PBP_PSRX, R92C_PBP_128) |
2570 SM(R92C_PBP_PSTX, R92C_PBP_128));
2571
2572 return (0);
2573}
2574
790340ea
SW
2575static void
2576urtwn_mac_init(struct urtwn_softc *sc)
2577{
2578 int i;
2579
2580 /* Write MAC initialization values. */
3521a462
SW
2581 if (sc->chip & URTWN_CHIP_88E) {
2582 for (i = 0; i < NELEM(rtl8188eu_mac); i++) {
2583 urtwn_write_1(sc, rtl8188eu_mac[i].reg,
2584 rtl8188eu_mac[i].val);
2585 }
2586 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07);
2587 } else {
2588 for (i = 0; i < NELEM(rtl8192cu_mac); i++)
2589 urtwn_write_1(sc, rtl8192cu_mac[i].reg,
2590 rtl8192cu_mac[i].val);
2591 }
790340ea
SW
2592}
2593
2594static void
2595urtwn_bb_init(struct urtwn_softc *sc)
2596{
2597 const struct urtwn_bb_prog *prog;
2598 uint32_t reg;
3521a462 2599 uint8_t crystalcap;
790340ea
SW
2600 int i;
2601
2602 /* Enable BB and RF. */
2603 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2604 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2605 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2606 R92C_SYS_FUNC_EN_DIO_RF);
2607
3521a462
SW
2608 if (!(sc->chip & URTWN_CHIP_88E))
2609 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
790340ea
SW
2610
2611 urtwn_write_1(sc, R92C_RF_CTRL,
2612 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2613 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2614 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
2615 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
2616
3521a462
SW
2617 if (!(sc->chip & URTWN_CHIP_88E)) {
2618 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
2619 urtwn_write_1(sc, 0x15, 0xe9);
2620 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2621 }
790340ea
SW
2622
2623 /* Select BB programming based on board type. */
3521a462
SW
2624 if (sc->chip & URTWN_CHIP_88E)
2625 prog = &rtl8188eu_bb_prog;
2626 else if (!(sc->chip & URTWN_CHIP_92C)) {
790340ea
SW
2627 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2628 prog = &rtl8188ce_bb_prog;
2629 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2630 prog = &rtl8188ru_bb_prog;
2631 else
2632 prog = &rtl8188cu_bb_prog;
2633 } else {
2634 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2635 prog = &rtl8192ce_bb_prog;
2636 else
2637 prog = &rtl8192cu_bb_prog;
2638 }
2639 /* Write BB initialization values. */
2640 for (i = 0; i < prog->count; i++) {
2641 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
3521a462 2642 urtwn_ms_delay(sc);
790340ea
SW
2643 }
2644
2645 if (sc->chip & URTWN_CHIP_92C_1T2R) {
2646 /* 8192C 1T only configuration. */
2647 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2648 reg = (reg & ~0x00000003) | 0x2;
2649 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2650
2651 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2652 reg = (reg & ~0x00300033) | 0x00200022;
2653 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2654
2655 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2656 reg = (reg & ~0xff000000) | 0x45 << 24;
2657 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2658
2659 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2660 reg = (reg & ~0x000000ff) | 0x23;
2661 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2662
2663 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2664 reg = (reg & ~0x00000030) | 1 << 4;
2665 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2666
2667 reg = urtwn_bb_read(sc, 0xe74);
2668 reg = (reg & ~0x0c000000) | 2 << 26;
2669 urtwn_bb_write(sc, 0xe74, reg);
2670 reg = urtwn_bb_read(sc, 0xe78);
2671 reg = (reg & ~0x0c000000) | 2 << 26;
2672 urtwn_bb_write(sc, 0xe78, reg);
2673 reg = urtwn_bb_read(sc, 0xe7c);
2674 reg = (reg & ~0x0c000000) | 2 << 26;
2675 urtwn_bb_write(sc, 0xe7c, reg);
2676 reg = urtwn_bb_read(sc, 0xe80);
2677 reg = (reg & ~0x0c000000) | 2 << 26;
2678 urtwn_bb_write(sc, 0xe80, reg);
2679 reg = urtwn_bb_read(sc, 0xe88);
2680 reg = (reg & ~0x0c000000) | 2 << 26;
2681 urtwn_bb_write(sc, 0xe88, reg);
2682 }
2683
2684 /* Write AGC values. */
2685 for (i = 0; i < prog->agccount; i++) {
2686 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2687 prog->agcvals[i]);
3521a462
SW
2688 urtwn_ms_delay(sc);
2689 }
2690
2691 if (sc->chip & URTWN_CHIP_88E) {
2692 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
2693 urtwn_ms_delay(sc);
2694 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
2695 urtwn_ms_delay(sc);
2696
2697 crystalcap = sc->r88e_rom[0xb9];
2698 if (crystalcap == 0xff)
2699 crystalcap = 0x20;
2700 crystalcap &= 0x3f;
2701 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
2702 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
2703 RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
2704 crystalcap | crystalcap << 6));
2705 } else {
2706 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2707 R92C_HSSI_PARAM2_CCK_HIPWR)
2708 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
790340ea 2709 }
790340ea
SW
2710}
2711
2712void
2713urtwn_rf_init(struct urtwn_softc *sc)
2714{
2715 const struct urtwn_rf_prog *prog;
2716 uint32_t reg, type;
2717 int i, j, idx, off;
2718
2719 /* Select RF programming based on board type. */
3521a462
SW
2720 if (sc->chip & URTWN_CHIP_88E)
2721 prog = rtl8188eu_rf_prog;
2722 else if (!(sc->chip & URTWN_CHIP_92C)) {
790340ea
SW
2723 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2724 prog = rtl8188ce_rf_prog;
2725 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2726 prog = rtl8188ru_rf_prog;
2727 else
2728 prog = rtl8188cu_rf_prog;
2729 } else
2730 prog = rtl8192ce_rf_prog;
2731
2732 for (i = 0; i < sc->nrxchains; i++) {
2733 /* Save RF_ENV control type. */
2734 idx = i / 2;
2735 off = (i % 2) * 16;
2736 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2737 type = (reg >> off) & 0x10;
2738
2739 /* Set RF_ENV enable. */
2740 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2741 reg |= 0x100000;
2742 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
3521a462 2743 urtwn_ms_delay(sc);
790340ea
SW
2744 /* Set RF_ENV output high. */
2745 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2746 reg |= 0x10;
2747 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
3521a462 2748 urtwn_ms_delay(sc);
790340ea
SW
2749 /* Set address and data lengths of RF registers. */
2750 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2751 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
2752 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
3521a462 2753 urtwn_ms_delay(sc);
790340ea
SW
2754 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2755 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
2756 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
3521a462 2757 urtwn_ms_delay(sc);
790340ea
SW
2758
2759 /* Write RF initialization values for this chain. */
2760 for (j = 0; j < prog[i].count; j++) {
2761 if (prog[i].regs[j] >= 0xf9 &&
2762 prog[i].regs[j] <= 0xfe) {
2763 /*
2764 * These are fake RF registers offsets that
2765 * indicate a delay is required.
2766 */
3521a462 2767 usb_pause_mtx(&sc->sc_lock, hz / 20);
790340ea
SW
2768 continue;
2769 }
2770 urtwn_rf_write(sc, i, prog[i].regs[j],
2771 prog[i].vals[j]);
3521a462 2772 urtwn_ms_delay(sc);
790340ea
SW
2773 }
2774
2775 /* Restore RF_ENV control type. */
2776 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2777 reg &= ~(0x10 << off) | (type << off);
2778 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
2779
2780 /* Cache RF register CHNLBW. */
2781 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
2782 }
2783
2784 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2785 URTWN_CHIP_UMC_A_CUT) {
2786 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
2787 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
2788 }
2789}
2790
2791static void
2792urtwn_cam_init(struct urtwn_softc *sc)
2793{
2794 /* Invalidate all CAM entries. */
2795 urtwn_write_4(sc, R92C_CAMCMD,
2796 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
2797}
2798
2799static void
2800urtwn_pa_bias_init(struct urtwn_softc *sc)
2801{
2802 uint8_t reg;
2803 int i;
2804
2805 for (i = 0; i < sc->nrxchains; i++) {
2806 if (sc->pa_setting & (1 << i))
2807 continue;
2808 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
2809 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
2810 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
2811 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
2812 }
2813 if (!(sc->pa_setting & 0x10)) {
2814 reg = urtwn_read_1(sc, 0x16);
2815 reg = (reg & ~0xf0) | 0x90;
2816 urtwn_write_1(sc, 0x16, reg);
2817 }
2818}
2819
2820static void
2821urtwn_rxfilter_init(struct urtwn_softc *sc)
2822{
2823 /* Initialize Rx filter. */
2824 /* TODO: use better filter for monitor mode. */
2825 urtwn_write_4(sc, R92C_RCR,
2826 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
2827 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
2828 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
2829 /* Accept all multicast frames. */
2830 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
2831 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
2832 /* Accept all management frames. */
2833 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
2834 /* Reject all control frames. */
2835 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
2836 /* Accept all data frames. */
2837 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2838}
2839
2840static void
2841urtwn_edca_init(struct urtwn_softc *sc)
2842{
2843 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
2844 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
2845 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
2846 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
2847 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
2848 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
2849 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
2850 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
2851}
2852
2853void
2854urtwn_write_txpower(struct urtwn_softc *sc, int chain,
2855 uint16_t power[URTWN_RIDX_COUNT])
2856{
2857 uint32_t reg;
2858
2859 /* Write per-CCK rate Tx power. */
2860 if (chain == 0) {
2861 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2862 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
2863 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
2864 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2865 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
2866 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
2867 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
2868 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2869 } else {
2870 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2871 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
2872 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
2873 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
2874 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
2875 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2876 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
2877 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2878 }
2879 /* Write per-OFDM rate Tx power. */
2880 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
2881 SM(R92C_TXAGC_RATE06, power[ 4]) |
2882 SM(R92C_TXAGC_RATE09, power[ 5]) |
2883 SM(R92C_TXAGC_RATE12, power[ 6]) |
2884 SM(R92C_TXAGC_RATE18, power[ 7]));
2885 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
2886 SM(R92C_TXAGC_RATE24, power[ 8]) |
2887 SM(R92C_TXAGC_RATE36, power[ 9]) |
2888 SM(R92C_TXAGC_RATE48, power[10]) |
2889 SM(R92C_TXAGC_RATE54, power[11]));
2890 /* Write per-MCS Tx power. */
2891 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
2892 SM(R92C_TXAGC_MCS00, power[12]) |
2893 SM(R92C_TXAGC_MCS01, power[13]) |
2894 SM(R92C_TXAGC_MCS02, power[14]) |
2895 SM(R92C_TXAGC_MCS03, power[15]));
2896 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
2897 SM(R92C_TXAGC_MCS04, power[16]) |
2898 SM(R92C_TXAGC_MCS05, power[17]) |
2899 SM(R92C_TXAGC_MCS06, power[18]) |
2900 SM(R92C_TXAGC_MCS07, power[19]));
2901 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
2902 SM(R92C_TXAGC_MCS08, power[20]) |
3521a462 2903 SM(R92C_TXAGC_MCS09, power[21]) |
790340ea
SW
2904 SM(R92C_TXAGC_MCS10, power[22]) |
2905 SM(R92C_TXAGC_MCS11, power[23]));
2906 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
2907 SM(R92C_TXAGC_MCS12, power[24]) |
2908 SM(R92C_TXAGC_MCS13, power[25]) |
2909 SM(R92C_TXAGC_MCS14, power[26]) |
2910 SM(R92C_TXAGC_MCS15, power[27]));
2911}
2912
2913void
2914urtwn_get_txpower(struct urtwn_softc *sc, int chain,
2915 struct ieee80211_channel *c, struct ieee80211_channel *extc,
2916 uint16_t power[URTWN_RIDX_COUNT])
2917{
2918 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2919 struct r92c_rom *rom = &sc->rom;
2920 uint16_t cckpow, ofdmpow, htpow, diff, max;
2921 const struct urtwn_txpwr *base;
2922 int ridx, chan, group;
2923
2924 /* Determine channel group. */
2925 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
2926 if (chan <= 3)
2927 group = 0;
2928 else if (chan <= 9)
2929 group = 1;
2930 else
2931 group = 2;
2932
2933 /* Get original Tx power based on board type and RF chain. */
2934 if (!(sc->chip & URTWN_CHIP_92C)) {
2935 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2936 base = &rtl8188ru_txagc[chain];
2937 else
2938 base = &rtl8192cu_txagc[chain];
2939 } else
2940 base = &rtl8192cu_txagc[chain];
2941
2942 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
2943 if (sc->regulatory == 0) {
2944 for (ridx = 0; ridx <= 3; ridx++)
2945 power[ridx] = base->pwr[0][ridx];
2946 }
2947 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
2948 if (sc->regulatory == 3) {
2949 power[ridx] = base->pwr[0][ridx];
2950 /* Apply vendor limits. */
2951 if (extc != NULL)
2952 max = rom->ht40_max_pwr[group];
2953 else
2954 max = rom->ht20_max_pwr[group];
2955 max = (max >> (chain * 4)) & 0xf;
2956 if (power[ridx] > max)
2957 power[ridx] = max;
2958 } else if (sc->regulatory == 1) {
2959 if (extc == NULL)
2960 power[ridx] = base->pwr[group][ridx];
2961 } else if (sc->regulatory != 2)
2962 power[ridx] = base->pwr[0][ridx];
2963 }
2964
2965 /* Compute per-CCK rate Tx power. */
2966 cckpow = rom->cck_tx_pwr[chain][group];
2967 for (ridx = 0; ridx <= 3; ridx++) {
2968 power[ridx] += cckpow;
2969 if (power[ridx] > R92C_MAX_TX_PWR)
2970 power[ridx] = R92C_MAX_TX_PWR;
2971 }
2972
2973 htpow = rom->ht40_1s_tx_pwr[chain][group];
2974 if (sc->ntxchains > 1) {
2975 /* Apply reduction for 2 spatial streams. */
2976 diff = rom->ht40_2s_tx_pwr_diff[group];
2977 diff = (diff >> (chain * 4)) & 0xf;
2978 htpow = (htpow > diff) ? htpow - diff : 0;
2979 }
2980
2981 /* Compute per-OFDM rate Tx power. */
2982 diff = rom->ofdm_tx_pwr_diff[group];
2983 diff = (diff >> (chain * 4)) & 0xf;
2984 ofdmpow = htpow + diff; /* HT->OFDM correction. */
2985 for (ridx = 4; ridx <= 11; ridx++) {
2986 power[ridx] += ofdmpow;
2987 if (power[ridx] > R92C_MAX_TX_PWR)
2988 power[ridx] = R92C_MAX_TX_PWR;
2989 }
2990
2991 /* Compute per-MCS Tx power. */
2992 if (extc == NULL) {
2993 diff = rom->ht20_tx_pwr_diff[group];
2994 diff = (diff >> (chain * 4)) & 0xf;
2995 htpow += diff; /* HT40->HT20 correction. */
2996 }
2997 for (ridx = 12; ridx <= 27; ridx++) {
2998 power[ridx] += htpow;
2999 if (power[ridx] > R92C_MAX_TX_PWR)
3000 power[ridx] = R92C_MAX_TX_PWR;
3001 }
3002#ifdef URTWN_DEBUG
3003 if (urtwn_debug >= 4) {
3004 /* Dump per-rate Tx power values. */
3005 printf("Tx power for chain %d:\n", chain);
3006 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++)
3007 printf("Rate %d = %u\n", ridx, power[ridx]);
3008 }
3009#endif
3010}
3011
3521a462
SW
3012void
3013urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain,
3014 struct ieee80211_channel *c, struct ieee80211_channel *extc,
3015 uint16_t power[URTWN_RIDX_COUNT])
3016{
3017 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3018 uint16_t cckpow, ofdmpow, bw20pow, htpow;
3019 const struct urtwn_r88e_txpwr *base;
3020 int ridx, chan, group;
3021
3022 /* Determine channel group. */
3023 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
3024 if (chan <= 2)
3025 group = 0;
3026 else if (chan <= 5)
3027 group = 1;
3028 else if (chan <= 8)
3029 group = 2;
3030 else if (chan <= 11)
3031 group = 3;
3032 else if (chan <= 13)
3033 group = 4;
3034 else
3035 group = 5;
3036
3037 /* Get original Tx power based on board type and RF chain. */
3038 base = &rtl8188eu_txagc[chain];
3039
3040 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
3041 if (sc->regulatory == 0) {
3042 for (ridx = 0; ridx <= 3; ridx++)
3043 power[ridx] = base->pwr[0][ridx];
3044 }
3045 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
3046 if (sc->regulatory == 3)
3047 power[ridx] = base->pwr[0][ridx];
3048 else if (sc->regulatory == 1) {
3049 if (extc == NULL)
3050 power[ridx] = base->pwr[group][ridx];
3051 } else if (sc->regulatory != 2)
3052 power[ridx] = base->pwr[0][ridx];
3053 }
3054
3055 /* Compute per-CCK rate Tx power. */
3056 cckpow = sc->cck_tx_pwr[group];
3057 for (ridx = 0; ridx <= 3; ridx++) {
3058 power[ridx] += cckpow;
3059 if (power[ridx] > R92C_MAX_TX_PWR)
3060 power[ridx] = R92C_MAX_TX_PWR;
3061 }
3062
3063 htpow = sc->ht40_tx_pwr[group];
3064
3065 /* Compute per-OFDM rate Tx power. */
3066 ofdmpow = htpow + sc->ofdm_tx_pwr_diff;
3067 for (ridx = 4; ridx <= 11; ridx++) {
3068 power[ridx] += ofdmpow;
3069 if (power[ridx] > R92C_MAX_TX_PWR)
3070 power[ridx] = R92C_MAX_TX_PWR;
3071 }
3072
3073 bw20pow = htpow + sc->bw20_tx_pwr_diff;
3074 for (ridx = 12; ridx <= 27; ridx++) {
3075 power[ridx] += bw20pow;
3076 if (power[ridx] > R92C_MAX_TX_PWR)
3077 power[ridx] = R92C_MAX_TX_PWR;
3078 }
3079}
3080
790340ea
SW
3081void
3082urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
3083 struct ieee80211_channel *extc)
3084{
3085 uint16_t power[URTWN_RIDX_COUNT];
3086 int i;
3087
3088 for (i = 0; i < sc->ntxchains; i++) {
3089 /* Compute per-rate Tx power values. */
3521a462
SW
3090 if (sc->chip & URTWN_CHIP_88E)
3091 urtwn_r88e_get_txpower(sc, i, c, extc, power);
3092 else
3093 urtwn_get_txpower(sc, i, c, extc, power);
790340ea
SW
3094 /* Write per-rate Tx power values to hardware. */
3095 urtwn_write_txpower(sc, i, power);
3096 }
3097}
3098
3099static void
3100urtwn_scan_start(struct ieee80211com *ic)
3101{
3102 /* XXX do nothing? */
3103}
3104
3105static void
3106urtwn_scan_end(struct ieee80211com *ic)
3107{
3108 /* XXX do nothing? */
3109}
3110
3111static void
3112urtwn_set_channel(struct ieee80211com *ic)
3113{
3114 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
3115
3116 URTWN_LOCK(sc);
3117 urtwn_set_chan(sc, ic->ic_curchan, NULL);
3118 URTWN_UNLOCK(sc);
3119}
3120
3121static void
3122urtwn_update_mcast(struct ifnet *ifp)
3123{
3124 /* XXX do nothing? */
3125}
3126
3127static void
3128urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
3129 struct ieee80211_channel *extc)
3130{
3131 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3132 uint32_t reg;
3133 u_int chan;
3134 int i;
3135
3136 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
3137 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
3138 device_printf(sc->sc_dev,
3139 "%s: invalid channel %x\n", __func__, chan);
3140 return;
3141 }
3142
3143 /* Set Tx power for this new channel. */
3144 urtwn_set_txpower(sc, c, extc);
3145
3146 for (i = 0; i < sc->nrxchains; i++) {
3147 urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
3148 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
3149 }
3150#ifndef IEEE80211_NO_HT
3151 if (extc != NULL) {
3152 /* Is secondary channel below or above primary? */
3153 int prichlo = c->ic_freq < extc->ic_freq;
3154
3155 urtwn_write_1(sc, R92C_BWOPMODE,
3156 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
3157
3158 reg = urtwn_read_1(sc, R92C_RRSR + 2);
3159 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
3160 urtwn_write_1(sc, R92C_RRSR + 2, reg);
3161
3162 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
3163 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
3164 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
3165 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
3166
3167 /* Set CCK side band. */
3168 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
3169 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
3170 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
3171
3172 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
3173 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
3174 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
3175
3176 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
3177 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
3178 ~R92C_FPGA0_ANAPARAM2_CBW20);
3179
3180 reg = urtwn_bb_read(sc, 0x818);
3181 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
3182 urtwn_bb_write(sc, 0x818, reg);
3183
3184 /* Select 40MHz bandwidth. */
3185 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3186 (sc->rf_chnlbw[0] & ~0xfff) | chan);
3187 } else
3188#endif
3189 {
3190 urtwn_write_1(sc, R92C_BWOPMODE,
3191 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
3192
3193 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
3194 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
3195 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
3196 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
3197
3521a462
SW
3198 if (!(sc->chip & URTWN_CHIP_88E)) {
3199 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
3200 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
3201 R92C_FPGA0_ANAPARAM2_CBW20);
3202 }
3203
790340ea
SW
3204 /* Select 20MHz bandwidth. */
3205 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3521a462
SW
3206 (sc->rf_chnlbw[0] & ~0xfff) | chan |
3207 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 :
3208 R92C_RF_CHNLBW_BW20));
790340ea
SW
3209 }
3210}
3211
3212static void
3213urtwn_iq_calib(struct urtwn_softc *sc)
3214{
3215 /* TODO */
3216}
3217
3218static void
3219urtwn_lc_calib(struct urtwn_softc *sc)
3220{
3221 uint32_t rf_ac[2];
3222 uint8_t txmode;
3223 int i;
3224
3225 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
3226 if ((txmode & 0x70) != 0) {
3227 /* Disable all continuous Tx. */
3228 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
3229
3230 /* Set RF mode to standby mode. */
3231 for (i = 0; i < sc->nrxchains; i++) {
3232 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
3233 urtwn_rf_write(sc, i, R92C_RF_AC,
3234 RW(rf_ac[i], R92C_RF_AC_MODE,
3235 R92C_RF_AC_MODE_STANDBY));
3236 }
3237 } else {
3238 /* Block all Tx queues. */
3239 urtwn_write_1(sc, R92C_TXPAUSE, 0xff);
3240 }
3241 /* Start calibration. */
3242 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3243 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
3244
3245 /* Give calibration the time to complete. */
3521a462 3246 usb_pause_mtx(&sc->sc_lock, hz / 10); /* 100ms */
790340ea
SW
3247
3248 /* Restore configuration. */
3249 if ((txmode & 0x70) != 0) {
3250 /* Restore Tx mode. */
3251 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
3252 /* Restore RF mode. */
3253 for (i = 0; i < sc->nrxchains; i++)
3254 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
3255 } else {
3256 /* Unblock all Tx queues. */
3257 urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
3258 }
3259}
3260
3261static void
3262urtwn_init_locked(void *arg)
3263{
3264 struct urtwn_softc *sc = arg;
3265 struct ifnet *ifp = sc->sc_ifp;
3266 uint32_t reg;
3267 int error;
3268
3521a462
SW
3269 URTWN_ASSERT_LOCKED(sc);
3270
790340ea 3271 if (ifp->if_flags & IFF_RUNNING)
3521a462 3272 urtwn_stop_locked(ifp);
790340ea
SW
3273
3274 /* Init firmware commands ring. */
3275 sc->fwcur = 0;
3276
3277 /* Allocate Tx/Rx buffers. */
3278 error = urtwn_alloc_rx_list(sc);
3279 if (error != 0)
3280 goto fail;
3281
3282 error = urtwn_alloc_tx_list(sc);
3283 if (error != 0)
3284 goto fail;
3285
3286 /* Power on adapter. */
3287 error = urtwn_power_on(sc);
3288 if (error != 0)
3289 goto fail;
3290
3291 /* Initialize DMA. */
3292 error = urtwn_dma_init(sc);
3293 if (error != 0)
3294 goto fail;
3295
3296 /* Set info size in Rx descriptors (in 64-bit words). */
3297 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
3298
3299 /* Init interrupts. */
3521a462
SW
3300 if (sc->chip & URTWN_CHIP_88E) {
3301 urtwn_write_4(sc, R88E_HISR, 0xffffffff);
3302 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
3303 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
3304 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
3305 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
3306 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
3307 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
3308 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
3309 } else {
3310 urtwn_write_4(sc, R92C_HISR, 0xffffffff);
3311 urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
3312 }
790340ea
SW
3313
3314 /* Set MAC address. */
3315 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp),
3316 IEEE80211_ADDR_LEN);
3317
3318 /* Set initial network type. */
3319 reg = urtwn_read_4(sc, R92C_CR);
3320 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
3321 urtwn_write_4(sc, R92C_CR, reg);
3322
3323 urtwn_rxfilter_init(sc);
3324
3325 reg = urtwn_read_4(sc, R92C_RRSR);
3326 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
3327 urtwn_write_4(sc, R92C_RRSR, reg);
3328
3329 /* Set short/long retry limits. */
3330 urtwn_write_2(sc, R92C_RL,
3331 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
3332
3333 /* Initialize EDCA parameters. */
3334 urtwn_edca_init(sc);
3335
3336 /* Setup rate fallback. */
3521a462
SW
3337 if (!(sc->chip & URTWN_CHIP_88E)) {
3338 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
3339 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
3340 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
3341 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
3342 }
790340ea
SW
3343
3344 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
3345 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
3346 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
3347 /* Set ACK timeout. */
3348 urtwn_write_1(sc, R92C_ACKTO, 0x40);
3349
3350 /* Setup USB aggregation. */
3351 reg = urtwn_read_4(sc, R92C_TDECTRL);
3352 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
3353 urtwn_write_4(sc, R92C_TDECTRL, reg);
3354 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
3355 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
3356 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
3357 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
3358 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
3359 R92C_USB_SPECIAL_OPTION_AGG_EN);
3360 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
3521a462
SW
3361 if (sc->chip & URTWN_CHIP_88E)
3362 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
3363 else
3364 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
790340ea
SW
3365 urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
3366 urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
3367
3368 /* Initialize beacon parameters. */
3521a462 3369 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
790340ea
SW
3370 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
3371 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
3372 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
3373 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
3374
3521a462
SW
3375 if (!(sc->chip & URTWN_CHIP_88E)) {
3376 /* Setup AMPDU aggregation. */
3377 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
3378 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
3379 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);
790340ea 3380
3521a462
SW
3381 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
3382 }
790340ea
SW
3383
3384 /* Load 8051 microcode. */
3385 error = urtwn_load_firmware(sc);
3386 if (error != 0)
3387 goto fail;
3388
3389 /* Initialize MAC/BB/RF blocks. */
3390 urtwn_mac_init(sc);
3391 urtwn_bb_init(sc);
3392 urtwn_rf_init(sc);
3393
3521a462
SW
3394 if (sc->chip & URTWN_CHIP_88E) {
3395 urtwn_write_2(sc, R92C_CR,
3396 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
3397 R92C_CR_MACRXEN);
3398 }
3399
790340ea
SW
3400 /* Turn CCK and OFDM blocks on. */
3401 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3402 reg |= R92C_RFMOD_CCK_EN;
3403 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3404 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3405 reg |= R92C_RFMOD_OFDM_EN;
3406 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3407
3408 /* Clear per-station keys table. */
3409 urtwn_cam_init(sc);
3410
3411 /* Enable hardware sequence numbering. */
3412 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
3413
3414 /* Perform LO and IQ calibrations. */
3415 urtwn_iq_calib(sc);
3416 /* Perform LC calibration. */
3417 urtwn_lc_calib(sc);
3418
3419 /* Fix USB interference issue. */
3521a462
SW
3420 if (!(sc->chip & URTWN_CHIP_88E)) {
3421 urtwn_write_1(sc, 0xfe40, 0xe0);
3422 urtwn_write_1(sc, 0xfe41, 0x8d);
3423 urtwn_write_1(sc, 0xfe42, 0x80);
790340ea 3424
3521a462
SW
3425 urtwn_pa_bias_init(sc);
3426 }
790340ea
SW
3427
3428 /* Initialize GPIO setting. */
3429 urtwn_write_1(sc, R92C_GPIO_MUXCFG,
3430 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
3431
3432 /* Fix for lower temperature. */
3521a462
SW
3433 if (!(sc->chip & URTWN_CHIP_88E))
3434 urtwn_write_1(sc, 0x15, 0xe9);
790340ea
SW
3435
3436 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
3437
3438 ifq_clr_oactive(&ifp->if_snd);
3439 ifp->if_flags |= IFF_RUNNING;
3440
3441 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
3442fail:
3443 return;
3444}
3445
3446static void
3447urtwn_init(void *arg)
3448{
3449 struct urtwn_softc *sc = arg;
3450
3451 URTWN_LOCK(sc);
3452 urtwn_init_locked(arg);
3453 URTWN_UNLOCK(sc);
3454}
3455
3456static void
3521a462 3457urtwn_stop_locked(struct ifnet *ifp)
790340ea
SW
3458{
3459 struct urtwn_softc *sc = ifp->if_softc;
3460
3521a462
SW
3461 URTWN_ASSERT_LOCKED(sc);
3462
790340ea
SW
3463 ifp->if_flags &= ~IFF_RUNNING;
3464 ifq_clr_oactive(&ifp->if_snd);
3465
3466 callout_stop(&sc->sc_watchdog_ch);
3467 urtwn_abort_xfers(sc);
3468}
3469
3470static void
3521a462 3471urtwn_stop(struct ifnet *ifp)
790340ea
SW
3472{
3473 struct urtwn_softc *sc = ifp->if_softc;
3474
3475 URTWN_LOCK(sc);
3521a462 3476 urtwn_stop_locked(ifp);
790340ea
SW
3477 URTWN_UNLOCK(sc);
3478}
3479
3480static void
3481urtwn_abort_xfers(struct urtwn_softc *sc)
3482{
3483 int i;
3484
3485 URTWN_ASSERT_LOCKED(sc);
3486
3487 /* abort any pending transfers */
3488 for (i = 0; i < URTWN_N_TRANSFER; i++)
3489 usbd_transfer_stop(sc->sc_xfer[i]);
3490}
3491
3492static int
3493urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3494 const struct ieee80211_bpf_params *params)
3495{
3496 struct ieee80211com *ic = ni->ni_ic;
3497 struct ifnet *ifp = ic->ic_ifp;
3498 struct urtwn_softc *sc = ifp->if_softc;
3499 struct urtwn_data *bf;
3500
3501 /* prevent management frames from being sent if we're not ready */
3502 if (!(ifp->if_flags & IFF_RUNNING)) {
3503 m_freem(m);
3504 ieee80211_free_node(ni);
3505 return (ENETDOWN);
3506 }
3507 URTWN_LOCK(sc);
3508 bf = urtwn_getbuf(sc);
3509 if (bf == NULL) {
3510 ieee80211_free_node(ni);
3511 m_freem(m);
3512 URTWN_UNLOCK(sc);
3513 return (ENOBUFS);
3514 }
3515
3516 ifp->if_opackets++;
3517 if (urtwn_tx_start(sc, ni, m, bf) != 0) {
3518 ieee80211_free_node(ni);
3519 ifp->if_oerrors++;
3520 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
3521 URTWN_UNLOCK(sc);
3522 return (EIO);
3523 }
3524 URTWN_UNLOCK(sc);
3525
3526 sc->sc_txtimer = 5;
3527 return (0);
3528}
3529
3521a462
SW
3530static void
3531urtwn_ms_delay(struct urtwn_softc *sc)
3532{
3533 usb_pause_ls(&sc->sc_lock, &wlan_global_serializer, hz / 100);
3534}
3535
790340ea
SW
3536static device_method_t urtwn_methods[] = {
3537 /* Device interface */
3538 DEVMETHOD(device_probe, urtwn_match),
3539 DEVMETHOD(device_attach, urtwn_attach),
3540 DEVMETHOD(device_detach, urtwn_detach),
3541
3521a462 3542 DEVMETHOD_END
790340ea
SW
3543};
3544
3545static driver_t urtwn_driver = {
3546 "urtwn",
3547 urtwn_methods,
3548 sizeof(struct urtwn_softc)
3549};
3550
3551static devclass_t urtwn_devclass;
3552
3553DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL);
3554MODULE_DEPEND(urtwn, usb, 1, 1, 1);
3555MODULE_DEPEND(urtwn, wlan, 1, 1, 1);
3556MODULE_DEPEND(urtwn, firmware, 1, 1, 1);
3557MODULE_VERSION(urtwn, 1);