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[dragonfly.git] / sys / dev / netif / ral / rt2560.c
CommitLineData
feb94d24
RP
1/* $FreeBSD: head/sys/dev/ral/rt2560.c 195618 2009-07-11 15:02:45Z rpaulo $ */
2
3/*-
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4 * Copyright (c) 2005, 2006
5 * Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
feb94d24
RP
18 *
19 * $FreeBSD: head/sys/dev/ral/rt2560.c 195618 2009-07-11 15:02:45Z rpaulo $
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20 */
21
feb94d24
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22
23/*-
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24 * Ralink Technology RT2560 chipset driver
25 * http://www.ralinktech.com/
26 */
27
28#include <sys/param.h>
feb94d24
RP
29#include <sys/sysctl.h>
30#include <sys/sockio.h>
31#include <sys/mbuf.h>
5fdff524 32#include <sys/kernel.h>
feb94d24
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33#include <sys/socket.h>
34#include <sys/systm.h>
5fdff524 35#include <sys/malloc.h>
feb94d24
RP
36#include <sys/lock.h>
37#include <sys/mutex.h>
5fdff524 38#include <sys/module.h>
feb94d24
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39#include <sys/bus.h>
40#include <sys/endian.h>
1f7ab7c9 41#include <sys/rman.h>
5fdff524 42
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43#include <net/bpf.h>
44#include <net/if.h>
45#include <net/if_arp.h>
46#include <net/ethernet.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
feb94d24 49#include <net/if_types.h>
5fdff524
SZ
50#include <net/ifq_var.h>
51
52#include <netproto/802_11/ieee80211_var.h>
53#include <netproto/802_11/ieee80211_radiotap.h>
feb94d24
RP
54#include <netproto/802_11/ieee80211_regdomain.h>
55#include <netproto/802_11/ieee80211_ratectl.h>
56
57#include <netinet/in.h>
58#include <netinet/in_systm.h>
59#include <netinet/in_var.h>
60#include <netinet/ip.h>
61#include <netinet/if_ether.h>
5fdff524 62
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63#include <dev/netif/ral/rt2560reg.h>
64#include <dev/netif/ral/rt2560var.h>
65
a5c68736
SZ
66#define RT2560_RSSI(sc, rssi) \
67 ((rssi) > (RT2560_NOISE_FLOOR + (sc)->rssi_corr) ? \
68 ((rssi) - RT2560_NOISE_FLOOR - (sc)->rssi_corr) : 0)
a5c68736 69
feb94d24 70#define RAL_DEBUG
5fdff524 71#ifdef RAL_DEBUG
feb94d24
RP
72#define DPRINTF(sc, fmt, ...) do { \
73 if (sc->sc_debug > 0) \
74 kprintf(fmt, __VA_ARGS__); \
75} while (0)
76#define DPRINTFN(sc, n, fmt, ...) do { \
77 if (sc->sc_debug >= (n)) \
78 kprintf(fmt, __VA_ARGS__); \
79} while (0)
5fdff524 80#else
feb94d24
RP
81#define DPRINTF(sc, fmt, ...)
82#define DPRINTFN(sc, n, fmt, ...)
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83#endif
84
feb94d24 85static struct ieee80211vap *rt2560_vap_create(struct ieee80211com *,
18ef6e46
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86 const char name[IFNAMSIZ], int unit,
87 enum ieee80211_opmode opmode,
feb94d24
RP
88 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
89 const uint8_t mac[IEEE80211_ADDR_LEN]);
90static void rt2560_vap_delete(struct ieee80211vap *);
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91static void rt2560_dma_map_addr(void *, bus_dma_segment_t *, int,
92 int);
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93static int rt2560_alloc_tx_ring(struct rt2560_softc *,
94 struct rt2560_tx_ring *, int);
95static void rt2560_reset_tx_ring(struct rt2560_softc *,
96 struct rt2560_tx_ring *);
97static void rt2560_free_tx_ring(struct rt2560_softc *,
98 struct rt2560_tx_ring *);
99static int rt2560_alloc_rx_ring(struct rt2560_softc *,
100 struct rt2560_rx_ring *, int);
101static void rt2560_reset_rx_ring(struct rt2560_softc *,
102 struct rt2560_rx_ring *);
103static void rt2560_free_rx_ring(struct rt2560_softc *,
104 struct rt2560_rx_ring *);
feb94d24 105static int rt2560_newstate(struct ieee80211vap *,
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106 enum ieee80211_state, int);
107static uint16_t rt2560_eeprom_read(struct rt2560_softc *, uint8_t);
108static void rt2560_encryption_intr(struct rt2560_softc *);
109static void rt2560_tx_intr(struct rt2560_softc *);
110static void rt2560_prio_intr(struct rt2560_softc *);
111static void rt2560_decryption_intr(struct rt2560_softc *);
112static void rt2560_rx_intr(struct rt2560_softc *);
feb94d24 113static void rt2560_beacon_update(struct ieee80211vap *, int item);
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SZ
114static void rt2560_beacon_expire(struct rt2560_softc *);
115static void rt2560_wakeup_expire(struct rt2560_softc *);
feb94d24
RP
116static void rt2560_scan_start(struct ieee80211com *);
117static void rt2560_scan_end(struct ieee80211com *);
118static void rt2560_set_channel(struct ieee80211com *);
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119static void rt2560_setup_tx_desc(struct rt2560_softc *,
120 struct rt2560_tx_desc *, uint32_t, int, int, int,
121 bus_addr_t);
122static int rt2560_tx_bcn(struct rt2560_softc *, struct mbuf *,
123 struct ieee80211_node *);
124static int rt2560_tx_mgt(struct rt2560_softc *, struct mbuf *,
125 struct ieee80211_node *);
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126static int rt2560_tx_data(struct rt2560_softc *, struct mbuf *,
127 struct ieee80211_node *);
feb94d24 128static void rt2560_start_locked(struct ifnet *);
f0a26983 129static void rt2560_start(struct ifnet *, struct ifaltq_subque *);
d8235d53 130static void rt2560_watchdog_callout(void *);
5fdff524 131static int rt2560_ioctl(struct ifnet *, u_long, caddr_t,
feb94d24 132 struct ucred *);
5fdff524
SZ
133static void rt2560_bbp_write(struct rt2560_softc *, uint8_t,
134 uint8_t);
135static uint8_t rt2560_bbp_read(struct rt2560_softc *, uint8_t);
136static void rt2560_rf_write(struct rt2560_softc *, uint8_t,
137 uint32_t);
138static void rt2560_set_chan(struct rt2560_softc *,
139 struct ieee80211_channel *);
feb94d24
RP
140#if 0
141static void rt2560_disable_rf_tune(struct rt2560_softc *);
142#endif
5fdff524 143static void rt2560_enable_tsf_sync(struct rt2560_softc *);
feb94d24 144static void rt2560_enable_tsf(struct rt2560_softc *);
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SZ
145static void rt2560_update_plcp(struct rt2560_softc *);
146static void rt2560_update_slot(struct ifnet *);
147static void rt2560_set_basicrates(struct rt2560_softc *);
148static void rt2560_update_led(struct rt2560_softc *, int, int);
feb94d24 149static void rt2560_set_bssid(struct rt2560_softc *, const uint8_t *);
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150static void rt2560_set_macaddr(struct rt2560_softc *, uint8_t *);
151static void rt2560_get_macaddr(struct rt2560_softc *, uint8_t *);
feb94d24 152static void rt2560_update_promisc(struct ifnet *);
5fdff524 153static const char *rt2560_get_rf(int);
d491e551 154static void rt2560_read_config(struct rt2560_softc *);
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SZ
155static int rt2560_bbp_init(struct rt2560_softc *);
156static void rt2560_set_txantenna(struct rt2560_softc *, int);
157static void rt2560_set_rxantenna(struct rt2560_softc *, int);
feb94d24 158static void rt2560_init_locked(struct rt2560_softc *);
5fdff524 159static void rt2560_init(void *);
feb94d24
RP
160static void rt2560_stop_locked(struct rt2560_softc *);
161static int rt2560_raw_xmit(struct ieee80211_node *, struct mbuf *,
162 const struct ieee80211_bpf_params *);
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163
164static const struct {
165 uint32_t reg;
166 uint32_t val;
167} rt2560_def_mac[] = {
168 RT2560_DEF_MAC
169};
170
171static const struct {
172 uint8_t reg;
173 uint8_t val;
174} rt2560_def_bbp[] = {
175 RT2560_DEF_BBP
176};
177
178static const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2;
179static const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2;
180static const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2;
181static const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2;
182static const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2;
183static const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2;
184static const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2;
185static const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2;
186
187static const struct {
188 uint8_t chan;
189 uint32_t r1, r2, r4;
190} rt2560_rf5222[] = {
191 RT2560_RF5222
192};
193
194int
195rt2560_attach(device_t dev, int id)
196{
197 struct rt2560_softc *sc = device_get_softc(dev);
feb94d24
RP
198 struct ieee80211com *ic;
199 struct ifnet *ifp;
200 int error;
201 uint8_t bands;
202 uint8_t macaddr[IEEE80211_ADDR_LEN];
203 struct sysctl_ctx_list *ctx;
204 struct sysctl_oid *tree;
5fdff524 205
feb94d24 206 sc->sc_dev = dev;
5fdff524 207
feb94d24 208 callout_init(&sc->watchdog_ch);
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SZ
209
210 /* retrieve RT2560 rev. no */
211 sc->asic_rev = RAL_READ(sc, RT2560_CSR0);
212
5fdff524 213 /* retrieve RF rev. no and various other things from EEPROM */
d491e551 214 rt2560_read_config(sc);
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215
216 device_printf(dev, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n",
217 sc->asic_rev, rt2560_get_rf(sc->rf_rev));
218
219 /*
220 * Allocate Tx and Rx rings.
221 */
222 error = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT);
223 if (error != 0) {
224 device_printf(sc->sc_dev, "could not allocate Tx ring\n");
feb94d24 225 goto fail1;
5fdff524
SZ
226 }
227
228 error = rt2560_alloc_tx_ring(sc, &sc->atimq, RT2560_ATIM_RING_COUNT);
229 if (error != 0) {
230 device_printf(sc->sc_dev, "could not allocate ATIM ring\n");
feb94d24 231 goto fail2;
5fdff524
SZ
232 }
233
234 error = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT);
235 if (error != 0) {
236 device_printf(sc->sc_dev, "could not allocate Prio ring\n");
feb94d24 237 goto fail3;
5fdff524
SZ
238 }
239
240 error = rt2560_alloc_tx_ring(sc, &sc->bcnq, RT2560_BEACON_RING_COUNT);
241 if (error != 0) {
242 device_printf(sc->sc_dev, "could not allocate Beacon ring\n");
feb94d24 243 goto fail4;
5fdff524
SZ
244 }
245
246 error = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT);
247 if (error != 0) {
248 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
feb94d24 249 goto fail5;
5fdff524
SZ
250 }
251
feb94d24
RP
252 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
253 if (ifp == NULL) {
254 device_printf(sc->sc_dev, "can not if_alloc()\n");
255 goto fail6;
5fdff524 256 }
feb94d24
RP
257 ic = ifp->if_l2com;
258
259 /* retrieve MAC address */
260 rt2560_get_macaddr(sc, macaddr);
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261
262 ifp->if_softc = sc;
263 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
264 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
265 ifp->if_init = rt2560_init;
266 ifp->if_ioctl = rt2560_ioctl;
267 ifp->if_start = rt2560_start;
5fdff524 268 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
c3d41318 269#ifdef notyet
5fdff524 270 ifq_set_ready(&ifp->if_snd);
c3d41318 271#endif
5fdff524 272
feb94d24
RP
273 ic->ic_ifp = ifp;
274 ic->ic_opmode = IEEE80211_M_STA;
5fdff524 275 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
0dba45fe 276
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SZ
277 /* set device capabilities */
278 ic->ic_caps =
feb94d24
RP
279 IEEE80211_C_STA /* station mode */
280 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
281 | IEEE80211_C_HOSTAP /* hostap mode */
282 | IEEE80211_C_MONITOR /* monitor mode */
283 | IEEE80211_C_AHDEMO /* adhoc demo mode */
284 | IEEE80211_C_WDS /* 4-address traffic works */
285 | IEEE80211_C_MBSS /* mesh point link mode */
286 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
287 | IEEE80211_C_SHSLOT /* short slot time supported */
288 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
289 | IEEE80211_C_BGSCAN /* capable of bg scanning */
290#ifdef notyet
291 | IEEE80211_C_TXFRAG /* handle tx frags */
292#endif
293 ;
5fdff524 294
feb94d24
RP
295 bands = 0;
296 setbit(&bands, IEEE80211_MODE_11B);
297 setbit(&bands, IEEE80211_MODE_11G);
298 if (sc->rf_rev == RT2560_RF_5222)
299 setbit(&bands, IEEE80211_MODE_11A);
300 ieee80211_init_channels(ic, NULL, &bands);
322b19a8 301
feb94d24
RP
302 ieee80211_ifattach(ic, macaddr);
303 ic->ic_raw_xmit = rt2560_raw_xmit;
5fdff524 304 ic->ic_updateslot = rt2560_update_slot;
feb94d24
RP
305 ic->ic_update_promisc = rt2560_update_promisc;
306 ic->ic_scan_start = rt2560_scan_start;
307 ic->ic_scan_end = rt2560_scan_end;
308 ic->ic_set_channel = rt2560_set_channel;
5fdff524 309
feb94d24
RP
310 ic->ic_vap_create = rt2560_vap_create;
311 ic->ic_vap_delete = rt2560_vap_delete;
5fdff524 312
feb94d24
RP
313 ieee80211_radiotap_attach(ic,
314 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
315 RT2560_TX_RADIOTAP_PRESENT,
316 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
317 RT2560_RX_RADIOTAP_PRESENT);
5fdff524
SZ
318
319 /*
320 * Add a few sysctl knobs.
321 */
26595b18
SW
322 ctx = device_get_sysctl_ctx(sc->sc_dev);
323 tree = device_get_sysctl_tree(sc->sc_dev);
cb3c6fae 324#ifdef RAL_DEBUG
feb94d24
RP
325 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
326 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
cb3c6fae 327#endif
feb94d24
RP
328 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
329 "txantenna", CTLFLAG_RW, &sc->tx_ant, 0, "tx antenna (0=auto)");
cb3c6fae 330
feb94d24
RP
331 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
332 "rxantenna", CTLFLAG_RW, &sc->rx_ant, 0, "rx antenna (0=auto)");
9db4b353 333
5fdff524
SZ
334 if (bootverbose)
335 ieee80211_announce(ic);
feb94d24 336
5fdff524 337 return 0;
feb94d24
RP
338
339fail6: rt2560_free_rx_ring(sc, &sc->rxq);
340fail5: rt2560_free_tx_ring(sc, &sc->bcnq);
341fail4: rt2560_free_tx_ring(sc, &sc->prioq);
342fail3: rt2560_free_tx_ring(sc, &sc->atimq);
343fail2: rt2560_free_tx_ring(sc, &sc->txq);
d8235d53 344fail1:
feb94d24
RP
345
346 return ENXIO;
5fdff524
SZ
347}
348
349int
350rt2560_detach(void *xsc)
351{
352 struct rt2560_softc *sc = xsc;
feb94d24
RP
353 struct ifnet *ifp = sc->sc_ifp;
354 struct ieee80211com *ic = ifp->if_l2com;
355
356 rt2560_stop(sc);
5fdff524 357
feb94d24 358 ieee80211_ifdetach(ic);
5fdff524
SZ
359
360 rt2560_free_tx_ring(sc, &sc->txq);
361 rt2560_free_tx_ring(sc, &sc->atimq);
362 rt2560_free_tx_ring(sc, &sc->prioq);
363 rt2560_free_tx_ring(sc, &sc->bcnq);
364 rt2560_free_rx_ring(sc, &sc->rxq);
365
feb94d24 366 if_free(ifp);
5fdff524 367
5fdff524
SZ
368 return 0;
369}
370
feb94d24
RP
371static struct ieee80211vap *
372rt2560_vap_create(struct ieee80211com *ic,
18ef6e46
SW
373 const char name[IFNAMSIZ], int unit,
374 enum ieee80211_opmode opmode, int flags,
feb94d24
RP
375 const uint8_t bssid[IEEE80211_ADDR_LEN],
376 const uint8_t mac[IEEE80211_ADDR_LEN])
5fdff524 377{
feb94d24
RP
378 struct ifnet *ifp = ic->ic_ifp;
379 struct rt2560_vap *rvp;
380 struct ieee80211vap *vap;
381
382 switch (opmode) {
383 case IEEE80211_M_STA:
384 case IEEE80211_M_IBSS:
385 case IEEE80211_M_AHDEMO:
386 case IEEE80211_M_MONITOR:
387 case IEEE80211_M_HOSTAP:
388 case IEEE80211_M_MBSS:
389 /* XXXRP: TBD */
390 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
391 if_printf(ifp, "only 1 vap supported\n");
392 return NULL;
393 }
394 if (opmode == IEEE80211_M_STA)
395 flags |= IEEE80211_CLONE_NOBEACONS;
396 break;
397 case IEEE80211_M_WDS:
398 if (TAILQ_EMPTY(&ic->ic_vaps) ||
399 ic->ic_opmode != IEEE80211_M_HOSTAP) {
400 if_printf(ifp, "wds only supported in ap mode\n");
401 return NULL;
402 }
403 /*
404 * Silently remove any request for a unique
405 * bssid; WDS vap's always share the local
406 * mac address.
407 */
408 flags &= ~IEEE80211_CLONE_BSSID;
409 break;
410 default:
411 if_printf(ifp, "unknown opmode %d\n", opmode);
412 return NULL;
413 }
414 rvp = (struct rt2560_vap *) kmalloc(sizeof(struct rt2560_vap),
57d5bd0d 415 M_80211_VAP, M_INTWAIT | M_ZERO);
feb94d24
RP
416 if (rvp == NULL)
417 return NULL;
418 vap = &rvp->ral_vap;
419 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
5fdff524 420
feb94d24
RP
421 /* override state transition machine */
422 rvp->ral_newstate = vap->iv_newstate;
423 vap->iv_newstate = rt2560_newstate;
424 vap->iv_update_beacon = rt2560_beacon_update;
425
426 ieee80211_ratectl_init(vap);
427 /* complete setup */
428 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status);
429 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
430 ic->ic_opmode = opmode;
431 return vap;
5fdff524
SZ
432}
433
feb94d24
RP
434static void
435rt2560_vap_delete(struct ieee80211vap *vap)
5fdff524 436{
feb94d24 437 struct rt2560_vap *rvp = RT2560_VAP(vap);
5fdff524 438
feb94d24
RP
439 ieee80211_ratectl_deinit(vap);
440 ieee80211_vap_detach(vap);
441 kfree(rvp, M_80211_VAP);
5fdff524
SZ
442}
443
444void
445rt2560_resume(void *xsc)
446{
447 struct rt2560_softc *sc = xsc;
feb94d24 448 struct ifnet *ifp = sc->sc_ifp;
5fdff524 449
feb94d24
RP
450 if (ifp->if_flags & IFF_UP)
451 rt2560_init(sc);
5fdff524
SZ
452}
453
454static void
455rt2560_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
456{
457 if (error != 0)
458 return;
459
460 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
461
462 *(bus_addr_t *)arg = segs[0].ds_addr;
463}
464
465static int
466rt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring,
467 int count)
468{
469 int i, error;
470
471 ring->count = count;
472 ring->queued = 0;
473 ring->cur = ring->next = 0;
474 ring->cur_encrypt = ring->next_encrypt = 0;
475
feb94d24
RP
476 error = bus_dma_tag_create(ring->desc_dmat, 4, 0,
477 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
478 count * RT2560_TX_DESC_SIZE, 1, count * RT2560_TX_DESC_SIZE,
479 0, &ring->desc_dmat);
5fdff524
SZ
480 if (error != 0) {
481 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
482 goto fail;
483 }
484
485 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
feb94d24 486 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
5fdff524
SZ
487 if (error != 0) {
488 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
489 goto fail;
490 }
491
492 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
feb94d24
RP
493 count * RT2560_TX_DESC_SIZE, rt2560_dma_map_addr, &ring->physaddr,
494 0);
5fdff524
SZ
495 if (error != 0) {
496 device_printf(sc->sc_dev, "could not load desc DMA map\n");
5fdff524
SZ
497 goto fail;
498 }
499
efda3bd0 500 ring->data = kmalloc(count * sizeof (struct rt2560_tx_data), M_DEVBUF,
57d5bd0d 501 M_INTWAIT | M_ZERO);
feb94d24
RP
502 if (ring->data == NULL) {
503 device_printf(sc->sc_dev, "could not allocate soft data\n");
504 error = ENOMEM;
505 goto fail;
506 }
5fdff524 507
feb94d24
RP
508 error = bus_dma_tag_create(ring->data_dmat, 1, 0,
509 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
510 MCLBYTES, RT2560_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat);
5fdff524
SZ
511 if (error != 0) {
512 device_printf(sc->sc_dev, "could not create data DMA tag\n");
513 goto fail;
514 }
515
516 for (i = 0; i < count; i++) {
517 error = bus_dmamap_create(ring->data_dmat, 0,
518 &ring->data[i].map);
519 if (error != 0) {
520 device_printf(sc->sc_dev, "could not create DMA map\n");
521 goto fail;
522 }
523 }
feb94d24 524
5fdff524
SZ
525 return 0;
526
527fail: rt2560_free_tx_ring(sc, ring);
528 return error;
529}
530
531static void
532rt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring)
533{
534 struct rt2560_tx_desc *desc;
535 struct rt2560_tx_data *data;
536 int i;
537
538 for (i = 0; i < ring->count; i++) {
539 desc = &ring->desc[i];
540 data = &ring->data[i];
541
542 if (data->m != NULL) {
543 bus_dmamap_sync(ring->data_dmat, data->map,
544 BUS_DMASYNC_POSTWRITE);
545 bus_dmamap_unload(ring->data_dmat, data->map);
546 m_freem(data->m);
547 data->m = NULL;
548 }
549
550 if (data->ni != NULL) {
551 ieee80211_free_node(data->ni);
552 data->ni = NULL;
553 }
554
555 desc->flags = 0;
556 }
557
558 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
559
560 ring->queued = 0;
561 ring->cur = ring->next = 0;
562 ring->cur_encrypt = ring->next_encrypt = 0;
563}
564
565static void
566rt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring)
567{
568 struct rt2560_tx_data *data;
569 int i;
570
571 if (ring->desc != NULL) {
572 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
573 BUS_DMASYNC_POSTWRITE);
574 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
575 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
5fdff524
SZ
576 }
577
feb94d24 578 if (ring->desc_dmat != NULL)
5fdff524 579 bus_dma_tag_destroy(ring->desc_dmat);
5fdff524
SZ
580
581 if (ring->data != NULL) {
582 for (i = 0; i < ring->count; i++) {
583 data = &ring->data[i];
584
585 if (data->m != NULL) {
586 bus_dmamap_sync(ring->data_dmat, data->map,
587 BUS_DMASYNC_POSTWRITE);
588 bus_dmamap_unload(ring->data_dmat, data->map);
589 m_freem(data->m);
5fdff524
SZ
590 }
591
feb94d24 592 if (data->ni != NULL)
5fdff524 593 ieee80211_free_node(data->ni);
5fdff524 594
feb94d24 595 if (data->map != NULL)
5fdff524 596 bus_dmamap_destroy(ring->data_dmat, data->map);
5fdff524
SZ
597 }
598
efda3bd0 599 kfree(ring->data, M_DEVBUF);
5fdff524
SZ
600 }
601
feb94d24 602 if (ring->data_dmat != NULL)
5fdff524 603 bus_dma_tag_destroy(ring->data_dmat);
5fdff524
SZ
604}
605
606static int
607rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring,
608 int count)
609{
610 struct rt2560_rx_desc *desc;
611 struct rt2560_rx_data *data;
612 bus_addr_t physaddr;
613 int i, error;
614
615 ring->count = count;
616 ring->cur = ring->next = 0;
617 ring->cur_decrypt = 0;
618
feb94d24
RP
619 error = bus_dma_tag_create(ring->desc_dmat, 4, 0,
620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
621 count * RT2560_RX_DESC_SIZE, 1, count * RT2560_RX_DESC_SIZE,
622 0, &ring->desc_dmat);
5fdff524
SZ
623 if (error != 0) {
624 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
625 goto fail;
626 }
627
628 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
feb94d24 629 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
5fdff524
SZ
630 if (error != 0) {
631 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
632 goto fail;
633 }
634
635 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
feb94d24
RP
636 count * RT2560_RX_DESC_SIZE, rt2560_dma_map_addr, &ring->physaddr,
637 0);
5fdff524
SZ
638 if (error != 0) {
639 device_printf(sc->sc_dev, "could not load desc DMA map\n");
5fdff524
SZ
640 goto fail;
641 }
642
efda3bd0 643 ring->data = kmalloc(count * sizeof (struct rt2560_rx_data), M_DEVBUF,
57d5bd0d 644 M_INTWAIT | M_ZERO);
feb94d24
RP
645 if (ring->data == NULL) {
646 device_printf(sc->sc_dev, "could not allocate soft data\n");
647 error = ENOMEM;
648 goto fail;
649 }
5fdff524
SZ
650
651 /*
652 * Pre-allocate Rx buffers and populate Rx ring.
653 */
feb94d24
RP
654 error = bus_dma_tag_create(ring->data_dmat, 1, 0,
655 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
656 1, MCLBYTES, 0, &ring->data_dmat);
5fdff524
SZ
657 if (error != 0) {
658 device_printf(sc->sc_dev, "could not create data DMA tag\n");
659 goto fail;
660 }
661
662 for (i = 0; i < count; i++) {
663 desc = &sc->rxq.desc[i];
664 data = &sc->rxq.data[i];
665
666 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
667 if (error != 0) {
668 device_printf(sc->sc_dev, "could not create DMA map\n");
669 goto fail;
670 }
671
feb94d24 672 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
5fdff524
SZ
673 if (data->m == NULL) {
674 device_printf(sc->sc_dev,
675 "could not allocate rx mbuf\n");
676 error = ENOMEM;
677 goto fail;
678 }
679
680 error = bus_dmamap_load(ring->data_dmat, data->map,
681 mtod(data->m, void *), MCLBYTES, rt2560_dma_map_addr,
682 &physaddr, 0);
683 if (error != 0) {
684 device_printf(sc->sc_dev,
685 "could not load rx buf DMA map");
5fdff524
SZ
686 goto fail;
687 }
688
689 desc->flags = htole32(RT2560_RX_BUSY);
690 desc->physaddr = htole32(physaddr);
691 }
692
693 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
694
695 return 0;
696
697fail: rt2560_free_rx_ring(sc, ring);
698 return error;
699}
700
701static void
702rt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring)
703{
704 int i;
705
706 for (i = 0; i < ring->count; i++) {
707 ring->desc[i].flags = htole32(RT2560_RX_BUSY);
708 ring->data[i].drop = 0;
709 }
710
711 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
712
713 ring->cur = ring->next = 0;
714 ring->cur_decrypt = 0;
715}
716
717static void
718rt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring)
719{
720 struct rt2560_rx_data *data;
feb94d24 721 int i;
5fdff524
SZ
722
723 if (ring->desc != NULL) {
724 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
725 BUS_DMASYNC_POSTWRITE);
726 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
727 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
5fdff524
SZ
728 }
729
feb94d24 730 if (ring->desc_dmat != NULL)
5fdff524 731 bus_dma_tag_destroy(ring->desc_dmat);
5fdff524
SZ
732
733 if (ring->data != NULL) {
5fdff524
SZ
734 for (i = 0; i < ring->count; i++) {
735 data = &ring->data[i];
736
737 if (data->m != NULL) {
738 bus_dmamap_sync(ring->data_dmat, data->map,
739 BUS_DMASYNC_POSTREAD);
740 bus_dmamap_unload(ring->data_dmat, data->map);
741 m_freem(data->m);
5fdff524
SZ
742 }
743
feb94d24 744 if (data->map != NULL)
5fdff524 745 bus_dmamap_destroy(ring->data_dmat, data->map);
5fdff524
SZ
746 }
747
efda3bd0 748 kfree(ring->data, M_DEVBUF);
5fdff524
SZ
749 }
750
feb94d24 751 if (ring->data_dmat != NULL)
5fdff524 752 bus_dma_tag_destroy(ring->data_dmat);
5fdff524
SZ
753}
754
5fdff524 755static int
feb94d24 756rt2560_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5fdff524 757{
feb94d24
RP
758 struct rt2560_vap *rvp = RT2560_VAP(vap);
759 struct ifnet *ifp = vap->iv_ic->ic_ifp;
5fdff524
SZ
760 struct rt2560_softc *sc = ifp->if_softc;
761 int error;
762
feb94d24
RP
763 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
764 /* abort TSF synchronization */
765 RAL_WRITE(sc, RT2560_CSR14, 0);
5fdff524 766
feb94d24
RP
767 /* turn association led off */
768 rt2560_update_led(sc, 0, 0);
769 }
5fdff524 770
feb94d24 771 error = rvp->ral_newstate(vap, nstate, arg);
5fdff524 772
feb94d24
RP
773 if (error == 0 && nstate == IEEE80211_S_RUN) {
774 struct ieee80211_node *ni = vap->iv_bss;
775 struct mbuf *m;
5fdff524 776
feb94d24 777 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
5fdff524
SZ
778 rt2560_update_plcp(sc);
779 rt2560_set_basicrates(sc);
780 rt2560_set_bssid(sc, ni->ni_bssid);
781 }
782
feb94d24
RP
783 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
784 vap->iv_opmode == IEEE80211_M_IBSS ||
785 vap->iv_opmode == IEEE80211_M_MBSS) {
786 m = ieee80211_beacon_alloc(ni, &rvp->ral_bo);
5fdff524 787 if (m == NULL) {
feb94d24
RP
788 if_printf(ifp, "could not allocate beacon\n");
789 return ENOBUFS;
5fdff524 790 }
5fdff524
SZ
791 ieee80211_ref_node(ni);
792 error = rt2560_tx_bcn(sc, m, ni);
793 if (error != 0)
feb94d24 794 return error;
5fdff524
SZ
795 }
796
797 /* turn assocation led on */
798 rt2560_update_led(sc, 1, 0);
799
feb94d24 800 if (vap->iv_opmode != IEEE80211_M_MONITOR)
5fdff524 801 rt2560_enable_tsf_sync(sc);
feb94d24
RP
802 else
803 rt2560_enable_tsf(sc);
5fdff524 804 }
feb94d24 805 return error;
5fdff524
SZ
806}
807
808/*
809 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
810 * 93C66).
811 */
812static uint16_t
813rt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr)
814{
815 uint32_t tmp;
816 uint16_t val;
817 int n;
818
819 /* clock C once before the first command */
820 RT2560_EEPROM_CTL(sc, 0);
821
822 RT2560_EEPROM_CTL(sc, RT2560_S);
823 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C);
824 RT2560_EEPROM_CTL(sc, RT2560_S);
825
826 /* write start bit (1) */
827 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D);
828 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C);
829
830 /* write READ opcode (10) */
831 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D);
832 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C);
833 RT2560_EEPROM_CTL(sc, RT2560_S);
834 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C);
835
836 /* write address (A5-A0 or A7-A0) */
837 n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7;
838 for (; n >= 0; n--) {
839 RT2560_EEPROM_CTL(sc, RT2560_S |
840 (((addr >> n) & 1) << RT2560_SHIFT_D));
841 RT2560_EEPROM_CTL(sc, RT2560_S |
842 (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C);
843 }
844
845 RT2560_EEPROM_CTL(sc, RT2560_S);
846
847 /* read data Q15-Q0 */
848 val = 0;
849 for (n = 15; n >= 0; n--) {
850 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C);
851 tmp = RAL_READ(sc, RT2560_CSR21);
852 val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
853 RT2560_EEPROM_CTL(sc, RT2560_S);
854 }
855
856 RT2560_EEPROM_CTL(sc, 0);
857
858 /* clear Chip Select and clock C */
859 RT2560_EEPROM_CTL(sc, RT2560_S);
860 RT2560_EEPROM_CTL(sc, 0);
861 RT2560_EEPROM_CTL(sc, RT2560_C);
862
863 return val;
864}
865
866/*
867 * Some frames were processed by the hardware cipher engine and are ready for
868 * transmission.
869 */
870static void
871rt2560_encryption_intr(struct rt2560_softc *sc)
872{
873 struct rt2560_tx_desc *desc;
874 int hw;
875
876 /* retrieve last descriptor index processed by cipher engine */
877 hw = RAL_READ(sc, RT2560_SECCSR1) - sc->txq.physaddr;
878 hw /= RT2560_TX_DESC_SIZE;
879
880 bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map,
881 BUS_DMASYNC_POSTREAD);
882
95301c6e
SZ
883 while (sc->txq.next_encrypt != hw) {
884 if (sc->txq.next_encrypt == sc->txq.cur_encrypt) {
885 kprintf("hw encrypt %d, cur_encrypt %d\n", hw,
feb94d24 886 sc->txq.cur_encrypt);
95301c6e
SZ
887 break;
888 }
889
5fdff524
SZ
890 desc = &sc->txq.desc[sc->txq.next_encrypt];
891
892 if ((le32toh(desc->flags) & RT2560_TX_BUSY) ||
893 (le32toh(desc->flags) & RT2560_TX_CIPHER_BUSY))
894 break;
895
896 /* for TKIP, swap eiv field to fix a bug in ASIC */
897 if ((le32toh(desc->flags) & RT2560_TX_CIPHER_MASK) ==
898 RT2560_TX_CIPHER_TKIP)
899 desc->eiv = bswap32(desc->eiv);
900
901 /* mark the frame ready for transmission */
9a18ddf4
SZ
902 desc->flags |= htole32(RT2560_TX_VALID);
903 desc->flags |= htole32(RT2560_TX_BUSY);
5fdff524 904
feb94d24
RP
905 DPRINTFN(sc, 15, "encryption done idx=%u\n",
906 sc->txq.next_encrypt);
5fdff524
SZ
907
908 sc->txq.next_encrypt =
909 (sc->txq.next_encrypt + 1) % RT2560_TX_RING_COUNT;
910 }
911
912 bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map,
913 BUS_DMASYNC_PREWRITE);
914
915 /* kick Tx */
916 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_TX);
917}
918
919static void
920rt2560_tx_intr(struct rt2560_softc *sc)
921{
feb94d24
RP
922 struct ifnet *ifp = sc->sc_ifp;
923 struct rt2560_tx_desc *desc;
924 struct rt2560_tx_data *data;
925 struct mbuf *m;
926 uint32_t flags;
927 int retrycnt;
928 struct ieee80211vap *vap;
929 struct ieee80211_node *ni;
5fdff524
SZ
930
931 bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map,
932 BUS_DMASYNC_POSTREAD);
933
934 for (;;) {
935 desc = &sc->txq.desc[sc->txq.next];
936 data = &sc->txq.data[sc->txq.next];
937
0dba45fe 938 flags = le32toh(desc->flags);
0dba45fe
SZ
939 if ((flags & RT2560_TX_BUSY) ||
940 (flags & RT2560_TX_CIPHER_BUSY) ||
941 !(flags & RT2560_TX_VALID))
5fdff524
SZ
942 break;
943
0dba45fe 944 m = data->m;
feb94d24
RP
945 ni = data->ni;
946 vap = ni->ni_vap;
5fdff524 947
0dba45fe 948 switch (flags & RT2560_TX_RESULT_MASK) {
5fdff524 949 case RT2560_TX_SUCCESS:
feb94d24
RP
950 retrycnt = 0;
951
952 DPRINTFN(sc, 10, "%s\n", "data frame sent successfully");
953 if (data->rix != IEEE80211_FIXED_RATE_NONE)
954 ieee80211_ratectl_tx_complete(vap, ni,
955 IEEE80211_RATECTL_TX_SUCCESS,
956 &retrycnt, NULL);
d40991ef 957 IFNET_STAT_INC(ifp, opackets, 1);
5fdff524
SZ
958 break;
959
960 case RT2560_TX_SUCCESS_RETRY:
feb94d24
RP
961 retrycnt = RT2560_TX_RETRYCNT(flags);
962
963 DPRINTFN(sc, 9, "data frame sent after %u retries\n",
964 retrycnt);
965 if (data->rix != IEEE80211_FIXED_RATE_NONE)
966 ieee80211_ratectl_tx_complete(vap, ni,
967 IEEE80211_RATECTL_TX_SUCCESS,
968 &retrycnt, NULL);
d40991ef 969 IFNET_STAT_INC(ifp, opackets, 1);
5fdff524
SZ
970 break;
971
972 case RT2560_TX_FAIL_RETRY:
feb94d24
RP
973 retrycnt = RT2560_TX_RETRYCNT(flags);
974
975 DPRINTFN(sc, 9, "data frame failed after %d retries\n",
976 retrycnt);
977 if (data->rix != IEEE80211_FIXED_RATE_NONE)
978 ieee80211_ratectl_tx_complete(vap, ni,
979 IEEE80211_RATECTL_TX_FAILURE,
980 &retrycnt, NULL);
d40991ef 981 IFNET_STAT_INC(ifp, oerrors, 1);
5fdff524
SZ
982 break;
983
984 case RT2560_TX_FAIL_INVALID:
985 case RT2560_TX_FAIL_OTHER:
986 default:
987 device_printf(sc->sc_dev, "sending data frame failed "
0dba45fe 988 "0x%08x\n", flags);
d40991ef 989 IFNET_STAT_INC(ifp, oerrors, 1);
5fdff524
SZ
990 }
991
992 bus_dmamap_sync(sc->txq.data_dmat, data->map,
993 BUS_DMASYNC_POSTWRITE);
994 bus_dmamap_unload(sc->txq.data_dmat, data->map);
0dba45fe 995 m_freem(m);
feb94d24
RP
996 data->m = NULL;
997 ieee80211_free_node(data->ni);
998 data->ni = NULL;
999 ni = NULL;
5fdff524
SZ
1000
1001 /* descriptor is no longer valid */
1002 desc->flags &= ~htole32(RT2560_TX_VALID);
1003
feb94d24 1004 DPRINTFN(sc, 15, "tx done idx=%u\n", sc->txq.next);
5fdff524
SZ
1005
1006 sc->txq.queued--;
1007 sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT;
1008 }
1009
1010 bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map,
1011 BUS_DMASYNC_PREWRITE);
1012
feb94d24 1013 if (sc->prioq.queued == 0 && sc->txq.queued == 0)
c22d69a1
SZ
1014 sc->sc_tx_timer = 0;
1015
b77254ce 1016 if (sc->txq.queued < RT2560_TX_RING_COUNT - 1) {
feb94d24 1017 sc->sc_flags &= ~RT2560_F_DATA_OACTIVE;
b77254ce 1018 if ((sc->sc_flags &
feb94d24 1019 (RT2560_F_DATA_OACTIVE | RT2560_F_PRIO_OACTIVE)) == 0)
9ed293e0 1020 ifq_clr_oactive(&ifp->if_snd);
feb94d24 1021 rt2560_start_locked(ifp);
b77254ce 1022 }
5fdff524
SZ
1023}
1024
1025static void
1026rt2560_prio_intr(struct rt2560_softc *sc)
1027{
feb94d24 1028 struct ifnet *ifp = sc->sc_ifp;
5fdff524
SZ
1029 struct rt2560_tx_desc *desc;
1030 struct rt2560_tx_data *data;
feb94d24
RP
1031 struct ieee80211_node *ni;
1032 struct mbuf *m;
1033 int flags;
5fdff524
SZ
1034
1035 bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map,
1036 BUS_DMASYNC_POSTREAD);
1037
1038 for (;;) {
1039 desc = &sc->prioq.desc[sc->prioq.next];
1040 data = &sc->prioq.data[sc->prioq.next];
1041
feb94d24
RP
1042 flags = le32toh(desc->flags);
1043 if ((flags & RT2560_TX_BUSY) || (flags & RT2560_TX_VALID) == 0)
5fdff524
SZ
1044 break;
1045
feb94d24 1046 switch (flags & RT2560_TX_RESULT_MASK) {
5fdff524 1047 case RT2560_TX_SUCCESS:
feb94d24 1048 DPRINTFN(sc, 10, "%s\n", "mgt frame sent successfully");
5fdff524
SZ
1049 break;
1050
1051 case RT2560_TX_SUCCESS_RETRY:
feb94d24
RP
1052 DPRINTFN(sc, 9, "mgt frame sent after %u retries\n",
1053 (flags >> 5) & 0x7);
5fdff524
SZ
1054 break;
1055
1056 case RT2560_TX_FAIL_RETRY:
feb94d24
RP
1057 DPRINTFN(sc, 9, "%s\n",
1058 "sending mgt frame failed (too much retries)");
5fdff524
SZ
1059 break;
1060
1061 case RT2560_TX_FAIL_INVALID:
1062 case RT2560_TX_FAIL_OTHER:
1063 default:
1064 device_printf(sc->sc_dev, "sending mgt frame failed "
feb94d24
RP
1065 "0x%08x\n", flags);
1066 break;
5fdff524
SZ
1067 }
1068
1069 bus_dmamap_sync(sc->prioq.data_dmat, data->map,
1070 BUS_DMASYNC_POSTWRITE);
1071 bus_dmamap_unload(sc->prioq.data_dmat, data->map);
0dba45fe 1072
feb94d24
RP
1073 m = data->m;
1074 data->m = NULL;
1075 ni = data->ni;
1076 data->ni = NULL;
5fdff524
SZ
1077
1078 /* descriptor is no longer valid */
1079 desc->flags &= ~htole32(RT2560_TX_VALID);
1080
feb94d24 1081 DPRINTFN(sc, 15, "prio done idx=%u\n", sc->prioq.next);
5fdff524
SZ
1082
1083 sc->prioq.queued--;
1084 sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT;
feb94d24
RP
1085
1086 if (m->m_flags & M_TXCB)
1087 ieee80211_process_callback(ni, m,
1088 (flags & RT2560_TX_RESULT_MASK) &~
1089 (RT2560_TX_SUCCESS | RT2560_TX_SUCCESS_RETRY));
1090 m_freem(m);
1091 ieee80211_free_node(ni);
5fdff524
SZ
1092 }
1093
1094 bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map,
1095 BUS_DMASYNC_PREWRITE);
1096
feb94d24 1097 if (sc->prioq.queued == 0 && sc->txq.queued == 0)
c22d69a1
SZ
1098 sc->sc_tx_timer = 0;
1099
b77254ce 1100 if (sc->prioq.queued < RT2560_PRIO_RING_COUNT) {
feb94d24 1101 sc->sc_flags &= ~RT2560_F_PRIO_OACTIVE;
b77254ce 1102 if ((sc->sc_flags &
feb94d24 1103 (RT2560_F_DATA_OACTIVE | RT2560_F_PRIO_OACTIVE)) == 0)
9ed293e0 1104 ifq_clr_oactive(&ifp->if_snd);
feb94d24 1105 rt2560_start_locked(ifp);
b77254ce 1106 }
5fdff524
SZ
1107}
1108
1109/*
1110 * Some frames were processed by the hardware cipher engine and are ready for
feb94d24 1111 * handoff to the IEEE802.11 layer.
5fdff524
SZ
1112 */
1113static void
1114rt2560_decryption_intr(struct rt2560_softc *sc)
1115{
feb94d24
RP
1116 struct ifnet *ifp = sc->sc_ifp;
1117 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1118 struct rt2560_rx_desc *desc;
1119 struct rt2560_rx_data *data;
1120 bus_addr_t physaddr;
1121 struct ieee80211_frame *wh;
1122 struct ieee80211_node *ni;
5fdff524
SZ
1123 struct mbuf *mnew, *m;
1124 int hw, error;
feb94d24 1125 int8_t rssi, nf;
5fdff524
SZ
1126
1127 /* retrieve last decriptor index processed by cipher engine */
1128 hw = RAL_READ(sc, RT2560_SECCSR0) - sc->rxq.physaddr;
1129 hw /= RT2560_RX_DESC_SIZE;
1130
1131 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1132 BUS_DMASYNC_POSTREAD);
1133
1134 for (; sc->rxq.cur_decrypt != hw;) {
1135 desc = &sc->rxq.desc[sc->rxq.cur_decrypt];
1136 data = &sc->rxq.data[sc->rxq.cur_decrypt];
1137
1138 if ((le32toh(desc->flags) & RT2560_RX_BUSY) ||
1139 (le32toh(desc->flags) & RT2560_RX_CIPHER_BUSY))
1140 break;
1141
1142 if (data->drop) {
d40991ef 1143 IFNET_STAT_INC(ifp, ierrors, 1);
5fdff524
SZ
1144 goto skip;
1145 }
1146
1147 if ((le32toh(desc->flags) & RT2560_RX_CIPHER_MASK) != 0 &&
1148 (le32toh(desc->flags) & RT2560_RX_ICV_ERROR)) {
d40991ef 1149 IFNET_STAT_INC(ifp, ierrors, 1);
5fdff524
SZ
1150 goto skip;
1151 }
1152
1153 /*
1154 * Try to allocate a new mbuf for this ring element and load it
1155 * before processing the current mbuf. If the ring element
1156 * cannot be loaded, drop the received packet and reuse the old
1157 * mbuf. In the unlikely case that the old mbuf can't be
1158 * reloaded either, explicitly panic.
1159 */
1160 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1161 if (mnew == NULL) {
d40991ef 1162 IFNET_STAT_INC(ifp, ierrors, 1);
5fdff524
SZ
1163 goto skip;
1164 }
1165
1166 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1167 BUS_DMASYNC_POSTREAD);
1168 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1169
1170 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1171 mtod(mnew, void *), MCLBYTES, rt2560_dma_map_addr,
1172 &physaddr, 0);
1173 if (error != 0) {
1174 m_freem(mnew);
1175
1176 /* try to reload the old mbuf */
1177 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1178 mtod(data->m, void *), MCLBYTES,
1179 rt2560_dma_map_addr, &physaddr, 0);
1180 if (error != 0) {
1181 /* very unlikely that it will fail... */
1182 panic("%s: could not load old rx mbuf",
1183 device_get_name(sc->sc_dev));
1184 }
d40991ef 1185 IFNET_STAT_INC(ifp, ierrors, 1);
5fdff524
SZ
1186 goto skip;
1187 }
1188
1189 /*
1190 * New mbuf successfully loaded, update Rx ring and continue
1191 * processing.
1192 */
1193 m = data->m;
1194 data->m = mnew;
1195 desc->physaddr = htole32(physaddr);
1196
1197 /* finalize mbuf */
1198 m->m_pkthdr.rcvif = ifp;
1199 m->m_pkthdr.len = m->m_len =
1200 (le32toh(desc->flags) >> 16) & 0xfff;
1201
2da757be 1202 rssi = RT2560_RSSI(sc, desc->rssi);
feb94d24
RP
1203 nf = RT2560_NOISE_FLOOR;
1204 if (ieee80211_radiotap_active(ic)) {
5fdff524
SZ
1205 struct rt2560_rx_radiotap_header *tap = &sc->sc_rxtap;
1206 uint32_t tsf_lo, tsf_hi;
1207
1208 /* get timestamp (low and high 32 bits) */
1209 tsf_hi = RAL_READ(sc, RT2560_CSR17);
1210 tsf_lo = RAL_READ(sc, RT2560_CSR16);
1211
1212 tap->wr_tsf =
1213 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1214 tap->wr_flags = 0;
feb94d24
RP
1215 tap->wr_rate = ieee80211_plcp2rate(desc->rate,
1216 (desc->flags & htole32(RT2560_RX_OFDM)) ?
1217 IEEE80211_T_OFDM : IEEE80211_T_CCK);
5fdff524 1218 tap->wr_antenna = sc->rx_ant;
feb94d24
RP
1219 tap->wr_antsignal = nf + rssi;
1220 tap->wr_antnoise = nf;
5fdff524
SZ
1221 }
1222
feb94d24 1223 sc->sc_flags |= RT2560_F_INPUT_RUNNING;
5fdff524
SZ
1224 wh = mtod(m, struct ieee80211_frame *);
1225 ni = ieee80211_find_rxnode(ic,
1226 (struct ieee80211_frame_min *)wh);
feb94d24
RP
1227 if (ni != NULL) {
1228 (void) ieee80211_input(ni, m, rssi, nf);
1229 ieee80211_free_node(ni);
1230 } else
1231 (void) ieee80211_input_all(ic, m, rssi, nf);
1232
feb94d24 1233 sc->sc_flags &= ~RT2560_F_INPUT_RUNNING;
5fdff524
SZ
1234skip: desc->flags = htole32(RT2560_RX_BUSY);
1235
feb94d24 1236 DPRINTFN(sc, 15, "decryption done idx=%u\n", sc->rxq.cur_decrypt);
5fdff524
SZ
1237
1238 sc->rxq.cur_decrypt =
1239 (sc->rxq.cur_decrypt + 1) % RT2560_RX_RING_COUNT;
1240 }
1241
1242 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1243 BUS_DMASYNC_PREWRITE);
1244}
1245
1246/*
1247 * Some frames were received. Pass them to the hardware cipher engine before
1248 * sending them to the 802.11 layer.
1249 */
1250static void
1251rt2560_rx_intr(struct rt2560_softc *sc)
1252{
1253 struct rt2560_rx_desc *desc;
1254 struct rt2560_rx_data *data;
1255
1256 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1257 BUS_DMASYNC_POSTREAD);
1258
1259 for (;;) {
1260 desc = &sc->rxq.desc[sc->rxq.cur];
1261 data = &sc->rxq.data[sc->rxq.cur];
1262
1263 if ((le32toh(desc->flags) & RT2560_RX_BUSY) ||
1264 (le32toh(desc->flags) & RT2560_RX_CIPHER_BUSY))
1265 break;
1266
1267 data->drop = 0;
1268
1269 if ((le32toh(desc->flags) & RT2560_RX_PHY_ERROR) ||
1270 (le32toh(desc->flags) & RT2560_RX_CRC_ERROR)) {
1271 /*
1272 * This should not happen since we did not request
1273 * to receive those frames when we filled RXCSR0.
1274 */
feb94d24
RP
1275 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n",
1276 le32toh(desc->flags));
5fdff524
SZ
1277 data->drop = 1;
1278 }
1279
1280 if (((le32toh(desc->flags) >> 16) & 0xfff) > MCLBYTES) {
feb94d24 1281 DPRINTFN(sc, 5, "%s\n", "bad length");
5fdff524
SZ
1282 data->drop = 1;
1283 }
1284
1285 /* mark the frame for decryption */
1286 desc->flags |= htole32(RT2560_RX_CIPHER_BUSY);
1287
feb94d24 1288 DPRINTFN(sc, 15, "rx done idx=%u\n", sc->rxq.cur);
5fdff524
SZ
1289
1290 sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT;
1291 }
1292
1293 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1294 BUS_DMASYNC_PREWRITE);
1295
1296 /* kick decrypt */
1297 RAL_WRITE(sc, RT2560_SECCSR0, RT2560_KICK_DECRYPT);
1298}
1299
feb94d24
RP
1300static void
1301rt2560_beacon_update(struct ieee80211vap *vap, int item)
1302{
1303 struct rt2560_vap *rvp = RT2560_VAP(vap);
1304 struct ieee80211_beacon_offsets *bo = &rvp->ral_bo;
1305
1306 setbit(bo->bo_flags, item);
1307}
1308
5fdff524
SZ
1309/*
1310 * This function is called periodically in IBSS mode when a new beacon must be
1311 * sent out.
1312 */
1313static void
1314rt2560_beacon_expire(struct rt2560_softc *sc)
1315{
feb94d24
RP
1316 struct ifnet *ifp = sc->sc_ifp;
1317 struct ieee80211com *ic = ifp->if_l2com;
1318 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1319 struct rt2560_vap *rvp = RT2560_VAP(vap);
5fdff524
SZ
1320 struct rt2560_tx_data *data;
1321
1322 if (ic->ic_opmode != IEEE80211_M_IBSS &&
feb94d24
RP
1323 ic->ic_opmode != IEEE80211_M_HOSTAP &&
1324 ic->ic_opmode != IEEE80211_M_MBSS)
1325 return;
5fdff524
SZ
1326
1327 data = &sc->bcnq.data[sc->bcnq.next];
feb94d24
RP
1328 /*
1329 * Don't send beacon if bsschan isn't set
1330 */
1331 if (data->ni == NULL)
1332 return;
5fdff524
SZ
1333
1334 bus_dmamap_sync(sc->bcnq.data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
1335 bus_dmamap_unload(sc->bcnq.data_dmat, data->map);
1336
feb94d24
RP
1337 /* XXX 1 =>'s mcast frames which means all PS sta's will wakeup! */
1338 ieee80211_beacon_update(data->ni, &rvp->ral_bo, data->m, 1);
5fdff524
SZ
1339
1340 rt2560_tx_bcn(sc, data->m, data->ni);
1341
feb94d24 1342 DPRINTFN(sc, 15, "%s", "beacon expired\n");
5fdff524
SZ
1343
1344 sc->bcnq.next = (sc->bcnq.next + 1) % RT2560_BEACON_RING_COUNT;
1345}
1346
1347/* ARGSUSED */
1348static void
1349rt2560_wakeup_expire(struct rt2560_softc *sc)
1350{
feb94d24 1351 DPRINTFN(sc, 2, "%s", "wakeup expired\n");
5fdff524
SZ
1352}
1353
feb94d24 1354void
5fdff524
SZ
1355rt2560_intr(void *arg)
1356{
1357 struct rt2560_softc *sc = arg;
feb94d24 1358 struct ifnet *ifp = sc->sc_ifp;
5fdff524
SZ
1359 uint32_t r;
1360
1361 /* disable interrupts */
1362 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff);
1363
1364 /* don't re-enable interrupts if we're shutting down */
feb94d24 1365 if (!(ifp->if_flags & IFF_RUNNING)) {
5fdff524 1366 return;
feb94d24 1367 }
5fdff524
SZ
1368
1369 r = RAL_READ(sc, RT2560_CSR7);
1370 RAL_WRITE(sc, RT2560_CSR7, r);
1371
1372 if (r & RT2560_BEACON_EXPIRE)
1373 rt2560_beacon_expire(sc);
1374
1375 if (r & RT2560_WAKEUP_EXPIRE)
1376 rt2560_wakeup_expire(sc);
1377
feb94d24
RP
1378 if (r & RT2560_ENCRYPTION_DONE)
1379 rt2560_encryption_intr(sc);
5fdff524 1380
feb94d24
RP
1381 if (r & RT2560_TX_DONE)
1382 rt2560_tx_intr(sc);
5fdff524 1383
feb94d24
RP
1384 if (r & RT2560_PRIO_DONE)
1385 rt2560_prio_intr(sc);
5fdff524 1386
feb94d24
RP
1387 if (r & RT2560_DECRYPTION_DONE)
1388 rt2560_decryption_intr(sc);
5fdff524 1389
feb94d24
RP
1390 if (r & RT2560_RX_DONE) {
1391 rt2560_rx_intr(sc);
1392 rt2560_encryption_intr(sc);
5fdff524
SZ
1393 }
1394
1395 /* re-enable interrupts */
1396 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK);
feb94d24 1397}
5fdff524 1398
feb94d24 1399#define RAL_SIFS 10 /* us */
5fdff524
SZ
1400
1401#define RT2560_TXRX_TURNAROUND 10 /* us */
1402
5fdff524
SZ
1403static uint8_t
1404rt2560_plcp_signal(int rate)
1405{
1406 switch (rate) {
5fdff524
SZ
1407 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1408 case 12: return 0xb;
1409 case 18: return 0xf;
1410 case 24: return 0xa;
1411 case 36: return 0xe;
1412 case 48: return 0x9;
1413 case 72: return 0xd;
1414 case 96: return 0x8;
1415 case 108: return 0xc;
1416
feb94d24
RP
1417 /* CCK rates (NB: not IEEE std, device-specific) */
1418 case 2: return 0x0;
1419 case 4: return 0x1;
1420 case 11: return 0x2;
1421 case 22: return 0x3;
5fdff524 1422 }
feb94d24 1423 return 0xff; /* XXX unsupported/unknown rate */
5fdff524
SZ
1424}
1425
1426static void
1427rt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc,
1428 uint32_t flags, int len, int rate, int encrypt, bus_addr_t physaddr)
1429{
feb94d24
RP
1430 struct ifnet *ifp = sc->sc_ifp;
1431 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1432 uint16_t plcp_length;
1433 int remainder;
1434
1435 desc->flags = htole32(flags);
1436 desc->flags |= htole32(len << 16);
5fdff524
SZ
1437
1438 desc->physaddr = htole32(physaddr);
1439 desc->wme = htole16(
1440 RT2560_AIFSN(2) |
1441 RT2560_LOGCWMIN(3) |
1442 RT2560_LOGCWMAX(8));
1443
1444 /* setup PLCP fields */
1445 desc->plcp_signal = rt2560_plcp_signal(rate);
1446 desc->plcp_service = 4;
1447
1448 len += IEEE80211_CRC_LEN;
feb94d24 1449 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) {
5fdff524
SZ
1450 desc->flags |= htole32(RT2560_TX_OFDM);
1451
1452 plcp_length = len & 0xfff;
1453 desc->plcp_length_hi = plcp_length >> 6;
1454 desc->plcp_length_lo = plcp_length & 0x3f;
1455 } else {
1456 plcp_length = (16 * len + rate - 1) / rate;
1457 if (rate == 22) {
1458 remainder = (16 * len) % 22;
1459 if (remainder != 0 && remainder < 7)
1460 desc->plcp_service |= RT2560_PLCP_LENGEXT;
1461 }
1462 desc->plcp_length_hi = plcp_length >> 8;
1463 desc->plcp_length_lo = plcp_length & 0xff;
1464
1465 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1466 desc->plcp_signal |= 0x08;
1467 }
9a18ddf4 1468
12109821
SZ
1469 if (!encrypt)
1470 desc->flags |= htole32(RT2560_TX_VALID);
9a18ddf4
SZ
1471 desc->flags |= encrypt ? htole32(RT2560_TX_CIPHER_BUSY)
1472 : htole32(RT2560_TX_BUSY);
5fdff524
SZ
1473}
1474
1475static int
1476rt2560_tx_bcn(struct rt2560_softc *sc, struct mbuf *m0,
1477 struct ieee80211_node *ni)
1478{
feb94d24 1479 struct ieee80211vap *vap = ni->ni_vap;
5fdff524
SZ
1480 struct rt2560_tx_desc *desc;
1481 struct rt2560_tx_data *data;
feb94d24
RP
1482 bus_dma_segment_t segs[RT2560_MAX_SCATTER];
1483 int nsegs, rate, error;
5fdff524
SZ
1484
1485 desc = &sc->bcnq.desc[sc->bcnq.cur];
1486 data = &sc->bcnq.data[sc->bcnq.cur];
1487
feb94d24
RP
1488 /* XXX maybe a separate beacon rate? */
1489 rate = vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)].mgmtrate;
5fdff524 1490
feb94d24
RP
1491 error = bus_dmamap_load_mbuf_segment(sc->bcnq.data_dmat, data->map, m0,
1492 segs, 1, &nsegs, BUS_DMA_NOWAIT);
5fdff524
SZ
1493 if (error != 0) {
1494 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1495 error);
1496 m_freem(m0);
1497 return error;
1498 }
1499
feb94d24 1500 if (ieee80211_radiotap_active_vap(vap)) {
5fdff524
SZ
1501 struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap;
1502
1503 tap->wt_flags = 0;
1504 tap->wt_rate = rate;
5fdff524
SZ
1505 tap->wt_antenna = sc->tx_ant;
1506
feb94d24 1507 ieee80211_radiotap_tx(vap, m0);
5fdff524
SZ
1508 }
1509
1510 data->m = m0;
1511 data->ni = ni;
1512
1513 rt2560_setup_tx_desc(sc, desc, RT2560_TX_IFS_NEWBACKOFF |
feb94d24 1514 RT2560_TX_TIMESTAMP, m0->m_pkthdr.len, rate, 0, segs->ds_addr);
5fdff524 1515
feb94d24
RP
1516 DPRINTFN(sc, 10, "sending beacon frame len=%u idx=%u rate=%u\n",
1517 m0->m_pkthdr.len, sc->bcnq.cur, rate);
5fdff524
SZ
1518
1519 bus_dmamap_sync(sc->bcnq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1520 bus_dmamap_sync(sc->bcnq.desc_dmat, sc->bcnq.desc_map,
1521 BUS_DMASYNC_PREWRITE);
1522
1523 sc->bcnq.cur = (sc->bcnq.cur + 1) % RT2560_BEACON_RING_COUNT;
1524
1525 return 0;
1526}
1527
1528static int
1529rt2560_tx_mgt(struct rt2560_softc *sc, struct mbuf *m0,
1530 struct ieee80211_node *ni)
1531{
feb94d24
RP
1532 struct ieee80211vap *vap = ni->ni_vap;
1533 struct ieee80211com *ic = ni->ni_ic;
5fdff524
SZ
1534 struct rt2560_tx_desc *desc;
1535 struct rt2560_tx_data *data;
1536 struct ieee80211_frame *wh;
feb94d24
RP
1537 struct ieee80211_key *k;
1538 bus_dma_segment_t segs[RT2560_MAX_SCATTER];
5fdff524
SZ
1539 uint16_t dur;
1540 uint32_t flags = 0;
feb94d24 1541 int nsegs, rate, error;
5fdff524
SZ
1542
1543 desc = &sc->prioq.desc[sc->prioq.cur];
1544 data = &sc->prioq.data[sc->prioq.cur];
1545
feb94d24
RP
1546 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate;
1547
1548 wh = mtod(m0, struct ieee80211_frame *);
1549
085ff963 1550 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
feb94d24
RP
1551 k = ieee80211_crypto_encap(ni, m0);
1552 if (k == NULL) {
1553 m_freem(m0);
1554 return ENOBUFS;
1555 }
1556 }
5fdff524 1557
feb94d24
RP
1558 error = bus_dmamap_load_mbuf_segment(sc->prioq.data_dmat, data->map, m0,
1559 segs, 1, &nsegs, 0);
5fdff524
SZ
1560 if (error != 0) {
1561 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1562 error);
1563 m_freem(m0);
1564 return error;
1565 }
1566
feb94d24 1567 if (ieee80211_radiotap_active_vap(vap)) {
5fdff524
SZ
1568 struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap;
1569
1570 tap->wt_flags = 0;
1571 tap->wt_rate = rate;
5fdff524
SZ
1572 tap->wt_antenna = sc->tx_ant;
1573
feb94d24 1574 ieee80211_radiotap_tx(vap, m0);
5fdff524
SZ
1575 }
1576
1577 data->m = m0;
feb94d24
RP
1578 data->ni = ni;
1579 /* management frames are not taken into account for amrr */
1580 data->rix = IEEE80211_FIXED_RATE_NONE;
5fdff524
SZ
1581
1582 wh = mtod(m0, struct ieee80211_frame *);
1583
1584 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1585 flags |= RT2560_TX_ACK;
1586
feb94d24
RP
1587 dur = ieee80211_ack_duration(ic->ic_rt,
1588 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
5fdff524
SZ
1589 *(uint16_t *)wh->i_dur = htole16(dur);
1590
1591 /* tell hardware to add timestamp for probe responses */
1592 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1593 IEEE80211_FC0_TYPE_MGT &&
1594 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1595 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1596 flags |= RT2560_TX_TIMESTAMP;
1597 }
1598
feb94d24
RP
1599 rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 0,
1600 segs->ds_addr);
5fdff524
SZ
1601
1602 bus_dmamap_sync(sc->prioq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1603 bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map,
1604 BUS_DMASYNC_PREWRITE);
1605
feb94d24
RP
1606 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n",
1607 m0->m_pkthdr.len, sc->prioq.cur, rate);
5fdff524
SZ
1608
1609 /* kick prio */
1610 sc->prioq.queued++;
1611 sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT;
1612 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO);
1613
feb94d24
RP
1614 return 0;
1615}
1616
1617static int
1618rt2560_sendprot(struct rt2560_softc *sc,
1619 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1620{
1621 struct ieee80211com *ic = ni->ni_ic;
1622 const struct ieee80211_frame *wh;
1623 struct rt2560_tx_desc *desc;
1624 struct rt2560_tx_data *data;
1625 struct mbuf *mprot;
1a5bc45f 1626 int protrate, pktlen, flags, isshort, error;
feb94d24
RP
1627 uint16_t dur;
1628 bus_dma_segment_t segs[RT2560_MAX_SCATTER];
1629 int nsegs;
1630
1631 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY,
1632 ("protection %d", prot));
1633
1634 wh = mtod(m, const struct ieee80211_frame *);
1635 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
1636
1637 protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
1a5bc45f 1638 ieee80211_ack_rate(ic->ic_rt, rate);
feb94d24
RP
1639
1640 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
1641 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort)
1642 + ieee80211_ack_duration(ic->ic_rt, rate, isshort);
1643 flags = RT2560_TX_MORE_FRAG;
1644 if (prot == IEEE80211_PROT_RTSCTS) {
1645 /* NB: CTS is the same size as an ACK */
1646 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort);
1647 flags |= RT2560_TX_ACK;
1648 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur);
1649 } else {
1650 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur);
1651 }
1652 if (mprot == NULL) {
1653 /* XXX stat + msg */
1654 return ENOBUFS;
1655 }
1656
1657 desc = &sc->txq.desc[sc->txq.cur_encrypt];
1658 data = &sc->txq.data[sc->txq.cur_encrypt];
1659
1660 error = bus_dmamap_load_mbuf_segment(sc->txq.data_dmat, data->map,
1661 mprot, segs, 1, &nsegs, 0);
1662 if (error != 0) {
1663 device_printf(sc->sc_dev,
1664 "could not map mbuf (error %d)\n", error);
1665 m_freem(mprot);
1666 return error;
1667 }
1668
1669 data->m = mprot;
1670 data->ni = ieee80211_ref_node(ni);
1671 /* ctl frames are not taken into account for amrr */
1672 data->rix = IEEE80211_FIXED_RATE_NONE;
1673
1674 rt2560_setup_tx_desc(sc, desc, flags, mprot->m_pkthdr.len, protrate, 1,
1675 segs->ds_addr);
1676
1677 bus_dmamap_sync(sc->txq.data_dmat, data->map,
1678 BUS_DMASYNC_PREWRITE);
1679
1680 sc->txq.queued++;
1681 sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RT2560_TX_RING_COUNT;
0dba45fe 1682
5fdff524
SZ
1683 return 0;
1684}
1685
feb94d24
RP
1686static int
1687rt2560_tx_raw(struct rt2560_softc *sc, struct mbuf *m0,
1688 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
5fdff524 1689{
feb94d24
RP
1690 struct ieee80211vap *vap = ni->ni_vap;
1691 struct ieee80211com *ic = ni->ni_ic;
1692 struct rt2560_tx_desc *desc;
1693 struct rt2560_tx_data *data;
1694 bus_dma_segment_t segs[RT2560_MAX_SCATTER];
1695 uint32_t flags;
1696 int nsegs, rate, error;
5fdff524 1697
feb94d24
RP
1698 desc = &sc->prioq.desc[sc->prioq.cur];
1699 data = &sc->prioq.data[sc->prioq.cur];
1700
1701 rate = params->ibp_rate0;
1702 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
1703 /* XXX fall back to mcast/mgmt rate? */
1704 m_freem(m0);
1705 return EINVAL;
1706 }
1707
1708 flags = 0;
1709 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
1710 flags |= RT2560_TX_ACK;
1711 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) {
1712 error = rt2560_sendprot(sc, m0, ni,
1713 params->ibp_flags & IEEE80211_BPF_RTS ?
1714 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY,
1715 rate);
1716 if (error) {
1717 m_freem(m0);
1718 return error;
1719 }
1720 flags |= RT2560_TX_LONG_RETRY | RT2560_TX_IFS_SIFS;
1721 }
1722
1723 error = bus_dmamap_load_mbuf_segment(sc->prioq.data_dmat, data->map, m0,
1724 segs, 1, &nsegs, 0);
1725 if (error != 0) {
1726 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1727 error);
1728 m_freem(m0);
1729 return error;
1730 }
1731
1732 if (ieee80211_radiotap_active_vap(vap)) {
1733 struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap;
1734
1735 tap->wt_flags = 0;
1736 tap->wt_rate = rate;
1737 tap->wt_antenna = sc->tx_ant;
1738
1739 ieee80211_radiotap_tx(ni->ni_vap, m0);
5fdff524
SZ
1740 }
1741
feb94d24
RP
1742 data->m = m0;
1743 data->ni = ni;
5fdff524 1744
feb94d24
RP
1745 /* XXX need to setup descriptor ourself */
1746 rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len,
1747 rate, (params->ibp_flags & IEEE80211_BPF_CRYPTO) != 0,
1748 segs->ds_addr);
5fdff524 1749
feb94d24
RP
1750 bus_dmamap_sync(sc->prioq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1751 bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map,
1752 BUS_DMASYNC_PREWRITE);
1753
1754 DPRINTFN(sc, 10, "sending raw frame len=%u idx=%u rate=%u\n",
1755 m0->m_pkthdr.len, sc->prioq.cur, rate);
5fdff524 1756
feb94d24
RP
1757 /* kick prio */
1758 sc->prioq.queued++;
1759 sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT;
1760 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO);
1761
1762 return 0;
5fdff524
SZ
1763}
1764
1765static int
1766rt2560_tx_data(struct rt2560_softc *sc, struct mbuf *m0,
1767 struct ieee80211_node *ni)
1768{
feb94d24
RP
1769 struct ieee80211vap *vap = ni->ni_vap;
1770 struct ieee80211com *ic = ni->ni_ic;
5fdff524
SZ
1771 struct rt2560_tx_desc *desc;
1772 struct rt2560_tx_data *data;
5fdff524 1773 struct ieee80211_frame *wh;
feb94d24 1774 const struct ieee80211_txparam *tp;
5fdff524
SZ
1775 struct ieee80211_key *k;
1776 struct mbuf *mnew;
feb94d24 1777 bus_dma_segment_t segs[RT2560_MAX_SCATTER];
5fdff524 1778 uint16_t dur;
feb94d24
RP
1779 uint32_t flags;
1780 int nsegs, rate, error;
5fdff524
SZ
1781
1782 wh = mtod(m0, struct ieee80211_frame *);
feb94d24
RP
1783
1784 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1785 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1786 rate = tp->mcastrate;
1787 } else if (m0->m_flags & M_EAPOL) {
1788 rate = tp->mgmtrate;
1789 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1790 rate = tp->ucastrate;
1791 } else {
1792 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1793 rate = ni->ni_txrate;
1794 }
1795
085ff963 1796 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
feb94d24 1797 k = ieee80211_crypto_encap(ni, m0);
5fdff524
SZ
1798 if (k == NULL) {
1799 m_freem(m0);
1800 return ENOBUFS;
1801 }
1802
1803 /* packet header may have moved, reset our local pointer */
1804 wh = mtod(m0, struct ieee80211_frame *);
1805 }
1806
feb94d24
RP
1807 flags = 0;
1808 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1809 int prot = IEEE80211_PROT_NONE;
1810 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1811 prot = IEEE80211_PROT_RTSCTS;
1812 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1813 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM)
1814 prot = ic->ic_protmode;
1815 if (prot != IEEE80211_PROT_NONE) {
1816 error = rt2560_sendprot(sc, m0, ni, prot, rate);
1817 if (error) {
1818 m_freem(m0);
1819 return error;
1820 }
1821 flags |= RT2560_TX_LONG_RETRY | RT2560_TX_IFS_SIFS;
5fdff524 1822 }
5fdff524
SZ
1823 }
1824
1825 data = &sc->txq.data[sc->txq.cur_encrypt];
1826 desc = &sc->txq.desc[sc->txq.cur_encrypt];
1827
feb94d24
RP
1828 error = bus_dmamap_load_mbuf_segment(sc->txq.data_dmat, data->map, m0,
1829 segs, 1, &nsegs, 0);
5fdff524
SZ
1830 if (error != 0 && error != EFBIG) {
1831 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1832 error);
1833 m_freem(m0);
1834 return error;
1835 }
1836 if (error != 0) {
1837 mnew = m_defrag(m0, MB_DONTWAIT);
1838 if (mnew == NULL) {
1839 device_printf(sc->sc_dev,
1840 "could not defragment mbuf\n");
1841 m_freem(m0);
1842 return ENOBUFS;
1843 }
1844 m0 = mnew;
1845
feb94d24
RP
1846 error = bus_dmamap_load_mbuf_segment(sc->txq.data_dmat, data->map,
1847 m0, segs, 1, &nsegs, 0);
5fdff524
SZ
1848 if (error != 0) {
1849 device_printf(sc->sc_dev,
1850 "could not map mbuf (error %d)\n", error);
1851 m_freem(m0);
1852 return error;
1853 }
1854
1855 /* packet header may have moved, reset our local pointer */
1856 wh = mtod(m0, struct ieee80211_frame *);
1857 }
1858
feb94d24 1859 if (ieee80211_radiotap_active_vap(vap)) {
5fdff524
SZ
1860 struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap;
1861
1862 tap->wt_flags = 0;
1863 tap->wt_rate = rate;
5fdff524
SZ
1864 tap->wt_antenna = sc->tx_ant;
1865
feb94d24 1866 ieee80211_radiotap_tx(vap, m0);
5fdff524
SZ
1867 }
1868
1869 data->m = m0;
1870 data->ni = ni;
feb94d24
RP
1871
1872 /* remember link conditions for rate adaptation algorithm */
1873 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) {
1874 data->rix = ni->ni_txrate;
1875 /* XXX probably need last rssi value and not avg */
1876 data->rssi = ic->ic_node_getrssi(ni);
1877 } else
1878 data->rix = IEEE80211_FIXED_RATE_NONE;
5fdff524
SZ
1879
1880 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1881 flags |= RT2560_TX_ACK;
feb94d24
RP
1882
1883 dur = ieee80211_ack_duration(ic->ic_rt,
1884 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
5fdff524
SZ
1885 *(uint16_t *)wh->i_dur = htole16(dur);
1886 }
1887
feb94d24
RP
1888 rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 1,
1889 segs->ds_addr);
5fdff524
SZ
1890
1891 bus_dmamap_sync(sc->txq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1892 bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map,
1893 BUS_DMASYNC_PREWRITE);
1894
feb94d24
RP
1895 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n",
1896 m0->m_pkthdr.len, sc->txq.cur_encrypt, rate);
5fdff524
SZ
1897
1898 /* kick encrypt */
1899 sc->txq.queued++;
1900 sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RT2560_TX_RING_COUNT;
1901 RAL_WRITE(sc, RT2560_SECCSR1, RT2560_KICK_ENCRYPT);
1902
1903 return 0;
1904}
1905
1906static void
feb94d24 1907rt2560_start_locked(struct ifnet *ifp)
5fdff524
SZ
1908{
1909 struct rt2560_softc *sc = ifp->if_softc;
feb94d24 1910 struct mbuf *m;
5fdff524
SZ
1911 struct ieee80211_node *ni;
1912
5fdff524 1913 for (;;) {
ac9843a1 1914 m = ifq_dequeue(&ifp->if_snd);
feb94d24
RP
1915 if (m == NULL)
1916 break;
1917 if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) {
2d6b4a73 1918 ifq_prepend(&ifp->if_snd, m);
9ed293e0 1919 ifq_set_oactive(&ifp->if_snd);
feb94d24
RP
1920 sc->sc_flags |= RT2560_F_DATA_OACTIVE;
1921 break;
1922 }
1923 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1924 if (rt2560_tx_data(sc, m, ni) != 0) {
1925 ieee80211_free_node(ni);
d40991ef 1926 IFNET_STAT_INC(ifp, oerrors, 1);
feb94d24 1927 break;
5fdff524
SZ
1928 }
1929
1930 sc->sc_tx_timer = 5;
5fdff524
SZ
1931 }
1932}
1933
1934static void
f0a26983 1935rt2560_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
5fdff524 1936{
f0a26983 1937 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
feb94d24 1938 rt2560_start_locked(ifp);
5fdff524
SZ
1939}
1940
feb94d24 1941static void
d8235d53 1942rt2560_watchdog_callout(void *arg)
5fdff524 1943{
feb94d24
RP
1944 struct rt2560_softc *sc = arg;
1945 struct ifnet *ifp = sc->sc_ifp;
5fdff524 1946
feb94d24 1947 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running"));
5fdff524 1948
feb94d24
RP
1949 if (sc->sc_invalid) /* card ejected */
1950 return;
1951
1952 rt2560_encryption_intr(sc);
1953 rt2560_tx_intr(sc);
1954
1955 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1956 if_printf(ifp, "device timeout\n");
1957 rt2560_init_locked(sc);
d40991ef 1958 IFNET_STAT_INC(ifp, oerrors, 1);
feb94d24
RP
1959 /* NB: callout is reset in rt2560_init() */
1960 return;
1961 }
d8235d53 1962 callout_reset(&sc->watchdog_ch, hz, rt2560_watchdog_callout, sc);
5fdff524
SZ
1963}
1964
1965static int
feb94d24 1966rt2560_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred)
5fdff524
SZ
1967{
1968 struct rt2560_softc *sc = ifp->if_softc;
feb94d24
RP
1969 struct ieee80211com *ic = ifp->if_l2com;
1970 struct ifreq *ifr = (struct ifreq *) data;
1971 int error = 0, startall = 0;
5fdff524
SZ
1972
1973 switch (cmd) {
1974 case SIOCSIFFLAGS:
1975 if (ifp->if_flags & IFF_UP) {
feb94d24
RP
1976 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1977 rt2560_init_locked(sc);
1978 startall = 1;
1979 } else
1980 rt2560_update_promisc(ifp);
5fdff524
SZ
1981 } else {
1982 if (ifp->if_flags & IFF_RUNNING)
feb94d24 1983 rt2560_stop_locked(sc);
5fdff524 1984 }
feb94d24
RP
1985 if (startall)
1986 ieee80211_start_all(ic);
1987 break;
1988 case SIOCGIFMEDIA:
1989 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1990 break;
1991 case SIOCGIFADDR:
1992 error = ether_ioctl(ifp, cmd, data);
5fdff524 1993 break;
5fdff524 1994 default:
feb94d24
RP
1995 error = EINVAL;
1996 break;
5fdff524 1997 }
5fdff524
SZ
1998 return error;
1999}
2000
2001static void
2002rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
2003{
2004 uint32_t tmp;
2005 int ntries;
2006
2007 for (ntries = 0; ntries < 100; ntries++) {
2008 if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY))
2009 break;
2010 DELAY(1);
2011 }
2012 if (ntries == 100) {
2013 device_printf(sc->sc_dev, "could not write to BBP\n");
2014 return;
2015 }
2016
2017 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
2018 RAL_WRITE(sc, RT2560_BBPCSR, tmp);
2019
feb94d24 2020 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
5fdff524
SZ
2021}
2022
2023static uint8_t
2024rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)
2025{
2026 uint32_t val;
2027 int ntries;
2028
dd8ea05f
SZ
2029 for (ntries = 0; ntries < 100; ntries++) {
2030 if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY))
2031 break;
2032 DELAY(1);
2033 }
2034 if (ntries == 100) {
2035 device_printf(sc->sc_dev, "could not read from BBP\n");
2036 return 0;
2037 }
2038
5fdff524
SZ
2039 val = RT2560_BBP_BUSY | reg << 8;
2040 RAL_WRITE(sc, RT2560_BBPCSR, val);
2041
2042 for (ntries = 0; ntries < 100; ntries++) {
2043 val = RAL_READ(sc, RT2560_BBPCSR);
2044 if (!(val & RT2560_BBP_BUSY))
2045 return val & 0xff;
2046 DELAY(1);
2047 }
2048
2049 device_printf(sc->sc_dev, "could not read from BBP\n");
2050 return 0;
2051}
2052
2053static void
2054rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
2055{
2056 uint32_t tmp;
2057 int ntries;
2058
2059 for (ntries = 0; ntries < 100; ntries++) {
2060 if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY))
2061 break;
2062 DELAY(1);
2063 }
2064 if (ntries == 100) {
2065 device_printf(sc->sc_dev, "could not write to RF\n");
2066 return;
2067 }
2068
2069 tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
2070 (reg & 0x3);
2071 RAL_WRITE(sc, RT2560_RFCSR, tmp);
2072
2073 /* remember last written value in sc */
2074 sc->rf_regs[reg] = val;
2075
feb94d24 2076 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
5fdff524
SZ
2077}
2078
2079static void
2080rt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c)
2081{
feb94d24
RP
2082 struct ifnet *ifp = sc->sc_ifp;
2083 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
2084 uint8_t power, tmp;
2085 u_int i, chan;
2086
2087 chan = ieee80211_chan2ieee(ic, c);
feb94d24 2088 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan));
5fdff524
SZ
2089
2090 if (IEEE80211_IS_CHAN_2GHZ(c))
feb94d24 2091 power = min(sc->txpow[chan - 1], 31);
de0a85ba 2092 else
feb94d24 2093 power = 31;
de0a85ba 2094
feb94d24
RP
2095 /* adjust txpower using ifconfig settings */
2096 power -= (100 - ic->ic_txpowlimit) / 8;
5fdff524 2097
feb94d24 2098 DPRINTFN(sc, 2, "setting channel to %u, txpower to %u\n", chan, power);
5fdff524
SZ
2099
2100 switch (sc->rf_rev) {
2101 case RT2560_RF_2522:
2102 rt2560_rf_write(sc, RAL_RF1, 0x00814);
2103 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2522_r2[chan - 1]);
2104 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
2105 break;
2106
2107 case RT2560_RF_2523:
2108 rt2560_rf_write(sc, RAL_RF1, 0x08804);
2109 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2523_r2[chan - 1]);
2110 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
2111 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
2112 break;
2113
2114 case RT2560_RF_2524:
2115 rt2560_rf_write(sc, RAL_RF1, 0x0c808);
2116 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2524_r2[chan - 1]);
2117 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
2118 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
2119 break;
2120
2121 case RT2560_RF_2525:
2122 rt2560_rf_write(sc, RAL_RF1, 0x08808);
2123 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_hi_r2[chan - 1]);
2124 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
2125 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
2126
2127 rt2560_rf_write(sc, RAL_RF1, 0x08808);
2128 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_r2[chan - 1]);
2129 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
2130 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
2131 break;
2132
2133 case RT2560_RF_2525E:
2134 rt2560_rf_write(sc, RAL_RF1, 0x08808);
2135 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525e_r2[chan - 1]);
2136 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
2137 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
2138 break;
2139
2140 case RT2560_RF_2526:
2141 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_hi_r2[chan - 1]);
2142 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
2143 rt2560_rf_write(sc, RAL_RF1, 0x08804);
2144
2145 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_r2[chan - 1]);
2146 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
2147 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
2148 break;
2149
2150 /* dual-band RF */
2151 case RT2560_RF_5222:
2152 for (i = 0; rt2560_rf5222[i].chan != chan; i++);
2153
2154 rt2560_rf_write(sc, RAL_RF1, rt2560_rf5222[i].r1);
2155 rt2560_rf_write(sc, RAL_RF2, rt2560_rf5222[i].r2);
2156 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
2157 rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4);
2158 break;
feb94d24
RP
2159 default:
2160 kprintf("unknown ral rev=%d\n", sc->rf_rev);
5fdff524
SZ
2161 }
2162
feb94d24
RP
2163 /* XXX */
2164 if ((ic->ic_flags & IEEE80211_F_SCAN) == 0) {
5fdff524
SZ
2165 /* set Japan filter bit for channel 14 */
2166 tmp = rt2560_bbp_read(sc, 70);
2167
2168 tmp &= ~RT2560_JAPAN_FILTER;
2169 if (chan == 14)
2170 tmp |= RT2560_JAPAN_FILTER;
2171
2172 rt2560_bbp_write(sc, 70, tmp);
2173
2174 /* clear CRC errors */
2175 RAL_READ(sc, RT2560_CNT0);
2176 }
feb94d24
RP
2177}
2178
2179static void
2180rt2560_set_channel(struct ieee80211com *ic)
2181{
2182 struct ifnet *ifp = ic->ic_ifp;
2183 struct rt2560_softc *sc = ifp->if_softc;
2184
feb94d24 2185 rt2560_set_chan(sc, ic->ic_curchan);
feb94d24
RP
2186
2187}
2188
2189#if 0
2190/*
2191 * Disable RF auto-tuning.
2192 */
2193static void
2194rt2560_disable_rf_tune(struct rt2560_softc *sc)
2195{
2196 uint32_t tmp;
2197
2198 if (sc->rf_rev != RT2560_RF_2523) {
2199 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
2200 rt2560_rf_write(sc, RAL_RF1, tmp);
2201 }
322b19a8 2202
feb94d24
RP
2203 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
2204 rt2560_rf_write(sc, RAL_RF3, tmp);
2205
2206 DPRINTFN(sc, 2, "%s", "disabling RF autotune\n");
5fdff524 2207}
feb94d24 2208#endif
5fdff524 2209
5fdff524
SZ
2210/*
2211 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF
2212 * synchronization.
2213 */
2214static void
2215rt2560_enable_tsf_sync(struct rt2560_softc *sc)
2216{
feb94d24
RP
2217 struct ifnet *ifp = sc->sc_ifp;
2218 struct ieee80211com *ic = ifp->if_l2com;
2219 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
5fdff524
SZ
2220 uint16_t logcwmin, preload;
2221 uint32_t tmp;
2222
2223 /* first, disable TSF synchronization */
2224 RAL_WRITE(sc, RT2560_CSR14, 0);
2225
feb94d24 2226 tmp = 16 * vap->iv_bss->ni_intval;
5fdff524
SZ
2227 RAL_WRITE(sc, RT2560_CSR12, tmp);
2228
2229 RAL_WRITE(sc, RT2560_CSR13, 0);
2230
2231 logcwmin = 5;
feb94d24 2232 preload = (vap->iv_opmode == IEEE80211_M_STA) ? 384 : 1024;
5fdff524
SZ
2233 tmp = logcwmin << 16 | preload;
2234 RAL_WRITE(sc, RT2560_BCNOCSR, tmp);
2235
2236 /* finally, enable TSF synchronization */
2237 tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN;
2238 if (ic->ic_opmode == IEEE80211_M_STA)
2239 tmp |= RT2560_ENABLE_TSF_SYNC(1);
2240 else
2241 tmp |= RT2560_ENABLE_TSF_SYNC(2) |
2242 RT2560_ENABLE_BEACON_GENERATOR;
2243 RAL_WRITE(sc, RT2560_CSR14, tmp);
2244
feb94d24
RP
2245 DPRINTF(sc, "%s", "enabling TSF synchronization\n");
2246}
2247
2248static void
2249rt2560_enable_tsf(struct rt2560_softc *sc)
2250{
2251 RAL_WRITE(sc, RT2560_CSR14, 0);
2252 RAL_WRITE(sc, RT2560_CSR14,
2253 RT2560_ENABLE_TSF_SYNC(2) | RT2560_ENABLE_TSF);
5fdff524
SZ
2254}
2255
2256static void
2257rt2560_update_plcp(struct rt2560_softc *sc)
2258{
feb94d24
RP
2259 struct ifnet *ifp = sc->sc_ifp;
2260 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
2261
2262 /* no short preamble for 1Mbps */
2263 RAL_WRITE(sc, RT2560_PLCP1MCSR, 0x00700400);
2264
2265 if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) {
2266 /* values taken from the reference driver */
2267 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380401);
2268 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x00150402);
2269 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b8403);
2270 } else {
2271 /* same values as above or'ed 0x8 */
2272 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380409);
2273 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x0015040a);
2274 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b840b);
2275 }
2276
feb94d24
RP
2277 DPRINTF(sc, "updating PLCP for %s preamble\n",
2278 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long");
5fdff524
SZ
2279}
2280
2281/*
2282 * This function can be called by ieee80211_set_shortslottime(). Refer to
2283 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed.
2284 */
2285static void
2286rt2560_update_slot(struct ifnet *ifp)
2287{
2288 struct rt2560_softc *sc = ifp->if_softc;
feb94d24 2289 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
2290 uint8_t slottime;
2291 uint16_t tx_sifs, tx_pifs, tx_difs, eifs;
2292 uint32_t tmp;
2293
feb94d24 2294#ifndef FORCE_SLOTTIME
5fdff524 2295 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
5179c63f
SZ
2296#else
2297 /*
2298 * Setting slot time according to "short slot time" capability
2299 * in beacon/probe_resp seems to cause problem to acknowledge
2300 * certain AP's data frames transimitted at CCK/DS rates: the
2301 * problematic AP keeps retransmitting data frames, probably
2302 * because MAC level acks are not received by hardware.
2303 * So we cheat a little bit here by claiming we are capable of
2304 * "short slot time" but setting hardware slot time to the normal
2305 * slot time. ral(4) does not seem to have trouble to receive
2306 * frames transmitted using short slot time even if hardware
2307 * slot time is set to normal slot time. If we didn't use this
2308 * trick, we would have to claim that short slot time is not
feb94d24 2309 * supported; this would give relative poor RX performance
5179c63f
SZ
2310 * (-1Mb~-2Mb lower) and the _whole_ BSS would stop using short
2311 * slot time.
2312 */
feb94d24 2313 slottime = 20;
5179c63f 2314#endif
5fdff524
SZ
2315
2316 /* update the MAC slot boundaries */
feb94d24 2317 tx_sifs = RAL_SIFS - RT2560_TXRX_TURNAROUND;
5fdff524
SZ
2318 tx_pifs = tx_sifs + slottime;
2319 tx_difs = tx_sifs + 2 * slottime;
2320 eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60;
2321
2322 tmp = RAL_READ(sc, RT2560_CSR11);
2323 tmp = (tmp & ~0x1f00) | slottime << 8;
2324 RAL_WRITE(sc, RT2560_CSR11, tmp);
2325
2326 tmp = tx_pifs << 16 | tx_sifs;
2327 RAL_WRITE(sc, RT2560_CSR18, tmp);
2328
2329 tmp = eifs << 16 | tx_difs;
2330 RAL_WRITE(sc, RT2560_CSR19, tmp);
2331
feb94d24 2332 DPRINTF(sc, "setting slottime to %uus\n", slottime);
5fdff524
SZ
2333}
2334
2335static void
2336rt2560_set_basicrates(struct rt2560_softc *sc)
2337{
feb94d24
RP
2338 struct ifnet *ifp = sc->sc_ifp;
2339 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
2340
2341 /* update basic rate set */
2342 if (ic->ic_curmode == IEEE80211_MODE_11B) {
2343 /* 11b basic rates: 1, 2Mbps */
2344 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x3);
2345 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
2346 /* 11a basic rates: 6, 12, 24Mbps */
2347 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x150);
2348 } else {
2349 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */
2350 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x15f);
2351 }
2352}
2353
2354static void
2355rt2560_update_led(struct rt2560_softc *sc, int led1, int led2)
2356{
2357 uint32_t tmp;
2358
2359 /* set ON period to 70ms and OFF period to 30ms */
2360 tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30;
2361 RAL_WRITE(sc, RT2560_LEDCSR, tmp);
2362}
2363
2364static void
feb94d24 2365rt2560_set_bssid(struct rt2560_softc *sc, const uint8_t *bssid)
5fdff524
SZ
2366{
2367 uint32_t tmp;
1e290df3 2368 char ethstr[ETHER_ADDRSTRLEN + 1];
5fdff524
SZ
2369
2370 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
2371 RAL_WRITE(sc, RT2560_CSR5, tmp);
2372
2373 tmp = bssid[4] | bssid[5] << 8;
2374 RAL_WRITE(sc, RT2560_CSR6, tmp);
2375
1e290df3 2376 DPRINTF(sc, "setting BSSID to %s\n", kether_ntoa(bssid, ethstr));
5fdff524
SZ
2377}
2378
2379static void
2380rt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr)
2381{
2382 uint32_t tmp;
1e290df3 2383 char ethstr[ETHER_ADDRSTRLEN + 1];
5fdff524
SZ
2384
2385 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2386 RAL_WRITE(sc, RT2560_CSR3, tmp);
2387
2388 tmp = addr[4] | addr[5] << 8;
2389 RAL_WRITE(sc, RT2560_CSR4, tmp);
2390
1e290df3 2391 DPRINTF(sc, "setting MAC address to %s\n", kether_ntoa(addr, ethstr));
5fdff524
SZ
2392}
2393
2394static void
2395rt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr)
2396{
2397 uint32_t tmp;
2398
2399 tmp = RAL_READ(sc, RT2560_CSR3);
2400 addr[0] = tmp & 0xff;
2401 addr[1] = (tmp >> 8) & 0xff;
2402 addr[2] = (tmp >> 16) & 0xff;
2403 addr[3] = (tmp >> 24);
2404
2405 tmp = RAL_READ(sc, RT2560_CSR4);
2406 addr[4] = tmp & 0xff;
2407 addr[5] = (tmp >> 8) & 0xff;
2408}
2409
2410static void
feb94d24 2411rt2560_update_promisc(struct ifnet *ifp)
5fdff524 2412{
feb94d24 2413 struct rt2560_softc *sc = ifp->if_softc;
5fdff524
SZ
2414 uint32_t tmp;
2415
2416 tmp = RAL_READ(sc, RT2560_RXCSR0);
2417
2418 tmp &= ~RT2560_DROP_NOT_TO_ME;
2419 if (!(ifp->if_flags & IFF_PROMISC))
2420 tmp |= RT2560_DROP_NOT_TO_ME;
2421
2422 RAL_WRITE(sc, RT2560_RXCSR0, tmp);
2423
feb94d24
RP
2424 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ?
2425 "entering" : "leaving");
5fdff524
SZ
2426}
2427
2428static const char *
2429rt2560_get_rf(int rev)
2430{
2431 switch (rev) {
2432 case RT2560_RF_2522: return "RT2522";
2433 case RT2560_RF_2523: return "RT2523";
2434 case RT2560_RF_2524: return "RT2524";
2435 case RT2560_RF_2525: return "RT2525";
2436 case RT2560_RF_2525E: return "RT2525e";
2437 case RT2560_RF_2526: return "RT2526";
2438 case RT2560_RF_5222: return "RT5222";
2439 default: return "unknown";
2440 }
2441}
2442
2443static void
d491e551 2444rt2560_read_config(struct rt2560_softc *sc)
5fdff524
SZ
2445{
2446 uint16_t val;
feb94d24 2447 int i;
5fdff524
SZ
2448
2449 val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0);
2450 sc->rf_rev = (val >> 11) & 0x7;
2451 sc->hw_radio = (val >> 10) & 0x1;
2452 sc->led_mode = (val >> 6) & 0x7;
2453 sc->rx_ant = (val >> 4) & 0x3;
2454 sc->tx_ant = (val >> 2) & 0x3;
2455 sc->nb_ant = val & 0x3;
2456
2457 /* read default values for BBP registers */
2458 for (i = 0; i < 16; i++) {
2459 val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i);
feb94d24 2460 if (val == 0 || val == 0xffff)
4601b177 2461 continue;
feb94d24 2462
5fdff524
SZ
2463 sc->bbp_prom[i].reg = val >> 8;
2464 sc->bbp_prom[i].val = val & 0xff;
2465 }
2466
2467 /* read Tx power for all b/g channels */
2468 for (i = 0; i < 14 / 2; i++) {
2469 val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i);
e1a9236e
SZ
2470 sc->txpow[i * 2] = val & 0xff;
2471 sc->txpow[i * 2 + 1] = val >> 8;
5fdff524 2472 }
d491e551 2473 for (i = 0; i < 14; ++i) {
2da757be 2474 if (sc->txpow[i] > 31)
feb94d24 2475 sc->txpow[i] = 24;
d491e551 2476 }
a5c68736
SZ
2477
2478 val = rt2560_eeprom_read(sc, RT2560_EEPROM_CALIBRATE);
35ac1c5e 2479 if ((val & 0xff) == 0xff)
a5c68736
SZ
2480 sc->rssi_corr = RT2560_DEFAULT_RSSI_CORR;
2481 else
35ac1c5e 2482 sc->rssi_corr = val & 0xff;
feb94d24
RP
2483 DPRINTF(sc, "rssi correction %d, calibrate 0x%02x\n",
2484 sc->rssi_corr, val);
2485}
4601b177 2486
feb94d24
RP
2487
2488static void
2489rt2560_scan_start(struct ieee80211com *ic)
2490{
2491 struct ifnet *ifp = ic->ic_ifp;
2492 struct rt2560_softc *sc = ifp->if_softc;
2493
2494 /* abort TSF synchronization */
2495 RAL_WRITE(sc, RT2560_CSR14, 0);
2496 rt2560_set_bssid(sc, ifp->if_broadcastaddr);
2497}
2498
2499static void
2500rt2560_scan_end(struct ieee80211com *ic)
2501{
2502 struct ifnet *ifp = ic->ic_ifp;
2503 struct rt2560_softc *sc = ifp->if_softc;
2504 struct ieee80211vap *vap = ic->ic_scan->ss_vap;
2505
2506 rt2560_enable_tsf_sync(sc);
2507 /* XXX keep local copy */
2508 rt2560_set_bssid(sc, vap->iv_bss->ni_bssid);
5fdff524
SZ
2509}
2510
2511static int
2512rt2560_bbp_init(struct rt2560_softc *sc)
2513{
2514#define N(a) (sizeof (a) / sizeof ((a)[0]))
2515 int i, ntries;
2516
2517 /* wait for BBP to be ready */
2518 for (ntries = 0; ntries < 100; ntries++) {
2519 if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0)
2520 break;
2521 DELAY(1);
2522 }
2523 if (ntries == 100) {
2524 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2525 return EIO;
2526 }
2527
2528 /* initialize BBP registers to default values */
2529 for (i = 0; i < N(rt2560_def_bbp); i++) {
2530 rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,
2531 rt2560_def_bbp[i].val);
2532 }
dd8ea05f 2533
5fdff524
SZ
2534 /* initialize BBP registers to values stored in EEPROM */
2535 for (i = 0; i < 16; i++) {
2da757be
SZ
2536 if (sc->bbp_prom[i].reg == 0 && sc->bbp_prom[i].val == 0)
2537 break;
5fdff524
SZ
2538 rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2539 }
feb94d24 2540 rt2560_bbp_write(sc, 17, 0x48); /* XXX restore bbp17 */
5fdff524
SZ
2541
2542 return 0;
2543#undef N
2544}
2545
2546static void
2547rt2560_set_txantenna(struct rt2560_softc *sc, int antenna)
2548{
2549 uint32_t tmp;
2550 uint8_t tx;
2551
2552 tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK;
2553 if (antenna == 1)
2554 tx |= RT2560_BBP_ANTA;
2555 else if (antenna == 2)
2556 tx |= RT2560_BBP_ANTB;
2557 else
2558 tx |= RT2560_BBP_DIVERSITY;
2559
feb94d24
RP
2560 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */
2561 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 ||
2562 sc->rf_rev == RT2560_RF_5222)
5fdff524
SZ
2563 tx |= RT2560_BBP_FLIPIQ;
2564
2565 rt2560_bbp_write(sc, RT2560_BBP_TX, tx);
2566
2567 /* update values for CCK and OFDM in BBPCSR1 */
2568 tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007;
2569 tmp |= (tx & 0x7) << 16 | (tx & 0x7);
2570 RAL_WRITE(sc, RT2560_BBPCSR1, tmp);
2571}
2572
2573static void
2574rt2560_set_rxantenna(struct rt2560_softc *sc, int antenna)
2575{
2576 uint8_t rx;
2577
2578 rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK;
2579 if (antenna == 1)
2580 rx |= RT2560_BBP_ANTA;
2581 else if (antenna == 2)
2582 rx |= RT2560_BBP_ANTB;
2583 else
2584 rx |= RT2560_BBP_DIVERSITY;
2585
feb94d24
RP
2586 /* need to force no I/Q flip for RF 2525e and 2526 */
2587 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526)
5fdff524
SZ
2588 rx &= ~RT2560_BBP_FLIPIQ;
2589
2590 rt2560_bbp_write(sc, RT2560_BBP_RX, rx);
2591}
2592
2593static void
feb94d24 2594rt2560_init_locked(struct rt2560_softc *sc)
5fdff524
SZ
2595{
2596#define N(a) (sizeof (a) / sizeof ((a)[0]))
feb94d24
RP
2597 struct ifnet *ifp = sc->sc_ifp;
2598 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
2599 uint32_t tmp;
2600 int i;
2601
feb94d24 2602 rt2560_stop_locked(sc);
5fdff524
SZ
2603
2604 /* setup tx rings */
2605 tmp = RT2560_PRIO_RING_COUNT << 24 |
2606 RT2560_ATIM_RING_COUNT << 16 |
2607 RT2560_TX_RING_COUNT << 8 |
2608 RT2560_TX_DESC_SIZE;
2609
2610 /* rings must be initialized in this exact order */
2611 RAL_WRITE(sc, RT2560_TXCSR2, tmp);
2612 RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr);
2613 RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr);
2614 RAL_WRITE(sc, RT2560_TXCSR4, sc->atimq.physaddr);
2615 RAL_WRITE(sc, RT2560_TXCSR6, sc->bcnq.physaddr);
2616
2617 /* setup rx ring */
2618 tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE;
2619
2620 RAL_WRITE(sc, RT2560_RXCSR1, tmp);
2621 RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr);
2622
2623 /* initialize MAC registers to default values */
2624 for (i = 0; i < N(rt2560_def_mac); i++)
2625 RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
2626
feb94d24 2627 rt2560_set_macaddr(sc, IF_LLADDR(ifp));
5fdff524
SZ
2628
2629 /* set basic rate set (will be updated later) */
2630 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x153);
2631
5fdff524
SZ
2632 rt2560_update_slot(ifp);
2633 rt2560_update_plcp(sc);
2634 rt2560_update_led(sc, 0, 0);
2635
2636 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC);
2637 RAL_WRITE(sc, RT2560_CSR1, RT2560_HOST_READY);
2638
2639 if (rt2560_bbp_init(sc) != 0) {
2640 rt2560_stop(sc);
2641 return;
2642 }
2643
dd8ea05f
SZ
2644 rt2560_set_txantenna(sc, sc->tx_ant);
2645 rt2560_set_rxantenna(sc, sc->rx_ant);
2646
5fdff524
SZ
2647 /* set default BSS channel */
2648 rt2560_set_chan(sc, ic->ic_curchan);
2649
2650 /* kick Rx */
2651 tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR;
2652 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2653 tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR;
feb94d24
RP
2654 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
2655 ic->ic_opmode != IEEE80211_M_MBSS)
5fdff524
SZ
2656 tmp |= RT2560_DROP_TODS;
2657 if (!(ifp->if_flags & IFF_PROMISC))
2658 tmp |= RT2560_DROP_NOT_TO_ME;
2659 }
2660 RAL_WRITE(sc, RT2560_RXCSR0, tmp);
2661
2662 /* clear old FCS and Rx FIFO errors */
2663 RAL_READ(sc, RT2560_CNT0);
2664 RAL_READ(sc, RT2560_CNT4);
2665
2666 /* clear any pending interrupts */
2667 RAL_WRITE(sc, RT2560_CSR7, 0xffffffff);
2668
2669 /* enable interrupts */
2670 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK);
2671
9ed293e0 2672 ifq_clr_oactive(&ifp->if_snd);
5fdff524
SZ
2673 ifp->if_flags |= IFF_RUNNING;
2674
d8235d53 2675 callout_reset(&sc->watchdog_ch, hz, rt2560_watchdog_callout, sc);
5fdff524
SZ
2676#undef N
2677}
2678
5fdff524 2679static void
feb94d24 2680rt2560_init(void *priv)
5fdff524 2681{
feb94d24
RP
2682 struct rt2560_softc *sc = priv;
2683 struct ifnet *ifp = sc->sc_ifp;
2684 struct ieee80211com *ic = ifp->if_l2com;
5fdff524 2685
feb94d24 2686 rt2560_init_locked(sc);
21028056 2687
feb94d24
RP
2688 if (ifp->if_flags & IFF_RUNNING)
2689 ieee80211_start_all(ic); /* start all vap's */
21028056 2690}
2da757be
SZ
2691
2692static void
feb94d24 2693rt2560_stop_locked(struct rt2560_softc *sc)
2da757be 2694{
feb94d24
RP
2695 struct ifnet *ifp = sc->sc_ifp;
2696 volatile int *flags = &sc->sc_flags;
2da757be 2697
feb94d24 2698 while (*flags & RT2560_F_INPUT_RUNNING)
d8235d53 2699 zsleep(sc, &wlan_global_serializer, 0, "ralrunning", hz/10);
2da757be 2700
feb94d24
RP
2701 callout_stop(&sc->watchdog_ch);
2702 sc->sc_tx_timer = 0;
2da757be 2703
feb94d24 2704 if (ifp->if_flags & IFF_RUNNING) {
9ed293e0
SZ
2705 ifp->if_flags &= ~IFF_RUNNING;
2706 ifq_clr_oactive(&ifp->if_snd);
feb94d24
RP
2707
2708 /* abort Tx */
2709 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX);
2710
2711 /* disable Rx */
2712 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX);
2713
2714 /* reset ASIC (imply reset BBP) */
2715 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC);
2716 RAL_WRITE(sc, RT2560_CSR1, 0);
2717
2718 /* disable interrupts */
2719 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff);
2720
2721 /* reset Tx and Rx rings */
2722 rt2560_reset_tx_ring(sc, &sc->txq);
2723 rt2560_reset_tx_ring(sc, &sc->atimq);
2724 rt2560_reset_tx_ring(sc, &sc->prioq);
2725 rt2560_reset_tx_ring(sc, &sc->bcnq);
2726 rt2560_reset_rx_ring(sc, &sc->rxq);
2727 }
2728 sc->sc_flags &= ~(RT2560_F_PRIO_OACTIVE | RT2560_F_DATA_OACTIVE);
2da757be
SZ
2729}
2730
feb94d24
RP
2731void
2732rt2560_stop(void *arg)
2da757be 2733{
feb94d24 2734 struct rt2560_softc *sc = arg;
2da757be 2735
feb94d24 2736 rt2560_stop_locked(sc);
2da757be 2737}
33882926
SZ
2738
2739static int
feb94d24
RP
2740rt2560_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2741 const struct ieee80211_bpf_params *params)
33882926 2742{
feb94d24
RP
2743 struct ieee80211com *ic = ni->ni_ic;
2744 struct ifnet *ifp = ic->ic_ifp;
2745 struct rt2560_softc *sc = ifp->if_softc;
33882926 2746
feb94d24
RP
2747 /* prevent management frames from being sent if we're not ready */
2748 if (!(ifp->if_flags & IFF_RUNNING)) {
feb94d24
RP
2749 m_freem(m);
2750 ieee80211_free_node(ni);
2751 return ENETDOWN;
2752 }
2753 if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) {
9ed293e0 2754 ifq_set_oactive(&ifp->if_snd);
feb94d24 2755 sc->sc_flags |= RT2560_F_PRIO_OACTIVE;
feb94d24
RP
2756 m_freem(m);
2757 ieee80211_free_node(ni);
2758 return ENOBUFS; /* XXX */
33882926
SZ
2759 }
2760
d40991ef 2761 IFNET_STAT_INC(ifp, opackets, 1);
feb94d24
RP
2762
2763 if (params == NULL) {
33882926 2764 /*
feb94d24
RP
2765 * Legacy path; interpret frame contents to decide
2766 * precisely how to send the frame.
33882926 2767 */
feb94d24
RP
2768 if (rt2560_tx_mgt(sc, m, ni) != 0)
2769 goto bad;
2770 } else {
2771 /*
2772 * Caller supplied explicit parameters to use in
2773 * sending the frame.
2774 */
2775 if (rt2560_tx_raw(sc, m, ni, params))
2776 goto bad;
33882926 2777 }
feb94d24
RP
2778 sc->sc_tx_timer = 5;
2779
feb94d24
RP
2780 return 0;
2781bad:
d40991ef 2782 IFNET_STAT_INC(ifp, oerrors, 1);
feb94d24 2783 ieee80211_free_node(ni);
feb94d24 2784 return EIO; /* XXX */
33882926 2785}