igb: Remove no longer referenced code
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
CommitLineData
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1/*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "opt_polling.h"
8d6600da 33#include "opt_igb.h"
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34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/interrupt.h>
39#include <sys/kernel.h>
40#include <sys/malloc.h>
41#include <sys/mbuf.h>
42#include <sys/proc.h>
43#include <sys/rman.h>
44#include <sys/serialize.h>
45#include <sys/serialize2.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48#include <sys/sysctl.h>
49#include <sys/systm.h>
50
51#include <net/bpf.h>
52#include <net/ethernet.h>
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#include <net/ifq_var.h>
58#include <net/toeplitz.h>
59#include <net/toeplitz2.h>
60#include <net/vlan/if_vlan_var.h>
61#include <net/vlan/if_vlan_ether.h>
62#include <net/if_poll.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/ip.h>
67#include <netinet/tcp.h>
68#include <netinet/udp.h>
69
70#include <bus/pci/pcivar.h>
71#include <bus/pci/pcireg.h>
72
73#include <dev/netif/ig_hal/e1000_api.h>
74#include <dev/netif/ig_hal/e1000_82575.h>
75#include <dev/netif/igb/if_igb.h>
76
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77#ifdef IGB_RSS_DEBUG
78#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79do { \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82} while (0)
83#else /* !IGB_RSS_DEBUG */
84#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85#endif /* IGB_RSS_DEBUG */
86
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87#define IGB_NAME "Intel(R) PRO/1000 "
88#define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90#define IGB_DEVICE_NULL { 0, 0, NULL }
91
92static struct igb_device {
93 uint16_t vid;
94 uint16_t did;
95 const char *desc;
96} igb_devices[] = {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
123 IGB_DEVICE(I350_VF),
124
125 /* required last entry */
126 IGB_DEVICE_NULL
127};
128
129static int igb_probe(device_t);
130static int igb_attach(device_t);
131static int igb_detach(device_t);
132static int igb_shutdown(device_t);
133static int igb_suspend(device_t);
134static int igb_resume(device_t);
135
136static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137static void igb_setup_ifp(struct igb_softc *);
48faa653 138static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
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139static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
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141static void igb_add_sysctl(struct igb_softc *);
142static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
9c0ecdcc 143static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
b6220144 144static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
9c0ecdcc 145static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
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146
147static void igb_vf_init_stats(struct igb_softc *);
148static void igb_reset(struct igb_softc *);
149static void igb_update_stats_counters(struct igb_softc *);
150static void igb_update_vf_stats_counters(struct igb_softc *);
151static void igb_update_link_status(struct igb_softc *);
152static void igb_init_tx_unit(struct igb_softc *);
153static void igb_init_rx_unit(struct igb_softc *);
154
155static void igb_set_vlan(struct igb_softc *);
156static void igb_set_multi(struct igb_softc *);
157static void igb_set_promisc(struct igb_softc *);
158static void igb_disable_promisc(struct igb_softc *);
159
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160static int igb_alloc_rings(struct igb_softc *);
161static void igb_free_rings(struct igb_softc *);
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162static int igb_create_tx_ring(struct igb_tx_ring *);
163static int igb_create_rx_ring(struct igb_rx_ring *);
164static void igb_free_tx_ring(struct igb_tx_ring *);
165static void igb_free_rx_ring(struct igb_rx_ring *);
166static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
167static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
168static void igb_init_tx_ring(struct igb_tx_ring *);
169static int igb_init_rx_ring(struct igb_rx_ring *);
170static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
171static int igb_encap(struct igb_tx_ring *, struct mbuf **);
172
173static void igb_stop(struct igb_softc *);
174static void igb_init(void *);
175static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
176static void igb_media_status(struct ifnet *, struct ifmediareq *);
177static int igb_media_change(struct ifnet *);
178static void igb_timer(void *);
179static void igb_watchdog(struct ifnet *);
180static void igb_start(struct ifnet *);
181#ifdef DEVICE_POLLING
182static void igb_poll(struct ifnet *, enum poll_cmd, int);
183#endif
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184static void igb_serialize(struct ifnet *, enum ifnet_serialize);
185static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
186static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
187#ifdef INVARIANTS
188static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
189 boolean_t);
190#endif
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191
192static void igb_intr(void *);
9c0ecdcc 193static void igb_intr_shared(void *);
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194static void igb_rxeof(struct igb_rx_ring *, int);
195static void igb_txeof(struct igb_tx_ring *);
9c0ecdcc 196static void igb_set_eitr(struct igb_softc *, int, int);
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197static void igb_enable_intr(struct igb_softc *);
198static void igb_disable_intr(struct igb_softc *);
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199static void igb_init_unshared_intr(struct igb_softc *);
200static void igb_init_intr(struct igb_softc *);
201static int igb_setup_intr(struct igb_softc *);
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202static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
203static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
be922da6 204static void igb_set_intr_mask(struct igb_softc *);
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205static int igb_alloc_intr(struct igb_softc *);
206static void igb_free_intr(struct igb_softc *);
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207static void igb_teardown_intr(struct igb_softc *);
208static void igb_msix_try_alloc(struct igb_softc *);
209static void igb_msix_free(struct igb_softc *, boolean_t);
210static int igb_msix_setup(struct igb_softc *);
211static void igb_msix_teardown(struct igb_softc *, int);
212static void igb_msix_rx(void *);
213static void igb_msix_tx(void *);
214static void igb_msix_status(void *);
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215
216/* Management and WOL Support */
217static void igb_get_mgmt(struct igb_softc *);
218static void igb_rel_mgmt(struct igb_softc *);
219static void igb_get_hw_control(struct igb_softc *);
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220static void igb_rel_hw_control(struct igb_softc *);
221static void igb_enable_wol(device_t);
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222
223static device_method_t igb_methods[] = {
224 /* Device interface */
225 DEVMETHOD(device_probe, igb_probe),
226 DEVMETHOD(device_attach, igb_attach),
227 DEVMETHOD(device_detach, igb_detach),
228 DEVMETHOD(device_shutdown, igb_shutdown),
229 DEVMETHOD(device_suspend, igb_suspend),
230 DEVMETHOD(device_resume, igb_resume),
231 { 0, 0 }
232};
233
234static driver_t igb_driver = {
235 "igb",
236 igb_methods,
237 sizeof(struct igb_softc),
238};
239
240static devclass_t igb_devclass;
241
242DECLARE_DUMMY_MODULE(if_igb);
243MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
244DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
245
246static int igb_rxd = IGB_DEFAULT_RXD;
247static int igb_txd = IGB_DEFAULT_TXD;
8d6600da 248static int igb_rxr = 0;
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249static int igb_msi_enable = 1;
250static int igb_msix_enable = 1;
251static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
252static int igb_fc_setting = e1000_fc_full;
253
254/*
255 * DMA Coalescing, only for i350 - default to off,
256 * this feature is for power savings
257 */
258static int igb_dma_coalesce = 0;
259
260TUNABLE_INT("hw.igb.rxd", &igb_rxd);
261TUNABLE_INT("hw.igb.txd", &igb_txd);
8d6600da 262TUNABLE_INT("hw.igb.rxr", &igb_rxr);
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263TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
264TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
265TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
266
267/* i350 specific */
268TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
269TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
270
271static __inline void
272igb_rxcsum(uint32_t staterr, struct mbuf *mp)
273{
274 /* Ignore Checksum bit is set */
275 if (staterr & E1000_RXD_STAT_IXSM)
276 return;
277
278 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
279 E1000_RXD_STAT_IPCS)
280 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
281
282 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
283 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
284 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
285 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
286 mp->m_pkthdr.csum_data = htons(0xffff);
287 }
288 }
289}
290
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291static __inline struct pktinfo *
292igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
293 uint32_t hash, uint32_t hashtype, uint32_t staterr)
294{
295 switch (hashtype) {
296 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
297 pi->pi_netisr = NETISR_IP;
298 pi->pi_flags = 0;
299 pi->pi_l3proto = IPPROTO_TCP;
300 break;
301
302 case E1000_RXDADV_RSSTYPE_IPV4:
303 if (staterr & E1000_RXD_STAT_IXSM)
304 return NULL;
305
306 if ((staterr &
307 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
308 E1000_RXD_STAT_TCPCS) {
309 pi->pi_netisr = NETISR_IP;
310 pi->pi_flags = 0;
311 pi->pi_l3proto = IPPROTO_UDP;
312 break;
313 }
314 /* FALL THROUGH */
315 default:
316 return NULL;
317 }
318
319 m->m_flags |= M_HASH;
320 m->m_pkthdr.hash = toeplitz_hash(hash);
321 return pi;
322}
323
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324static int
325igb_probe(device_t dev)
326{
327 const struct igb_device *d;
328 uint16_t vid, did;
329
330 vid = pci_get_vendor(dev);
331 did = pci_get_device(dev);
332
333 for (d = igb_devices; d->desc != NULL; ++d) {
334 if (vid == d->vid && did == d->did) {
335 device_set_desc(dev, d->desc);
336 return 0;
337 }
338 }
339 return ENXIO;
340}
341
342static int
343igb_attach(device_t dev)
344{
345 struct igb_softc *sc = device_get_softc(dev);
1f7e3916 346 uint16_t eeprom_data;
8d6600da 347 int error = 0, i, j, ring_max;
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348
349#ifdef notyet
350 /* SYSCTL stuff */
351 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
352 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
353 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
354 igb_sysctl_nvm_info, "I", "NVM Information");
355
356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
358 OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
359 &igb_enable_aim, 1, "Interrupt Moderation");
360
361 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
362 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
363 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
364 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
365#endif
366
367 callout_init_mp(&sc->timer);
9c0ecdcc 368 lwkt_serialize_init(&sc->main_serialize);
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369
370 sc->dev = sc->osdep.dev = dev;
371
372 /*
373 * Determine hardware and mac type
374 */
375 sc->hw.vendor_id = pci_get_vendor(dev);
376 sc->hw.device_id = pci_get_device(dev);
377 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
378 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
379 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
380
381 if (e1000_set_mac_type(&sc->hw))
382 return ENXIO;
383
384 /* Are we a VF device? */
385 if (sc->hw.mac.type == e1000_vfadapt ||
386 sc->hw.mac.type == e1000_vfadapt_i350)
387 sc->vf_ifp = 1;
388 else
389 sc->vf_ifp = 0;
390
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391 /*
392 * Configure total supported RX/TX ring count
393 */
394 switch (sc->hw.mac.type) {
395 case e1000_82575:
396 ring_max = IGB_MAX_RING_82575;
397 break;
398 case e1000_82580:
399 ring_max = IGB_MAX_RING_82580;
400 break;
401 case e1000_i350:
402 ring_max = IGB_MAX_RING_I350;
403 break;
404 case e1000_82576:
405 ring_max = IGB_MAX_RING_82576;
406 break;
407 default:
408 ring_max = IGB_MIN_RING;
409 break;
410 }
411 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
412 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
413#ifdef IGB_RSS_DEBUG
414 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
415#endif
416 sc->rx_ring_inuse = sc->rx_ring_cnt;
417 sc->tx_ring_cnt = 1; /* XXX */
418
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419 if (sc->hw.mac.type == e1000_82575)
420 sc->flags |= IGB_FLAG_TSO_IPLEN0;
421
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422 /* Enable bus mastering */
423 pci_enable_busmaster(dev);
424
425 /*
426 * Allocate IO memory
427 */
428 sc->mem_rid = PCIR_BAR(0);
429 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
430 RF_ACTIVE);
431 if (sc->mem_res == NULL) {
432 device_printf(dev, "Unable to allocate bus resource: memory\n");
433 error = ENXIO;
434 goto failed;
435 }
436 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
437 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
438
439 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
440
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441 /* Save PCI command register for Shared Code */
442 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
443 sc->hw.back = &sc->osdep;
444
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445 /* Do Shared Code initialization */
446 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
447 device_printf(dev, "Setup of Shared code failed\n");
448 error = ENXIO;
449 goto failed;
450 }
451
452 e1000_get_bus_info(&sc->hw);
453
454 sc->hw.mac.autoneg = DO_AUTO_NEG;
455 sc->hw.phy.autoneg_wait_to_complete = FALSE;
456 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
457
458 /* Copper options */
459 if (sc->hw.phy.media_type == e1000_media_type_copper) {
460 sc->hw.phy.mdix = AUTO_ALL_MODES;
461 sc->hw.phy.disable_polarity_correction = FALSE;
462 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
463 }
464
465 /* Set the frame limits assuming standard ethernet sized frames. */
466 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
1f7e3916 467
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468 /* Allocate RX/TX rings */
469 error = igb_alloc_rings(sc);
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470 if (error)
471 goto failed;
472
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473 /* Allocate interrupt */
474 error = igb_alloc_intr(sc);
475 if (error)
a1647e40 476 goto failed;
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477
478 /*
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479 * Setup serializers
480 */
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481 i = 0;
482 sc->serializes[i++] = &sc->main_serialize;
483
484 sc->tx_serialize = i;
485 for (j = 0; j < sc->tx_ring_cnt; ++j)
486 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
487
488 sc->rx_serialize = i;
489 for (j = 0; j < sc->rx_ring_cnt; ++j)
490 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
491
492 sc->serialize_cnt = i;
493 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
494
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495 /* Allocate the appropriate stats memory */
496 if (sc->vf_ifp) {
497 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
498 M_WAITOK | M_ZERO);
499 igb_vf_init_stats(sc);
500 } else {
501 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
502 M_WAITOK | M_ZERO);
503 }
504
505 /* Allocate multicast array memory. */
506 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
507 M_DEVBUF, M_WAITOK);
508
509 /* Some adapter-specific advanced features */
510 if (sc->hw.mac.type >= e1000_i350) {
511#ifdef notyet
512 igb_set_sysctl_value(adapter, "dma_coalesce",
513 "configure dma coalesce",
514 &adapter->dma_coalesce, igb_dma_coalesce);
515 igb_set_sysctl_value(adapter, "eee_disabled",
516 "enable Energy Efficient Ethernet",
517 &adapter->hw.dev_spec._82575.eee_disable,
518 igb_eee_disabled);
519#else
520 sc->dma_coalesce = igb_dma_coalesce;
521 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
522#endif
523 e1000_set_eee_i350(&sc->hw);
524 }
525
526 /*
527 * Start from a known state, this is important in reading the nvm and
528 * mac from that.
529 */
530 e1000_reset_hw(&sc->hw);
531
532 /* Make sure we have a good EEPROM before we read from it */
533 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
534 /*
535 * Some PCI-E parts fail the first check due to
536 * the link being in sleep state, call it again,
537 * if it fails a second time its a real issue.
538 */
539 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
540 device_printf(dev,
541 "The EEPROM Checksum Is Not Valid\n");
542 error = EIO;
543 goto failed;
544 }
545 }
546
547 /* Copy the permanent MAC address out of the EEPROM */
548 if (e1000_read_mac_addr(&sc->hw) < 0) {
549 device_printf(dev, "EEPROM read error while reading MAC"
550 " address\n");
551 error = EIO;
552 goto failed;
553 }
554 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
555 device_printf(dev, "Invalid MAC address\n");
556 error = EIO;
557 goto failed;
558 }
559
560#ifdef notyet
561 /*
562 ** Configure Interrupts
563 */
564 if ((adapter->msix > 1) && (igb_enable_msix))
565 error = igb_allocate_msix(adapter);
566 else /* MSI or Legacy */
567 error = igb_allocate_legacy(adapter);
568 if (error)
569 goto err_late;
570#endif
571
572 /* Setup OS specific network interface */
573 igb_setup_ifp(sc);
574
575 /* Add sysctl tree, must after igb_setup_ifp() */
576 igb_add_sysctl(sc);
577
578 /* Now get a good starting state */
579 igb_reset(sc);
580
581 /* Initialize statistics */
582 igb_update_stats_counters(sc);
583
584 sc->hw.mac.get_link_status = 1;
585 igb_update_link_status(sc);
586
587 /* Indicate SOL/IDER usage */
588 if (e1000_check_reset_block(&sc->hw)) {
589 device_printf(dev,
590 "PHY reset is blocked due to SOL/IDER session.\n");
591 }
592
593 /* Determine if we have to control management hardware */
396b7048
SZ
594 if (e1000_enable_mng_pass_thru(&sc->hw))
595 sc->flags |= IGB_FLAG_HAS_MGMT;
1f7e3916
SZ
596
597 /*
598 * Setup Wake-on-Lan
599 */
600 /* APME bit in EEPROM is mapped to WUC.APME */
601 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
602 if (eeprom_data)
603 sc->wol = E1000_WUFC_MAG;
604 /* XXX disable WOL */
605 sc->wol = 0;
606
607#ifdef notyet
608 /* Register for VLAN events */
609 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
610 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
611 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
612 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
613#endif
614
615#ifdef notyet
616 igb_add_hw_stats(adapter);
617#endif
618
f6167a56 619 error = igb_setup_intr(sc);
1f7e3916 620 if (error) {
1f7e3916
SZ
621 ether_ifdetach(&sc->arpcom.ac_if);
622 goto failed;
623 }
1f7e3916
SZ
624 return 0;
625
626failed:
627 igb_detach(dev);
628 return error;
629}
630
631static int
632igb_detach(device_t dev)
633{
634 struct igb_softc *sc = device_get_softc(dev);
635
636 if (device_is_attached(dev)) {
637 struct ifnet *ifp = &sc->arpcom.ac_if;
638
639 ifnet_serialize_all(ifp);
640
641 igb_stop(sc);
642
643 e1000_phy_hw_reset(&sc->hw);
644
645 /* Give control back to firmware */
646 igb_rel_mgmt(sc);
647 igb_rel_hw_control(sc);
648
649 if (sc->wol) {
650 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
651 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
652 igb_enable_wol(dev);
653 }
654
9c0ecdcc 655 igb_teardown_intr(sc);
1f7e3916
SZ
656
657 ifnet_deserialize_all(ifp);
658
659 ether_ifdetach(ifp);
660 } else if (sc->mem_res != NULL) {
661 igb_rel_hw_control(sc);
662 }
663 bus_generic_detach(dev);
664
9c0ecdcc
SZ
665 if (sc->sysctl_tree != NULL)
666 sysctl_ctx_free(&sc->sysctl_ctx);
667
3c7cc5e2 668 igb_free_intr(sc);
1f7e3916 669
9c0ecdcc
SZ
670 if (sc->msix_mem_res != NULL) {
671 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
672 sc->msix_mem_res);
673 }
1f7e3916
SZ
674 if (sc->mem_res != NULL) {
675 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
676 sc->mem_res);
677 }
678
a619b256 679 igb_free_rings(sc);
1f7e3916
SZ
680
681 if (sc->mta != NULL)
682 kfree(sc->mta, M_DEVBUF);
683 if (sc->stats != NULL)
684 kfree(sc->stats, M_DEVBUF);
685
1f7e3916
SZ
686 return 0;
687}
688
689static int
690igb_shutdown(device_t dev)
691{
692 return igb_suspend(dev);
693}
694
695static int
696igb_suspend(device_t dev)
697{
698 struct igb_softc *sc = device_get_softc(dev);
699 struct ifnet *ifp = &sc->arpcom.ac_if;
700
701 ifnet_serialize_all(ifp);
702
703 igb_stop(sc);
704
705 igb_rel_mgmt(sc);
706 igb_rel_hw_control(sc);
707
708 if (sc->wol) {
709 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
710 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
711 igb_enable_wol(dev);
712 }
713
714 ifnet_deserialize_all(ifp);
715
716 return bus_generic_suspend(dev);
717}
718
719static int
720igb_resume(device_t dev)
721{
722 struct igb_softc *sc = device_get_softc(dev);
723 struct ifnet *ifp = &sc->arpcom.ac_if;
724
725 ifnet_serialize_all(ifp);
726
727 igb_init(sc);
728 igb_get_mgmt(sc);
729
730 if_devstart(ifp);
731
732 ifnet_deserialize_all(ifp);
733
734 return bus_generic_resume(dev);
735}
736
737static int
738igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
739{
740 struct igb_softc *sc = ifp->if_softc;
741 struct ifreq *ifr = (struct ifreq *)data;
742 int max_frame_size, mask, reinit;
743 int error = 0;
744
745 ASSERT_IFNET_SERIALIZED_ALL(ifp);
746
747 switch (command) {
748 case SIOCSIFMTU:
749 max_frame_size = 9234;
750 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
751 ETHER_CRC_LEN) {
752 error = EINVAL;
753 break;
754 }
755
756 ifp->if_mtu = ifr->ifr_mtu;
757 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
758 ETHER_CRC_LEN;
759
760 if (ifp->if_flags & IFF_RUNNING)
761 igb_init(sc);
762 break;
763
764 case SIOCSIFFLAGS:
765 if (ifp->if_flags & IFF_UP) {
766 if (ifp->if_flags & IFF_RUNNING) {
767 if ((ifp->if_flags ^ sc->if_flags) &
768 (IFF_PROMISC | IFF_ALLMULTI)) {
769 igb_disable_promisc(sc);
770 igb_set_promisc(sc);
771 }
772 } else {
773 igb_init(sc);
774 }
775 } else if (ifp->if_flags & IFF_RUNNING) {
776 igb_stop(sc);
777 }
778 sc->if_flags = ifp->if_flags;
779 break;
780
781 case SIOCADDMULTI:
782 case SIOCDELMULTI:
783 if (ifp->if_flags & IFF_RUNNING) {
784 igb_disable_intr(sc);
785 igb_set_multi(sc);
786#ifdef DEVICE_POLLING
787 if (!(ifp->if_flags & IFF_POLLING))
788#endif
789 igb_enable_intr(sc);
790 }
791 break;
792
793 case SIOCSIFMEDIA:
794 /*
795 * As the speed/duplex settings are being
796 * changed, we need toreset the PHY.
797 */
798 sc->hw.phy.reset_disable = FALSE;
799
800 /* Check SOL/IDER usage */
801 if (e1000_check_reset_block(&sc->hw)) {
802 if_printf(ifp, "Media change is "
803 "blocked due to SOL/IDER session.\n");
804 break;
805 }
806 /* FALL THROUGH */
807
808 case SIOCGIFMEDIA:
809 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
810 break;
811
812 case SIOCSIFCAP:
813 reinit = 0;
814 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
77d8cab9
SZ
815 if (mask & IFCAP_RXCSUM) {
816 ifp->if_capenable ^= IFCAP_RXCSUM;
1f7e3916
SZ
817 reinit = 1;
818 }
819 if (mask & IFCAP_VLAN_HWTAGGING) {
820 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
821 reinit = 1;
822 }
77d8cab9
SZ
823 if (mask & IFCAP_TXCSUM) {
824 ifp->if_capenable ^= IFCAP_TXCSUM;
825 if (ifp->if_capenable & IFCAP_TXCSUM)
826 ifp->if_hwassist |= IGB_CSUM_FEATURES;
827 else
828 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
829 }
23f6ffe4
SZ
830 if (mask & IFCAP_TSO) {
831 ifp->if_capenable ^= IFCAP_TSO;
832 if (ifp->if_capenable & IFCAP_TSO)
833 ifp->if_hwassist |= CSUM_TSO;
834 else
835 ifp->if_hwassist &= ~CSUM_TSO;
836 }
8d6600da
SZ
837 if (mask & IFCAP_RSS)
838 ifp->if_capenable ^= IFCAP_RSS;
1f7e3916
SZ
839 if (reinit && (ifp->if_flags & IFF_RUNNING))
840 igb_init(sc);
841 break;
842
843 default:
844 error = ether_ioctl(ifp, command, data);
845 break;
846 }
847 return error;
848}
849
850static void
851igb_init(void *xsc)
852{
853 struct igb_softc *sc = xsc;
854 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 855 boolean_t polling;
1f7e3916
SZ
856 int i;
857
858 ASSERT_IFNET_SERIALIZED_ALL(ifp);
859
860 igb_stop(sc);
861
862 /* Get the latest mac address, User can use a LAA */
863 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
864
865 /* Put the address into the Receive Address Array */
866 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
867
868 igb_reset(sc);
869 igb_update_link_status(sc);
870
871 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
872
1f7e3916
SZ
873 /* Configure for OS presence */
874 igb_get_mgmt(sc);
875
9c0ecdcc 876 polling = FALSE;
be922da6 877#ifdef DEVICE_POLLING
9c0ecdcc
SZ
878 if (ifp->if_flags & IFF_POLLING)
879 polling = TRUE;
be922da6 880#endif
9c0ecdcc
SZ
881
882 /* Configured used RX/TX rings */
883 igb_set_ring_inuse(sc, polling);
884
885 /* Initialize interrupt */
886 igb_init_intr(sc);
be922da6 887
1f7e3916 888 /* Prepare transmit descriptors and buffers */
27866bf1 889 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916
SZ
890 igb_init_tx_ring(&sc->tx_rings[i]);
891 igb_init_tx_unit(sc);
892
893 /* Setup Multicast table */
894 igb_set_multi(sc);
895
896#if 0
897 /*
898 * Figure out the desired mbuf pool
899 * for doing jumbo/packetsplit
900 */
901 if (adapter->max_frame_size <= 2048)
902 adapter->rx_mbuf_sz = MCLBYTES;
903 else if (adapter->max_frame_size <= 4096)
904 adapter->rx_mbuf_sz = MJUMPAGESIZE;
905 else
906 adapter->rx_mbuf_sz = MJUM9BYTES;
1f7e3916
SZ
907#endif
908
909 /* Prepare receive descriptors and buffers */
be922da6 910 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
911 int error;
912
913 error = igb_init_rx_ring(&sc->rx_rings[i]);
914 if (error) {
915 if_printf(ifp, "Could not setup receive structures\n");
916 igb_stop(sc);
917 return;
918 }
919 }
920 igb_init_rx_unit(sc);
921
922 /* Enable VLAN support */
923 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
924 igb_set_vlan(sc);
925
926 /* Don't lose promiscuous settings */
927 igb_set_promisc(sc);
928
1f7e3916
SZ
929 ifp->if_flags |= IFF_RUNNING;
930 ifp->if_flags &= ~IFF_OACTIVE;
931
932 callout_reset(&sc->timer, hz, igb_timer, sc);
933 e1000_clear_hw_cntrs_base_generic(&sc->hw);
934
9c0ecdcc 935 /* This clears any pending interrupts */
1f7e3916 936 E1000_READ_REG(&sc->hw, E1000_ICR);
9c0ecdcc 937
1f7e3916
SZ
938 /*
939 * Only enable interrupts if we are not polling, make sure
940 * they are off otherwise.
941 */
9c0ecdcc 942 if (polling) {
1f7e3916 943 igb_disable_intr(sc);
9c0ecdcc 944 } else {
1f7e3916
SZ
945 igb_enable_intr(sc);
946 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
947 }
948
949 /* Set Energy Efficient Ethernet */
950 e1000_set_eee_i350(&sc->hw);
951
952 /* Don't reset the phy next time init gets called */
953 sc->hw.phy.reset_disable = TRUE;
954}
955
956static void
957igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
958{
959 struct igb_softc *sc = ifp->if_softc;
960 u_char fiber_type = IFM_1000_SX;
961
962 ASSERT_IFNET_SERIALIZED_ALL(ifp);
963
964 igb_update_link_status(sc);
965
966 ifmr->ifm_status = IFM_AVALID;
967 ifmr->ifm_active = IFM_ETHER;
968
969 if (!sc->link_active)
970 return;
971
972 ifmr->ifm_status |= IFM_ACTIVE;
973
974 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
975 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
976 ifmr->ifm_active |= fiber_type | IFM_FDX;
977 } else {
978 switch (sc->link_speed) {
979 case 10:
980 ifmr->ifm_active |= IFM_10_T;
981 break;
982
983 case 100:
984 ifmr->ifm_active |= IFM_100_TX;
985 break;
986
987 case 1000:
988 ifmr->ifm_active |= IFM_1000_T;
989 break;
990 }
991 if (sc->link_duplex == FULL_DUPLEX)
992 ifmr->ifm_active |= IFM_FDX;
993 else
994 ifmr->ifm_active |= IFM_HDX;
995 }
996}
997
998static int
999igb_media_change(struct ifnet *ifp)
1000{
1001 struct igb_softc *sc = ifp->if_softc;
1002 struct ifmedia *ifm = &sc->media;
1003
1004 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1005
1006 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1007 return EINVAL;
1008
1009 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1010 case IFM_AUTO:
1011 sc->hw.mac.autoneg = DO_AUTO_NEG;
1012 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1013 break;
1014
1015 case IFM_1000_LX:
1016 case IFM_1000_SX:
1017 case IFM_1000_T:
1018 sc->hw.mac.autoneg = DO_AUTO_NEG;
1019 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1020 break;
1021
1022 case IFM_100_TX:
1023 sc->hw.mac.autoneg = FALSE;
1024 sc->hw.phy.autoneg_advertised = 0;
1025 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1026 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1027 else
1028 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1029 break;
1030
1031 case IFM_10_T:
1032 sc->hw.mac.autoneg = FALSE;
1033 sc->hw.phy.autoneg_advertised = 0;
1034 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1035 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1036 else
1037 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1038 break;
1039
1040 default:
1041 if_printf(ifp, "Unsupported media type\n");
1042 break;
1043 }
1044
1045 igb_init(sc);
1046
1047 return 0;
1048}
1049
1050static void
1051igb_set_promisc(struct igb_softc *sc)
1052{
1053 struct ifnet *ifp = &sc->arpcom.ac_if;
1054 struct e1000_hw *hw = &sc->hw;
1055 uint32_t reg;
1056
1057 if (sc->vf_ifp) {
1058 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1059 return;
1060 }
1061
1062 reg = E1000_READ_REG(hw, E1000_RCTL);
1063 if (ifp->if_flags & IFF_PROMISC) {
1064 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1065 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1066 } else if (ifp->if_flags & IFF_ALLMULTI) {
1067 reg |= E1000_RCTL_MPE;
1068 reg &= ~E1000_RCTL_UPE;
1069 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1070 }
1071}
1072
1073static void
1074igb_disable_promisc(struct igb_softc *sc)
1075{
1076 struct e1000_hw *hw = &sc->hw;
1077 uint32_t reg;
1078
1079 if (sc->vf_ifp) {
1080 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1081 return;
1082 }
1083 reg = E1000_READ_REG(hw, E1000_RCTL);
1084 reg &= ~E1000_RCTL_UPE;
1085 reg &= ~E1000_RCTL_MPE;
1086 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1087}
1088
1089static void
1090igb_set_multi(struct igb_softc *sc)
1091{
1092 struct ifnet *ifp = &sc->arpcom.ac_if;
1093 struct ifmultiaddr *ifma;
1094 uint32_t reg_rctl = 0;
1095 uint8_t *mta;
1096 int mcnt = 0;
1097
1098 mta = sc->mta;
1099 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1100
1101 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1102 if (ifma->ifma_addr->sa_family != AF_LINK)
1103 continue;
1104
1105 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1106 break;
1107
1108 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1109 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1110 mcnt++;
1111 }
1112
1113 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1114 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1115 reg_rctl |= E1000_RCTL_MPE;
1116 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1117 } else {
1118 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1119 }
1120}
1121
1122static void
1123igb_timer(void *xsc)
1124{
1125 struct igb_softc *sc = xsc;
1f7e3916 1126
27dd00d6 1127 lwkt_serialize_enter(&sc->main_serialize);
1f7e3916
SZ
1128
1129 igb_update_link_status(sc);
1130 igb_update_stats_counters(sc);
1131
1132 callout_reset(&sc->timer, hz, igb_timer, sc);
1133
27dd00d6 1134 lwkt_serialize_exit(&sc->main_serialize);
1f7e3916
SZ
1135}
1136
1137static void
1138igb_update_link_status(struct igb_softc *sc)
1139{
1140 struct ifnet *ifp = &sc->arpcom.ac_if;
1141 struct e1000_hw *hw = &sc->hw;
1142 uint32_t link_check, thstat, ctrl;
1143
1144 link_check = thstat = ctrl = 0;
1145
1146 /* Get the cached link value or read for real */
1147 switch (hw->phy.media_type) {
1148 case e1000_media_type_copper:
1149 if (hw->mac.get_link_status) {
1150 /* Do the work to read phy */
1151 e1000_check_for_link(hw);
1152 link_check = !hw->mac.get_link_status;
1153 } else {
1154 link_check = TRUE;
1155 }
1156 break;
1157
1158 case e1000_media_type_fiber:
1159 e1000_check_for_link(hw);
1160 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1161 break;
1162
1163 case e1000_media_type_internal_serdes:
1164 e1000_check_for_link(hw);
1165 link_check = hw->mac.serdes_has_link;
1166 break;
1167
1168 /* VF device is type_unknown */
1169 case e1000_media_type_unknown:
1170 e1000_check_for_link(hw);
1171 link_check = !hw->mac.get_link_status;
1172 /* Fall thru */
1173 default:
1174 break;
1175 }
1176
1177 /* Check for thermal downshift or shutdown */
1178 if (hw->mac.type == e1000_i350) {
1179 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1180 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1181 }
1182
1183 /* Now we check if a transition has happened */
1184 if (link_check && sc->link_active == 0) {
1185 e1000_get_speed_and_duplex(hw,
1186 &sc->link_speed, &sc->link_duplex);
1187 if (bootverbose) {
1188 if_printf(ifp, "Link is up %d Mbps %s\n",
1189 sc->link_speed,
1190 sc->link_duplex == FULL_DUPLEX ?
1191 "Full Duplex" : "Half Duplex");
1192 }
1193 sc->link_active = 1;
1194
1195 ifp->if_baudrate = sc->link_speed * 1000000;
1196 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1197 (thstat & E1000_THSTAT_LINK_THROTTLE))
1198 if_printf(ifp, "Link: thermal downshift\n");
1199 /* This can sleep */
1200 ifp->if_link_state = LINK_STATE_UP;
1201 if_link_state_change(ifp);
1202 } else if (!link_check && sc->link_active == 1) {
1203 ifp->if_baudrate = sc->link_speed = 0;
1204 sc->link_duplex = 0;
1205 if (bootverbose)
1206 if_printf(ifp, "Link is Down\n");
1207 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1208 (thstat & E1000_THSTAT_PWR_DOWN))
1209 if_printf(ifp, "Link: thermal shutdown\n");
1210 sc->link_active = 0;
1211 /* This can sleep */
1212 ifp->if_link_state = LINK_STATE_DOWN;
1213 if_link_state_change(ifp);
1214 }
1215}
1216
1217static void
1218igb_stop(struct igb_softc *sc)
1219{
1220 struct ifnet *ifp = &sc->arpcom.ac_if;
1221 int i;
1222
1223 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1224
1225 igb_disable_intr(sc);
1226
1227 callout_stop(&sc->timer);
1228
1229 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1230 ifp->if_timer = 0;
1231
1232 e1000_reset_hw(&sc->hw);
1233 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1234
1235 e1000_led_off(&sc->hw);
1236 e1000_cleanup_led(&sc->hw);
1237
27866bf1 1238 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916 1239 igb_free_tx_ring(&sc->tx_rings[i]);
27866bf1 1240 for (i = 0; i < sc->rx_ring_cnt; ++i)
1f7e3916
SZ
1241 igb_free_rx_ring(&sc->rx_rings[i]);
1242}
1243
1244static void
1245igb_reset(struct igb_softc *sc)
1246{
1247 struct ifnet *ifp = &sc->arpcom.ac_if;
1248 struct e1000_hw *hw = &sc->hw;
1249 struct e1000_fc_info *fc = &hw->fc;
1250 uint32_t pba = 0;
1251 uint16_t hwm;
1252
1253 /* Let the firmware know the OS is in control */
1254 igb_get_hw_control(sc);
1255
1256 /*
1257 * Packet Buffer Allocation (PBA)
1258 * Writing PBA sets the receive portion of the buffer
1259 * the remainder is used for the transmit buffer.
1260 */
1261 switch (hw->mac.type) {
1262 case e1000_82575:
1263 pba = E1000_PBA_32K;
1264 break;
1265
1266 case e1000_82576:
1267 case e1000_vfadapt:
1268 pba = E1000_READ_REG(hw, E1000_RXPBS);
1269 pba &= E1000_RXPBS_SIZE_MASK_82576;
1270 break;
1271
1272 case e1000_82580:
1273 case e1000_i350:
1274 case e1000_vfadapt_i350:
1275 pba = E1000_READ_REG(hw, E1000_RXPBS);
1276 pba = e1000_rxpbs_adjust_82580(pba);
1277 break;
1278 /* XXX pba = E1000_PBA_35K; */
1279
1280 default:
1281 break;
1282 }
1283
1284 /* Special needs in case of Jumbo frames */
1285 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1286 uint32_t tx_space, min_tx, min_rx;
1287
1288 pba = E1000_READ_REG(hw, E1000_PBA);
1289 tx_space = pba >> 16;
1290 pba &= 0xffff;
1291
1292 min_tx = (sc->max_frame_size +
1293 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1294 min_tx = roundup2(min_tx, 1024);
1295 min_tx >>= 10;
1296 min_rx = sc->max_frame_size;
1297 min_rx = roundup2(min_rx, 1024);
1298 min_rx >>= 10;
1299 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1300 pba = pba - (min_tx - tx_space);
1301 /*
1302 * if short on rx space, rx wins
1303 * and must trump tx adjustment
1304 */
1305 if (pba < min_rx)
1306 pba = min_rx;
1307 }
1308 E1000_WRITE_REG(hw, E1000_PBA, pba);
1309 }
1310
1311 /*
1312 * These parameters control the automatic generation (Tx) and
1313 * response (Rx) to Ethernet PAUSE frames.
1314 * - High water mark should allow for at least two frames to be
1315 * received after sending an XOFF.
1316 * - Low water mark works best when it is very near the high water mark.
1317 * This allows the receiver to restart by sending XON when it has
1318 * drained a bit.
1319 */
1320 hwm = min(((pba << 10) * 9 / 10),
1321 ((pba << 10) - 2 * sc->max_frame_size));
1322
1323 if (hw->mac.type < e1000_82576) {
1324 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1325 fc->low_water = fc->high_water - 8;
1326 } else {
1327 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1328 fc->low_water = fc->high_water - 16;
1329 }
1330 fc->pause_time = IGB_FC_PAUSE_TIME;
1331 fc->send_xon = TRUE;
1332
1333 /* Issue a global reset */
1334 e1000_reset_hw(hw);
1335 E1000_WRITE_REG(hw, E1000_WUC, 0);
1336
1337 if (e1000_init_hw(hw) < 0)
1338 if_printf(ifp, "Hardware Initialization Failed\n");
1339
1340 /* Setup DMA Coalescing */
1341 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1342 uint32_t reg;
1343
1344 hwm = (pba - 4) << 10;
1345 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1346 & E1000_DMACR_DMACTHR_MASK;
1347
1348 /* transition to L0x or L1 if available..*/
1349 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1350
1351 /* timer = +-1000 usec in 32usec intervals */
1352 reg |= (1000 >> 5);
1353 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1354
1355 /* No lower threshold */
1356 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1357
1358 /* set hwm to PBA - 2 * max frame size */
1359 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1360
1361 /* Set the interval before transition */
1362 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1363 reg |= 0x800000FF; /* 255 usec */
1364 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1365
1366 /* free space in tx packet buffer to wake from DMA coal */
1367 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1368 (20480 - (2 * sc->max_frame_size)) >> 6);
1369
1370 /* make low power state decision controlled by DMA coal */
1371 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1372 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1373 reg | E1000_PCIEMISC_LX_DECISION);
1374 if_printf(ifp, "DMA Coalescing enabled\n");
1375 }
1376
1377 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1378 e1000_get_phy_info(hw);
1379 e1000_check_for_link(hw);
1380}
1381
1382static void
1383igb_setup_ifp(struct igb_softc *sc)
1384{
1385 struct ifnet *ifp = &sc->arpcom.ac_if;
1386
1387 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1388 ifp->if_softc = sc;
1389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c0ecdcc 1390 ifp->if_init = igb_init;
1f7e3916
SZ
1391 ifp->if_ioctl = igb_ioctl;
1392 ifp->if_start = igb_start;
7d235eb5
SZ
1393 ifp->if_serialize = igb_serialize;
1394 ifp->if_deserialize = igb_deserialize;
1395 ifp->if_tryserialize = igb_tryserialize;
1396#ifdef INVARIANTS
1397 ifp->if_serialize_assert = igb_serialize_assert;
1398#endif
1f7e3916
SZ
1399#ifdef DEVICE_POLLING
1400 ifp->if_poll = igb_poll;
1401#endif
1402 ifp->if_watchdog = igb_watchdog;
1403
91b8700a 1404 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1f7e3916
SZ
1405 ifq_set_ready(&ifp->if_snd);
1406
1407 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1408
1409 ifp->if_capabilities =
23f6ffe4 1410 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
8d6600da
SZ
1411 if (IGB_ENABLE_HWRSS(sc))
1412 ifp->if_capabilities |= IFCAP_RSS;
1f7e3916 1413 ifp->if_capenable = ifp->if_capabilities;
23f6ffe4 1414 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1f7e3916
SZ
1415
1416 /*
1417 * Tell the upper layer(s) we support long frames
1418 */
1419 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1420
1421 /*
1422 * Specify the media types supported by this adapter and register
1423 * callbacks to update media and link information
1424 */
1425 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1426 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1427 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1428 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1429 0, NULL);
1430 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1431 } else {
1432 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1433 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1434 0, NULL);
1435 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1436 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1437 0, NULL);
1438 if (sc->hw.phy.type != e1000_phy_ife) {
1439 ifmedia_add(&sc->media,
1440 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1441 ifmedia_add(&sc->media,
1442 IFM_ETHER | IFM_1000_T, 0, NULL);
1443 }
1444 }
1445 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1446 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1447}
1448
1449static void
1450igb_add_sysctl(struct igb_softc *sc)
1451{
9c0ecdcc 1452 char node[32];
8d6600da 1453 int i;
8d6600da 1454
1f7e3916
SZ
1455 sysctl_ctx_init(&sc->sysctl_ctx);
1456 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1457 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1458 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1459 if (sc->sysctl_tree == NULL) {
1460 device_printf(sc->dev, "can't add sysctl node\n");
1461 return;
1462 }
1463
1464 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1465 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1466 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
be922da6
SZ
1467 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1468 "# of RX rings used");
1469 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1470 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1471 "# of RX descs");
1f7e3916 1472 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1473 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1474 "# of TX descs");
1f7e3916 1475
9c0ecdcc
SZ
1476 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1477 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1478 SYSCTL_CHILDREN(sc->sysctl_tree),
1479 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1480 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1481 } else {
1482 for (i = 0; i < sc->msix_cnt; ++i) {
1483 struct igb_msix_data *msix = &sc->msix_data[i];
1484
1485 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1486 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1487 SYSCTL_CHILDREN(sc->sysctl_tree),
1488 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1489 msix, 0, igb_sysctl_msix_rate, "I",
1490 msix->msix_rate_desc);
1491 }
1492 }
b6220144
SZ
1493
1494 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1495 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1496 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
8d6600da
SZ
1497 "# of segments per TX interrupt");
1498
1499#ifdef IGB_RSS_DEBUG
1500 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1501 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1502 "RSS debug level");
1503 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9c0ecdcc 1504 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
8d6600da 1505 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
9c0ecdcc 1506 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
8d6600da
SZ
1507 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1508 }
1509#endif
1f7e3916
SZ
1510}
1511
1512static int
a619b256 1513igb_alloc_rings(struct igb_softc *sc)
1f7e3916
SZ
1514{
1515 int error, i;
1516
1f7e3916
SZ
1517 /*
1518 * Create top level busdma tag
1519 */
1520 error = bus_dma_tag_create(NULL, 1, 0,
1521 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1522 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1523 &sc->parent_tag);
1524 if (error) {
1525 device_printf(sc->dev, "could not create top level DMA tag\n");
1526 return error;
1527 }
1528
1529 /*
1530 * Allocate TX descriptor rings and buffers
1531 */
27866bf1 1532 sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1f7e3916 1533 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1534 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1535 struct igb_tx_ring *txr = &sc->tx_rings[i];
1536
1537 /* Set up some basics */
1538 txr->sc = sc;
1539 txr->me = i;
7d235eb5 1540 lwkt_serialize_init(&txr->tx_serialize);
1f7e3916
SZ
1541
1542 error = igb_create_tx_ring(txr);
1543 if (error)
1544 return error;
1545 }
1546
1547 /*
1548 * Allocate RX descriptor rings and buffers
1549 */
27866bf1 1550 sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1f7e3916 1551 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1552 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1f7e3916
SZ
1553 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1554
1555 /* Set up some basics */
1556 rxr->sc = sc;
1557 rxr->me = i;
7d235eb5 1558 lwkt_serialize_init(&rxr->rx_serialize);
1f7e3916
SZ
1559
1560 error = igb_create_rx_ring(rxr);
1561 if (error)
1562 return error;
1563 }
1564
1f7e3916
SZ
1565 return 0;
1566}
1567
1568static void
a619b256 1569igb_free_rings(struct igb_softc *sc)
1f7e3916
SZ
1570{
1571 int i;
1572
1f7e3916 1573 if (sc->tx_rings != NULL) {
91b8700a
SZ
1574 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1575 struct igb_tx_ring *txr = &sc->tx_rings[i];
1576
1577 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1578 }
1f7e3916
SZ
1579 kfree(sc->tx_rings, M_DEVBUF);
1580 }
1581
1582 if (sc->rx_rings != NULL) {
91b8700a
SZ
1583 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1584 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1585
1586 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1587 }
1f7e3916
SZ
1588 kfree(sc->rx_rings, M_DEVBUF);
1589 }
1590}
1591
1592static int
1593igb_create_tx_ring(struct igb_tx_ring *txr)
1594{
1595 int tsize, error, i;
1596
1597 /*
1598 * Validate number of transmit descriptors. It must not exceed
1599 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1600 */
1601 if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1602 (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1603 device_printf(txr->sc->dev,
1604 "Using %d TX descriptors instead of %d!\n",
1605 IGB_DEFAULT_TXD, igb_txd);
91b8700a 1606 txr->num_tx_desc = IGB_DEFAULT_TXD;
1f7e3916 1607 } else {
91b8700a 1608 txr->num_tx_desc = igb_txd;
1f7e3916
SZ
1609 }
1610
1611 /*
1612 * Allocate TX descriptor ring
1613 */
91b8700a 1614 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1f7e3916
SZ
1615 IGB_DBA_ALIGN);
1616 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1617 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1618 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1619 if (txr->txdma.dma_vaddr == NULL) {
1620 device_printf(txr->sc->dev,
1621 "Unable to allocate TX Descriptor memory\n");
1622 return ENOMEM;
1623 }
1624 txr->tx_base = txr->txdma.dma_vaddr;
1625 bzero(txr->tx_base, tsize);
1626
91b8700a 1627 txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1f7e3916
SZ
1628 M_DEVBUF, M_WAITOK | M_ZERO);
1629
1630 /*
b6220144
SZ
1631 * Allocate TX head write-back buffer
1632 */
1633 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1634 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1635 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1636 if (txr->tx_hdr == NULL) {
1637 device_printf(txr->sc->dev,
1638 "Unable to allocate TX head write-back buffer\n");
1639 return ENOMEM;
1640 }
1641
1642 /*
1f7e3916
SZ
1643 * Create DMA tag for TX buffers
1644 */
1645 error = bus_dma_tag_create(txr->sc->parent_tag,
1646 1, 0, /* alignment, bounds */
1647 BUS_SPACE_MAXADDR, /* lowaddr */
1648 BUS_SPACE_MAXADDR, /* highaddr */
1649 NULL, NULL, /* filter, filterarg */
1650 IGB_TSO_SIZE, /* maxsize */
1651 IGB_MAX_SCATTER, /* nsegments */
1652 PAGE_SIZE, /* maxsegsize */
1653 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1654 BUS_DMA_ONEBPAGE, /* flags */
1655 &txr->tx_tag);
1656 if (error) {
1657 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1658 kfree(txr->tx_buf, M_DEVBUF);
1659 txr->tx_buf = NULL;
1660 return error;
1661 }
1662
1663 /*
1664 * Create DMA maps for TX buffers
1665 */
91b8700a 1666 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1667 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1668
1669 error = bus_dmamap_create(txr->tx_tag,
1670 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1671 if (error) {
1672 device_printf(txr->sc->dev,
1673 "Unable to create TX DMA map\n");
1674 igb_destroy_tx_ring(txr, i);
1675 return error;
1676 }
1677 }
b6220144
SZ
1678
1679 /*
1680 * Initialize various watermark
1681 */
1682 txr->spare_desc = IGB_TX_SPARE;
91b8700a
SZ
1683 txr->intr_nsegs = txr->num_tx_desc / 16;
1684 txr->oact_hi_desc = txr->num_tx_desc / 2;
1685 txr->oact_lo_desc = txr->num_tx_desc / 8;
b6220144
SZ
1686 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1687 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1688 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1689 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1690
1f7e3916
SZ
1691 return 0;
1692}
1693
1694static void
1695igb_free_tx_ring(struct igb_tx_ring *txr)
1696{
1697 int i;
1698
91b8700a 1699 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1700 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1701
1702 if (txbuf->m_head != NULL) {
1703 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1704 m_freem(txbuf->m_head);
1705 txbuf->m_head = NULL;
1706 }
1707 }
1708}
1709
1710static void
1711igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1712{
1713 int i;
1714
1715 if (txr->txdma.dma_vaddr != NULL) {
1716 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1717 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1718 txr->txdma.dma_map);
1719 bus_dma_tag_destroy(txr->txdma.dma_tag);
1720 txr->txdma.dma_vaddr = NULL;
1721 }
1722
b6220144
SZ
1723 if (txr->tx_hdr != NULL) {
1724 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1725 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1726 txr->tx_hdr_dmap);
1727 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1728 txr->tx_hdr = NULL;
1729 }
1730
1f7e3916
SZ
1731 if (txr->tx_buf == NULL)
1732 return;
1733
1734 for (i = 0; i < ndesc; ++i) {
1735 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1736
1737 KKASSERT(txbuf->m_head == NULL);
1738 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1739 }
1740 bus_dma_tag_destroy(txr->tx_tag);
1741
1742 kfree(txr->tx_buf, M_DEVBUF);
1743 txr->tx_buf = NULL;
1744}
1745
1746static void
1747igb_init_tx_ring(struct igb_tx_ring *txr)
1748{
1f7e3916
SZ
1749 /* Clear the old descriptor contents */
1750 bzero(txr->tx_base,
91b8700a 1751 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1f7e3916 1752
b6220144
SZ
1753 /* Clear TX head write-back buffer */
1754 *(txr->tx_hdr) = 0;
1755
1f7e3916
SZ
1756 /* Reset indices */
1757 txr->next_avail_desc = 0;
1758 txr->next_to_clean = 0;
b6220144 1759 txr->tx_nsegs = 0;
1f7e3916
SZ
1760
1761 /* Set number of descriptors available */
91b8700a 1762 txr->tx_avail = txr->num_tx_desc;
1f7e3916
SZ
1763}
1764
1765static void
1766igb_init_tx_unit(struct igb_softc *sc)
1767{
1768 struct e1000_hw *hw = &sc->hw;
1769 uint32_t tctl;
1770 int i;
1771
1772 /* Setup the Tx Descriptor Rings */
27866bf1 1773 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1774 struct igb_tx_ring *txr = &sc->tx_rings[i];
1775 uint64_t bus_addr = txr->txdma.dma_paddr;
c3162c4e 1776 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1f7e3916 1777 uint32_t txdctl = 0;
b6220144 1778 uint32_t dca_txctrl;
1f7e3916
SZ
1779
1780 E1000_WRITE_REG(hw, E1000_TDLEN(i),
91b8700a 1781 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1f7e3916
SZ
1782 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1783 (uint32_t)(bus_addr >> 32));
1784 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1785 (uint32_t)bus_addr);
1786
1787 /* Setup the HW Tx Head and Tail descriptor pointers */
1788 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1789 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1790
54691ff1
SZ
1791 /*
1792 * WTHRESH is ignored by the hardware, since header
1793 * write back mode is used.
1794 */
1f7e3916
SZ
1795 txdctl |= IGB_TX_PTHRESH;
1796 txdctl |= IGB_TX_HTHRESH << 8;
1797 txdctl |= IGB_TX_WTHRESH << 16;
1798 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1799 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
b6220144
SZ
1800
1801 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1802 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1803 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1804
54691ff1
SZ
1805 /*
1806 * Don't set WB_on_EITR:
1807 * - 82575 does not have it
1808 * - It almost has no effect on 82576, see:
1809 * 82576 specification update errata #26
1810 * - It causes unnecessary bus traffic
1811 */
b6220144 1812 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
c3162c4e 1813 (uint32_t)(hdr_paddr >> 32));
b6220144 1814 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
c3162c4e 1815 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1f7e3916
SZ
1816 }
1817
1818 if (sc->vf_ifp)
1819 return;
1820
1821 e1000_config_collision_dist(hw);
1822
1823 /* Program the Transmit Control Register */
1824 tctl = E1000_READ_REG(hw, E1000_TCTL);
1825 tctl &= ~E1000_TCTL_CT;
1826 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1827 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1828
1829 /* This write will effectively turn on the transmit unit. */
1830 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1831}
1832
1833static boolean_t
48faa653 1834igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1f7e3916
SZ
1835{
1836 struct e1000_adv_tx_context_desc *TXD;
1f7e3916 1837 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1f7e3916 1838 int ehdrlen, ctxd, ip_hlen = 0;
1f7e3916
SZ
1839 boolean_t offload = TRUE;
1840
1841 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1842 offload = FALSE;
1843
1844 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
48faa653 1845
1f7e3916 1846 ctxd = txr->next_avail_desc;
1f7e3916
SZ
1847 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1848
1849 /*
1850 * In advanced descriptors the vlan tag must
1851 * be placed into the context descriptor, thus
1852 * we need to be here just for that setup.
1853 */
1854 if (mp->m_flags & M_VLANTAG) {
23f6ffe4
SZ
1855 uint16_t vlantag;
1856
1f7e3916
SZ
1857 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1858 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1859 } else if (!offload) {
1860 return FALSE;
1861 }
1862
48faa653
SZ
1863 ehdrlen = mp->m_pkthdr.csum_lhlen;
1864 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1f7e3916
SZ
1865
1866 /* Set the ether header length */
1867 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
48faa653
SZ
1868 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1869 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1870 ip_hlen = mp->m_pkthdr.csum_iphlen;
1871 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1f7e3916 1872 }
1f7e3916 1873 vlan_macip_lens |= ip_hlen;
1f7e3916 1874
23f6ffe4 1875 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1f7e3916
SZ
1876 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1877 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1878 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1879 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1880
1881 /* 82575 needs the queue index added */
1882 if (txr->sc->hw.mac.type == e1000_82575)
1883 mss_l4len_idx = txr->me << 4;
1884
1885 /* Now copy bits into descriptor */
1886 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1887 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1888 TXD->seqnum_seed = htole32(0);
1889 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1890
1f7e3916 1891 /* We've consumed the first desc, adjust counters */
91b8700a 1892 if (++ctxd == txr->num_tx_desc)
1f7e3916
SZ
1893 ctxd = 0;
1894 txr->next_avail_desc = ctxd;
1895 --txr->tx_avail;
1896
1897 return offload;
1898}
1899
1900static void
1901igb_txeof(struct igb_tx_ring *txr)
1902{
1903 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
b6220144 1904 int first, hdr, avail;
1f7e3916 1905
91b8700a 1906 if (txr->tx_avail == txr->num_tx_desc)
1f7e3916
SZ
1907 return;
1908
1909 first = txr->next_to_clean;
b6220144 1910 hdr = *(txr->tx_hdr);
1f7e3916 1911
b6220144
SZ
1912 if (first == hdr)
1913 return;
1f7e3916 1914
b6220144
SZ
1915 avail = txr->tx_avail;
1916 while (first != hdr) {
1917 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1f7e3916 1918
b6220144
SZ
1919 ++avail;
1920 if (txbuf->m_head) {
1921 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1922 m_freem(txbuf->m_head);
1923 txbuf->m_head = NULL;
1924 ++ifp->if_opackets;
1f7e3916 1925 }
91b8700a 1926 if (++first == txr->num_tx_desc)
b6220144 1927 first = 0;
1f7e3916
SZ
1928 }
1929 txr->next_to_clean = first;
b6220144 1930 txr->tx_avail = avail;
1f7e3916
SZ
1931
1932 /*
1933 * If we have a minimum free, clear IFF_OACTIVE
1934 * to tell the stack that it is OK to send packets.
1935 */
b6220144 1936 if (IGB_IS_NOT_OACTIVE(txr)) {
1f7e3916
SZ
1937 ifp->if_flags &= ~IFF_OACTIVE;
1938
1f7e3916
SZ
1939 /*
1940 * We have enough TX descriptors, turn off
b6220144
SZ
1941 * the watchdog. We allow small amount of
1942 * packets (roughly intr_nsegs) pending on
1943 * the transmit ring.
1f7e3916
SZ
1944 */
1945 ifp->if_timer = 0;
1f7e3916
SZ
1946 }
1947}
1948
1949static int
1950igb_create_rx_ring(struct igb_rx_ring *rxr)
1951{
1952 int rsize, i, error;
1953
1954 /*
1955 * Validate number of receive descriptors. It must not exceed
1956 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1957 */
1958 if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1959 (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1960 device_printf(rxr->sc->dev,
1961 "Using %d RX descriptors instead of %d!\n",
1962 IGB_DEFAULT_RXD, igb_rxd);
91b8700a 1963 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1f7e3916 1964 } else {
91b8700a 1965 rxr->num_rx_desc = igb_rxd;
1f7e3916
SZ
1966 }
1967
1968 /*
1969 * Allocate RX descriptor ring
1970 */
91b8700a 1971 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1f7e3916
SZ
1972 IGB_DBA_ALIGN);
1973 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1974 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1975 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1976 &rxr->rxdma.dma_paddr);
1977 if (rxr->rxdma.dma_vaddr == NULL) {
1978 device_printf(rxr->sc->dev,
1979 "Unable to allocate RxDescriptor memory\n");
1980 return ENOMEM;
1981 }
1982 rxr->rx_base = rxr->rxdma.dma_vaddr;
1983 bzero(rxr->rx_base, rsize);
1984
91b8700a 1985 rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1f7e3916
SZ
1986 M_DEVBUF, M_WAITOK | M_ZERO);
1987
1988 /*
1989 * Create DMA tag for RX buffers
1990 */
1991 error = bus_dma_tag_create(rxr->sc->parent_tag,
1992 1, 0, /* alignment, bounds */
1993 BUS_SPACE_MAXADDR, /* lowaddr */
1994 BUS_SPACE_MAXADDR, /* highaddr */
1995 NULL, NULL, /* filter, filterarg */
1996 MCLBYTES, /* maxsize */
1997 1, /* nsegments */
1998 MCLBYTES, /* maxsegsize */
1999 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2000 &rxr->rx_tag);
2001 if (error) {
2002 device_printf(rxr->sc->dev,
2003 "Unable to create RX payload DMA tag\n");
2004 kfree(rxr->rx_buf, M_DEVBUF);
2005 rxr->rx_buf = NULL;
2006 return error;
2007 }
2008
2009 /*
2010 * Create spare DMA map for RX buffers
2011 */
2012 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2013 &rxr->rx_sparemap);
2014 if (error) {
2015 device_printf(rxr->sc->dev,
2016 "Unable to create spare RX DMA maps\n");
2017 bus_dma_tag_destroy(rxr->rx_tag);
2018 kfree(rxr->rx_buf, M_DEVBUF);
2019 rxr->rx_buf = NULL;
2020 return error;
2021 }
2022
2023 /*
2024 * Create DMA maps for RX buffers
2025 */
91b8700a 2026 for (i = 0; i < rxr->num_rx_desc; i++) {
1f7e3916
SZ
2027 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2028
2029 error = bus_dmamap_create(rxr->rx_tag,
2030 BUS_DMA_WAITOK, &rxbuf->map);
2031 if (error) {
2032 device_printf(rxr->sc->dev,
2033 "Unable to create RX DMA maps\n");
2034 igb_destroy_rx_ring(rxr, i);
2035 return error;
2036 }
2037 }
2038 return 0;
2039}
2040
2041static void
2042igb_free_rx_ring(struct igb_rx_ring *rxr)
2043{
2044 int i;
2045
91b8700a 2046 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2047 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2048
2049 if (rxbuf->m_head != NULL) {
2050 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2051 m_freem(rxbuf->m_head);
2052 rxbuf->m_head = NULL;
2053 }
2054 }
2055
2056 if (rxr->fmp != NULL)
2057 m_freem(rxr->fmp);
2058 rxr->fmp = NULL;
2059 rxr->lmp = NULL;
2060}
2061
2062static void
2063igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2064{
2065 int i;
2066
2067 if (rxr->rxdma.dma_vaddr != NULL) {
2068 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2069 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2070 rxr->rxdma.dma_map);
2071 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2072 rxr->rxdma.dma_vaddr = NULL;
2073 }
2074
2075 if (rxr->rx_buf == NULL)
2076 return;
2077
2078 for (i = 0; i < ndesc; ++i) {
2079 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2080
2081 KKASSERT(rxbuf->m_head == NULL);
2082 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2083 }
2084 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2085 bus_dma_tag_destroy(rxr->rx_tag);
2086
2087 kfree(rxr->rx_buf, M_DEVBUF);
2088 rxr->rx_buf = NULL;
2089}
2090
2091static void
2092igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2093{
2094 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2095 rxd->wb.upper.status_error = 0;
2096}
2097
2098static int
2099igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2100{
2101 struct mbuf *m;
2102 bus_dma_segment_t seg;
2103 bus_dmamap_t map;
2104 struct igb_rx_buf *rxbuf;
2105 int error, nseg;
2106
2107 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2108 if (m == NULL) {
2109 if (wait) {
2110 if_printf(&rxr->sc->arpcom.ac_if,
2111 "Unable to allocate RX mbuf\n");
2112 }
2113 return ENOBUFS;
2114 }
2115 m->m_len = m->m_pkthdr.len = MCLBYTES;
2116
2117 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2118 m_adj(m, ETHER_ALIGN);
2119
2120 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2121 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2122 if (error) {
2123 m_freem(m);
2124 if (wait) {
2125 if_printf(&rxr->sc->arpcom.ac_if,
2126 "Unable to load RX mbuf\n");
2127 }
2128 return error;
2129 }
2130
2131 rxbuf = &rxr->rx_buf[i];
2132 if (rxbuf->m_head != NULL)
2133 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2134
2135 map = rxbuf->map;
2136 rxbuf->map = rxr->rx_sparemap;
2137 rxr->rx_sparemap = map;
2138
2139 rxbuf->m_head = m;
2140 rxbuf->paddr = seg.ds_addr;
2141
2142 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2143 return 0;
2144}
2145
2146static int
2147igb_init_rx_ring(struct igb_rx_ring *rxr)
2148{
2149 int i;
2150
2151 /* Clear the ring contents */
2152 bzero(rxr->rx_base,
91b8700a 2153 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
1f7e3916
SZ
2154
2155 /* Now replenish the ring mbufs */
91b8700a 2156 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2157 int error;
2158
2159 error = igb_newbuf(rxr, i, TRUE);
2160 if (error)
2161 return error;
2162 }
2163
2164 /* Setup our descriptor indices */
2165 rxr->next_to_check = 0;
2166
2167 rxr->fmp = NULL;
2168 rxr->lmp = NULL;
2169 rxr->discard = FALSE;
2170
2171 return 0;
2172}
2173
2174static void
2175igb_init_rx_unit(struct igb_softc *sc)
2176{
2177 struct ifnet *ifp = &sc->arpcom.ac_if;
2178 struct e1000_hw *hw = &sc->hw;
2179 uint32_t rctl, rxcsum, srrctl = 0;
2180 int i;
2181
2182 /*
2183 * Make sure receives are disabled while setting
2184 * up the descriptor ring
2185 */
2186 rctl = E1000_READ_REG(hw, E1000_RCTL);
2187 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2188
2189#if 0
2190 /*
2191 ** Set up for header split
2192 */
2193 if (igb_header_split) {
2194 /* Use a standard mbuf for the header */
2195 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2196 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2197 } else
2198#endif
2199 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2200
2201 /*
2202 ** Set up for jumbo frames
2203 */
2204 if (ifp->if_mtu > ETHERMTU) {
2205 rctl |= E1000_RCTL_LPE;
2206#if 0
2207 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2208 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2209 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2210 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2211 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2212 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2213 }
2214 /* Set maximum packet len */
2215 psize = adapter->max_frame_size;
2216 /* are we on a vlan? */
2217 if (adapter->ifp->if_vlantrunk != NULL)
2218 psize += VLAN_TAG_SIZE;
2219 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2220#else
2221 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2222 rctl |= E1000_RCTL_SZ_2048;
2223#endif
2224 } else {
2225 rctl &= ~E1000_RCTL_LPE;
2226 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2227 rctl |= E1000_RCTL_SZ_2048;
2228 }
2229
2230 /* Setup the Base and Length of the Rx Descriptor Rings */
be922da6 2231 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2232 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2233 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2234 uint32_t rxdctl;
2235
2236 E1000_WRITE_REG(hw, E1000_RDLEN(i),
91b8700a 2237 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
1f7e3916
SZ
2238 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2239 (uint32_t)(bus_addr >> 32));
2240 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2241 (uint32_t)bus_addr);
2242 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2243 /* Enable this Queue */
2244 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2245 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2246 rxdctl &= 0xFFF00000;
2247 rxdctl |= IGB_RX_PTHRESH;
2248 rxdctl |= IGB_RX_HTHRESH << 8;
54691ff1
SZ
2249 /*
2250 * Don't set WTHRESH to a value above 1 on 82576, see:
2251 * 82576 specification update errata #26
2252 */
1f7e3916
SZ
2253 rxdctl |= IGB_RX_WTHRESH << 16;
2254 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2255 }
2256
8d6600da
SZ
2257 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2258 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2259
1f7e3916 2260 /*
8d6600da
SZ
2261 * Receive Checksum Offload for TCP and UDP
2262 *
2263 * Checksum offloading is also enabled if multiple receive
2264 * queue is to be supported, since we need it to figure out
2265 * fragments.
1f7e3916 2266 */
8d6600da
SZ
2267 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2268 /*
2269 * NOTE:
2270 * PCSD must be enabled to enable multiple
2271 * receive queues.
2272 */
2273 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2274 E1000_RXCSUM_PCSD;
2275 } else {
2276 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2277 E1000_RXCSUM_PCSD);
2278 }
2279 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2280
2281 if (IGB_ENABLE_HWRSS(sc)) {
2282 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
d1218435
SZ
2283 uint32_t reta_shift;
2284 int j, r;
8d6600da
SZ
2285
2286 /*
2287 * NOTE:
2288 * When we reach here, RSS has already been disabled
2289 * in igb_stop(), so we could safely configure RSS key
2290 * and redirect table.
2291 */
2292
2293 /*
2294 * Configure RSS key
2295 */
2296 toeplitz_get_key(key, sizeof(key));
2297 for (i = 0; i < IGB_NRSSRK; ++i) {
2298 uint32_t rssrk;
2299
2300 rssrk = IGB_RSSRK_VAL(key, i);
2301 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2302
2303 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
1f7e3916 2304 }
1f7e3916
SZ
2305
2306 /*
8d6600da
SZ
2307 * Configure RSS redirect table in following fashion:
2308 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2309 */
2310 reta_shift = IGB_RETA_SHIFT;
2311 if (hw->mac.type == e1000_82575)
2312 reta_shift = IGB_RETA_SHIFT_82575;
8d6600da 2313
d1218435
SZ
2314 r = 0;
2315 for (j = 0; j < IGB_NRETA; ++j) {
2316 uint32_t reta = 0;
8d6600da 2317
d1218435
SZ
2318 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2319 uint32_t q;
2320
be922da6 2321 q = (r % sc->rx_ring_inuse) << reta_shift;
d1218435
SZ
2322 reta |= q << (8 * i);
2323 ++r;
2324 }
2325 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2326 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2327 }
8d6600da
SZ
2328
2329 /*
2330 * Enable multiple receive queues.
2331 * Enable IPv4 RSS standard hash functions.
2332 * Disable RSS interrupt on 82575
2333 */
2334 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2335 E1000_MRQC_ENABLE_RSS_4Q |
2336 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2337 E1000_MRQC_RSS_FIELD_IPV4);
1f7e3916 2338 }
1f7e3916
SZ
2339
2340 /* Setup the Receive Control Register */
2341 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2342 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2343 E1000_RCTL_RDMTS_HALF |
2344 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2345 /* Strip CRC bytes. */
2346 rctl |= E1000_RCTL_SECRC;
2347 /* Make sure VLAN Filters are off */
2348 rctl &= ~E1000_RCTL_VFE;
2349 /* Don't store bad packets */
2350 rctl &= ~E1000_RCTL_SBP;
2351
2352 /* Enable Receives */
2353 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2354
2355 /*
2356 * Setup the HW Rx Head and Tail Descriptor Pointers
2357 * - needs to be after enable
2358 */
be922da6 2359 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2360 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2361
2362 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
91b8700a 2363 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
1f7e3916
SZ
2364 }
2365}
2366
2367static void
2368igb_rxeof(struct igb_rx_ring *rxr, int count)
2369{
2370 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2371 union e1000_adv_rx_desc *cur;
2372 uint32_t staterr;
2373 int i;
2374
2375 i = rxr->next_to_check;
2376 cur = &rxr->rx_base[i];
2377 staterr = le32toh(cur->wb.upper.status_error);
2378
2379 if ((staterr & E1000_RXD_STAT_DD) == 0)
2380 return;
2381
2382 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
8d6600da 2383 struct pktinfo *pi = NULL, pi0;
1f7e3916
SZ
2384 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2385 struct mbuf *m = NULL;
2386 boolean_t eop;
2387
2388 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2389 if (eop)
2390 --count;
2391
2392 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2393 !rxr->discard) {
2394 struct mbuf *mp = rxbuf->m_head;
8d6600da 2395 uint32_t hash, hashtype;
1f7e3916
SZ
2396 uint16_t vlan;
2397 int len;
2398
2399 len = le16toh(cur->wb.upper.length);
2400 if (rxr->sc->hw.mac.type == e1000_i350 &&
2401 (staterr & E1000_RXDEXT_STATERR_LB))
2402 vlan = be16toh(cur->wb.upper.vlan);
2403 else
2404 vlan = le16toh(cur->wb.upper.vlan);
2405
8d6600da
SZ
2406 hash = le32toh(cur->wb.lower.hi_dword.rss);
2407 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2408 E1000_RXDADV_RSSTYPE_MASK;
2409
2410 IGB_RSS_DPRINTF(rxr->sc, 10,
2411 "ring%d, hash 0x%08x, hashtype %u\n",
2412 rxr->me, hash, hashtype);
2413
1f7e3916
SZ
2414 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2415 BUS_DMASYNC_POSTREAD);
2416
2417 if (igb_newbuf(rxr, i, FALSE) != 0) {
2418 ifp->if_iqdrops++;
2419 goto discard;
2420 }
2421
2422 mp->m_len = len;
2423 if (rxr->fmp == NULL) {
2424 mp->m_pkthdr.len = len;
2425 rxr->fmp = mp;
2426 rxr->lmp = mp;
2427 } else {
2428 rxr->lmp->m_next = mp;
2429 rxr->lmp = rxr->lmp->m_next;
2430 rxr->fmp->m_pkthdr.len += len;
2431 }
2432
2433 if (eop) {
2434 m = rxr->fmp;
2435 rxr->fmp = NULL;
2436 rxr->lmp = NULL;
2437
2438 m->m_pkthdr.rcvif = ifp;
2439 ifp->if_ipackets++;
2440
2441 if (ifp->if_capenable & IFCAP_RXCSUM)
2442 igb_rxcsum(staterr, m);
2443
2444 if (staterr & E1000_RXD_STAT_VP) {
2445 m->m_pkthdr.ether_vlantag = vlan;
2446 m->m_flags |= M_VLANTAG;
2447 }
2448
1f7e3916 2449 if (ifp->if_capenable & IFCAP_RSS) {
8d6600da
SZ
2450 pi = igb_rssinfo(m, &pi0,
2451 hash, hashtype, staterr);
1f7e3916 2452 }
8d6600da
SZ
2453#ifdef IGB_RSS_DEBUG
2454 rxr->rx_packets++;
1f7e3916
SZ
2455#endif
2456 }
2457 } else {
2458 ifp->if_ierrors++;
2459discard:
2460 igb_setup_rxdesc(cur, rxbuf);
2461 if (!eop)
2462 rxr->discard = TRUE;
2463 else
2464 rxr->discard = FALSE;
2465 if (rxr->fmp != NULL) {
2466 m_freem(rxr->fmp);
2467 rxr->fmp = NULL;
2468 rxr->lmp = NULL;
2469 }
2470 m = NULL;
2471 }
2472
2473 if (m != NULL)
8d6600da 2474 ether_input_pkt(ifp, m, pi);
1f7e3916
SZ
2475
2476 /* Advance our pointers to the next descriptor. */
91b8700a 2477 if (++i == rxr->num_rx_desc)
1f7e3916
SZ
2478 i = 0;
2479
2480 cur = &rxr->rx_base[i];
2481 staterr = le32toh(cur->wb.upper.status_error);
2482 }
2483 rxr->next_to_check = i;
2484
2485 if (--i < 0)
91b8700a 2486 i = rxr->num_rx_desc - 1;
1f7e3916
SZ
2487 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2488}
2489
2490
2491static void
2492igb_set_vlan(struct igb_softc *sc)
2493{
2494 struct e1000_hw *hw = &sc->hw;
2495 uint32_t reg;
2496#if 0
2497 struct ifnet *ifp = sc->arpcom.ac_if;
2498#endif
2499
2500 if (sc->vf_ifp) {
2501 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2502 return;
2503 }
2504
2505 reg = E1000_READ_REG(hw, E1000_CTRL);
2506 reg |= E1000_CTRL_VME;
2507 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2508
2509#if 0
2510 /* Enable the Filter Table */
2511 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2512 reg = E1000_READ_REG(hw, E1000_RCTL);
2513 reg &= ~E1000_RCTL_CFIEN;
2514 reg |= E1000_RCTL_VFE;
2515 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2516 }
2517#endif
2518
2519 /* Update the frame size */
2520 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2521 sc->max_frame_size + VLAN_TAG_SIZE);
2522
2523#if 0
2524 /* Don't bother with table if no vlans */
2525 if ((adapter->num_vlans == 0) ||
2526 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2527 return;
2528 /*
2529 ** A soft reset zero's out the VFTA, so
2530 ** we need to repopulate it now.
2531 */
2532 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2533 if (adapter->shadow_vfta[i] != 0) {
2534 if (adapter->vf_ifp)
2535 e1000_vfta_set_vf(hw,
2536 adapter->shadow_vfta[i], TRUE);
2537 else
2538 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2539 i, adapter->shadow_vfta[i]);
2540 }
2541#endif
2542}
2543
2544static void
2545igb_enable_intr(struct igb_softc *sc)
2546{
9c0ecdcc
SZ
2547 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2548 lwkt_serialize_handler_enable(&sc->main_serialize);
2549 } else {
2550 int i;
2551
2552 for (i = 0; i < sc->msix_cnt; ++i) {
2553 lwkt_serialize_handler_enable(
2554 sc->msix_data[i].msix_serialize);
2555 }
2556 }
1f7e3916 2557
f6167a56 2558 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
9c0ecdcc
SZ
2559 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2560 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2561 else
2562 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56
SZ
2563 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2564 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
1f7e3916
SZ
2565 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2566 } else {
2567 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2568 }
2569 E1000_WRITE_FLUSH(&sc->hw);
2570}
2571
2572static void
2573igb_disable_intr(struct igb_softc *sc)
2574{
f6167a56 2575 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
1f7e3916
SZ
2576 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2577 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56 2578 }
1f7e3916
SZ
2579 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2580 E1000_WRITE_FLUSH(&sc->hw);
2581
9c0ecdcc
SZ
2582 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2583 lwkt_serialize_handler_disable(&sc->main_serialize);
2584 } else {
2585 int i;
2586
2587 for (i = 0; i < sc->msix_cnt; ++i) {
2588 lwkt_serialize_handler_disable(
2589 sc->msix_data[i].msix_serialize);
2590 }
2591 }
1f7e3916
SZ
2592}
2593
2594/*
2595 * Bit of a misnomer, what this really means is
2596 * to enable OS management of the system... aka
2597 * to disable special hardware management features
2598 */
2599static void
2600igb_get_mgmt(struct igb_softc *sc)
2601{
396b7048 2602 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2603 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2604 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2605
2606 /* disable hardware interception of ARP */
2607 manc &= ~E1000_MANC_ARP_EN;
2608
2609 /* enable receiving management packets to the host */
2610 manc |= E1000_MANC_EN_MNG2HOST;
2611 manc2h |= 1 << 5; /* Mng Port 623 */
2612 manc2h |= 1 << 6; /* Mng Port 664 */
2613 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2614 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2615 }
2616}
2617
2618/*
2619 * Give control back to hardware management controller
2620 * if there is one.
2621 */
2622static void
2623igb_rel_mgmt(struct igb_softc *sc)
2624{
396b7048 2625 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2626 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2627
2628 /* Re-enable hardware interception of ARP */
2629 manc |= E1000_MANC_ARP_EN;
2630 manc &= ~E1000_MANC_EN_MNG2HOST;
2631
2632 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2633 }
2634}
2635
2636/*
2637 * Sets CTRL_EXT:DRV_LOAD bit.
2638 *
2639 * For ASF and Pass Through versions of f/w this means that
2640 * the driver is loaded.
2641 */
2642static void
2643igb_get_hw_control(struct igb_softc *sc)
2644{
2645 uint32_t ctrl_ext;
2646
2647 if (sc->vf_ifp)
2648 return;
2649
2650 /* Let firmware know the driver has taken over */
2651 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2652 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2653 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2654}
2655
2656/*
2657 * Resets CTRL_EXT:DRV_LOAD bit.
2658 *
2659 * For ASF and Pass Through versions of f/w this means that the
2660 * driver is no longer loaded.
2661 */
2662static void
2663igb_rel_hw_control(struct igb_softc *sc)
2664{
2665 uint32_t ctrl_ext;
2666
2667 if (sc->vf_ifp)
2668 return;
2669
2670 /* Let firmware taken over control of h/w */
2671 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2672 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2673 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2674}
2675
2676static int
2677igb_is_valid_ether_addr(const uint8_t *addr)
2678{
2679 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2680
2681 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2682 return FALSE;
2683 return TRUE;
2684}
2685
2686/*
2687 * Enable PCI Wake On Lan capability
2688 */
2689static void
2690igb_enable_wol(device_t dev)
2691{
2692 uint16_t cap, status;
2693 uint8_t id;
2694
2695 /* First find the capabilities pointer*/
2696 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2697
2698 /* Read the PM Capabilities */
2699 id = pci_read_config(dev, cap, 1);
2700 if (id != PCIY_PMG) /* Something wrong */
2701 return;
2702
2703 /*
2704 * OK, we have the power capabilities,
2705 * so now get the status register
2706 */
2707 cap += PCIR_POWER_STATUS;
2708 status = pci_read_config(dev, cap, 2);
2709 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2710 pci_write_config(dev, cap, status, 2);
2711}
2712
2713static void
2714igb_update_stats_counters(struct igb_softc *sc)
2715{
2716 struct e1000_hw *hw = &sc->hw;
2717 struct e1000_hw_stats *stats;
2718 struct ifnet *ifp = &sc->arpcom.ac_if;
2719
2720 /*
2721 * The virtual function adapter has only a
2722 * small controlled set of stats, do only
2723 * those and return.
2724 */
2725 if (sc->vf_ifp) {
2726 igb_update_vf_stats_counters(sc);
2727 return;
2728 }
2729 stats = sc->stats;
2730
2731 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2732 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2733 stats->symerrs +=
2734 E1000_READ_REG(hw,E1000_SYMERRS);
2735 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2736 }
2737
2738 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2739 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2740 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2741 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2742
2743 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2744 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2745 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2746 stats->dc += E1000_READ_REG(hw, E1000_DC);
2747 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2748 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2749 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2750
2751 /*
2752 * For watchdog management we need to know if we have been
2753 * paused during the last interval, so capture that here.
2754 */
2755 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2756 stats->xoffrxc += sc->pause_frames;
2757 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2758 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2759 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2760 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2761 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2762 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2763 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2764 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2765 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2766 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2767 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2768 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2769
2770 /* For the 64-bit byte counters the low dword must be read first. */
2771 /* Both registers clear on the read of the high dword */
2772
2773 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2774 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2775 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2776 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2777
2778 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2779 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2780 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2781 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2782 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2783
2784 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2785 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2786
2787 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2788 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2789 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2790 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2791 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2792 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2793 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2794 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2795 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2796 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2797
2798 /* Interrupt Counts */
2799
2800 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2801 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2802 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2803 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2804 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2805 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2806 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2807 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2808 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2809
2810 /* Host to Card Statistics */
2811
2812 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2813 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2814 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2815 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2816 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2817 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2818 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2819 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2820 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2821 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2822 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2823 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2824 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2825 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2826
2827 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2828 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2829 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2830 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2831 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2832 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2833
2834 ifp->if_collisions = stats->colc;
2835
2836 /* Rx Errors */
2837 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2838 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2839
2840 /* Tx Errors */
2841 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2842
2843 /* Driver specific counters */
2844 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2845 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2846 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2847 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2848 sc->packet_buf_alloc_tx =
2849 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2850 sc->packet_buf_alloc_rx =
2851 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2852}
2853
2854static void
2855igb_vf_init_stats(struct igb_softc *sc)
2856{
2857 struct e1000_hw *hw = &sc->hw;
2858 struct e1000_vf_stats *stats;
2859
2860 stats = sc->stats;
2861 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2862 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2863 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2864 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2865 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2866}
2867
2868static void
2869igb_update_vf_stats_counters(struct igb_softc *sc)
2870{
2871 struct e1000_hw *hw = &sc->hw;
2872 struct e1000_vf_stats *stats;
2873
2874 if (sc->link_speed == 0)
2875 return;
2876
2877 stats = sc->stats;
2878 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2879 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2880 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2881 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2882 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2883}
2884
2885#ifdef DEVICE_POLLING
2886
2887static void
2888igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2889{
2890 struct igb_softc *sc = ifp->if_softc;
2891 uint32_t reg_icr;
2892
1f7e3916
SZ
2893 switch (cmd) {
2894 case POLL_REGISTER:
1f7e3916 2895 case POLL_DEREGISTER:
9c0ecdcc
SZ
2896 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2897 igb_init(sc);
1f7e3916
SZ
2898 break;
2899
2900 case POLL_AND_CHECK_STATUS:
9c0ecdcc 2901 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
2902 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2903 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2904 sc->hw.mac.get_link_status = 1;
2905 igb_update_link_status(sc);
2906 }
2907 /* FALL THROUGH */
2908 case POLL_ONLY:
9c0ecdcc 2909 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916 2910 if (ifp->if_flags & IFF_RUNNING) {
7d235eb5
SZ
2911 struct igb_tx_ring *txr;
2912 int i;
2913
be922da6 2914 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
2915 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2916
2917 lwkt_serialize_enter(&rxr->rx_serialize);
2918 igb_rxeof(rxr, count);
2919 lwkt_serialize_exit(&rxr->rx_serialize);
2920 }
1f7e3916 2921
7d235eb5
SZ
2922 txr = &sc->tx_rings[0];
2923 lwkt_serialize_enter(&txr->tx_serialize);
2924 igb_txeof(txr);
1f7e3916
SZ
2925 if (!ifq_is_empty(&ifp->if_snd))
2926 if_devstart(ifp);
7d235eb5 2927 lwkt_serialize_exit(&txr->tx_serialize);
1f7e3916
SZ
2928 }
2929 break;
2930 }
2931}
2932
2933#endif /* DEVICE_POLLING */
2934
2935static void
2936igb_intr(void *xsc)
2937{
2938 struct igb_softc *sc = xsc;
2939 struct ifnet *ifp = &sc->arpcom.ac_if;
f6167a56
SZ
2940 uint32_t eicr;
2941
7d235eb5 2942 ASSERT_SERIALIZED(&sc->main_serialize);
f6167a56
SZ
2943
2944 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2945
2946 if (eicr == 0)
2947 return;
2948
2949 if (ifp->if_flags & IFF_RUNNING) {
7d235eb5
SZ
2950 struct igb_tx_ring *txr;
2951 int i;
f6167a56 2952
be922da6 2953 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
2954 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2955
2956 if (eicr & rxr->rx_intr_mask) {
2957 lwkt_serialize_enter(&rxr->rx_serialize);
2958 igb_rxeof(rxr, -1);
2959 lwkt_serialize_exit(&rxr->rx_serialize);
2960 }
2961 }
2962
2963 txr = &sc->tx_rings[0];
2964 if (eicr & txr->tx_intr_mask) {
2965 lwkt_serialize_enter(&txr->tx_serialize);
2966 igb_txeof(txr);
f6167a56
SZ
2967 if (!ifq_is_empty(&ifp->if_snd))
2968 if_devstart(ifp);
7d235eb5 2969 lwkt_serialize_exit(&txr->tx_serialize);
f6167a56
SZ
2970 }
2971 }
2972
2973 if (eicr & E1000_EICR_OTHER) {
2974 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2975
2976 /* Link status change */
2977 if (icr & E1000_ICR_LSC) {
2978 sc->hw.mac.get_link_status = 1;
2979 igb_update_link_status(sc);
2980 }
2981 }
2982
2983 /*
2984 * Reading EICR has the side effect to clear interrupt mask,
2985 * so all interrupts need to be enabled here.
2986 */
2987 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2988}
2989
2990static void
9c0ecdcc 2991igb_intr_shared(void *xsc)
f6167a56
SZ
2992{
2993 struct igb_softc *sc = xsc;
2994 struct ifnet *ifp = &sc->arpcom.ac_if;
1f7e3916
SZ
2995 uint32_t reg_icr;
2996
7d235eb5 2997 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
2998
2999 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3000
3001 /* Hot eject? */
3002 if (reg_icr == 0xffffffff)
3003 return;
3004
3005 /* Definitely not our interrupt. */
3006 if (reg_icr == 0x0)
3007 return;
3008
3009 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3010 return;
3011
3012 if (ifp->if_flags & IFF_RUNNING) {
71b8b086
SZ
3013 if (reg_icr &
3014 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3015 int i;
7d235eb5 3016
71b8b086
SZ
3017 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3018 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1f7e3916 3019
71b8b086
SZ
3020 lwkt_serialize_enter(&rxr->rx_serialize);
3021 igb_rxeof(rxr, -1);
3022 lwkt_serialize_exit(&rxr->rx_serialize);
3023 }
7d235eb5
SZ
3024 }
3025
71b8b086
SZ
3026 if (reg_icr & E1000_ICR_TXDW) {
3027 struct igb_tx_ring *txr = &sc->tx_rings[0];
3028
3029 lwkt_serialize_enter(&txr->tx_serialize);
3030 igb_txeof(txr);
3031 if (!ifq_is_empty(&ifp->if_snd))
3032 if_devstart(ifp);
3033 lwkt_serialize_exit(&txr->tx_serialize);
3034 }
1f7e3916
SZ
3035 }
3036
3037 /* Link status change */
3038 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3039 sc->hw.mac.get_link_status = 1;
3040 igb_update_link_status(sc);
3041 }
3042
3043 if (reg_icr & E1000_ICR_RXO)
3044 sc->rx_overruns++;
3045}
3046
3047static int
1f7e3916
SZ
3048igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3049{
3050 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3051 bus_dmamap_t map;
3052 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3053 union e1000_adv_tx_desc *txd = NULL;
3054 struct mbuf *m_head = *m_headp;
b6220144
SZ
3055 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3056 int maxsegs, nsegs, i, j, error, last = 0;
1f7e3916
SZ
3057 uint32_t hdrlen = 0;
3058
23f6ffe4
SZ
3059 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3060 error = igb_tso_pullup(txr, m_headp);
3061 if (error)
3062 return error;
3063 m_head = *m_headp;
3064 }
3065
1f7e3916
SZ
3066 /* Set basic descriptor constants */
3067 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3068 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3069 if (m_head->m_flags & M_VLANTAG)
3070 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3071
3072 /*
3073 * Map the packet for DMA.
1f7e3916 3074 */
b6220144 3075 tx_buf = &txr->tx_buf[txr->next_avail_desc];
1f7e3916
SZ
3076 tx_buf_mapped = tx_buf;
3077 map = tx_buf->map;
3078
b6220144
SZ
3079 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3080 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
1f7e3916
SZ
3081 if (maxsegs > IGB_MAX_SCATTER)
3082 maxsegs = IGB_MAX_SCATTER;
3083
3084 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3085 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3086 if (error) {
3087 if (error == ENOBUFS)
3088 txr->sc->mbuf_defrag_failed++;
3089 else
3090 txr->sc->no_tx_dma_setup++;
3091
3092 m_freem(*m_headp);
3093 *m_headp = NULL;
3094 return error;
3095 }
3096 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3097
3098 m_head = *m_headp;
3099
1f7e3916 3100 /*
66c68b4b
SZ
3101 * Set up the TX context descriptor, if any hardware offloading is
3102 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3103 * TX descriptor.
3104 *
3105 * Unlike these chips' predecessors (em/emx), TX context descriptor
3106 * will _not_ interfere TX data fetching pipelining.
1f7e3916
SZ
3107 */
3108 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
23f6ffe4
SZ
3109 igb_tso_ctx(txr, m_head, &hdrlen);
3110 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3111 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3112 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3113 txr->tx_nsegs++;
3114 } else if (igb_txcsum_ctx(txr, m_head)) {
48faa653
SZ
3115 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3116 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
1f7e3916
SZ
3117 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3118 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
b6220144 3119 txr->tx_nsegs++;
1f7e3916 3120 }
1f7e3916 3121
b6220144
SZ
3122 txr->tx_nsegs += nsegs;
3123 if (txr->tx_nsegs >= txr->intr_nsegs) {
3124 /*
3125 * Report Status (RS) is turned on every intr_nsegs
3126 * descriptors (roughly).
3127 */
3128 txr->tx_nsegs = 0;
3129 cmd_rs = E1000_ADVTXD_DCMD_RS;
3130 }
3131
1f7e3916
SZ
3132 /* Calculate payload length */
3133 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3134 << E1000_ADVTXD_PAYLEN_SHIFT);
3135
3136 /* 82575 needs the queue index added */
3137 if (txr->sc->hw.mac.type == e1000_82575)
3138 olinfo_status |= txr->me << 4;
3139
3140 /* Set up our transmit descriptors */
3141 i = txr->next_avail_desc;
3142 for (j = 0; j < nsegs; j++) {
3143 bus_size_t seg_len;
3144 bus_addr_t seg_addr;
3145
3146 tx_buf = &txr->tx_buf[i];
3147 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3148 seg_addr = segs[j].ds_addr;
3149 seg_len = segs[j].ds_len;
3150
3151 txd->read.buffer_addr = htole64(seg_addr);
3152 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3153 txd->read.olinfo_status = htole32(olinfo_status);
3154 last = i;
91b8700a 3155 if (++i == txr->num_tx_desc)
1f7e3916
SZ
3156 i = 0;
3157 tx_buf->m_head = NULL;
1f7e3916
SZ
3158 }
3159
3160 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3161 txr->next_avail_desc = i;
3162 txr->tx_avail -= nsegs;
3163
3164 tx_buf->m_head = m_head;
3165 tx_buf_mapped->map = tx_buf->map;
3166 tx_buf->map = map;
3167
3168 /*
b6220144 3169 * Last Descriptor of Packet needs End Of Packet (EOP)
1f7e3916 3170 */
b6220144 3171 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
1f7e3916
SZ
3172
3173 /*
3174 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3175 * that this frame is available to transmit.
3176 */
3177 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3178 ++txr->tx_packets;
3179
3180 return 0;
3181}
3182
3183static void
3184igb_start(struct ifnet *ifp)
3185{
3186 struct igb_softc *sc = ifp->if_softc;
27866bf1 3187 struct igb_tx_ring *txr = &sc->tx_rings[0];
1f7e3916
SZ
3188 struct mbuf *m_head;
3189
7d235eb5 3190 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3191
9c0ecdcc 3192 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1f7e3916
SZ
3193 return;
3194
3195 if (!sc->link_active) {
3196 ifq_purge(&ifp->if_snd);
3197 return;
3198 }
3199
b6220144 3200 if (!IGB_IS_NOT_OACTIVE(txr))
1f7e3916
SZ
3201 igb_txeof(txr);
3202
3203 while (!ifq_is_empty(&ifp->if_snd)) {
b6220144 3204 if (IGB_IS_OACTIVE(txr)) {
1f7e3916
SZ
3205 ifp->if_flags |= IFF_OACTIVE;
3206 /* Set watchdog on */
3207 ifp->if_timer = 5;
3208 break;
3209 }
3210
3211 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3212 if (m_head == NULL)
3213 break;
3214
3215 if (igb_encap(txr, &m_head)) {
3216 ifp->if_oerrors++;
3217 continue;
3218 }
3219
3220 /* Send a copy of the frame to the BPF listener */
3221 ETHER_BPF_MTAP(ifp, m_head);
3222 }
3223}
3224
3225static void
3226igb_watchdog(struct ifnet *ifp)
3227{
3228 struct igb_softc *sc = ifp->if_softc;
27866bf1 3229 struct igb_tx_ring *txr = &sc->tx_rings[0];
1f7e3916
SZ
3230
3231 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3232
3233 /*
3234 * If flow control has paused us since last checking
3235 * it invalidates the watchdog timing, so dont run it.
3236 */
3237 if (sc->pause_frames) {
3238 sc->pause_frames = 0;
3239 ifp->if_timer = 5;
3240 return;
3241 }
3242
3243 if_printf(ifp, "Watchdog timeout -- resetting\n");
3244 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3245 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3246 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3247 if_printf(ifp, "TX(%d) desc avail = %d, "
3248 "Next TX to Clean = %d\n",
3249 txr->me, txr->tx_avail, txr->next_to_clean);
3250
3251 ifp->if_oerrors++;
3252 sc->watchdog_events++;
3253
3254 igb_init(sc);
3255 if (!ifq_is_empty(&ifp->if_snd))
3256 if_devstart(ifp);
3257}
3258
3259static void
9c0ecdcc 3260igb_set_eitr(struct igb_softc *sc, int idx, int rate)
1f7e3916 3261{
9c0ecdcc 3262 uint32_t eitr = 0;
1f7e3916 3263
9c0ecdcc 3264 if (rate > 0) {
1f7e3916 3265 if (sc->hw.mac.type == e1000_82575) {
9c0ecdcc 3266 eitr = 1000000000 / 256 / rate;
1f7e3916
SZ
3267 /*
3268 * NOTE:
3269 * Document is wrong on the 2 bits left shift
3270 */
3271 } else {
9c0ecdcc 3272 eitr = 1000000 / rate;
d4beffa9
SZ
3273 eitr <<= IGB_EITR_INTVL_SHIFT;
3274 }
3275
3276 if (eitr == 0) {
3277 /* Don't disable it */
3278 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3279 } else if (eitr > IGB_EITR_INTVL_MASK) {
3280 /* Don't allow it to be too large */
3281 eitr = IGB_EITR_INTVL_MASK;
1f7e3916 3282 }
1f7e3916
SZ
3283 }
3284 if (sc->hw.mac.type == e1000_82575)
9c0ecdcc 3285 eitr |= eitr << 16;
1f7e3916 3286 else
9c0ecdcc
SZ
3287 eitr |= E1000_EITR_CNT_IGNR;
3288 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
1f7e3916
SZ
3289}
3290
3291static int
3292igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3293{
3294 struct igb_softc *sc = (void *)arg1;
3295 struct ifnet *ifp = &sc->arpcom.ac_if;
3296 int error, intr_rate;
3297
3298 intr_rate = sc->intr_rate;
3299 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3300 if (error || req->newptr == NULL)
3301 return error;
3302 if (intr_rate < 0)
3303 return EINVAL;
3304
3305 ifnet_serialize_all(ifp);
3306
3307 sc->intr_rate = intr_rate;
3308 if (ifp->if_flags & IFF_RUNNING)
9c0ecdcc
SZ
3309 igb_set_eitr(sc, 0, sc->intr_rate);
3310
3311 if (bootverbose)
3312 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
1f7e3916
SZ
3313
3314 ifnet_deserialize_all(ifp);
3315
9c0ecdcc
SZ
3316 return 0;
3317}
3318
3319static int
3320igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3321{
3322 struct igb_msix_data *msix = (void *)arg1;
3323 struct igb_softc *sc = msix->msix_sc;
3324 struct ifnet *ifp = &sc->arpcom.ac_if;
3325 int error, msix_rate;
3326
3327 msix_rate = msix->msix_rate;
3328 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3329 if (error || req->newptr == NULL)
3330 return error;
3331 if (msix_rate < 0)
3332 return EINVAL;
3333
3334 lwkt_serialize_enter(msix->msix_serialize);
3335
3336 msix->msix_rate = msix_rate;
3337 if (ifp->if_flags & IFF_RUNNING)
3338 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3339
3340 if (bootverbose) {
3341 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3342 msix->msix_rate);
3343 }
3344
3345 lwkt_serialize_exit(msix->msix_serialize);
3346
1f7e3916
SZ
3347 return 0;
3348}
b6220144
SZ
3349
3350static int
3351igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3352{
3353 struct igb_softc *sc = (void *)arg1;
3354 struct ifnet *ifp = &sc->arpcom.ac_if;
27866bf1 3355 struct igb_tx_ring *txr = &sc->tx_rings[0];
b6220144
SZ
3356 int error, nsegs;
3357
3358 nsegs = txr->intr_nsegs;
3359 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3360 if (error || req->newptr == NULL)
3361 return error;
3362 if (nsegs <= 0)
3363 return EINVAL;
3364
3365 ifnet_serialize_all(ifp);
3366
91b8700a 3367 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
b6220144
SZ
3368 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3369 error = EINVAL;
3370 } else {
3371 error = 0;
3372 txr->intr_nsegs = nsegs;
3373 }
3374
3375 ifnet_deserialize_all(ifp);
3376
3377 return error;
3378}
f6167a56
SZ
3379
3380static void
3381igb_init_intr(struct igb_softc *sc)
3382{
be922da6 3383 igb_set_intr_mask(sc);
9c0ecdcc
SZ
3384
3385 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
f6167a56 3386 igb_init_unshared_intr(sc);
9c0ecdcc
SZ
3387
3388 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3389 igb_set_eitr(sc, 0, sc->intr_rate);
3390 } else {
3391 int i;
3392
3393 for (i = 0; i < sc->msix_cnt; ++i)
3394 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3395 }
f6167a56
SZ
3396}
3397
3398static void
3399igb_init_unshared_intr(struct igb_softc *sc)
3400{
3401 struct e1000_hw *hw = &sc->hw;
3402 const struct igb_rx_ring *rxr;
3403 const struct igb_tx_ring *txr;
3404 uint32_t ivar, index;
3405 int i;
3406
3407 /*
3408 * Enable extended mode
3409 */
3410 if (sc->hw.mac.type != e1000_82575) {
9c0ecdcc
SZ
3411 uint32_t gpie;
3412 int ivar_max;
3413
3414 gpie = E1000_GPIE_NSICR;
3415 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3416 gpie |= E1000_GPIE_MSIX_MODE |
3417 E1000_GPIE_EIAME |
3418 E1000_GPIE_PBA;
3419 }
3420 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3421
3422 /*
3423 * Clear IVARs
3424 */
3425 switch (sc->hw.mac.type) {
3426 case e1000_82580:
3427 ivar_max = IGB_MAX_IVAR_82580;
3428 break;
3429
3430 case e1000_i350:
3431 ivar_max = IGB_MAX_IVAR_I350;
3432 break;
3433
3434 case e1000_vfadapt:
3435 case e1000_vfadapt_i350:
3436 ivar_max = IGB_MAX_IVAR_VF;
3437 break;
3438
3439 case e1000_82576:
3440 ivar_max = IGB_MAX_IVAR_82576;
3441 break;
3442
3443 default:
3444 panic("unknown mac type %d\n", sc->hw.mac.type);
3445 }
3446 for (i = 0; i < ivar_max; ++i)
3447 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3448 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
f6167a56
SZ
3449 } else {
3450 uint32_t tmp;
3451
9c0ecdcc
SZ
3452 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3453 ("82575 w/ MSI-X"));
f6167a56
SZ
3454 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3455 tmp |= E1000_CTRL_EXT_IRCA;
3456 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3457 }
3458
3459 /*
3460 * Map TX/RX interrupts to EICR
3461 */
3462 switch (sc->hw.mac.type) {
3463 case e1000_82580:
3464 case e1000_i350:
3465 case e1000_vfadapt:
3466 case e1000_vfadapt_i350:
3467 /* RX entries */
be922da6 3468 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ
3469 rxr = &sc->rx_rings[i];
3470
3471 index = i >> 1;
3472 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3473
3474 if (i & 1) {
3475 ivar &= 0xff00ffff;
3476 ivar |=
3477 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3478 } else {
3479 ivar &= 0xffffff00;
3480 ivar |=
3481 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3482 }
3483 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3484 }
3485 /* TX entries */
27866bf1 3486 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f6167a56
SZ
3487 txr = &sc->tx_rings[i];
3488
3489 index = i >> 1;
3490 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3491
3492 if (i & 1) {
3493 ivar &= 0x00ffffff;
3494 ivar |=
3495 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3496 } else {
3497 ivar &= 0xffff00ff;
3498 ivar |=
3499 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3500 }
3501 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3502 }
9c0ecdcc
SZ
3503 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3504 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3505 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3506 }
f6167a56
SZ
3507 break;
3508
3509 case e1000_82576:
3510 /* RX entries */
be922da6 3511 for (i = 0; i < sc->rx_ring_inuse; ++i) {
f6167a56
SZ
3512 rxr = &sc->rx_rings[i];
3513
3514 index = i & 0x7; /* Each IVAR has two entries */
3515 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3516
3517 if (i < 8) {
3518 ivar &= 0xffffff00;
3519 ivar |=
3520 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3521 } else {
3522 ivar &= 0xff00ffff;
3523 ivar |=
3524 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3525 }
3526 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3527 }
3528 /* TX entries */
27866bf1 3529 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f6167a56
SZ
3530 txr = &sc->tx_rings[i];
3531
3532 index = i & 0x7; /* Each IVAR has two entries */
3533 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3534
3535 if (i < 8) {
3536 ivar &= 0xffff00ff;
3537 ivar |=
3538 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3539 } else {
3540 ivar &= 0x00ffffff;
3541 ivar |=
3542 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3543 }
3544 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3545 }
9c0ecdcc
SZ
3546 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3547 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3548 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3549 }
f6167a56
SZ
3550 break;
3551
3552 case e1000_82575:
3553 /*
3554 * Enable necessary interrupt bits.
3555 *
3556 * The name of the register is confusing; in addition to
3557 * configuring the first vector of MSI-X, it also configures
3558 * which bits of EICR could be set by the hardware even when
3559 * MSI or line interrupt is used; it thus controls interrupt
3560 * generation. It MUST be configured explicitly; the default
3561 * value mentioned in the datasheet is wrong: RX queue0 and
3562 * TX queue0 are NOT enabled by default.
3563 */
3564 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3565 break;
3566
3567 default:
9c0ecdcc 3568 panic("unknown mac type %d\n", sc->hw.mac.type);
f6167a56 3569 }
f6167a56
SZ
3570}
3571
3572static int
3573igb_setup_intr(struct igb_softc *sc)
3574{
3575 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 3576 int error;
f6167a56 3577
9c0ecdcc
SZ
3578 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3579 return igb_msix_setup(sc);
f6167a56 3580
f6167a56 3581 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
9c0ecdcc 3582 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
7d235eb5 3583 sc, &sc->intr_tag, &sc->main_serialize);
f6167a56
SZ
3584 if (error) {
3585 device_printf(sc->dev, "Failed to register interrupt handler");
3586 return error;
3587 }
3588
3589 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3590 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3591
3592 return 0;
3593}
3594
3595static void
9c0ecdcc 3596igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
f6167a56
SZ
3597{
3598 if (txr->sc->hw.mac.type == e1000_82575) {
3599 txr->tx_intr_bit = 0; /* unused */
3600 switch (txr->me) {
3601 case 0:
3602 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3603 break;
3604 case 1:
3605 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3606 break;
3607 case 2:
3608 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3609 break;
3610 case 3:
3611 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3612 break;
3613 default:
3614 panic("unsupported # of TX ring, %d\n", txr->me);
3615 }
3616 } else {
8d6600da
SZ
3617 int intr_bit = *intr_bit0;
3618
3619 txr->tx_intr_bit = intr_bit % intr_bitmax;
f6167a56 3620 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
8d6600da
SZ
3621
3622 *intr_bit0 = intr_bit + 1;
f6167a56
SZ
3623 }
3624}
3625
3626static void
9c0ecdcc 3627igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
f6167a56
SZ
3628{
3629 if (rxr->sc->hw.mac.type == e1000_82575) {
3630 rxr->rx_intr_bit = 0; /* unused */
3631 switch (rxr->me) {
3632 case 0:
3633 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3634 break;
3635 case 1:
3636 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3637 break;
3638 case 2:
3639 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3640 break;
3641 case 3:
3642 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3643 break;
3644 default:
3645 panic("unsupported # of RX ring, %d\n", rxr->me);
3646 }
3647 } else {
8d6600da
SZ
3648 int intr_bit = *intr_bit0;
3649
3650 rxr->rx_intr_bit = intr_bit % intr_bitmax;
f6167a56 3651 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
8d6600da
SZ
3652
3653 *intr_bit0 = intr_bit + 1;
f6167a56
SZ
3654 }
3655}
7d235eb5
SZ
3656
3657static void
3658igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3659{
3660 struct igb_softc *sc = ifp->if_softc;
3661
3662 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3663 sc->tx_serialize, sc->rx_serialize, slz);
3664}
3665
3666static void
3667igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3668{
3669 struct igb_softc *sc = ifp->if_softc;
3670
3671 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3672 sc->tx_serialize, sc->rx_serialize, slz);
3673}
3674
3675static int
3676igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3677{
3678 struct igb_softc *sc = ifp->if_softc;
3679
3680 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3681 sc->tx_serialize, sc->rx_serialize, slz);
3682}
3683
7d235eb5
SZ
3684#ifdef INVARIANTS
3685
3686static void
3687igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3688 boolean_t serialized)
3689{
3690 struct igb_softc *sc = ifp->if_softc;
3691
3692 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3693 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3694}
3695
3696#endif /* INVARIANTS */
be922da6
SZ
3697
3698static void
3699igb_set_intr_mask(struct igb_softc *sc)
3700{
3701 int i;
3702
9c0ecdcc 3703 sc->intr_mask = sc->sts_intr_mask;
be922da6
SZ
3704 for (i = 0; i < sc->rx_ring_inuse; ++i)
3705 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3706 for (i = 0; i < sc->tx_ring_cnt; ++i)
3707 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
9c0ecdcc
SZ
3708 if (bootverbose)
3709 device_printf(sc->dev, "intr mask 0x%08x\n", sc->intr_mask);
be922da6 3710}
3c7cc5e2
SZ
3711
3712static int
3713igb_alloc_intr(struct igb_softc *sc)
3714{
9c0ecdcc 3715 int i, intr_bit, intr_bitmax;
3c7cc5e2
SZ
3716 u_int intr_flags;
3717
9c0ecdcc
SZ
3718 igb_msix_try_alloc(sc);
3719 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3720 goto done;
3721
3722 /*
3723 * Allocate MSI/legacy interrupt resource
3724 */
3c7cc5e2
SZ
3725 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3726 &sc->intr_rid, &intr_flags);
3727
677d7b99
SZ
3728 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3729 int unshared;
3730
3731 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3732 if (!unshared) {
3733 sc->flags |= IGB_FLAG_SHARED_INTR;
3734 if (bootverbose)
3735 device_printf(sc->dev, "IRQ shared\n");
3736 } else {
3737 intr_flags &= ~RF_SHAREABLE;
3738 if (bootverbose)
3739 device_printf(sc->dev, "IRQ unshared\n");
3740 }
3741 }
3742
3c7cc5e2
SZ
3743 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3744 &sc->intr_rid, intr_flags);
3745 if (sc->intr_res == NULL) {
3746 device_printf(sc->dev, "Unable to allocate bus resource: "
3747 "interrupt\n");
3748 return ENXIO;
3749 }
9c0ecdcc
SZ
3750
3751 /*
3752 * Setup MSI/legacy interrupt mask
3753 */
3754 switch (sc->hw.mac.type) {
3755 case e1000_82575:
3756 intr_bitmax = IGB_MAX_TXRXINT_82575;
3757 break;
3758 case e1000_82580:
3759 intr_bitmax = IGB_MAX_TXRXINT_82580;
3760 break;
3761 case e1000_i350:
3762 intr_bitmax = IGB_MAX_TXRXINT_I350;
3763 break;
3764 case e1000_82576:
3765 intr_bitmax = IGB_MAX_TXRXINT_82576;
3766 break;
3767 default:
3768 intr_bitmax = IGB_MIN_TXRXINT;
3769 break;
3770 }
3771 intr_bit = 0;
3772 for (i = 0; i < sc->tx_ring_cnt; ++i)
3773 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3774 for (i = 0; i < sc->rx_ring_cnt; ++i)
3775 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3776 sc->sts_intr_bit = 0;
3777 sc->sts_intr_mask = E1000_EICR_OTHER;
3778
3779 /* Initialize interrupt rate */
3780 sc->intr_rate = IGB_INTR_RATE;
3781done:
3782 igb_set_ring_inuse(sc, FALSE);
3783 igb_set_intr_mask(sc);
3c7cc5e2
SZ
3784 return 0;
3785}
3786
3787static void
3788igb_free_intr(struct igb_softc *sc)
3789{
9c0ecdcc
SZ
3790 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3791 if (sc->intr_res != NULL) {
3792 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3793 sc->intr_res);
3794 }
3795 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3796 pci_release_msi(sc->dev);
3797 } else {
3798 igb_msix_free(sc, TRUE);
3799 }
3800}
3801
3802static void
3803igb_teardown_intr(struct igb_softc *sc)
3804{
3805 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3806 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3807 else
3808 igb_msix_teardown(sc, sc->msix_cnt);
3809}
3810
3811static void
3812igb_msix_try_alloc(struct igb_softc *sc)
3813{
3814 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3815 int i, x, error;
3816 struct igb_msix_data *msix;
3817 boolean_t aggregate, setup = FALSE;
3818
3819 /*
fea3f48a
SZ
3820 * Don't enable MSI-X on 82575, see:
3821 * 82575 specification update errata #25
9c0ecdcc
SZ
3822 */
3823 if (sc->hw.mac.type == e1000_82575)
3824 return;
3825
3826 /* Don't enable MSI-X on VF */
3827 if (sc->vf_ifp)
3828 return;
3829
3830 msix_enable = device_getenv_int(sc->dev, "msix.enable",
3831 igb_msix_enable);
3832 if (!msix_enable)
3833 return;
3834
3835 msix_cnt = pci_msix_count(sc->dev);
3836#ifdef IGB_MSIX_DEBUG
3837 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3838#endif
3839 if (msix_cnt <= 1) {
3840 /* One MSI-X model does not make sense */
3841 return;
3842 }
3843
3844 i = 0;
3845 while ((1 << (i + 1)) <= msix_cnt)
3846 ++i;
3847 msix_cnt2 = 1 << i;
3848
3849 if (bootverbose) {
3850 device_printf(sc->dev, "MSI-X count %d/%d\n",
3851 msix_cnt2, msix_cnt);
3852 }
3853
3854 KKASSERT(msix_cnt2 <= msix_cnt);
3855 if (msix_cnt == msix_cnt2) {
3856 /* We need at least one MSI-X for link status */
3857 msix_cnt2 >>= 1;
3858 if (msix_cnt2 <= 1) {
3859 /* One MSI-X for RX/TX does not make sense */
3860 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3861 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3862 return;
3863 }
3864 KKASSERT(msix_cnt > msix_cnt2);
3865
3866 if (bootverbose) {
3867 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",