em: Add TSO support for certain PCIe chips
[dragonfly.git] / sys / dev / netif / em / if_em.h
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1/*
2 * Copyright (c) 2001-2008, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
984263bc 31
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32#ifndef _IF_EM_H_
33#define _IF_EM_H_
984263bc 34
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35/* Tunables */
36
37/*
1eca7b82 38 * EM_TXD: Maximum number of Transmit Descriptors
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39 * Valid Range: 256 for 82542 and 82543-based adapters
40 * 256-4096 for others
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41 * Default Value: 256
42 * This value is the number of transmit descriptors allocated by the driver.
43 * Increasing this value allows the driver to queue more transmits. Each
44 * descriptor is 16 bytes.
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45 * Since TDLEN should be multiple of 128bytes, the number of transmit
46 * desscriptors should meet the following condition.
9c80d176 47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
984263bc 48 */
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49#define EM_MIN_TXD 256
50#define EM_MAX_TXD_82543 EM_MIN_TXD
9c80d176 51#define EM_MAX_TXD 4096
df2de25f 52#define EM_DEFAULT_TXD 512
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53
54/*
1eca7b82 55 * EM_RXD - Maximum number of receive Descriptors
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56 * Valid Range: 256 for 82542 and 82543-based adapters
57 * 256-4096 for others
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58 * Default Value: 256
59 * This value is the number of receive descriptors allocated by the driver.
60 * Increasing this value allows the driver to buffer more incoming packets.
61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
62 * descriptor. The maximum MTU size is 16110.
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63 * Since TDLEN should be multiple of 128bytes, the number of transmit
64 * desscriptors should meet the following condition.
9c80d176 65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
984263bc 66 */
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67#define EM_MIN_RXD 256
68#define EM_MAX_RXD_82543 EM_MIN_RXD
9c80d176 69#define EM_MAX_RXD 4096
df2de25f 70#define EM_DEFAULT_RXD 512
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71
72/*
9ccd8c1f 73 * EM_TIDV - Transmit Interrupt Delay Value
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74 * Valid Range: 0-65535 (0=off)
75 * Default Value: 64
76 * This value delays the generation of transmit interrupts in units of
77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
78 * efficiency if properly tuned for specific network traffic. If the
79 * system is reporting dropped transmits, this value may be set too high
80 * causing the driver to run out of available transmit descriptors.
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81 *
82 * NOTE:
83 * It is not used. In DragonFly the TX interrupt moderation is done by
84 * conditionally setting RS bit in TX descriptors. See the description
85 * in struct adapter.
984263bc 86 */
9c80d176 87#define EM_TIDV 64
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88
89/*
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90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
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92 * Valid Range: 0-65535 (0=off)
93 * Default Value: 64
94 * This value, in units of 1.024 microseconds, limits the delay in which a
0d366ee7 95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
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96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
0d366ee7 98 * along with EM_TIDV, may improve traffic throughput in specific
984263bc 99 * network conditions.
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100 *
101 * NOTE:
102 * It is not used. In DragonFly the TX interrupt moderation is done by
103 * conditionally setting RS bit in TX descriptors. See the description
104 * in struct adapter.
984263bc 105 */
9c80d176 106#define EM_TADV 64
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107
108/*
2cc36323 109 * Receive Interrupt Delay Timer (Packet Timer)
984263bc 110 *
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111 * NOTE:
112 * RDTR and RADV are deprecated; use ITR instead. They are only used to
113 * workaround hardware bug on certain 82573 based NICs.
984263bc 114 */
2cc36323 115#define EM_RDTR_82573 32
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116
117/*
0d366ee7 118 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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119 *
120 * NOTE:
121 * RDTR and RADV are deprecated; use ITR instead. They are only used to
122 * workaround hardware bug on certain 82573 based NICs.
984263bc 123 */
2cc36323 124#define EM_RADV_82573 64
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125
126/*
127 * This parameter controls the duration of transmit watchdog timer.
128 */
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129#define EM_TX_TIMEOUT 5
130
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131/* One for TX csum offloading desc, the other 2 are reserved */
132#define EM_TX_RESERVED 3
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133
134/* Large enough for 16K jumbo frame */
135#define EM_TX_SPARE 8
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136/* Large enough for 64K jumbo frame */
137#define EM_TX_SPARE_TSO 33
9c80d176 138
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139#define EM_TX_OACTIVE_MAX 64
140
9c80d176 141/* Interrupt throttle rate */
3245f71e 142#define EM_DEFAULT_ITR 6000
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143
144/*
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145 * This parameter controls whether or not autonegotation is enabled.
146 * 0 - Disable autonegotiation
147 * 1 - Enable autonegotiation
148 */
9c80d176 149#define DO_AUTO_NEG 1
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150
151/*
152 * This parameter control whether or not the driver will wait for
153 * autonegotiation to complete.
154 * 1 - Wait for autonegotiation to complete
155 * 0 - Don't wait for autonegotiation to complete
156 */
9c80d176 157#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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158
159/* Tunables -- End */
160
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161#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
162 ADVERTISE_10_FULL | \
163 ADVERTISE_100_HALF | \
164 ADVERTISE_100_FULL | \
165 ADVERTISE_1000_FULL)
984263bc 166
9c80d176 167#define AUTO_ALL_MODES 0
984263bc 168
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169/* PHY master/slave setting */
170#define EM_MASTER_SLAVE e1000_ms_hw_default
984263bc 171
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172/*
173 * Micellaneous constants
174 */
175#define EM_VENDOR_ID 0x8086
87307ba1 176
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177#define EM_BAR_MEM PCIR_BAR(0)
178#define EM_BAR_FLASH PCIR_BAR(1)
179
180#define EM_JUMBO_PBA 0x00000028
181#define EM_DEFAULT_PBA 0x00000030
182#define EM_SMARTSPEED_DOWNSHIFT 3
183#define EM_SMARTSPEED_MAX 15
184#define EM_MAX_INTR 10
185
186#define MAX_NUM_MULTICAST_ADDRESSES 128
187#define PCI_ANY_ID (~0U)
188#define EM_FC_PAUSE_TIME 1000
189#define EM_EEPROM_APME 0x400;
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190
191/*
192 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
193 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
194 * also optimize cache line size effect. H/W supports up to cache line size 128.
195 */
196#define EM_DBA_ALIGN 128
197
9c80d176 198#define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
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199
200/* PCI Config defines */
201#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
202#define EM_BAR_TYPE_MASK 0x00000001
203#define EM_BAR_TYPE_MMEM 0x00000000
204#define EM_BAR_TYPE_IO 0x00000001
205#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
206#define EM_BAR_MEM_TYPE_MASK 0x00000006
207#define EM_BAR_MEM_TYPE_32BIT 0x00000000
208#define EM_BAR_MEM_TYPE_64BIT 0x00000004
209
9c80d176 210#define EM_MAX_SCATTER 64
0bbb59f3 211#define EM_TSO_SIZE (IP_MAXPACKET + \
9c80d176 212 sizeof(struct ether_vlan_header))
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213#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
214#define ETH_ZLEN 60
215
216#define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
9c80d176 217
87307ba1 218/*
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219 * 82574 has a nonstandard address for EIAC
220 * and since its only used in MSIX, and in
221 * the em driver only 82574 uses MSIX we can
222 * solve it just using this define.
87307ba1 223 */
9c80d176 224#define EM_EIAC 0x000DC
984263bc 225
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226/* Used in for 82547 10Mb Half workaround */
227#define EM_PBA_BYTES_SHIFT 0xA
228#define EM_TX_HEAD_ADDR_SHIFT 7
229#define EM_PBA_TX_MASK 0xFFFF0000
230#define EM_FIFO_HDR 0x10
231#define EM_82547_PKT_THRESH 0x3e0
984263bc 232
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233/*
234 * Bus dma allocation structure used by
f7b52b45 235 * em_dma_malloc and em_dma_free.
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236 */
237struct em_dma_alloc {
238 bus_addr_t dma_paddr;
9c80d176 239 void *dma_vaddr;
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240 bus_dma_tag_t dma_tag;
241 bus_dmamap_t dma_map;
9ccd8c1f 242};
984263bc 243
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244/* Our adapter structure */
245struct adapter {
246 struct arpcom arpcom;
247 struct e1000_hw hw;
87ab432b 248 int flags;
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249#define EM_FLAG_SHARED_INTR 0x0001
250#define EM_FLAG_HAS_MGMT 0x0002
251#define EM_FLAG_HAS_AMT 0x0004
252#define EM_FLAG_HW_CTRL 0x0008
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253#define EM_FLAG_TSO 0x0010
254#define EM_FLAG_TSO_PULLEX 0x0020
984263bc 255
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256 /* DragonFly operating-system-specific structures. */
257 struct e1000_osdep osdep;
258 device_t dev;
0d366ee7 259
9c80d176 260 bus_dma_tag_t parent_dtag;
0d366ee7 261
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262 struct resource *memory;
263 int memory_rid;
264 struct resource *flash;
265 int flash_rid;
9ccd8c1f 266
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267 struct resource *ioport;
268 int io_rid;
269
270 struct resource *intr_res;
271 void *intr_tag;
272 int intr_rid;
053f3ae6 273 int intr_type;
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274
275 struct ifmedia media;
276 struct callout timer;
277 struct callout tx_fifo_timer;
278 int if_flags;
279 int max_frame_size;
280 int min_frame_size;
281
79878f87 282 /* WOL register value */
9c80d176 283 int wol;
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284
285 /* Multicast array memory */
286 uint8_t *mta;
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287
288 /* Info about the board itself */
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289 uint8_t link_active;
290 uint16_t link_speed;
291 uint16_t link_duplex;
292 uint32_t smartspeed;
9c80d176 293 int int_throttle_ceil;
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294
295 /*
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296 * Transmit definitions
297 *
298 * We have an array of num_tx_desc descriptors (handled
299 * by the controller) paired with an array of tx_buffers
300 * (at tx_buffer_area).
301 * The index of the next available descriptor is next_avail_tx_desc.
302 * The number of remaining tx_desc is num_tx_desc_avail.
303 */
9ccd8c1f 304 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
9c80d176 305 struct e1000_tx_desc *tx_desc_base;
9f60d74b 306 struct em_buffer *tx_buffer_area;
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307 uint32_t next_avail_tx_desc;
308 uint32_t next_tx_to_clean;
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309 int num_tx_desc_avail;
310 int num_tx_desc;
9ccd8c1f 311 bus_dma_tag_t txtag; /* dma tag for tx */
9c80d176 312 int spare_tx_desc;
9f60d74b 313 int oact_tx_desc;
984263bc 314
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315 /* Saved csum offloading context information */
316 int csum_flags;
ed4fc0fe 317 int csum_lhlen;
51e6819f 318 int csum_iphlen;
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319
320 int csum_thlen; /* TSO */
321 int csum_mss; /* TSO */
322 int csum_pktlen; /* TSO */
323
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324 uint32_t csum_txd_upper;
325 uint32_t csum_txd_lower;
326
327 /*
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328 * Variables used to reduce TX interrupt rate and
329 * number of device's TX ring write requests.
330 *
331 * tx_nsegs:
332 * Number of TX descriptors setup so far.
333 *
334 * tx_int_nsegs:
335 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
336 * in the last TX descriptor of the packet, and
337 * tx_nsegs will be reset to 0. So TX interrupt and
338 * TX ring write request should be generated roughly
339 * every tx_int_nsegs TX descriptors.
340 *
341 * tx_dd[]:
342 * Index of the TX descriptors which have RS bit set,
343 * i.e. DD bit will be set on this TX descriptor after
344 * the data of the TX descriptor are transfered to
345 * hardware's internal packet buffer. Only the TX
346 * descriptors listed in tx_dd[] will be checked upon
347 * TX interrupt. This array is used as circular ring.
348 *
349 * tx_dd_tail, tx_dd_head:
350 * Tail and head index of valid elements in tx_dd[].
351 * tx_dd_tail == tx_dd_head means there is no valid
352 * elements in tx_dd[]. tx_dd_tail points to the position
353 * which is one beyond the last valid element in tx_dd[].
354 * tx_dd_head points to the first valid element in
355 * tx_dd[].
356 */
357 int tx_int_nsegs;
358 int tx_nsegs;
359 int tx_dd_tail;
360 int tx_dd_head;
361#define EM_TXDD_MAX 64
af2ee69f 362#define EM_TXDD_SAFE 48 /* must be less than EM_TXDD_MAX */
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363 int tx_dd[EM_TXDD_MAX];
364
365 /*
984263bc 366 * Receive definitions
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367 *
368 * we have an array of num_rx_desc rx_desc (handled by the
369 * controller), and paired with an array of rx_buffers
370 * (at rx_buffer_area).
371 * The next pair to check on receive is at offset next_rx_desc_to_check
372 */
9ccd8c1f 373 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
9c80d176 374 struct e1000_rx_desc *rx_desc_base;
87307ba1 375 uint32_t next_rx_desc_to_check;
87307ba1 376 uint32_t rx_buffer_len;
9c80d176 377 int num_rx_desc;
87307ba1 378 struct em_buffer *rx_buffer_area;
9ccd8c1f 379 bus_dma_tag_t rxtag;
9c80d176 380 bus_dmamap_t rx_sparemap;
984263bc 381
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382 /*
383 * First/last mbuf pointers, for
384 * collecting multisegment RX packets.
385 */
386 struct mbuf *fmp;
387 struct mbuf *lmp;
984263bc 388
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389 /* Misc stats maintained by the driver */
390 unsigned long dropped_pkts;
391 unsigned long mbuf_alloc_failed;
392 unsigned long mbuf_cluster_failed;
393 unsigned long no_tx_desc_avail1;
394 unsigned long no_tx_desc_avail2;
395 unsigned long no_tx_map_avail;
396 unsigned long no_tx_dma_setup;
397 unsigned long watchdog_events;
398 unsigned long rx_overruns;
399 unsigned long rx_irq;
400 unsigned long tx_irq;
401 unsigned long link_irq;
402
403 /* sysctl tree glue */
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404 struct sysctl_ctx_list sysctl_ctx;
405 struct sysctl_oid *sysctl_tree;
984263bc 406
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407 /* 82547 workaround */
408 uint32_t tx_fifo_size;
409 uint32_t tx_fifo_head;
410 uint32_t tx_fifo_head_addr;
411 uint64_t tx_fifo_reset_cnt;
412 uint64_t tx_fifo_wrk_cnt;
413 uint32_t tx_head_addr;
414
415 /* For 82544 PCIX Workaround */
416 boolean_t pcix_82544;
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417
418 struct e1000_hw_stats stats;
419};
420
421struct em_vendor_info {
422 uint16_t vendor_id;
423 uint16_t device_id;
96ced48a 424 int ret;
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425 const char *desc;
426};
427
428struct em_buffer {
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429 struct mbuf *m_head;
430 bus_dmamap_t map; /* bus_dma map for packet */
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431};
432
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433/* For 82544 PCIX Workaround */
434typedef struct _ADDRESS_LENGTH_PAIR {
435 uint64_t address;
436 uint32_t length;
437} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
438
439typedef struct _DESCRIPTOR_PAIR {
440 ADDRESS_LENGTH_PAIR descriptor[4];
441 uint32_t elements;
442} DESC_ARRAY, *PDESC_ARRAY;
443
444#define EM_IS_OACTIVE(adapter) \
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445 ((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc)
446
447#define EM_INC_TXDD_IDX(idx) \
448do { \
449 if (++(idx) == EM_TXDD_MAX) \
450 (idx) = 0; \
451} while (0)
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452
453#endif /* _IF_EM_H_ */