Update the 825xx GigE support. Add a large number of new device id's and
[dragonfly.git] / sys / dev / netif / em / if_em_hw.c
CommitLineData
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1/*******************************************************************************
2
3 Copyright (c) 2001-2003, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33
34/*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/
0d366ee7 35/*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.4 2004/03/17 04:59:41 dillon Exp $*/
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36/* if_em_hw.c
37 * Shared functions for accessing and configuring the MAC
38 */
39
1f2de5d4 40#include "if_em_hw.h"
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41
42static int32_t em_set_phy_type(struct em_hw *hw);
43static void em_phy_init_script(struct em_hw *hw);
984263bc 44static int32_t em_setup_copper_link(struct em_hw *hw);
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45static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
46static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
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47static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
48static int32_t em_config_mac_to_phy(struct em_hw *hw);
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49static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
50static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
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51static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
52 uint16_t count);
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53static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
54static int32_t em_phy_reset_dsp(struct em_hw *hw);
55static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
56 uint16_t words, uint16_t *data);
57static int32_t em_write_eeprom_microwire(struct em_hw *hw,
58 uint16_t offset, uint16_t words,
59 uint16_t *data);
60static int32_t em_spi_eeprom_ready(struct em_hw *hw);
61static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
62static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
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63static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
64 uint16_t count);
65static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
66 uint16_t phy_data);
67static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
68 uint16_t *phy_data);
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69static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
70static int32_t em_acquire_eeprom(struct em_hw *hw);
71static void em_release_eeprom(struct em_hw *hw);
72static void em_standby_eeprom(struct em_hw *hw);
73static int32_t em_id_led_init(struct em_hw * hw);
0d366ee7 74static int32_t em_set_vco_speed(struct em_hw *hw);
984263bc 75
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76/* IGP cable length table */
77static const
78uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
79 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
80 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
81 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
82 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
83 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
84 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
85 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
86 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
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87
88
89/******************************************************************************
90 * Set the phy type member in the hw struct.
91 *
92 * hw - Struct containing variables accessed by shared code
93 *****************************************************************************/
94int32_t
95em_set_phy_type(struct em_hw *hw)
96{
97 DEBUGFUNC("em_set_phy_type");
98
99 switch(hw->phy_id) {
100 case M88E1000_E_PHY_ID:
101 case M88E1000_I_PHY_ID:
102 case M88E1011_I_PHY_ID:
103 hw->phy_type = em_phy_m88;
104 break;
105 case IGP01E1000_I_PHY_ID:
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106 if(hw->mac_type == em_82541 ||
107 hw->mac_type == em_82541_rev_2 ||
108 hw->mac_type == em_82547 ||
109 hw->mac_type == em_82547_rev_2) {
110 hw->phy_type = em_phy_igp;
111 break;
112 }
113 /* Fall Through */
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114 default:
115 /* Should never have loaded on this device */
116 hw->phy_type = em_phy_undefined;
117 return -E1000_ERR_PHY_TYPE;
118 }
119
120 return E1000_SUCCESS;
121}
122
123/******************************************************************************
124 * IGP phy init script - initializes the GbE PHY
125 *
126 * hw - Struct containing variables accessed by shared code
127 *****************************************************************************/
128static void
129em_phy_init_script(struct em_hw *hw)
130{
131 DEBUGFUNC("em_phy_init_script");
132
133 if(hw->phy_init_script) {
0d366ee7 134 msec_delay(20);
984263bc 135
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136 em_write_phy_reg(hw,0x0000,0x0140);
137
138 msec_delay(5);
984263bc 139
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140 if(hw->mac_type == em_82541 || hw->mac_type == em_82547) {
141 em_write_phy_reg(hw, 0x1F95, 0x0001);
142
143 em_write_phy_reg(hw, 0x1F71, 0xBD21);
144
145 em_write_phy_reg(hw, 0x1F79, 0x0018);
146
147 em_write_phy_reg(hw, 0x1F30, 0x1600);
148
149 em_write_phy_reg(hw, 0x1F31, 0x0014);
984263bc 150
0d366ee7 151 em_write_phy_reg(hw, 0x1F32, 0x161C);
984263bc 152
0d366ee7 153 em_write_phy_reg(hw, 0x1F94, 0x0003);
984263bc 154
0d366ee7 155 em_write_phy_reg(hw, 0x1F96, 0x003F);
984263bc 156
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157 em_write_phy_reg(hw, 0x2010, 0x0008);
158 } else {
159 em_write_phy_reg(hw, 0x1F73, 0x0099);
160 }
161
162 em_write_phy_reg(hw, 0x0000, 0x3300);
163
164 if(hw->mac_type == em_82547) {
165 uint16_t fused, fine, coarse;
984263bc 166
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167 /* Move to analog registers page */
168 em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
984263bc 169
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170 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
171 em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
984263bc 172
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173 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
174 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
984263bc 175
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176 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
177 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
178 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
179 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
180 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
181
182 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
183 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
184 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
185
186 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
187 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
188 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
189 }
190 }
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191 }
192}
193
194/******************************************************************************
195 * Set the mac type member in the hw struct.
196 *
197 * hw - Struct containing variables accessed by shared code
198 *****************************************************************************/
199int32_t
200em_set_mac_type(struct em_hw *hw)
201{
202 DEBUGFUNC("em_set_mac_type");
203
204 switch (hw->device_id) {
205 case E1000_DEV_ID_82542:
206 switch (hw->revision_id) {
207 case E1000_82542_2_0_REV_ID:
208 hw->mac_type = em_82542_rev2_0;
209 break;
210 case E1000_82542_2_1_REV_ID:
211 hw->mac_type = em_82542_rev2_1;
212 break;
213 default:
214 /* Invalid 82542 revision ID */
215 return -E1000_ERR_MAC_TYPE;
216 }
217 break;
218 case E1000_DEV_ID_82543GC_FIBER:
219 case E1000_DEV_ID_82543GC_COPPER:
220 hw->mac_type = em_82543;
221 break;
222 case E1000_DEV_ID_82544EI_COPPER:
223 case E1000_DEV_ID_82544EI_FIBER:
224 case E1000_DEV_ID_82544GC_COPPER:
225 case E1000_DEV_ID_82544GC_LOM:
226 hw->mac_type = em_82544;
227 break;
228 case E1000_DEV_ID_82540EM:
229 case E1000_DEV_ID_82540EM_LOM:
230 case E1000_DEV_ID_82540EP:
231 case E1000_DEV_ID_82540EP_LOM:
232 case E1000_DEV_ID_82540EP_LP:
233 hw->mac_type = em_82540;
234 break;
235 case E1000_DEV_ID_82545EM_COPPER:
236 case E1000_DEV_ID_82545EM_FIBER:
237 hw->mac_type = em_82545;
238 break;
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239 case E1000_DEV_ID_82545GM_COPPER:
240 case E1000_DEV_ID_82545GM_FIBER:
241 case E1000_DEV_ID_82545GM_SERDES:
242 hw->mac_type = em_82545_rev_3;
243 break;
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244 case E1000_DEV_ID_82546EB_COPPER:
245 case E1000_DEV_ID_82546EB_FIBER:
246 case E1000_DEV_ID_82546EB_QUAD_COPPER:
247 hw->mac_type = em_82546;
248 break;
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249 case E1000_DEV_ID_82546GB_COPPER:
250 case E1000_DEV_ID_82546GB_FIBER:
251 case E1000_DEV_ID_82546GB_SERDES:
252 hw->mac_type = em_82546_rev_3;
253 break;
984263bc 254 case E1000_DEV_ID_82541EI:
0d366ee7 255 case E1000_DEV_ID_82541EI_MOBILE:
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256 hw->mac_type = em_82541;
257 break;
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258 case E1000_DEV_ID_82541ER:
259 case E1000_DEV_ID_82541GI:
260 case E1000_DEV_ID_82541GI_MOBILE:
261 hw->mac_type = em_82541_rev_2;
262 break;
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263 case E1000_DEV_ID_82547EI:
264 hw->mac_type = em_82547;
265 break;
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266 case E1000_DEV_ID_82547GI:
267 hw->mac_type = em_82547_rev_2;
268 break;
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269 default:
270 /* Should never have loaded on this device */
271 return -E1000_ERR_MAC_TYPE;
272 }
273
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274 return E1000_SUCCESS;
275}
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276
277/*****************************************************************************
278 * Set media type and TBI compatibility.
279 *
280 * hw - Struct containing variables accessed by shared code
281 * **************************************************************************/
282void
283em_set_media_type(struct em_hw *hw)
284{
285 uint32_t status;
286
287 DEBUGFUNC("em_set_media_type");
288
289 if(hw->mac_type != em_82543) {
290 /* tbi_compatibility is only valid on 82543 */
291 hw->tbi_compatibility_en = FALSE;
292 }
293
294 switch (hw->device_id) {
295 case E1000_DEV_ID_82545GM_SERDES:
296 case E1000_DEV_ID_82546GB_SERDES:
297 hw->media_type = em_media_type_internal_serdes;
298 break;
299 default:
300 if(hw->mac_type >= em_82543) {
301 status = E1000_READ_REG(hw, STATUS);
302 if(status & E1000_STATUS_TBIMODE) {
303 hw->media_type = em_media_type_fiber;
304 /* tbi_compatibility not valid on fiber */
305 hw->tbi_compatibility_en = FALSE;
306 } else {
307 hw->media_type = em_media_type_copper;
308 }
309 } else {
310 /* This is an 82542 (fiber only) */
311 hw->media_type = em_media_type_fiber;
312 }
313 }
314}
315
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316/******************************************************************************
317 * Reset the transmit and receive units; mask and clear all interrupts.
318 *
319 * hw - Struct containing variables accessed by shared code
320 *****************************************************************************/
0d366ee7 321int32_t
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322em_reset_hw(struct em_hw *hw)
323{
324 uint32_t ctrl;
325 uint32_t ctrl_ext;
326 uint32_t icr;
327 uint32_t manc;
328 uint32_t led_ctrl;
329
330 DEBUGFUNC("em_reset_hw");
331
332 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
333 if(hw->mac_type == em_82542_rev2_0) {
334 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
335 em_pci_clear_mwi(hw);
336 }
337
338 /* Clear interrupt mask to stop board from generating interrupts */
339 DEBUGOUT("Masking off all interrupts\n");
340 E1000_WRITE_REG(hw, IMC, 0xffffffff);
341
342 /* Disable the Transmit and Receive units. Then delay to allow
343 * any pending transactions to complete before we hit the MAC with
344 * the global reset.
345 */
346 E1000_WRITE_REG(hw, RCTL, 0);
347 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
348 E1000_WRITE_FLUSH(hw);
349
350 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
351 hw->tbi_compatibility_on = FALSE;
352
353 /* Delay to allow any outstanding PCI transactions to complete before
354 * resetting the device
355 */
356 msec_delay(10);
357
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358 ctrl = E1000_READ_REG(hw, CTRL);
359
360 /* Must reset the PHY before resetting the MAC */
361 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
362 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
0d366ee7 363 msec_delay(5);
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364 }
365
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366 /* Issue a global reset to the MAC. This will reset the chip's
367 * transmit, receive, DMA, and link units. It will not effect
368 * the current PCI configuration. The global reset bit is self-
369 * clearing, and should clear within a microsecond.
370 */
371 DEBUGOUT("Issuing a global reset to MAC\n");
372
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373 switch(hw->mac_type) {
374 case em_82544:
375 case em_82540:
376 case em_82545:
377 case em_82546:
378 case em_82541:
0d366ee7 379 case em_82541_rev_2:
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380 /* These controllers can't ack the 64-bit write when issuing the
381 * reset, so use IO-mapping as a workaround to issue the reset */
382 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
383 break;
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384 case em_82545_rev_3:
385 case em_82546_rev_3:
386 /* Reset is performed on a shadow of the control register */
387 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
388 break;
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389 default:
390 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
391 break;
392 }
393
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394 /* After MAC reset, force reload of EEPROM to restore power-on settings to
395 * device. Later controllers reload the EEPROM automatically, so just wait
396 * for reload to complete.
397 */
398 switch(hw->mac_type) {
399 case em_82542_rev2_0:
400 case em_82542_rev2_1:
401 case em_82543:
402 case em_82544:
403 /* Wait for reset to complete */
404 usec_delay(10);
405 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
406 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
407 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
408 E1000_WRITE_FLUSH(hw);
409 /* Wait for EEPROM reload */
410 msec_delay(2);
411 break;
412 case em_82541:
413 case em_82541_rev_2:
414 case em_82547:
415 case em_82547_rev_2:
416 /* Wait for EEPROM reload */
417 msec_delay(20);
418 break;
419 default:
420 /* Wait for EEPROM reload (it happens automatically) */
421 msec_delay(5);
422 break;
423 }
424
425 /* Disable HW ARPs on ASF enabled adapters */
426 if(hw->mac_type >= em_82540) {
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427 manc = E1000_READ_REG(hw, MANC);
428 manc &= ~(E1000_MANC_ARP_EN);
429 E1000_WRITE_REG(hw, MANC, manc);
430 }
431
432 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
433 em_phy_init_script(hw);
434
435 /* Configure activity LED after PHY reset */
436 led_ctrl = E1000_READ_REG(hw, LEDCTL);
437 led_ctrl &= IGP_ACTIVITY_LED_MASK;
438 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
439 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
440 }
441
442 /* Clear interrupt mask to stop board from generating interrupts */
443 DEBUGOUT("Masking off all interrupts\n");
444 E1000_WRITE_REG(hw, IMC, 0xffffffff);
445
446 /* Clear any pending interrupt events. */
447 icr = E1000_READ_REG(hw, ICR);
448
449 /* If MWI was previously enabled, reenable it. */
450 if(hw->mac_type == em_82542_rev2_0) {
451 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
452 em_pci_set_mwi(hw);
453 }
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454
455 return E1000_SUCCESS;
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456}
457
458/******************************************************************************
459 * Performs basic configuration of the adapter.
460 *
461 * hw - Struct containing variables accessed by shared code
462 *
463 * Assumes that the controller has previously been reset and is in a
464 * post-reset uninitialized state. Initializes the receive address registers,
465 * multicast table, and VLAN filter table. Calls routines to setup link
466 * configuration and flow control settings. Clears all on-chip counters. Leaves
467 * the transmit and receive units disabled and uninitialized.
468 *****************************************************************************/
469int32_t
470em_init_hw(struct em_hw *hw)
471{
0d366ee7 472 uint32_t ctrl;
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473 uint32_t i;
474 int32_t ret_val;
475 uint16_t pcix_cmd_word;
476 uint16_t pcix_stat_hi_word;
477 uint16_t cmd_mmrbc;
478 uint16_t stat_mmrbc;
479
480 DEBUGFUNC("em_init_hw");
481
482 /* Initialize Identification LED */
0d366ee7 483 if((ret_val = em_id_led_init(hw))) {
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484 DEBUGOUT("Error Initializing Identification LED\n");
485 return ret_val;
486 }
487
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488 /* Set the media type and TBI compatibility */
489 em_set_media_type(hw);
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490
491 /* Disabling VLAN filtering. */
492 DEBUGOUT("Initializing the IEEE VLAN\n");
493 E1000_WRITE_REG(hw, VET, 0);
494
495 em_clear_vfta(hw);
496
497 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
498 if(hw->mac_type == em_82542_rev2_0) {
499 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
500 em_pci_clear_mwi(hw);
501 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
502 E1000_WRITE_FLUSH(hw);
503 msec_delay(5);
504 }
505
506 /* Setup the receive address. This involves initializing all of the Receive
507 * Address Registers (RARs 0 - 15).
508 */
509 em_init_rx_addrs(hw);
510
511 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
512 if(hw->mac_type == em_82542_rev2_0) {
513 E1000_WRITE_REG(hw, RCTL, 0);
514 E1000_WRITE_FLUSH(hw);
515 msec_delay(1);
516 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
517 em_pci_set_mwi(hw);
518 }
519
520 /* Zero out the Multicast HASH table */
521 DEBUGOUT("Zeroing the MTA\n");
522 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
523 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
524
525 /* Set the PCI priority bit correctly in the CTRL register. This
526 * determines if the adapter gives priority to receives, or if it
527 * gives equal priority to transmits and receives.
528 */
529 if(hw->dma_fairness) {
530 ctrl = E1000_READ_REG(hw, CTRL);
531 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
532 }
533
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534 switch(hw->mac_type) {
535 case em_82545_rev_3:
536 case em_82546_rev_3:
537 break;
538 default:
539 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
540 if(hw->bus_type == em_bus_type_pcix) {
541 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
542 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
543 &pcix_stat_hi_word);
544 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
545 PCIX_COMMAND_MMRBC_SHIFT;
546 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
547 PCIX_STATUS_HI_MMRBC_SHIFT;
548 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
549 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
550 if(cmd_mmrbc > stat_mmrbc) {
551 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
552 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
553 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
554 &pcix_cmd_word);
555 }
984263bc 556 }
0d366ee7 557 break;
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558 }
559
560 /* Call a subroutine to configure the link and setup flow control. */
561 ret_val = em_setup_link(hw);
562
563 /* Set the transmit descriptor write-back policy */
564 if(hw->mac_type > em_82544) {
565 ctrl = E1000_READ_REG(hw, TXDCTL);
566 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
567 E1000_WRITE_REG(hw, TXDCTL, ctrl);
568 }
569
570 /* Clear all of the statistics registers (clear on read). It is
571 * important that we do this after we have tried to establish link
572 * because the symbol error count will increment wildly if there
573 * is no link.
574 */
575 em_clear_hw_cntrs(hw);
576
577 return ret_val;
578}
579
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580/******************************************************************************
581 * Adjust SERDES output amplitude based on EEPROM setting.
582 *
583 * hw - Struct containing variables accessed by shared code.
584 *****************************************************************************/
585static int32_t
586em_adjust_serdes_amplitude(struct em_hw *hw)
587{
588 uint16_t eeprom_data;
589 int32_t ret_val;
590
591 DEBUGFUNC("em_adjust_serdes_amplitude");
592
593 if(hw->media_type != em_media_type_internal_serdes)
594 return E1000_SUCCESS;
595
596 switch(hw->mac_type) {
597 case em_82545_rev_3:
598 case em_82546_rev_3:
599 break;
600 default:
601 return E1000_SUCCESS;
602 }
603
604 if ((ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
605 &eeprom_data))) {
606 return ret_val;
607 }
608
609 if(eeprom_data != EEPROM_RESERVED_WORD) {
610 /* Adjust SERDES output amplitude only. */
611 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
612 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
613 eeprom_data)))
614 return ret_val;
615 }
616
617 return E1000_SUCCESS;
618}
619
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620/******************************************************************************
621 * Configures flow control and link settings.
622 *
623 * hw - Struct containing variables accessed by shared code
624 *
625 * Determines which flow control settings to use. Calls the apropriate media-
626 * specific link configuration function. Configures the flow control settings.
627 * Assuming the adapter has a valid link partner, a valid link should be
628 * established. Assumes the hardware has previously been reset and the
629 * transmitter and receiver are not enabled.
630 *****************************************************************************/
631int32_t
632em_setup_link(struct em_hw *hw)
633{
634 uint32_t ctrl_ext;
635 int32_t ret_val;
636 uint16_t eeprom_data;
637
638 DEBUGFUNC("em_setup_link");
639
640 /* Read and store word 0x0F of the EEPROM. This word contains bits
641 * that determine the hardware's default PAUSE (flow control) mode,
642 * a bit that determines whether the HW defaults to enabling or
643 * disabling auto-negotiation, and the direction of the
644 * SW defined pins. If there is no SW over-ride of the flow
645 * control setting, then the variable hw->fc will
646 * be initialized based on a value in the EEPROM.
647 */
648 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
649 DEBUGOUT("EEPROM Read Error\n");
650 return -E1000_ERR_EEPROM;
651 }
652
653 if(hw->fc == em_fc_default) {
654 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
655 hw->fc = em_fc_none;
656 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
657 EEPROM_WORD0F_ASM_DIR)
658 hw->fc = em_fc_tx_pause;
659 else
660 hw->fc = em_fc_full;
661 }
662
663 /* We want to save off the original Flow Control configuration just
664 * in case we get disconnected and then reconnected into a different
665 * hub or switch with different Flow Control capabilities.
666 */
667 if(hw->mac_type == em_82542_rev2_0)
668 hw->fc &= (~em_fc_tx_pause);
669
670 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
671 hw->fc &= (~em_fc_rx_pause);
672
673 hw->original_fc = hw->fc;
674
675 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
676
677 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
678 * polarity value for the SW controlled pins, and setup the
679 * Extended Device Control reg with that info.
680 * This is needed because one of the SW controlled pins is used for
681 * signal detection. So this should be done before em_setup_pcs_link()
682 * or em_phy_setup() is called.
683 */
684 if(hw->mac_type == em_82543) {
685 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
686 SWDPIO__EXT_SHIFT);
687 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
688 }
689
690 /* Call the necessary subroutine to configure the link. */
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691 ret_val = (hw->media_type == em_media_type_copper) ?
692 em_setup_copper_link(hw) :
693 em_setup_fiber_serdes_link(hw);
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694
695 /* Initialize the flow control address, type, and PAUSE timer
696 * registers to their default values. This is done even if flow
697 * control is disabled, because it does not hurt anything to
698 * initialize these registers.
699 */
700 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
701
702 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
703 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
704 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
705 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
706
707 /* Set the flow control receive threshold registers. Normally,
708 * these registers will be set to a default threshold that may be
709 * adjusted later by the driver's runtime code. However, if the
710 * ability to transmit pause frames in not enabled, then these
711 * registers will be set to 0.
712 */
713 if(!(hw->fc & em_fc_tx_pause)) {
714 E1000_WRITE_REG(hw, FCRTL, 0);
715 E1000_WRITE_REG(hw, FCRTH, 0);
716 } else {
717 /* We need to set up the Receive Threshold high and low water marks
718 * as well as (optionally) enabling the transmission of XON frames.
719 */
720 if(hw->fc_send_xon) {
721 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
722 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
723 } else {
724 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
725 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
726 }
727 }
728 return ret_val;
729}
730
731/******************************************************************************
0d366ee7 732 * Sets up link for a fiber based or serdes based adapter
984263bc
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733 *
734 * hw - Struct containing variables accessed by shared code
735 *
736 * Manipulates Physical Coding Sublayer functions in order to configure
737 * link. Assumes the hardware has been previously reset and the transmitter
738 * and receiver are not enabled.
739 *****************************************************************************/
740static int32_t
0d366ee7 741em_setup_fiber_serdes_link(struct em_hw *hw)
984263bc
MD
742{
743 uint32_t ctrl;
744 uint32_t status;
745 uint32_t txcw = 0;
746 uint32_t i;
0d366ee7 747 uint32_t signal = 0;
984263bc
MD
748 int32_t ret_val;
749
0d366ee7 750 DEBUGFUNC("em_setup_fiber_serdes_link");
984263bc 751
0d366ee7 752 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
984263bc 753 * set when the optics detect a signal. On older adapters, it will be
0d366ee7
MD
754 * cleared when there is a signal. This applies to fiber media only.
755 * If we're on serdes media, adjust the output amplitude to value set in
756 * the EEPROM.
984263bc
MD
757 */
758 ctrl = E1000_READ_REG(hw, CTRL);
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MD
759 if(hw->media_type == em_media_type_fiber)
760 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
761
762 if((ret_val = em_adjust_serdes_amplitude(hw)))
763 return ret_val;
984263bc
MD
764
765 /* Take the link out of reset */
766 ctrl &= ~(E1000_CTRL_LRST);
767
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MD
768 /* Adjust VCO speed to improve BER performance */
769 if((ret_val = em_set_vco_speed(hw)))
770 return ret_val;
771
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MD
772 em_config_collision_dist(hw);
773
774 /* Check for a software override of the flow control settings, and setup
775 * the device accordingly. If auto-negotiation is enabled, then software
776 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
777 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
778 * auto-negotiation is disabled, then software will have to manually
779 * configure the two flow control enable bits in the CTRL register.
780 *
781 * The possible values of the "fc" parameter are:
782 * 0: Flow control is completely disabled
783 * 1: Rx flow control is enabled (we can receive pause frames, but
784 * not send pause frames).
785 * 2: Tx flow control is enabled (we can send pause frames but we do
786 * not support receiving pause frames).
787 * 3: Both Rx and TX flow control (symmetric) are enabled.
788 */
789 switch (hw->fc) {
790 case em_fc_none:
791 /* Flow control is completely disabled by a software over-ride. */
792 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
793 break;
794 case em_fc_rx_pause:
795 /* RX Flow control is enabled and TX Flow control is disabled by a
796 * software over-ride. Since there really isn't a way to advertise
797 * that we are capable of RX Pause ONLY, we will advertise that we
798 * support both symmetric and asymmetric RX PAUSE. Later, we will
799 * disable the adapter's ability to send PAUSE frames.
800 */
801 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
802 break;
803 case em_fc_tx_pause:
804 /* TX Flow control is enabled, and RX Flow control is disabled, by a
805 * software over-ride.
806 */
807 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
808 break;
809 case em_fc_full:
810 /* Flow control (both RX and TX) is enabled by a software over-ride. */
811 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
812 break;
813 default:
814 DEBUGOUT("Flow control param set incorrectly\n");
815 return -E1000_ERR_CONFIG;
816 break;
817 }
818
819 /* Since auto-negotiation is enabled, take the link out of reset (the link
820 * will be in reset, because we previously reset the chip). This will
821 * restart auto-negotiation. If auto-neogtiation is successful then the
822 * link-up status bit will be set and the flow control enable bits (RFCE
823 * and TFCE) will be set according to their negotiated value.
824 */
825 DEBUGOUT("Auto-negotiation enabled\n");
826
827 E1000_WRITE_REG(hw, TXCW, txcw);
828 E1000_WRITE_REG(hw, CTRL, ctrl);
829 E1000_WRITE_FLUSH(hw);
830
831 hw->txcw = txcw;
832 msec_delay(1);
833
834 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
835 * indication in the Device Status Register. Time-out if a link isn't
836 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
837 * less than 500 milliseconds even if the other end is doing it in SW).
0d366ee7 838 * For internal serdes, we just assume a signal is present, then poll.
984263bc 839 */
0d366ee7
MD
840 if(hw->media_type == em_media_type_internal_serdes ||
841 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
984263bc
MD
842 DEBUGOUT("Looking for Link\n");
843 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
844 msec_delay(10);
845 status = E1000_READ_REG(hw, STATUS);
846 if(status & E1000_STATUS_LU) break;
847 }
848 if(i == (LINK_UP_TIMEOUT / 10)) {
0d366ee7
MD
849 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
850 hw->autoneg_failed = 1;
984263bc 851 /* AutoNeg failed to achieve a link, so we'll call
0d366ee7
MD
852 * em_check_for_link. This routine will force the link up if
853 * we detect a signal. This will allow us to communicate with
984263bc
MD
854 * non-autonegotiating link partners.
855 */
0d366ee7 856 if((ret_val = em_check_for_link(hw))) {
984263bc
MD
857 DEBUGOUT("Error while checking for link\n");
858 return ret_val;
859 }
860 hw->autoneg_failed = 0;
861 } else {
862 hw->autoneg_failed = 0;
863 DEBUGOUT("Valid Link Found\n");
864 }
865 } else {
866 DEBUGOUT("No Signal Detected\n");
867 }
0d366ee7 868 return E1000_SUCCESS;
984263bc
MD
869}
870
871/******************************************************************************
872* Detects which PHY is present and the speed and duplex
873*
874* hw - Struct containing variables accessed by shared code
875******************************************************************************/
876static int32_t
877em_setup_copper_link(struct em_hw *hw)
878{
879 uint32_t ctrl;
880 uint32_t led_ctrl;
881 int32_t ret_val;
882 uint16_t i;
883 uint16_t phy_data;
884
885 DEBUGFUNC("em_setup_copper_link");
886
887 ctrl = E1000_READ_REG(hw, CTRL);
888 /* With 82543, we need to force speed and duplex on the MAC equal to what
889 * the PHY speed and duplex configuration is. In addition, we need to
890 * perform a hardware reset on the PHY to take it out of reset.
891 */
892 if(hw->mac_type > em_82543) {
893 ctrl |= E1000_CTRL_SLU;
894 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
895 E1000_WRITE_REG(hw, CTRL, ctrl);
896 } else {
897 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
898 E1000_WRITE_REG(hw, CTRL, ctrl);
899 em_phy_hw_reset(hw);
900 }
901
902 /* Make sure we have a valid PHY */
0d366ee7 903 if((ret_val = em_detect_gig_phy(hw))) {
984263bc
MD
904 DEBUGOUT("Error, did not detect valid phy.\n");
905 return ret_val;
906 }
907 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
908
0d366ee7
MD
909 if(hw->mac_type <= em_82543 ||
910 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
911 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
912 hw->phy_reset_disable = FALSE;
984263bc 913
0d366ee7
MD
914 if(!hw->phy_reset_disable) {
915 if (hw->phy_type == em_phy_igp) {
984263bc 916
0d366ee7
MD
917 if((ret_val = em_phy_reset(hw))) {
918 DEBUGOUT("Error Resetting the PHY\n");
919 return ret_val;
920 }
984263bc 921
0d366ee7
MD
922 /* Wait 10ms for MAC to configure PHY from eeprom settings */
923 msec_delay(15);
984263bc 924
0d366ee7
MD
925 /* Configure activity LED after PHY reset */
926 led_ctrl = E1000_READ_REG(hw, LEDCTL);
927 led_ctrl &= IGP_ACTIVITY_LED_MASK;
928 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
929 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
984263bc 930
0d366ee7
MD
931 /* disable lplu d3 during driver init */
932 if((ret_val = em_set_d3_lplu_state(hw, FALSE))) {
933 DEBUGOUT("Error Disabling LPLU D3\n");
934 return ret_val;
984263bc 935 }
0d366ee7
MD
936
937 /* Configure mdi-mdix settings */
938 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
939 &phy_data)))
940 return ret_val;
941
942 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
943 hw->dsp_config_state = em_dsp_config_disabled;
944 /* Force MDI for IGP B-0 PHY */
945 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
946 IGP01E1000_PSCR_FORCE_MDI_MDIX);
947 hw->mdix = 1;
948
949 } else {
950 hw->dsp_config_state = em_dsp_config_enabled;
951 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
952
953 switch (hw->mdix) {
954 case 1:
955 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
956 break;
957 case 2:
958 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
959 break;
960 case 0:
961 default:
962 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
963 break;
964 }
984263bc 965 }
0d366ee7
MD
966 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
967 phy_data)))
968 return ret_val;
984263bc 969
0d366ee7
MD
970 /* set auto-master slave resolution settings */
971 if(hw->autoneg) {
972 em_ms_type phy_ms_setting = hw->master_slave;
973
974 if(hw->ffe_config_state == em_ffe_config_active)
975 hw->ffe_config_state = em_ffe_config_enabled;
976
977 if(hw->dsp_config_state == em_dsp_config_activated)
978 hw->dsp_config_state = em_dsp_config_enabled;
979
980 /* when autonegotiation advertisment is only 1000Mbps then we
981 * should disable SmartSpeed and enable Auto MasterSlave
982 * resolution as hardware default. */
983 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
984 /* Disable SmartSpeed */
985 if((ret_val = em_read_phy_reg(hw,
986 IGP01E1000_PHY_PORT_CONFIG,
987 &phy_data)))
988 return ret_val;
989 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
990 if((ret_val = em_write_phy_reg(hw,
991 IGP01E1000_PHY_PORT_CONFIG,
992 phy_data)))
993 return ret_val;
994 /* Set auto Master/Slave resolution process */
995 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
996 &phy_data)))
997 return ret_val;
998 phy_data &= ~CR_1000T_MS_ENABLE;
999 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
1000 phy_data)))
1001 return ret_val;
1002 }
984263bc 1003
0d366ee7
MD
1004 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
1005 &phy_data)))
1006 return ret_val;
984263bc 1007
0d366ee7
MD
1008 /* load defaults for future use */
1009 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1010 ((phy_data & CR_1000T_MS_VALUE) ?
1011 em_ms_force_master :
1012 em_ms_force_slave) :
1013 em_ms_auto;
984263bc 1014
0d366ee7
MD
1015 switch (phy_ms_setting) {
1016 case em_ms_force_master:
1017 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1018 break;
1019 case em_ms_force_slave:
1020 phy_data |= CR_1000T_MS_ENABLE;
1021 phy_data &= ~(CR_1000T_MS_VALUE);
1022 break;
1023 case em_ms_auto:
1024 phy_data &= ~CR_1000T_MS_ENABLE;
1025 default:
1026 break;
1027 }
1028 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
1029 phy_data)))
1030 return ret_val;
1031 }
1032 } else {
1033 /* Enable CRS on TX. This must be set for half-duplex operation. */
1034 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1035 &phy_data)))
1036 return ret_val;
984263bc 1037
0d366ee7 1038 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
984263bc 1039
0d366ee7
MD
1040 /* Options:
1041 * MDI/MDI-X = 0 (default)
1042 * 0 - Auto for all speeds
1043 * 1 - MDI mode
1044 * 2 - MDI-X mode
1045 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1046 */
1047 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
984263bc 1048
0d366ee7
MD
1049 switch (hw->mdix) {
1050 case 1:
1051 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1052 break;
1053 case 2:
1054 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1055 break;
1056 case 3:
1057 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1058 break;
1059 case 0:
1060 default:
1061 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1062 break;
1063 }
984263bc 1064
0d366ee7
MD
1065 /* Options:
1066 * disable_polarity_correction = 0 (default)
1067 * Automatic Correction for Reversed Cable Polarity
1068 * 0 - Disabled
1069 * 1 - Enabled
1070 */
1071 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1072 if(hw->disable_polarity_correction == 1)
1073 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1074 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1075 phy_data)))
1076 return ret_val;
984263bc 1077
0d366ee7
MD
1078 /* Force TX_CLK in the Extended PHY Specific Control Register
1079 * to 25MHz clock.
1080 */
1081 if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1082 &phy_data)))
1083 return ret_val;
984263bc 1084
0d366ee7
MD
1085 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1086
1087 if (hw->phy_revision < M88E1011_I_REV_4) {
1088 /* Configure Master and Slave downshift values */
1089 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1090 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1091 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1092 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1093 if((ret_val = em_write_phy_reg(hw,
1094 M88E1000_EXT_PHY_SPEC_CTRL,
1095 phy_data)))
1096 return ret_val;
984263bc 1097 }
984263bc 1098
0d366ee7
MD
1099 /* SW Reset the PHY so all changes take effect */
1100 if((ret_val = em_phy_reset(hw))) {
1101 DEBUGOUT("Error Resetting the PHY\n");
1102 return ret_val;
1103 }
984263bc 1104 }
984263bc 1105
0d366ee7
MD
1106 /* Options:
1107 * autoneg = 1 (default)
1108 * PHY will advertise value(s) parsed from
1109 * autoneg_advertised and fc
1110 * autoneg = 0
1111 * PHY will be set to 10H, 10F, 100H, or 100F
1112 * depending on value parsed from forced_speed_duplex.
984263bc 1113 */
984263bc 1114
0d366ee7
MD
1115 /* Is autoneg enabled? This is enabled by default or by software
1116 * override. If so, call em_phy_setup_autoneg routine to parse the
1117 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1118 * the user should have provided a speed/duplex override. If so, then
1119 * call em_phy_force_speed_duplex to parse and set this up.
984263bc 1120 */
0d366ee7
MD
1121 if(hw->autoneg) {
1122 /* Perform some bounds checking on the hw->autoneg_advertised
1123 * parameter. If this variable is zero, then set it to the default.
1124 */
1125 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
984263bc 1126
0d366ee7
MD
1127 /* If autoneg_advertised is zero, we assume it was not defaulted
1128 * by the calling code so we set to advertise full capability.
1129 */
1130 if(hw->autoneg_advertised == 0)
1131 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
984263bc 1132
0d366ee7
MD
1133 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1134 if((ret_val = em_phy_setup_autoneg(hw))) {
1135 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1136 return ret_val;
1137 }
1138 DEBUGOUT("Restarting Auto-Neg\n");
984263bc 1139
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1140 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1141 * the Auto Neg Restart bit in the PHY control register.
1142 */
1143 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1144 return ret_val;
1145
1146 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1147 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
1148 return ret_val;
1149
1150 /* Does the user want to wait for Auto-Neg to complete here, or
1151 * check at a later time (for example, callback routine).
1152 */
1153 if(hw->wait_autoneg_complete) {
1154 if((ret_val = em_wait_autoneg(hw))) {
1155 DEBUGOUT("Error while waiting for autoneg to complete\n");
1156 return ret_val;
1157 }
1158 }
1159 hw->get_link_status = TRUE;
1160 } else {
1161 DEBUGOUT("Forcing speed and duplex\n");
1162 if((ret_val = em_phy_force_speed_duplex(hw))) {
1163 DEBUGOUT("Error Forcing Speed and Duplex\n");
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1164 return ret_val;
1165 }
1166 }
0d366ee7 1167 } /* !hw->phy_reset_disable */
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MD
1168
1169 /* Check link status. Wait up to 100 microseconds for link to become
1170 * valid.
1171 */
1172 for(i = 0; i < 10; i++) {
0d366ee7
MD
1173 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1174 return ret_val;
1175 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1176 return ret_val;
1177
1178 if(phy_data & MII_SR_LINK_STATUS) {
1179 /* We have link, so we need to finish the config process:
984263bc
MD
1180 * 1) Set up the MAC to the current PHY speed/duplex
1181 * if we are on 82543. If we
1182 * are on newer silicon, we only need to configure
1183 * collision distance in the Transmit Control Register.
1184 * 2) Set up flow control on the MAC to that established with
1185 * the link partner.
1186 */
1187 if(hw->mac_type >= em_82544) {
1188 em_config_collision_dist(hw);
1189 } else {
0d366ee7 1190 if((ret_val = em_config_mac_to_phy(hw))) {
984263bc
MD
1191 DEBUGOUT("Error configuring MAC to PHY settings\n");
1192 return ret_val;
0d366ee7 1193 }
984263bc 1194 }
0d366ee7 1195 if((ret_val = em_config_fc_after_link_up(hw))) {
984263bc
MD
1196 DEBUGOUT("Error Configuring Flow Control\n");
1197 return ret_val;
1198 }
1199 DEBUGOUT("Valid link established!!!\n");
0d366ee7
MD
1200
1201 if(hw->phy_type == em_phy_igp) {
1202 if((ret_val = em_config_dsp_after_link_change(hw, TRUE))) {
1203 DEBUGOUT("Error Configuring DSP after link up\n");
1204 return ret_val;
1205 }
1206 }
1207 DEBUGOUT("Valid link established!!!\n");
1208 return E1000_SUCCESS;
984263bc
MD
1209 }
1210 usec_delay(10);
1211 }
1212
1213 DEBUGOUT("Unable to establish link!!!\n");
0d366ee7 1214 return E1000_SUCCESS;
984263bc
MD
1215}
1216
1217/******************************************************************************
1218* Configures PHY autoneg and flow control advertisement settings
1219*
1220* hw - Struct containing variables accessed by shared code
1221******************************************************************************/
1222int32_t
1223em_phy_setup_autoneg(struct em_hw *hw)
1224{
0d366ee7 1225 int32_t ret_val;
984263bc
MD
1226 uint16_t mii_autoneg_adv_reg;
1227 uint16_t mii_1000t_ctrl_reg;
1228
1229 DEBUGFUNC("em_phy_setup_autoneg");
1230
1231 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
0d366ee7
MD
1232 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
1233 &mii_autoneg_adv_reg)))
1234 return ret_val;
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1235
1236 /* Read the MII 1000Base-T Control Register (Address 9). */
0d366ee7
MD
1237 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1238 return ret_val;
984263bc
MD
1239
1240 /* Need to parse both autoneg_advertised and fc and set up
1241 * the appropriate PHY registers. First we will parse for
1242 * autoneg_advertised software override. Since we can advertise
1243 * a plethora of combinations, we need to check each bit
1244 * individually.
1245 */
1246
1247 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1248 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1249 * the 1000Base-T Control Register (Address 9).
1250 */
1251 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1252 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1253
1254 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1255
1256 /* Do we want to advertise 10 Mb Half Duplex? */
1257 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1258 DEBUGOUT("Advertise 10mb Half duplex\n");
1259 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1260 }
1261
1262 /* Do we want to advertise 10 Mb Full Duplex? */
1263 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1264 DEBUGOUT("Advertise 10mb Full duplex\n");
1265 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1266 }
1267
1268 /* Do we want to advertise 100 Mb Half Duplex? */
1269 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1270 DEBUGOUT("Advertise 100mb Half duplex\n");
1271 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1272 }
1273
1274 /* Do we want to advertise 100 Mb Full Duplex? */
1275 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1276 DEBUGOUT("Advertise 100mb Full duplex\n");
1277 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1278 }
1279
1280 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1281 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1282 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1283 }
1284
1285 /* Do we want to advertise 1000 Mb Full Duplex? */
1286 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1287 DEBUGOUT("Advertise 1000mb Full duplex\n");
1288 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1289 }
1290
1291 /* Check for a software override of the flow control settings, and
1292 * setup the PHY advertisement registers accordingly. If
1293 * auto-negotiation is enabled, then software will have to set the
1294 * "PAUSE" bits to the correct value in the Auto-Negotiation
1295 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1296 *
1297 * The possible values of the "fc" parameter are:
1298 * 0: Flow control is completely disabled
1299 * 1: Rx flow control is enabled (we can receive pause frames
1300 * but not send pause frames).
1301 * 2: Tx flow control is enabled (we can send pause frames
1302 * but we do not support receiving pause frames).
1303 * 3: Both Rx and TX flow control (symmetric) are enabled.
1304 * other: No software override. The flow control configuration
1305 * in the EEPROM is used.
1306 */
1307 switch (hw->fc) {
1308 case em_fc_none: /* 0 */
1309 /* Flow control (RX & TX) is completely disabled by a
1310 * software over-ride.
1311 */
1312 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1313 break;
1314 case em_fc_rx_pause: /* 1 */
1315 /* RX Flow control is enabled, and TX Flow control is
1316 * disabled, by a software over-ride.
1317 */
1318 /* Since there really isn't a way to advertise that we are
1319 * capable of RX Pause ONLY, we will advertise that we
1320 * support both symmetric and asymmetric RX PAUSE. Later
1321 * (in em_config_fc_after_link_up) we will disable the
1322 *hw's ability to send PAUSE frames.
1323 */
1324 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1325 break;
1326 case em_fc_tx_pause: /* 2 */
1327 /* TX Flow control is enabled, and RX Flow control is
1328 * disabled, by a software over-ride.
1329 */
1330 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1331 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1332 break;
1333 case em_fc_full: /* 3 */
1334 /* Flow control (both RX and TX) is enabled by a software
1335 * over-ride.
1336 */
1337 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1338 break;
1339 default:
1340 DEBUGOUT("Flow control param set incorrectly\n");
1341 return -E1000_ERR_CONFIG;
1342 }
1343
0d366ee7
MD
1344 if((ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV,
1345 mii_autoneg_adv_reg)))
1346 return ret_val;
984263bc
MD
1347
1348 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1349
0d366ee7
MD
1350 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1351 return ret_val;
1352
1353 return E1000_SUCCESS;
984263bc
MD
1354}
1355
1356/******************************************************************************
1357* Force PHY speed and duplex settings to hw->forced_speed_duplex
1358*
1359* hw - Struct containing variables accessed by shared code
1360******************************************************************************/
1361static int32_t
1362em_phy_force_speed_duplex(struct em_hw *hw)
1363{
1364 uint32_t ctrl;
1365 int32_t ret_val;
1366 uint16_t mii_ctrl_reg;
1367 uint16_t mii_status_reg;
1368 uint16_t phy_data;
1369 uint16_t i;
1370
1371 DEBUGFUNC("em_phy_force_speed_duplex");
1372
1373 /* Turn off Flow control if we are forcing speed and duplex. */
1374 hw->fc = em_fc_none;
1375
1376 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1377
1378 /* Read the Device Control Register. */
1379 ctrl = E1000_READ_REG(hw, CTRL);
1380
1381 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1382 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1383 ctrl &= ~(DEVICE_SPEED_MASK);
1384
1385 /* Clear the Auto Speed Detect Enable bit. */
1386 ctrl &= ~E1000_CTRL_ASDE;
1387
1388 /* Read the MII Control Register. */
0d366ee7
MD
1389 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
1390 return ret_val;
984263bc
MD
1391
1392 /* We need to disable autoneg in order to force link and duplex. */
1393
1394 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1395
1396 /* Are we forcing Full or Half Duplex? */
1397 if(hw->forced_speed_duplex == em_100_full ||
1398 hw->forced_speed_duplex == em_10_full) {
1399 /* We want to force full duplex so we SET the full duplex bits in the
1400 * Device and MII Control Registers.
1401 */
1402 ctrl |= E1000_CTRL_FD;
1403 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1404 DEBUGOUT("Full Duplex\n");
1405 } else {
1406 /* We want to force half duplex so we CLEAR the full duplex bits in
1407 * the Device and MII Control Registers.
1408 */
1409 ctrl &= ~E1000_CTRL_FD;
1410 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1411 DEBUGOUT("Half Duplex\n");
1412 }
1413
1414 /* Are we forcing 100Mbps??? */
1415 if(hw->forced_speed_duplex == em_100_full ||
1416 hw->forced_speed_duplex == em_100_half) {
1417 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1418 ctrl |= E1000_CTRL_SPD_100;
1419 mii_ctrl_reg |= MII_CR_SPEED_100;
1420 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1421 DEBUGOUT("Forcing 100mb ");
1422 } else {
1423 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1424 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1425 mii_ctrl_reg |= MII_CR_SPEED_10;
1426 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1427 DEBUGOUT("Forcing 10mb ");
1428 }
1429
1430 em_config_collision_dist(hw);
1431
1432 /* Write the configured values back to the Device Control Reg. */
1433 E1000_WRITE_REG(hw, CTRL, ctrl);
1434
1435 if (hw->phy_type == em_phy_m88) {
0d366ee7
MD
1436 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1437 &phy_data)))
1438 return ret_val;
984263bc
MD
1439
1440 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1441 * forced whenever speed are duplex are forced.
1442 */
1443 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
0d366ee7
MD
1444 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1445 phy_data)))
1446 return ret_val;
1447
984263bc
MD
1448 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1449
1450 /* Need to reset the PHY or these changes will be ignored */
1451 mii_ctrl_reg |= MII_CR_RESET;
1452 } else {
1453 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1454 * forced whenever speed or duplex are forced.
1455 */
0d366ee7
MD
1456 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1457 &phy_data)))
1458 return ret_val;
984263bc
MD
1459
1460 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1461 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1462
0d366ee7
MD
1463 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1464 phy_data)))
1465 return ret_val;
984263bc
MD
1466 }
1467
1468 /* Write back the modified PHY MII control register. */
0d366ee7
MD
1469 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
1470 return ret_val;
1471
984263bc
MD
1472 usec_delay(1);
1473
1474 /* The wait_autoneg_complete flag may be a little misleading here.
1475 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1476 * But we do want to delay for a period while forcing only so we
1477 * don't generate false No Link messages. So we will wait here
1478 * only if the user has set wait_autoneg_complete to 1, which is
1479 * the default.
1480 */
1481 if(hw->wait_autoneg_complete) {
1482 /* We will wait for autoneg to complete. */
1483 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1484 mii_status_reg = 0;
1485
1486 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1487 for(i = PHY_FORCE_TIME; i > 0; i--) {
1488 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1489 * to be set.
1490 */
0d366ee7
MD
1491 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1492 return ret_val;
1493
1494 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1495 return ret_val;
1496
984263bc
MD
1497 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1498 msec_delay(100);
1499 }
0d366ee7
MD
1500 if((i == 0) && (hw->phy_type == em_phy_m88)) {
1501 /* We didn't get link. Reset the DSP and wait again for link. */
1502 if((ret_val = em_phy_reset_dsp(hw))) {
984263bc
MD
1503 DEBUGOUT("Error Resetting PHY DSP\n");
1504 return ret_val;
1505 }
1506 }
1507 /* This loop will early-out if the link condition has been met. */
1508 for(i = PHY_FORCE_TIME; i > 0; i--) {
1509 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1510 msec_delay(100);
1511 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1512 * to be set.
1513 */
0d366ee7
MD
1514 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1515 return ret_val;
1516
1517 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1518 return ret_val;
984263bc
MD
1519 }
1520 }
1521
1522 if (hw->phy_type == em_phy_m88) {
1523 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1524 * Extended PHY Specific Control Register to 25MHz clock. This value
1525 * defaults back to a 2.5MHz clock when the PHY is reset.
1526 */
0d366ee7
MD
1527 if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1528 &phy_data)))
1529 return ret_val;
1530
984263bc 1531 phy_data |= M88E1000_EPSCR_TX_CLK_25;
0d366ee7
MD
1532 if((ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1533 phy_data)))
1534 return ret_val;
984263bc
MD
1535
1536 /* In addition, because of the s/w reset above, we need to enable CRS on
1537 * TX. This must be set for both full and half duplex operation.
1538 */
0d366ee7
MD
1539 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1540 &phy_data)))
1541 return ret_val;
1542
984263bc 1543 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
0d366ee7
MD
1544 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1545 phy_data)))
1546 return ret_val;
1547
1548 /* Polarity reversal workaround for forced 10F/10H links. */
1549 if(hw->mac_type <= em_82544 &&
1550 (hw->forced_speed_duplex == em_10_full ||
1551 hw->forced_speed_duplex == em_10_half)) {
1552 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
1553 0x0019)))
1554 return ret_val;
1555 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
1556 0x8F0F)))
1557 return ret_val;
1558 /* IEEE requirement is 150ms */
1559 msec_delay(200);
1560 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
1561 0x0019)))
1562 return ret_val;
1563 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
1564 0x8F00)))
1565 return ret_val;
984263bc
MD
1566 }
1567 }
0d366ee7 1568 return E1000_SUCCESS;
984263bc
MD
1569}
1570
1571/******************************************************************************
1572* Sets the collision distance in the Transmit Control register
1573*
1574* hw - Struct containing variables accessed by shared code
1575*
1576* Link should have been established previously. Reads the speed and duplex
1577* information from the Device Status register.
1578******************************************************************************/
1579void
1580em_config_collision_dist(struct em_hw *hw)
1581{
1582 uint32_t tctl;
1583
1584 DEBUGFUNC("em_config_collision_dist");
1585
1586 tctl = E1000_READ_REG(hw, TCTL);
1587
1588 tctl &= ~E1000_TCTL_COLD;
1589 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1590
1591 E1000_WRITE_REG(hw, TCTL, tctl);
1592 E1000_WRITE_FLUSH(hw);
1593}
1594
1595/******************************************************************************
1596* Sets MAC speed and duplex settings to reflect the those in the PHY
1597*
1598* hw - Struct containing variables accessed by shared code
1599* mii_reg - data to write to the MII control register
1600*
1601* The contents of the PHY register containing the needed information need to
1602* be passed in.
1603******************************************************************************/
1604static int32_t
1605em_config_mac_to_phy(struct em_hw *hw)
1606{
1607 uint32_t ctrl;
0d366ee7 1608 int32_t ret_val;
984263bc
MD
1609 uint16_t phy_data;
1610
1611 DEBUGFUNC("em_config_mac_to_phy");
1612
1613 /* Read the Device Control Register and set the bits to Force Speed
1614 * and Duplex.
1615 */
1616 ctrl = E1000_READ_REG(hw, CTRL);
1617 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1618 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1619
1620 /* Set up duplex in the Device Control and Transmit Control
1621 * registers depending on negotiated values.
1622 */
1623 if (hw->phy_type == em_phy_igp) {
0d366ee7
MD
1624 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1625 &phy_data)))
1626 return ret_val;
1627
984263bc
MD
1628 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1629 else ctrl &= ~E1000_CTRL_FD;
1630
1631 em_config_collision_dist(hw);
1632
1633 /* Set up speed in the Device Control register depending on
1634 * negotiated values.
1635 */
1636 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1637 IGP01E1000_PSSR_SPEED_1000MBPS)
1638 ctrl |= E1000_CTRL_SPD_1000;
1639 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1640 IGP01E1000_PSSR_SPEED_100MBPS)
1641 ctrl |= E1000_CTRL_SPD_100;
1642 } else {
0d366ee7
MD
1643 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1644 &phy_data)))
1645 return ret_val;
1646
984263bc
MD
1647 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1648 else ctrl &= ~E1000_CTRL_FD;
1649
1650 em_config_collision_dist(hw);
1651
1652 /* Set up speed in the Device Control register depending on
1653 * negotiated values.
1654 */
1655 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1656 ctrl |= E1000_CTRL_SPD_1000;
1657 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1658 ctrl |= E1000_CTRL_SPD_100;
1659 }
1660 /* Write the configured values back to the Device Control Reg. */
1661 E1000_WRITE_REG(hw, CTRL, ctrl);
0d366ee7 1662 return E1000_SUCCESS;
984263bc
MD
1663}
1664
1665/******************************************************************************
1666 * Forces the MAC's flow control settings.
1667 *
1668 * hw - Struct containing variables accessed by shared code
1669 *
1670 * Sets the TFCE and RFCE bits in the device control register to reflect
1671 * the adapter settings. TFCE and RFCE need to be explicitly set by
1672 * software when a Copper PHY is used because autonegotiation is managed
1673 * by the PHY rather than the MAC. Software must also configure these
1674 * bits when link is forced on a fiber connection.
1675 *****************************************************************************/
0d366ee7 1676int32_t
984263bc
MD
1677em_force_mac_fc(struct em_hw *hw)
1678{
1679 uint32_t ctrl;
1680
1681 DEBUGFUNC("em_force_mac_fc");
1682
1683 /* Get the current configuration of the Device Control Register */
1684 ctrl = E1000_READ_REG(hw, CTRL);
1685
1686 /* Because we didn't get link via the internal auto-negotiation
1687 * mechanism (we either forced link or we got link via PHY
1688 * auto-neg), we have to manually enable/disable transmit an
1689 * receive flow control.
1690 *
1691 * The "Case" statement below enables/disable flow control
1692 * according to the "hw->fc" parameter.
1693 *
1694 * The possible values of the "fc" parameter are:
1695 * 0: Flow control is completely disabled
1696 * 1: Rx flow control is enabled (we can receive pause
1697 * frames but not send pause frames).
1698 * 2: Tx flow control is enabled (we can send pause frames
1699 * frames but we do not receive pause frames).
1700 * 3: Both Rx and TX flow control (symmetric) is enabled.
1701 * other: No other values should be possible at this point.
1702 */
1703
1704 switch (hw->fc) {
1705 case em_fc_none:
1706 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1707 break;
1708 case em_fc_rx_pause:
1709 ctrl &= (~E1000_CTRL_TFCE);
1710 ctrl |= E1000_CTRL_RFCE;
1711 break;
1712 case em_fc_tx_pause:
1713 ctrl &= (~E1000_CTRL_RFCE);
1714 ctrl |= E1000_CTRL_TFCE;
1715 break;
1716 case em_fc_full:
1717 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1718 break;
1719 default:
1720 DEBUGOUT("Flow control param set incorrectly\n");
1721 return -E1000_ERR_CONFIG;
1722 }
1723
1724 /* Disable TX Flow Control for 82542 (rev 2.0) */
1725 if(hw->mac_type == em_82542_rev2_0)
1726 ctrl &= (~E1000_CTRL_TFCE);
1727
1728 E1000_WRITE_REG(hw, CTRL, ctrl);
0d366ee7 1729 return E1000_SUCCESS;
984263bc
MD
1730}
1731
1732/******************************************************************************
1733 * Configures flow control settings after link is established
1734 *
1735 * hw - Struct containing variables accessed by shared code
1736 *
1737 * Should be called immediately after a valid link has been established.
1738 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1739 * and autonegotiation is enabled, the MAC flow control settings will be set
1740 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1741 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1742 *****************************************************************************/
1743int32_t
1744em_config_fc_after_link_up(struct em_hw *hw)
1745{
1746 int32_t ret_val;
1747 uint16_t mii_status_reg;
1748 uint16_t mii_nway_adv_reg;
1749 uint16_t mii_nway_lp_ability_reg;
1750 uint16_t speed;
1751 uint16_t duplex;
1752
1753 DEBUGFUNC("em_config_fc_after_link_up");
1754
1755 /* Check for the case where we have fiber media and auto-neg failed
1756 * so we had to force link. In this case, we need to force the
1757 * configuration of the MAC to match the "fc" parameter.
1758 */
1759 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
0d366ee7 1760 ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) ||
984263bc 1761 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
0d366ee7 1762 if((ret_val = em_force_mac_fc(hw))) {
984263bc
MD
1763 DEBUGOUT("Error forcing flow control settings\n");
1764 return ret_val;
1765 }
1766 }
1767
1768 /* Check for the case where we have copper media and auto-neg is
1769 * enabled. In this case, we need to check and see if Auto-Neg
1770 * has completed, and if so, how the PHY and link partner has
1771 * flow control configured.
1772 */
1773 if((hw->media_type == em_media_type_copper) && hw->autoneg) {
1774 /* Read the MII Status Register and check to see if AutoNeg
1775 * has completed. We read this twice because this reg has
1776 * some "sticky" (latched) bits.
1777 */
0d366ee7
MD
1778 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1779 return ret_val;
1780 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1781 return ret_val;
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MD
1782
1783 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1784 /* The AutoNeg process has completed, so we now need to
1785 * read both the Auto Negotiation Advertisement Register
1786 * (Address 4) and the Auto_Negotiation Base Page Ability
1787 * Register (Address 5) to determine how flow control was
1788 * negotiated.
1789 */
0d366ee7
MD
1790 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
1791 &mii_nway_adv_reg)))
1792 return ret_val;
1793 if((ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
1794 &mii_nway_lp_ability_reg)))
1795 return ret_val;
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MD
1796
1797 /* Two bits in the Auto Negotiation Advertisement Register
1798 * (Address 4) and two bits in the Auto Negotiation Base
1799 * Page Ability Register (Address 5) determine flow control
1800 * for both the PHY and the link partner. The following
1801 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1802 * 1999, describes these PAUSE resolution bits and how flow
1803 * control is determined based upon these settings.
1804 * NOTE: DC = Don't Care
1805 *
1806 * LOCAL DEVICE | LINK PARTNER
1807 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1808 *-------|---------|-------|---------|--------------------
1809 * 0 | 0 | DC | DC | em_fc_none
1810 * 0 | 1 | 0 | DC | em_fc_none
1811 * 0 | 1 | 1 | 0 | em_fc_none
1812 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1813 * 1 | 0 | 0 | DC | em_fc_none
1814 * 1 | DC | 1 | DC | em_fc_full
1815 * 1 | 1 | 0 | 0 | em_fc_none
1816 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1817 *
1818 */
1819 /* Are both PAUSE bits set to 1? If so, this implies
1820 * Symmetric Flow Control is enabled at both ends. The
1821 * ASM_DIR bits are irrelevant per the spec.
1822 *
1823 * For Symmetric Flow Control:
1824 *
1825 * LOCAL DEVICE | LINK PARTNER
1826 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1827 *-------|---------|-------|---------|--------------------
1828 * 1 | DC | 1 | DC | em_fc_full
1829 *
1830 */
1831 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1832 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1833 /* Now we need to check if the user selected RX ONLY
1834 * of pause frames. In this case, we had to advertise
1835 * FULL flow control because we could not advertise RX
1836 * ONLY. Hence, we must now check to see if we need to
1837 * turn OFF the TRANSMISSION of PAUSE frames.
1838 */
1839 if(hw->original_fc == em_fc_full) {
1840 hw->fc = em_fc_full;
1841 DEBUGOUT("Flow Control = FULL.\r\n");
1842 } else {
1843 hw->fc = em_fc_rx_pause;
1844 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1845 }
1846 }
1847 /* For receiving PAUSE frames ONLY.
1848 *
1849 * LOCAL DEVICE | LINK PARTNER
1850 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1851 *-------|---------|-------|---------|--------------------
1852 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1853 *
1854 */
1855 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1856 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1857 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1858 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1859 hw->fc = em_fc_tx_pause;
1860 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1861 }
1862 /* For transmitting PAUSE frames ONLY.
1863 *
1864 * LOCAL DEVICE | LINK PARTNER
1865 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1866 *-------|---------|-------|---------|--------------------
1867 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1868 *
1869 */
1870 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1871 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1872 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1873 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1874 hw->fc = em_fc_rx_pause;
1875 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1876 }
1877 /* Per the IEEE spec, at this point flow control should be
1878 * disabled. However, we want to consider that we could
1879 * be connected to a legacy switch that doesn't advertise
1880 * desired flow control, but can be forced on the link
1881 * partner. So if we advertised no flow control, that is
1882 * what we will resolve to. If we advertised some kind of
1883 * receive capability (Rx Pause Only or Full Flow Control)
1884 * and the link partner advertised none, we will configure
1885 * ourselves to enable Rx Flow Control only. We can do
1886 * this safely for two reasons: If the link partner really
1887 * didn't want flow control enabled, and we enable Rx, no
1888 * harm done since we won't be receiving any PAUSE frames
1889 * anyway. If the intent on the link partner was to have
1890 * flow control enabled, then by us enabling RX only, we
1891 * can at least receive pause frames and process them.
1892 * This is a good idea because in most cases, since we are
1893 * predominantly a server NIC, more times than not we will
1894 * be asked to delay transmission of packets than asking
1895 * our link partner to pause transmission of frames.
1896 */
0d366ee7
MD
1897 else if((hw->original_fc == em_fc_none ||
1898 hw->original_fc == em_fc_tx_pause) ||
1899 hw->fc_strict_ieee) {
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1900 hw->fc = em_fc_none;
1901 DEBUGOUT("Flow Control = NONE.\r\n");
1902 } else {
1903 hw->fc = em_fc_rx_pause;
1904 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1905 }
1906
1907 /* Now we need to do one last check... If we auto-
1908 * negotiated to HALF DUPLEX, flow control should not be
1909 * enabled per IEEE 802.3 spec.
1910 */
0d366ee7
MD
1911 if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
1912 DEBUGOUT("Error getting link speed and duplex\n");
1913 return ret_val;
1914 }
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MD
1915
1916 if(duplex == HALF_DUPLEX)
1917 hw->fc = em_fc_none;
1918
1919 /* Now we call a subroutine to actually force the MAC
1920 * controller to use the correct flow control settings.
1921 */
0d366ee7 1922 if((ret_val = em_force_mac_fc(hw))) {
984263bc
MD
1923 DEBUGOUT("Error forcing flow control settings\n");
1924 return ret_val;
0d366ee7 1925 }
984263bc
MD
1926 } else {
1927 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1928 }
1929 }
0d366ee7 1930 return E1000_SUCCESS;
984263bc
MD
1931}
1932
1933/******************************************************************************
1934 * Checks to see if the link status of the hardware has changed.
1935 *
1936 * hw - Struct containing variables accessed by shared code
1937 *
1938 * Called by any function that needs to check the link status of the adapter.
1939 *****************************************************************************/
1940int32_t
1941em_check_for_link(struct em_hw *hw)
1942{
1943 uint32_t rxcw;
1944 uint32_t ctrl;
1945 uint32_t status;
1946 uint32_t rctl;
0d366ee7 1947 uint32_t signal = 0;
984263bc
MD
1948 int32_t ret_val;
1949 uint16_t phy_data;
984263bc
MD
1950
1951 DEBUGFUNC("em_check_for_link");
1952
0d366ee7 1953 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
984263bc 1954 * set when the optics detect a signal. On older adapters, it will be
0d366ee7 1955 * cleared when there is a signal. This applies to fiber media only.
984263bc 1956 */
0d366ee7
MD
1957 if(hw->media_type == em_media_type_fiber)
1958 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
984263bc
MD
1959
1960 ctrl = E1000_READ_REG(hw, CTRL);
1961 status = E1000_READ_REG(hw, STATUS);
1962 rxcw = E1000_READ_REG(hw, RXCW);
1963
1964 /* If we have a copper PHY then we only want to go out to the PHY
1965 * registers to see if Auto-Neg has completed and/or if our link
1966 * status has changed. The get_link_status flag will be set if we
1967 * receive a Link Status Change interrupt or we have Rx Sequence
1968 * Errors.
1969 */
1970 if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
1971 /* First we want to see if the MII Status Register reports
1972 * link. If so, then we want to get the current speed/duplex
1973 * of the PHY.
1974 * Read the register twice since the link bit is sticky.
1975 */
0d366ee7
MD
1976 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1977 return ret_val;
1978 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1979 return ret_val;
984263bc
MD
1980
1981 if(phy_data & MII_SR_LINK_STATUS) {
1982 hw->get_link_status = FALSE;
1983 /* Check if there was DownShift, must be checked immediately after
1984 * link-up */
1985 em_check_downshift(hw);
1986
1987 } else {
1988 /* No link detected */
0d366ee7 1989 em_config_dsp_after_link_change(hw, FALSE);
984263bc
MD
1990 return 0;
1991 }
1992
1993 /* If we are forcing speed/duplex, then we simply return since
1994 * we have already determined whether we have link or not.
1995 */
1996 if(!hw->autoneg) return -E1000_ERR_CONFIG;
1997
0d366ee7
MD
1998 /* optimize the dsp settings for the igp phy */
1999 em_config_dsp_after_link_change(hw, TRUE);
2000
984263bc
MD
2001 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2002 * have Si on board that is 82544 or newer, Auto
2003 * Speed Detection takes care of MAC speed/duplex
2004 * configuration. So we only need to configure Collision
2005 * Distance in the MAC. Otherwise, we need to force
2006 * speed/duplex on the MAC to the current PHY speed/duplex
2007 * settings.
2008 */
2009 if(hw->mac_type >= em_82544)
2010 em_config_collision_dist(hw);
2011 else {
0d366ee7 2012 if((ret_val = em_config_mac_to_phy(hw))) {
984263bc
MD
2013 DEBUGOUT("Error configuring MAC to PHY settings\n");
2014 return ret_val;
2015 }
2016 }
2017
2018 /* Configure Flow Control now that Auto-Neg has completed. First, we
2019 * need to restore the desired flow control settings because we may
2020 * have had to re-autoneg with a different link partner.
2021 */
0d366ee7 2022 if((ret_val = em_config_fc_after_link_up(hw))) {
984263bc
MD
2023 DEBUGOUT("Error configuring flow control\n");
2024 return ret_val;
2025 }
2026
2027 /* At this point we know that we are on copper and we have
2028 * auto-negotiated link. These are conditions for checking the link
0d366ee7
MD
2029 * partner capability register. We use the link speed to determine if
2030 * TBI compatibility needs to be turned on or off. If the link is not
2031 * at gigabit speed, then TBI compatibility is not needed. If we are
2032 * at gigabit speed, we turn on TBI compatibility.
984263bc 2033 */
0d366ee7
MD
2034 if(hw->tbi_compatibility_en) {
2035 uint16_t speed, duplex;
2036 em_get_speed_and_duplex(hw, &speed, &duplex);
2037 if(speed != SPEED_1000) {
2038 /* If link speed is not set to gigabit speed, we do not need
2039 * to enable TBI compatibility.
984263bc
MD
2040 */
2041 if(hw->tbi_compatibility_on) {
2042 /* If we previously were in the mode, turn it off. */
2043 rctl = E1000_READ_REG(hw, RCTL);
2044 rctl &= ~E1000_RCTL_SBP;
2045 E1000_WRITE_REG(hw, RCTL, rctl);
2046 hw->tbi_compatibility_on = FALSE;
2047 }
2048 } else {
2049 /* If TBI compatibility is was previously off, turn it on. For
2050 * compatibility with a TBI link partner, we will store bad
2051 * packets. Some frames have an additional byte on the end and
2052 * will look like CRC errors to to the hardware.
2053 */
2054 if(!hw->tbi_compatibility_on) {
2055 hw->tbi_compatibility_on = TRUE;
2056 rctl = E1000_READ_REG(hw, RCTL);
2057 rctl |= E1000_RCTL_SBP;
2058 E1000_WRITE_REG(hw, RCTL, rctl);
2059 }
2060 }
2061 }
2062 }
2063 /* If we don't have link (auto-negotiation failed or link partner cannot
2064 * auto-negotiate), the cable is plugged in (we have signal), and our
2065 * link partner is not trying to auto-negotiate with us (we are receiving
2066 * idles or data), we need to force link up. We also need to give
2067 * auto-negotiation time to complete, in case the cable was just plugged
2068 * in. The autoneg_failed flag does this.
2069 */
0d366ee7
MD
2070 else if((((hw->media_type == em_media_type_fiber) &&
2071 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2072 (hw->media_type == em_media_type_internal_serdes)) &&
984263bc 2073 (!(status & E1000_STATUS_LU)) &&
984263bc
MD
2074 (!(rxcw & E1000_RXCW_C))) {
2075 if(hw->autoneg_failed == 0) {
2076 hw->autoneg_failed = 1;
2077 return 0;
2078 }
2079 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2080
2081 /* Disable auto-negotiation in the TXCW register */
2082 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2083
2084 /* Force link-up and also force full-duplex. */
2085 ctrl = E1000_READ_REG(hw, CTRL);
2086 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2087 E1000_WRITE_REG(hw, CTRL, ctrl);
2088
2089 /* Configure Flow Control after forcing link up. */
0d366ee7 2090 if((ret_val = em_config_fc_after_link_up(hw))) {
984263bc
MD
2091 DEBUGOUT("Error configuring flow control\n");
2092 return ret_val;
2093 }
2094 }
2095 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2096 * auto-negotiation in the TXCW register and disable forced link in the
2097 * Device Control register in an attempt to auto-negotiate with our link
2098 * partner.
2099 */
0d366ee7
MD
2100 else if(((hw->media_type == em_media_type_fiber) ||
2101 (hw->media_type == em_media_type_internal_serdes)) &&
984263bc
MD
2102 (ctrl & E1000_CTRL_SLU) &&
2103 (rxcw & E1000_RXCW_C)) {
2104 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2105 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2106 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
0d366ee7
MD
2107
2108 hw->serdes_link_down = FALSE;
2109 }
2110 /* If we force link for non-auto-negotiation switch, check link status
2111 * based on MAC synchronization for internal serdes media type.
2112 */
2113 else if((hw->media_type == em_media_type_internal_serdes) &&
2114 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2115 /* SYNCH bit and IV bit are sticky. */
2116 usec_delay(10);
2117 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2118 if(!(rxcw & E1000_RXCW_IV)) {
2119 hw->serdes_link_down = FALSE;
2120 DEBUGOUT("SERDES: Link is up.\n");
2121 }
2122 } else {
2123 hw->serdes_link_down = TRUE;
2124 DEBUGOUT("SERDES: Link is down.\n");
2125 }
984263bc 2126 }
0d366ee7
MD
2127 if((hw->media_type == em_media_type_internal_serdes) &&
2128 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2129 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2130 }
2131 return E1000_SUCCESS;
984263bc
MD
2132}
2133
2134/******************************************************************************
2135 * Detects the current speed and duplex settings of the hardware.
2136 *
2137 * hw - Struct containing variables accessed by shared code
2138 * speed - Speed of the connection
2139 * duplex - Duplex setting of the connection
2140 *****************************************************************************/
0d366ee7 2141int32_t
984263bc
MD
2142em_get_speed_and_duplex(struct em_hw *hw,
2143 uint16_t *speed,
2144 uint16_t *duplex)
2145{
2146 uint32_t status;
0d366ee7
MD
2147 int32_t ret_val;
2148 uint16_t phy_data;
984263bc
MD
2149
2150 DEBUGFUNC("em_get_speed_and_duplex");
2151
2152 if(hw->mac_type >= em_82543) {
2153 status = E1000_READ_REG(hw, STATUS);
2154 if(status & E1000_STATUS_SPEED_1000) {
2155 *speed = SPEED_1000;
2156 DEBUGOUT("1000 Mbs, ");
2157 } else if(status & E1000_STATUS_SPEED_100) {
2158 *speed = SPEED_100;
2159 DEBUGOUT("100 Mbs, ");
2160 } else {
2161 *speed = SPEED_10;
2162 DEBUGOUT("10 Mbs, ");
2163 }
2164
2165 if(status & E1000_STATUS_FD) {
2166 *duplex = FULL_DUPLEX;
2167 DEBUGOUT("Full Duplex\r\n");
2168 } else {
2169 *duplex = HALF_DUPLEX;
2170 DEBUGOUT(" Half Duplex\r\n");
2171 }
2172 } else {
2173 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2174 *speed = SPEED_1000;
2175 *duplex = FULL_DUPLEX;
2176 }
0d366ee7
MD
2177
2178 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2179 * if it is operating at half duplex. Here we set the duplex settings to
2180 * match the duplex in the link partner's capabilities.
2181 */
2182 if(hw->phy_type == em_phy_igp && hw->speed_downgraded) {
2183 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
2184 return ret_val;
2185
2186 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2187 *duplex = HALF_DUPLEX;
2188 else {
2189 if((ret_val == em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
2190 return ret_val;
2191 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2192 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2193 *duplex = HALF_DUPLEX;
2194 }
2195 }
2196
2197 return E1000_SUCCESS;
984263bc
MD
2198}
2199
2200/******************************************************************************
2201* Blocks until autoneg completes or times out (~4.5 seconds)
2202*
2203* hw - Struct containing variables accessed by shared code
2204******************************************************************************/
2205int32_t
2206em_wait_autoneg(struct em_hw *hw)
2207{
0d366ee7 2208 int32_t ret_val;
984263bc
MD
2209 uint16_t i;
2210 uint16_t phy_data;
2211
2212 DEBUGFUNC("em_wait_autoneg");
2213 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2214
2215 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2216 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2217 /* Read the MII Status Register and wait for Auto-Neg
2218 * Complete bit to be set.
2219 */
0d366ee7
MD
2220 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2221 return ret_val;
2222 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2223 return ret_val;
984263bc 2224 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
0d366ee7 2225 return E1000_SUCCESS;
984263bc
MD
2226 }
2227 msec_delay(100);
2228 }
0d366ee7 2229 return E1000_SUCCESS;
984263bc
MD
2230}
2231
2232/******************************************************************************
2233* Raises the Management Data Clock
2234*
2235* hw - Struct containing variables accessed by shared code
2236* ctrl - Device control register's current value
2237******************************************************************************/
2238static void
2239em_raise_mdi_clk(struct em_hw *hw,
2240 uint32_t *ctrl)
2241{
2242 /* Raise the clock input to the Management Data Clock (by setting the MDC
0d366ee7 2243 * bit), and then delay 10 microseconds.
984263bc
MD
2244 */
2245 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2246 E1000_WRITE_FLUSH(hw);
0d366ee7 2247 usec_delay(10);
984263bc
MD
2248}
2249
2250/******************************************************************************
2251* Lowers the Management Data Clock
2252*
2253* hw - Struct containing variables accessed by shared code
2254* ctrl - Device control register's current value
2255******************************************************************************/
2256static void
2257em_lower_mdi_clk(struct em_hw *hw,
2258 uint32_t *ctrl)
2259{
2260 /* Lower the clock input to the Management Data Clock (by clearing the MDC
0d366ee7 2261 * bit), and then delay 10 microseconds.
984263bc
MD
2262 */
2263 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2264 E1000_WRITE_FLUSH(hw);
0d366ee7 2265 usec_delay(10);
984263bc
MD
2266}
2267
2268/******************************************************************************
2269* Shifts data bits out to the PHY
2270*
2271* hw - Struct containing variables accessed by shared code
2272* data - Data to send out to the PHY
2273* count - Number of bits to shift out
2274*
2275* Bits are shifted out in MSB to LSB order.
2276******************************************************************************/
2277static void
2278em_shift_out_mdi_bits(struct em_hw *hw,
2279 uint32_t data,
2280 uint16_t count)
2281{
2282 uint32_t ctrl;
2283 uint32_t mask;
2284
2285 /* We need to shift "count" number of bits out to the PHY. So, the value
2286 * in the "data" parameter will be shifted out to the PHY one bit at a
2287 * time. In order to do this, "data" must be broken down into bits.
2288 */
2289 mask = 0x01;
2290 mask <<= (count - 1);
2291
2292 ctrl = E1000_READ_REG(hw, CTRL);
2293
2294 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2295 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2296
2297 while(mask) {
2298 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2299 * then raising and lowering the Management Data Clock. A "0" is
2300 * shifted out to the PHY by setting the MDIO bit to "0" and then
2301 * raising and lowering the clock.
2302 */
2303 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2304 else ctrl &= ~E1000_CTRL_MDIO;
2305
2306 E1000_WRITE_REG(hw, CTRL, ctrl);
2307 E1000_WRITE_FLUSH(hw);
2308
0d366ee7 2309 usec_delay(10);
984263bc
MD
2310
2311 em_raise_mdi_clk(hw, &ctrl);
2312 em_lower_mdi_clk(hw, &ctrl);
2313
2314 mask = mask >> 1;
2315 }
2316}
2317
2318/******************************************************************************
2319* Shifts data bits in from the PHY
2320*
2321* hw - Struct containing variables accessed by shared code
2322*
2323* Bits are shifted in in MSB to LSB order.
2324******************************************************************************/
2325static uint16_t
2326em_shift_in_mdi_bits(struct em_hw *hw)
2327{
2328 uint32_t ctrl;
2329 uint16_t data = 0;
2330 uint8_t i;
2331
2332 /* In order to read a register from the PHY, we need to shift in a total
2333 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2334 * to avoid contention on the MDIO pin when a read operation is performed.
2335 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2336 * by raising the input to the Management Data Clock (setting the MDC bit),
2337 * and then reading the value of the MDIO bit.
2338 */
2339 ctrl = E1000_READ_REG(hw, CTRL);
2340
2341 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2342 ctrl &= ~E1000_CTRL_MDIO_DIR;
2343 ctrl &= ~E1000_CTRL_MDIO;
2344
2345 E1000_WRITE_REG(hw, CTRL, ctrl);
2346 E1000_WRITE_FLUSH(hw);
2347
2348 /* Raise and Lower the clock before reading in the data. This accounts for
2349 * the turnaround bits. The first clock occurred when we clocked out the
2350 * last bit of the Register Address.
2351 */
2352 em_raise_mdi_clk(hw, &ctrl);
2353 em_lower_mdi_clk(hw, &ctrl);
2354
2355 for(data = 0, i = 0; i < 16; i++) {
2356 data = data << 1;
2357 em_raise_mdi_clk(hw, &ctrl);
2358 ctrl = E1000_READ_REG(hw, CTRL);
2359 /* Check to see if we shifted in a "1". */
2360 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2361 em_lower_mdi_clk(hw, &ctrl);
2362 }
2363
2364 em_raise_mdi_clk(hw, &ctrl);
2365 em_lower_mdi_clk(hw, &ctrl);
2366
2367 return data;
2368}
2369
2370/*****************************************************************************
0d366ee7
MD
2371* Reads the value from a PHY register, if the value is on a specific non zero
2372* page, sets the page first.
984263bc
MD
2373* hw - Struct containing variables accessed by shared code
2374* reg_addr - address of the PHY register to read
2375******************************************************************************/
2376int32_t
2377em_read_phy_reg(struct em_hw *hw,
2378 uint32_t reg_addr,
2379 uint16_t *phy_data)
0d366ee7
MD
2380{
2381 uint32_t ret_val;
2382
2383 DEBUGFUNC("em_read_phy_reg");
2384
2385 if(hw->phy_type == em_phy_igp &&
2386 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2387 if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2388 (uint16_t)reg_addr)))
2389 return ret_val;
2390 }
2391
2392 ret_val = em_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2393 phy_data);
2394
2395 return ret_val;
2396}
2397
2398int32_t
2399em_read_phy_reg_ex(struct em_hw *hw,
2400 uint32_t reg_addr,
2401 uint16_t *phy_data)
984263bc
MD
2402{
2403 uint32_t i;
2404 uint32_t mdic = 0;
2405 const uint32_t phy_addr = 1;
2406
0d366ee7 2407 DEBUGFUNC("em_read_phy_reg_ex");
984263bc
MD
2408
2409 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2410 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2411 return -E1000_ERR_PARAM;
2412 }
2413
2414 if(hw->mac_type > em_82543) {
2415 /* Set up Op-code, Phy Address, and register address in the MDI
2416 * Control register. The MAC will take care of interfacing with the
2417 * PHY to retrieve the desired data.
2418 */
2419 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2420 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2421 (E1000_MDIC_OP_READ));
2422
2423 E1000_WRITE_REG(hw, MDIC, mdic);
2424
2425 /* Poll the ready bit to see if the MDI read completed */
2426 for(i = 0; i < 64; i++) {
0d366ee7 2427 usec_delay(50);
984263bc
MD
2428 mdic = E1000_READ_REG(hw, MDIC);
2429 if(mdic & E1000_MDIC_READY) break;
2430 }
2431 if(!(mdic & E1000_MDIC_READY)) {
2432 DEBUGOUT("MDI Read did not complete\n");
2433 return -E1000_ERR_PHY;
2434 }
2435 if(mdic & E1000_MDIC_ERROR) {
2436 DEBUGOUT("MDI Error\n");
2437 return -E1000_ERR_PHY;
2438 }
2439 *phy_data = (uint16_t) mdic;
2440 } else {
2441 /* We must first send a preamble through the MDIO pin to signal the
2442 * beginning of an MII instruction. This is done by sending 32
2443 * consecutive "1" bits.
2444 */
2445 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2446
2447 /* Now combine the next few fields that are required for a read
2448 * operation. We use this method instead of calling the
2449 * em_shift_out_mdi_bits routine five different times. The format of
2450 * a MII read instruction consists of a shift out of 14 bits and is
2451 * defined as follows:
2452 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2453 * followed by a shift in of 18 bits. This first two bits shifted in
2454 * are TurnAround bits used to avoid contention on the MDIO pin when a
2455 * READ operation is performed. These two bits are thrown away
2456 * followed by a shift in of 16 bits which contains the desired data.
2457 */
2458 mdic = ((reg_addr) | (phy_addr << 5) |
2459 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2460
2461 em_shift_out_mdi_bits(hw, mdic, 14);
2462
2463 /* Now that we've shifted out the read command to the MII, we need to
2464 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2465 * register address.
2466 */
2467 *phy_data = em_shift_in_mdi_bits(hw);
2468 }
0d366ee7 2469 return E1000_SUCCESS;
984263bc
MD
2470}
2471
2472/******************************************************************************
2473* Writes a value to a PHY register
2474*
2475* hw - Struct containing variables accessed by shared code
2476* reg_addr - address of the PHY register to write
2477* data - data to write to the PHY
2478******************************************************************************/
2479int32_t
2480em_write_phy_reg(struct em_hw *hw,
2481 uint32_t reg_addr,
2482 uint16_t phy_data)
0d366ee7
MD
2483{
2484 uint32_t ret_val;
2485
2486 DEBUGFUNC("em_write_phy_reg");
2487
2488 if(hw->phy_type == em_phy_igp &&
2489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2490 if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2491 (uint16_t)reg_addr)))
2492 return ret_val;
2493 }
2494
2495 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2496 phy_data);
2497
2498 return ret_val;
2499}
2500
2501int32_t
2502em_write_phy_reg_ex(struct em_hw *hw,
2503 uint32_t reg_addr,
2504 uint16_t phy_data)
984263bc
MD
2505{
2506 uint32_t i;
2507 uint32_t mdic = 0;
2508 const uint32_t phy_addr = 1;
2509
0d366ee7 2510 DEBUGFUNC("em_write_phy_reg_ex");
984263bc
MD
2511
2512 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2513 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2514 return -E1000_ERR_PARAM;
2515 }
2516
2517 if(hw->mac_type > em_82543) {
2518 /* Set up Op-code, Phy Address, register address, and data intended
2519 * for the PHY register in the MDI Control register. The MAC will take
2520 * care of interfacing with the PHY to send the desired data.
2521 */
2522 mdic = (((uint32_t) phy_data) |
2523 (reg_addr << E1000_MDIC_REG_SHIFT) |
2524 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2525 (E1000_MDIC_OP_WRITE));
2526
2527 E1000_WRITE_REG(hw, MDIC, mdic);
2528
2529 /* Poll the ready bit to see if the MDI read completed */
0d366ee7
MD
2530 for(i = 0; i < 640; i++) {
2531 usec_delay(5);
984263bc
MD
2532 mdic = E1000_READ_REG(hw, MDIC);
2533 if(mdic & E1000_MDIC_READY) break;
2534 }
2535 if(!(mdic & E1000_MDIC_READY)) {
2536 DEBUGOUT("MDI Write did not complete\n");
2537 return -E1000_ERR_PHY;
2538 }
2539 } else {
2540 /* We'll need to use the SW defined pins to shift the write command
2541 * out to the PHY. We first send a preamble to the PHY to signal the
2542 * beginning of the MII instruction. This is done by sending 32
2543 * consecutive "1" bits.
2544 */
2545 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2546
2547 /* Now combine the remaining required fields that will indicate a
2548 * write operation. We use this method instead of calling the
2549 * em_shift_out_mdi_bits routine for each field in the command. The
2550 * format of a MII write instruction is as follows:
2551 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2552 */
2553 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2554 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2555 mdic <<= 16;
2556 mdic |= (uint32_t) phy_data;
2557
2558 em_shift_out_mdi_bits(hw, mdic, 32);
2559 }
2560
0d366ee7 2561 return E1000_SUCCESS;
984263bc
MD
2562}
2563
2564/******************************************************************************
2565* Returns the PHY to the power-on reset state
2566*
2567* hw - Struct containing variables accessed by shared code
2568******************************************************************************/
2569void
2570em_phy_hw_reset(struct em_hw *hw)
2571{
2572 uint32_t ctrl, ctrl_ext;
2573 uint32_t led_ctrl;
2574
2575 DEBUGFUNC("em_phy_hw_reset");
2576
2577 DEBUGOUT("Resetting Phy...\n");
2578
2579 if(hw->mac_type > em_82543) {
2580 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2581 * bit. Then, take it out of reset.
2582 */
2583 ctrl = E1000_READ_REG(hw, CTRL);
2584 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2585 E1000_WRITE_FLUSH(hw);
2586 msec_delay(10);
2587 E1000_WRITE_REG(hw, CTRL, ctrl);
2588 E1000_WRITE_FLUSH(hw);
2589 } else {
2590 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2591 * bit to put the PHY into reset. Then, take it out of reset.
2592 */
2593 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2594 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2595 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2596 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2597 E1000_WRITE_FLUSH(hw);
2598 msec_delay(10);
2599 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2600 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2601 E1000_WRITE_FLUSH(hw);
2602 }
2603 usec_delay(150);
2604
2605 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
984263bc
MD
2606 /* Configure activity LED after PHY reset */
2607 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2608 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2609 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2610 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2611 }
2612}
2613
2614/******************************************************************************
2615* Resets the PHY
2616*
2617* hw - Struct containing variables accessed by shared code
2618*
2619* Sets bit 15 of the MII Control regiser
2620******************************************************************************/
2621int32_t
2622em_phy_reset(struct em_hw *hw)
2623{
0d366ee7 2624 int32_t ret_val;
984263bc
MD
2625 uint16_t phy_data;
2626
2627 DEBUGFUNC("em_phy_reset");
2628
0d366ee7
MD
2629 if(hw->mac_type != em_82541_rev_2) {
2630 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2631 return ret_val;
2632
2633 phy_data |= MII_CR_RESET;
2634 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
2635 return ret_val;
2636
2637 usec_delay(1);
2638 } else em_phy_hw_reset(hw);
2639
2640 if(hw->phy_type == em_phy_igp)
984263bc 2641 em_phy_init_script(hw);
0d366ee7
MD
2642
2643 return E1000_SUCCESS;
984263bc
MD
2644}
2645
2646/******************************************************************************
2647* Probes the expected PHY address for known PHY IDs
2648*
2649* hw - Struct containing variables accessed by shared code
2650******************************************************************************/
2651int32_t
2652em_detect_gig_phy(struct em_hw *hw)
2653{
0d366ee7 2654 int32_t phy_init_status, ret_val;
984263bc
MD
2655 uint16_t phy_id_high, phy_id_low;
2656 boolean_t match = FALSE;
984263bc
MD
2657
2658 DEBUGFUNC("em_detect_gig_phy");
2659
2660 /* Read the PHY ID Registers to identify which PHY is onboard. */
0d366ee7
MD
2661 if((ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2662 return ret_val;
2663
984263bc
MD
2664 hw->phy_id = (uint32_t) (phy_id_high << 16);
2665 usec_delay(20);
0d366ee7
MD
2666 if((ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2667 return ret_val;
2668
984263bc
MD
2669 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2670 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2671
2672 switch(hw->mac_type) {
2673 case em_82543:
2674 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2675 break;
2676 case em_82544:
2677 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2678 break;
2679 case em_82540:
2680 case em_82545:
0d366ee7 2681 case em_82545_rev_3:
984263bc 2682 case em_82546:
0d366ee7 2683 case em_82546_rev_3:
984263bc
MD
2684 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2685 break;
2686 case em_82541:
0d366ee7 2687 case em_82541_rev_2:
984263bc 2688 case em_82547:
0d366ee7 2689 case em_82547_rev_2:
984263bc
MD
2690 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2691 break;
2692 default:
2693 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2694 return -E1000_ERR_CONFIG;
2695 }
2696 phy_init_status = em_set_phy_type(hw);
2697
2698 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2699 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
0d366ee7 2700 return E1000_SUCCESS;
984263bc
MD
2701 }
2702 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2703 return -E1000_ERR_PHY;
2704}
2705
2706/******************************************************************************
2707* Resets the PHY's DSP
2708*
2709* hw - Struct containing variables accessed by shared code
2710******************************************************************************/
2711static int32_t
2712em_phy_reset_dsp(struct em_hw *hw)
2713{
0d366ee7 2714 int32_t ret_val;
984263bc
MD
2715 DEBUGFUNC("em_phy_reset_dsp");
2716
2717 do {
0d366ee7
MD
2718 if((ret_val = em_write_phy_reg(hw, 29, 0x001d))) break;
2719 if((ret_val = em_write_phy_reg(hw, 30, 0x00c1))) break;
2720 if((ret_val = em_write_phy_reg(hw, 30, 0x0000))) break;
2721 ret_val = E1000_SUCCESS;
984263bc
MD
2722 } while(0);
2723
984263bc
MD
2724 return ret_val;
2725}
2726
2727/******************************************************************************
2728* Get PHY information from various PHY registers for igp PHY only.
2729*
2730* hw - Struct containing variables accessed by shared code
2731* phy_info - PHY information structure
2732******************************************************************************/
2733int32_t
0d366ee7
MD
2734em_phy_igp_get_info(struct em_hw *hw,
2735 struct em_phy_info *phy_info)
984263bc 2736{
0d366ee7 2737 int32_t ret_val;
984263bc
MD
2738 uint16_t phy_data, polarity, min_length, max_length, average;
2739
2740 DEBUGFUNC("em_phy_igp_get_info");
2741
2742 /* The downshift status is checked only once, after link is established,
2743 * and it stored in the hw->speed_downgraded parameter. */
2744 phy_info->downshift = hw->speed_downgraded;
2745
2746 /* IGP01E1000 does not need to support it. */
2747 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
2748
2749 /* IGP01E1000 always correct polarity reversal */
2750 phy_info->polarity_correction = em_polarity_reversal_enabled;
2751
2752 /* Check polarity status */
0d366ee7
MD
2753 if((ret_val = em_check_polarity(hw, &polarity)))
2754 return ret_val;
984263bc
MD
2755
2756 phy_info->cable_polarity = polarity;
2757
0d366ee7
MD
2758 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2759 &phy_data)))
2760 return ret_val;
984263bc
MD
2761
2762 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2763 IGP01E1000_PSSR_MDIX_SHIFT;
2764
2765 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2766 IGP01E1000_PSSR_SPEED_1000MBPS) {
2767 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
0d366ee7
MD
2768 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2769 return ret_val;
984263bc
MD
2770
2771 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2772 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2773 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2774 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2775
2776 /* Get cable length */
0d366ee7
MD
2777 if((ret_val = em_get_cable_length(hw, &min_length, &max_length)))
2778 return ret_val;
984263bc
MD
2779
2780 /* transalte to old method */
2781 average = (max_length + min_length) / 2;
2782
2783 if(average <= em_igp_cable_length_50)
2784 phy_info->cable_length = em_cable_length_50;
2785 else if(average <= em_igp_cable_length_80)
2786 phy_info->cable_length = em_cable_length_50_80;
2787 else if(average <= em_igp_cable_length_110)
2788 phy_info->cable_length = em_cable_length_80_110;
2789 else if(average <= em_igp_cable_length_140)
2790 phy_info->cable_length = em_cable_length_110_140;
2791 else
2792 phy_info->cable_length = em_cable_length_140;
2793 }
2794
2795 return E1000_SUCCESS;
2796}
2797
2798/******************************************************************************
2799* Get PHY information from various PHY registers fot m88 PHY only.
2800*
2801* hw - Struct containing variables accessed by shared code
2802* phy_info - PHY information structure
2803******************************************************************************/
2804int32_t
0d366ee7
MD
2805em_phy_m88_get_info(struct em_hw *hw,
2806 struct em_phy_info *phy_info)
984263bc 2807{
0d366ee7 2808 int32_t ret_val;
984263bc
MD
2809 uint16_t phy_data, polarity;
2810
2811 DEBUGFUNC("em_phy_m88_get_info");
2812
2813 /* The downshift status is checked only once, after link is established,
2814 * and it stored in the hw->speed_downgraded parameter. */
2815 phy_info->downshift = hw->speed_downgraded;
2816
0d366ee7
MD
2817 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
2818 return ret_val;
984263bc
MD
2819
2820 phy_info->extended_10bt_distance =
2821 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2822 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2823 phy_info->polarity_correction =
2824 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2825 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2826
2827 /* Check polarity status */
0d366ee7
MD
2828 if((ret_val = em_check_polarity(hw, &polarity)))
2829 return ret_val;
984263bc
MD
2830
2831 phy_info->cable_polarity = polarity;
2832
0d366ee7
MD
2833 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
2834 return ret_val;
984263bc
MD
2835
2836 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2837 M88E1000_PSSR_MDIX_SHIFT;
2838
2839 if(phy_data & M88E1000_PSSR_1000MBS) {
2840 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2841 * are only valid at 1000 Mbps
2842 */
2843 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2844 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2845
0d366ee7
MD
2846 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2847 return ret_val;
984263bc
MD
2848
2849 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2850 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2851
2852 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2853 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2854 }
2855
2856 return E1000_SUCCESS;
2857}
2858
2859/******************************************************************************
2860* Get PHY information from various PHY registers
2861*
2862* hw - Struct containing variables accessed by shared code
2863* phy_info - PHY information structure
2864******************************************************************************/
2865int32_t
2866em_phy_get_info(struct em_hw *hw,
2867 struct em_phy_info *phy_info)
2868{
0d366ee7 2869 int32_t ret_val;
984263bc
MD
2870 uint16_t phy_data;
2871
2872 DEBUGFUNC("em_phy_get_info");
2873
2874 phy_info->cable_length = em_cable_length_undefined;
2875 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
2876 phy_info->cable_polarity = em_rev_polarity_undefined;
2877 phy_info->downshift = em_downshift_undefined;
2878 phy_info->polarity_correction = em_polarity_reversal_undefined;
2879 phy_info->mdix_mode = em_auto_x_mode_undefined;
2880 phy_info->local_rx = em_1000t_rx_status_undefined;
2881 phy_info->remote_rx = em_1000t_rx_status_undefined;
2882
2883 if(hw->media_type != em_media_type_copper) {
2884 DEBUGOUT("PHY info is only valid for copper media\n");
2885 return -E1000_ERR_CONFIG;
2886 }
2887
0d366ee7
MD
2888 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2889 return ret_val;
2890
2891 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2892 return ret_val;
2893
984263bc
MD
2894 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2895 DEBUGOUT("PHY info is only valid if link is up\n");
2896 return -E1000_ERR_CONFIG;
2897 }
2898
0d366ee7 2899 if(hw->phy_type == em_phy_igp)
984263bc
MD
2900 return em_phy_igp_get_info(hw, phy_info);
2901 else
2902 return em_phy_m88_get_info(hw, phy_info);
2903}
2904
2905int32_t
2906em_validate_mdi_setting(struct em_hw *hw)
2907{
2908 DEBUGFUNC("em_validate_mdi_settings");
2909
2910 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2911 DEBUGOUT("Invalid MDI setting detected\n");
2912 hw->mdix = 1;
2913 return -E1000_ERR_CONFIG;
2914 }
0d366ee7 2915 return E1000_SUCCESS;
984263bc
MD
2916}
2917
2918
2919/******************************************************************************
2920 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2921 * is configured.
2922 *
2923 * hw - Struct containing variables accessed by shared code
2924 *****************************************************************************/
2925void
2926em_init_eeprom_params(struct em_hw *hw)
2927{
2928 struct em_eeprom_info *eeprom = &hw->eeprom;
2929 uint32_t eecd = E1000_READ_REG(hw, EECD);
2930 uint16_t eeprom_size;
2931
2932 DEBUGFUNC("em_init_eeprom_params");
2933
2934 switch (hw->mac_type) {
2935 case em_82542_rev2_0:
2936 case em_82542_rev2_1:
2937 case em_82543:
2938 case em_82544:
2939 eeprom->type = em_eeprom_microwire;
2940 eeprom->word_size = 64;
2941 eeprom->opcode_bits = 3;
2942 eeprom->address_bits = 6;
2943 eeprom->delay_usec = 50;
2944 break;
2945 case em_82540:
2946 case em_82545:
0d366ee7 2947 case em_82545_rev_3:
984263bc 2948 case em_82546:
0d366ee7 2949 case em_82546_rev_3:
984263bc
MD
2950 eeprom->type = em_eeprom_microwire;
2951 eeprom->opcode_bits = 3;
2952 eeprom->delay_usec = 50;
2953 if(eecd & E1000_EECD_SIZE) {
2954 eeprom->word_size = 256;
2955 eeprom->address_bits = 8;
2956 } else {
2957 eeprom->word_size = 64;
2958 eeprom->address_bits = 6;
2959 }
2960 break;
2961 case em_82541:
0d366ee7 2962 case em_82541_rev_2:
984263bc 2963 case em_82547:
0d366ee7 2964 case em_82547_rev_2:
984263bc
MD
2965 if (eecd & E1000_EECD_TYPE) {
2966 eeprom->type = em_eeprom_spi;
2967 eeprom->opcode_bits = 8;
2968 eeprom->delay_usec = 1;
2969 if (eecd & E1000_EECD_ADDR_BITS) {
2970 eeprom->page_size = 32;
2971 eeprom->address_bits = 16;
2972 } else {
2973 eeprom->page_size = 8;
2974 eeprom->address_bits = 8;
2975 }
2976 } else {
2977 eeprom->type = em_eeprom_microwire;
2978 eeprom->opcode_bits = 3;
2979 eeprom->delay_usec = 50;
2980 if (eecd & E1000_EECD_ADDR_BITS) {
2981 eeprom->word_size = 256;
2982 eeprom->address_bits = 8;
2983 } else {
2984 eeprom->word_size = 64;
2985 eeprom->address_bits = 6;
2986 }
2987 }
2988 break;
0d366ee7
MD
2989 default:
2990 eeprom->type = em_eeprom_spi;
2991 eeprom->opcode_bits = 8;
2992 eeprom->delay_usec = 1;
2993 if (eecd & E1000_EECD_ADDR_BITS) {
2994 eeprom->page_size = 32;
2995 eeprom->address_bits = 16;
2996 } else {
2997 eeprom->page_size = 8;
2998 eeprom->address_bits = 8;
2999 }
3000 break;
984263bc
MD
3001 }
3002
3003 if (eeprom->type == em_eeprom_spi) {
3004 eeprom->word_size = 64;
3005 if (em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3006 eeprom_size &= EEPROM_SIZE_MASK;
3007
3008 switch (eeprom_size) {
0d366ee7
MD
3009 case EEPROM_SIZE_16KB:
3010 eeprom->word_size = 8192;
3011 break;
3012 case EEPROM_SIZE_8KB:
3013 eeprom->word_size = 4096;
3014 break;
3015 case EEPROM_SIZE_4KB:
3016 eeprom->word_size = 2048;
3017 break;
3018 case EEPROM_SIZE_2KB:
3019 eeprom->word_size = 1024;
3020 break;
3021 case EEPROM_SIZE_1KB:
3022 eeprom->word_size = 512;
3023 break;
3024 case EEPROM_SIZE_512B:
3025 eeprom->word_size = 256;
3026 break;
3027 case EEPROM_SIZE_128B:
3028 default:
3029 eeprom->word_size = 64;
3030 break;
984263bc
MD
3031 }
3032 }
3033 }
3034}
3035
3036/******************************************************************************
3037 * Raises the EEPROM's clock input.
3038 *
3039 * hw - Struct containing variables accessed by shared code
3040 * eecd - EECD's current value
3041 *****************************************************************************/
3042static void
3043em_raise_ee_clk(struct em_hw *hw,
3044 uint32_t *eecd)
3045{
3046 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3047 * wait <delay> microseconds.
3048 */
3049 *eecd = *eecd | E1000_EECD_SK;
3050 E1000_WRITE_REG(hw, EECD, *eecd);
3051 E1000_WRITE_FLUSH(hw);
3052 usec_delay(hw->eeprom.delay_usec);
3053}
3054
3055/******************************************************************************
3056 * Lowers the EEPROM's clock input.
3057 *
3058 * hw - Struct containing variables accessed by shared code
3059 * eecd - EECD's current value
3060 *****************************************************************************/
3061static void
3062em_lower_ee_clk(struct em_hw *hw,
3063 uint32_t *eecd)
3064{
3065 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3066 * wait 50 microseconds.
3067 */
3068 *eecd = *eecd & ~E1000_EECD_SK;
3069 E1000_WRITE_REG(hw, EECD, *eecd);
3070 E1000_WRITE_FLUSH(hw);
3071 usec_delay(hw->eeprom.delay_usec);
3072}
3073
3074/******************************************************************************
3075 * Shift data bits out to the EEPROM.
3076 *
3077 * hw - Struct containing variables accessed by shared code
3078 * data - data to send to the EEPROM
3079 * count - number of bits to shift out
3080 *****************************************************************************/
3081static void
3082em_shift_out_ee_bits(struct em_hw *hw,
3083 uint16_t data,
3084 uint16_t count)
3085{
3086 struct em_eeprom_info *eeprom = &hw->eeprom;
3087 uint32_t eecd;
3088 uint32_t mask;
3089
3090 /* We need to shift "count" bits out to the EEPROM. So, value in the
3091 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3092 * In order to do this, "data" must be broken down into bits.
3093 */
3094 mask = 0x01 << (count - 1);
3095 eecd = E1000_READ_REG(hw, EECD);
3096 if (eeprom->type == em_eeprom_microwire) {
3097 eecd &= ~E1000_EECD_DO;
3098 } else if (eeprom->type == em_eeprom_spi) {
3099 eecd |= E1000_EECD_DO;
3100 }
3101 do {
3102 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3103 * and then raising and then lowering the clock (the SK bit controls
3104 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3105 * by setting "DI" to "0" and then raising and then lowering the clock.
3106 */
3107 eecd &= ~E1000_EECD_DI;
3108
3109 if(data & mask)
3110 eecd |= E1000_EECD_DI;
3111
3112 E1000_WRITE_REG(hw, EECD, eecd);
3113 E1000_WRITE_FLUSH(hw);
3114
3115 usec_delay(eeprom->delay_usec);
3116
3117 em_raise_ee_clk(hw, &eecd);
3118 em_lower_ee_clk(hw, &eecd);
3119
3120 mask = mask >> 1;
3121
3122 } while(mask);
3123
3124 /* We leave the "DI" bit set to "0" when we leave this routine. */
3125 eecd &= ~E1000_EECD_DI;
3126 E1000_WRITE_REG(hw, EECD, eecd);
3127}
3128
3129/******************************************************************************
3130 * Shift data bits in from the EEPROM
3131 *
3132 * hw - Struct containing variables accessed by shared code
3133 *****************************************************************************/
3134static uint16_t
0d366ee7
MD
3135em_shift_in_ee_bits(struct em_hw *hw,
3136 uint16_t count)
984263bc
MD
3137{
3138 uint32_t eecd;
3139 uint32_t i;
3140 uint16_t data;
3141
3142 /* In order to read a register from the EEPROM, we need to shift 'count'
3143 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3144 * input to the EEPROM (setting the SK bit), and then reading the value of
3145 * the "DO" bit. During this "shifting in" process the "DI" bit should
3146 * always be clear.
3147 */
3148
3149 eecd = E1000_READ_REG(hw, EECD);
3150
3151 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3152 data = 0;
3153
3154 for(i = 0; i < count; i++) {
3155 data = data << 1;
3156 em_raise_ee_clk(hw, &eecd);
3157
3158 eecd = E1000_READ_REG(hw, EECD);
3159
3160 eecd &= ~(E1000_EECD_DI);
3161 if(eecd & E1000_EECD_DO)
3162 data |= 1;
3163
3164 em_lower_ee_clk(hw, &eecd);
3165 }
3166
3167 return data;
3168}
3169
3170/******************************************************************************
3171 * Prepares EEPROM for access
3172 *
3173 * hw - Struct containing variables accessed by shared code
3174 *
3175 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3176 * function should be called before issuing a command to the EEPROM.
3177 *****************************************************************************/
3178static int32_t
3179em_acquire_eeprom(struct em_hw *hw)
3180{
3181 struct em_eeprom_info *eeprom = &hw->eeprom;
3182 uint32_t eecd, i=0;
3183
3184 DEBUGFUNC("em_acquire_eeprom");
3185
3186 eecd = E1000_READ_REG(hw, EECD);
3187
3188 /* Request EEPROM Access */
3189 if(hw->mac_type > em_82544) {
3190 eecd |= E1000_EECD_REQ;
3191 E1000_WRITE_REG(hw, EECD, eecd);
3192 eecd = E1000_READ_REG(hw, EECD);
3193 while((!(eecd & E1000_EECD_GNT)) &&
3194 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3195 i++;
3196 usec_delay(5);
3197 eecd = E1000_READ_REG(hw, EECD);
3198 }
3199 if(!(eecd & E1000_EECD_GNT)) {
3200 eecd &= ~E1000_EECD_REQ;
3201 E1000_WRITE_REG(hw, EECD, eecd);
3202 DEBUGOUT("Could not acquire EEPROM grant\n");
3203 return -E1000_ERR_EEPROM;
3204 }
3205 }
3206
3207 /* Setup EEPROM for Read/Write */
3208
3209 if (eeprom->type == em_eeprom_microwire) {
3210 /* Clear SK and DI */
3211 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3212 E1000_WRITE_REG(hw, EECD, eecd);
3213
3214 /* Set CS */
3215 eecd |= E1000_EECD_CS;
3216 E1000_WRITE_REG(hw, EECD, eecd);
3217 } else if (eeprom->type == em_eeprom_spi) {
3218 /* Clear SK and CS */
3219 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3220 E1000_WRITE_REG(hw, EECD, eecd);
3221 usec_delay(1);
3222 }
3223
3224 return E1000_SUCCESS;
3225}
3226
3227/******************************************************************************
3228 * Returns EEPROM to a "standby" state
3229 *
3230 * hw - Struct containing variables accessed by shared code
3231 *****************************************************************************/
3232static void
3233em_standby_eeprom(struct em_hw *hw)
3234{
3235 struct em_eeprom_info *eeprom = &hw->eeprom;
3236 uint32_t eecd;
3237
3238 eecd = E1000_READ_REG(hw, EECD);
3239
3240 if(eeprom->type == em_eeprom_microwire) {
3241 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3242 E1000_WRITE_REG(hw, EECD, eecd);
3243 E1000_WRITE_FLUSH(hw);
3244 usec_delay(eeprom->delay_usec);
3245
3246 /* Clock high */
3247 eecd |= E1000_EECD_SK;
3248 E1000_WRITE_REG(hw, EECD, eecd);
3249 E1000_WRITE_FLUSH(hw);
3250 usec_delay(eeprom->delay_usec);
3251
3252 /* Select EEPROM */
3253 eecd |= E1000_EECD_CS;
3254 E1000_WRITE_REG(hw, EECD, eecd);
3255 E1000_WRITE_FLUSH(hw);
3256 usec_delay(eeprom->delay_usec);
3257
3258 /* Clock low */
3259 eecd &= ~E1000_EECD_SK;
3260 E1000_WRITE_REG(hw, EECD, eecd);
3261 E1000_WRITE_FLUSH(hw);
3262 usec_delay(eeprom->delay_usec);
3263 } else if(eeprom->type == em_eeprom_spi) {
3264 /* Toggle CS to flush commands */
3265 eecd |= E1000_EECD_CS;
3266 E1000_WRITE_REG(hw, EECD, eecd);
3267 E1000_WRITE_FLUSH(hw);
3268 usec_delay(eeprom->delay_usec);
3269 eecd &= ~E1000_EECD_CS;
3270 E1000_WRITE_REG(hw, EECD, eecd);
3271 E1000_WRITE_FLUSH(hw);
3272 usec_delay(eeprom->delay_usec);
3273 }
3274}
3275
3276/******************************************************************************
3277 * Terminates a command by inverting the EEPROM's chip select pin
3278 *
3279 * hw - Struct containing variables accessed by shared code
3280 *****************************************************************************/
3281static void
3282em_release_eeprom(struct em_hw *hw)
3283{
3284 uint32_t eecd;
3285
3286 DEBUGFUNC("em_release_eeprom");
3287
3288 eecd = E1000_READ_REG(hw, EECD);
3289
3290 if (hw->eeprom.type == em_eeprom_spi) {
3291 eecd |= E1000_EECD_CS; /* Pull CS high */
3292 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3293
3294 E1000_WRITE_REG(hw, EECD, eecd);
3295
3296 usec_delay(hw->eeprom.delay_usec);
3297 } else if(hw->eeprom.type == em_eeprom_microwire) {
3298 /* cleanup eeprom */
3299
3300 /* CS on Microwire is active-high */
3301 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3302
3303 E1000_WRITE_REG(hw, EECD, eecd);
3304
3305 /* Rising edge of clock */
3306 eecd |= E1000_EECD_SK;
3307 E1000_WRITE_REG(hw, EECD, eecd);
3308 E1000_WRITE_FLUSH(hw);
3309 usec_delay(hw->eeprom.delay_usec);
3310
3311 /* Falling edge of clock */
3312 eecd &= ~E1000_EECD_SK;
3313 E1000_WRITE_REG(hw, EECD, eecd);
3314 E1000_WRITE_FLUSH(hw);
3315 usec_delay(hw->eeprom.delay_usec);
3316 }
3317
3318 /* Stop requesting EEPROM access */
3319 if(hw->mac_type > em_82544) {
3320 eecd &= ~E1000_EECD_REQ;
3321 E1000_WRITE_REG(hw, EECD, eecd);
3322 }
3323}
3324
3325/******************************************************************************
3326 * Reads a 16 bit word from the EEPROM.
3327 *
3328 * hw - Struct containing variables accessed by shared code
3329 *****************************************************************************/
3330int32_t
3331em_spi_eeprom_ready(struct em_hw *hw)
3332{
3333 uint16_t retry_count = 0;
3334 uint8_t spi_stat_reg;
3335
3336 DEBUGFUNC("em_spi_eeprom_ready");
3337
3338 /* Read "Status Register" repeatedly until the LSB is cleared. The
3339 * EEPROM will signal that the command has been completed by clearing
3340 * bit 0 of the internal status register. If it's not cleared within
3341 * 5 milliseconds, then error out.
3342 */
3343 retry_count = 0;
3344 do {
3345 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3346 hw->eeprom.opcode_bits);
3347 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
3348 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3349 break;
3350
3351 usec_delay(5);
3352 retry_count += 5;
3353
3354 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3355
3356 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3357 * only 0-5mSec on 5V devices)
3358 */
3359 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3360 DEBUGOUT("SPI EEPROM Status error\n");
3361 return -E1000_ERR_EEPROM;
3362 }
3363
3364 return E1000_SUCCESS;
3365}
3366
3367/******************************************************************************
3368 * Reads a 16 bit word from the EEPROM.
3369 *
3370 * hw - Struct containing variables accessed by shared code
3371 * offset - offset of word in the EEPROM to read
3372 * data - word read from the EEPROM
3373 * words - number of words to read
3374 *****************************************************************************/
3375int32_t
3376em_read_eeprom(struct em_hw *hw,
3377 uint16_t offset,
3378 uint16_t words,
3379 uint16_t *data)
3380{
3381 struct em_eeprom_info *eeprom = &hw->eeprom;
3382 uint32_t i = 0;
3383
3384 DEBUGFUNC("em_read_eeprom");
3385
3386 /* A check for invalid values: offset too large, too many words, and not
3387 * enough words.
3388 */
3389 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3390 (words == 0)) {
3391 DEBUGOUT("\"words\" parameter out of bounds\n");
3392 return -E1000_ERR_EEPROM;
3393 }
3394
3395 /* Prepare the EEPROM for reading */
0d366ee7 3396 if(em_acquire_eeprom(hw) != E1000_SUCCESS)
984263bc
MD
3397 return -E1000_ERR_EEPROM;
3398
3399 if(eeprom->type == em_eeprom_spi) {
0d366ee7 3400 uint16_t word_in;
984263bc
MD
3401 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3402
0d366ee7
MD
3403 if(em_spi_eeprom_ready(hw)) {
3404 em_release_eeprom(hw);
3405 return -E1000_ERR_EEPROM;
3406 }
984263bc
MD
3407
3408 em_standby_eeprom(hw);
3409
3410 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3411 if((eeprom->address_bits == 8) && (offset >= 128))
3412 read_opcode |= EEPROM_A8_OPCODE_SPI;
3413
3414 /* Send the READ command (opcode + addr) */
3415 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3416 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
984263bc 3417
0d366ee7
MD
3418 /* Read the data. The address of the eeprom internally increments with
3419 * each byte (spi) being read, saving on the overhead of eeprom setup
3420 * and tear-down. The address counter will roll over if reading beyond
3421 * the size of the eeprom, thus allowing the entire memory to be read
3422 * starting from any offset. */
3423 for (i = 0; i < words; i++) {
3424 word_in = em_shift_in_ee_bits(hw, 16);
3425 data[i] = (word_in >> 8) | (word_in << 8);
3426 }
3427 } else if(eeprom->type == em_eeprom_microwire) {
3428 for (i = 0; i < words; i++) {
3429 /* Send the READ command (opcode + addr) */
3430 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3431 eeprom->opcode_bits);
3432 em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3433 eeprom->address_bits);
3434
3435 /* Read the data. For microwire, each word requires the overhead
3436 * of eeprom setup and tear-down. */
3437 data[i] = em_shift_in_ee_bits(hw, 16);
3438 em_standby_eeprom(hw);
3439 }
984263bc
MD
3440 }
3441
3442 /* End this read operation */
3443 em_release_eeprom(hw);
3444
0d366ee7 3445 return E1000_SUCCESS;
984263bc
MD
3446}
3447
3448/******************************************************************************
3449 * Verifies that the EEPROM has a valid checksum
3450 *
3451 * hw - Struct containing variables accessed by shared code
3452 *
3453 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3454 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3455 * valid.
3456 *****************************************************************************/
3457int32_t
3458em_validate_eeprom_checksum(struct em_hw *hw)
3459{
3460 uint16_t checksum = 0;
3461 uint16_t i, eeprom_data;
3462
3463 DEBUGFUNC("em_validate_eeprom_checksum");
3464
3465 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3466 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3467 DEBUGOUT("EEPROM Read Error\n");
3468 return -E1000_ERR_EEPROM;
3469 }
3470 checksum += eeprom_data;
3471 }
3472
0d366ee7
MD
3473 if(checksum == (uint16_t) EEPROM_SUM)
3474 return E1000_SUCCESS;
3475 else {
984263bc
MD
3476 DEBUGOUT("EEPROM Checksum Invalid\n");
3477 return -E1000_ERR_EEPROM;
3478 }
3479}
3480
3481/******************************************************************************
3482 * Calculates the EEPROM checksum and writes it to the EEPROM
3483 *
3484 * hw - Struct containing variables accessed by shared code
3485 *
3486 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3487 * Writes the difference to word offset 63 of the EEPROM.
3488 *****************************************************************************/
3489int32_t
3490em_update_eeprom_checksum(struct em_hw *hw)
3491{
3492 uint16_t checksum = 0;
3493 uint16_t i, eeprom_data;
3494
3495 DEBUGFUNC("em_update_eeprom_checksum");
3496
3497 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3498 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3499 DEBUGOUT("EEPROM Read Error\n");
3500 return -E1000_ERR_EEPROM;
3501 }
3502 checksum += eeprom_data;
3503 }
3504 checksum = (uint16_t) EEPROM_SUM - checksum;
3505 if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3506 DEBUGOUT("EEPROM Write Error\n");
3507 return -E1000_ERR_EEPROM;
3508 }
0d366ee7 3509 return E1000_SUCCESS;
984263bc
MD
3510}
3511
3512/******************************************************************************
3513 * Parent function for writing words to the different EEPROM types.
3514 *
3515 * hw - Struct containing variables accessed by shared code
3516 * offset - offset within the EEPROM to be written to
3517 * words - number of words to write
3518 * data - 16 bit word to be written to the EEPROM
3519 *
3520 * If em_update_eeprom_checksum is not called after this function, the
3521 * EEPROM will most likely contain an invalid checksum.
3522 *****************************************************************************/
3523int32_t
3524em_write_eeprom(struct em_hw *hw,
3525 uint16_t offset,
3526 uint16_t words,
3527 uint16_t *data)
3528{
3529 struct em_eeprom_info *eeprom = &hw->eeprom;
3530 int32_t status = 0;
3531
3532 DEBUGFUNC("em_write_eeprom");
3533
3534 /* A check for invalid values: offset too large, too many words, and not
3535 * enough words.
3536 */
3537 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3538 (words == 0)) {
3539 DEBUGOUT("\"words\" parameter out of bounds\n");
3540 return -E1000_ERR_EEPROM;
3541 }
3542
3543 /* Prepare the EEPROM for writing */
3544 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3545 return -E1000_ERR_EEPROM;
3546
0d366ee7 3547 if(eeprom->type == em_eeprom_microwire) {
984263bc 3548 status = em_write_eeprom_microwire(hw, offset, words, data);
0d366ee7 3549 } else {
984263bc 3550 status = em_write_eeprom_spi(hw, offset, words, data);
0d366ee7
MD
3551 msec_delay(10);
3552 }
984263bc
MD
3553
3554 /* Done with writing */
3555 em_release_eeprom(hw);
3556
3557 return status;
3558}
3559
3560/******************************************************************************
3561 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3562 *
3563 * hw - Struct containing variables accessed by shared code
3564 * offset - offset within the EEPROM to be written to
3565 * words - number of words to write
3566 * data - pointer to array of 8 bit words to be written to the EEPROM
3567 *
3568 *****************************************************************************/
3569int32_t
3570em_write_eeprom_spi(struct em_hw *hw,
3571 uint16_t offset,
3572 uint16_t words,
3573 uint16_t *data)
3574{
3575 struct em_eeprom_info *eeprom = &hw->eeprom;
3576 uint16_t widx = 0;
3577
3578 DEBUGFUNC("em_write_eeprom_spi");
3579
3580 while (widx < words) {
3581 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3582
3583 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3584
3585 em_standby_eeprom(hw);
3586
3587 /* Send the WRITE ENABLE command (8 bit opcode ) */
3588 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3589 eeprom->opcode_bits);
3590
3591 em_standby_eeprom(hw);
3592
3593 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3594 if((eeprom->address_bits == 8) && (offset >= 128))
3595 write_opcode |= EEPROM_A8_OPCODE_SPI;
3596
3597 /* Send the Write command (8-bit opcode + addr) */
3598 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3599
3600 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3601 eeprom->address_bits);
3602
3603 /* Send the data */
3604
3605 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3606 while (widx < words) {
3607 uint16_t word_out = data[widx];
3608 word_out = (word_out >> 8) | (word_out << 8);
3609 em_shift_out_ee_bits(hw, word_out, 16);
3610 widx++;
3611
3612 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3613 * operation, while the smaller eeproms are capable of an 8-byte
3614 * PAGE WRITE operation. Break the inner loop to pass new address
3615 */
3616 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3617 em_standby_eeprom(hw);
3618 break;
3619 }
3620 }
3621 }
3622
3623 return E1000_SUCCESS;
3624}
3625
3626/******************************************************************************
3627 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3628 *
3629 * hw - Struct containing variables accessed by shared code
3630 * offset - offset within the EEPROM to be written to
3631 * words - number of words to write
3632 * data - pointer to array of 16 bit words to be written to the EEPROM
3633 *
3634 *****************************************************************************/
3635int32_t
3636em_write_eeprom_microwire(struct em_hw *hw,
3637 uint16_t offset,
3638 uint16_t words,
3639 uint16_t *data)
3640{
3641 struct em_eeprom_info *eeprom = &hw->eeprom;
3642 uint32_t eecd;
3643 uint16_t words_written = 0;
3644 uint16_t i = 0;
3645
3646 DEBUGFUNC("em_write_eeprom_microwire");
3647