MP table related static function renaming
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29#include "opt_cpu.h"
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
37#include <sys/cons.h> /* cngetc() */
38#include <sys/machintr.h>
39
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40#include <sys/mplock2.h>
41
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42#include <vm/vm.h>
43#include <vm/vm_param.h>
44#include <vm/pmap.h>
45#include <vm/vm_kern.h>
46#include <vm/vm_extern.h>
47#include <sys/lock.h>
48#include <vm/vm_map.h>
49#include <sys/user.h>
50#ifdef GPROF
51#include <sys/gmon.h>
52#endif
53
54#include <machine/smp.h>
55#include <machine_base/apic/apicreg.h>
56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
58#include <machine_base/apic/mpapic.h>
59#include <machine/psl.h>
60#include <machine/segments.h>
61#include <machine/tss.h>
62#include <machine/specialreg.h>
63#include <machine/globaldata.h>
64
65#include <machine/md_var.h> /* setidt() */
66#include <machine_base/icu/icu.h> /* IPIs */
67#include <machine_base/isa/intr_machdep.h> /* IPIs */
68
69#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
70
71#define WARMBOOT_TARGET 0
72#define WARMBOOT_OFF (KERNBASE + 0x0467)
73#define WARMBOOT_SEG (KERNBASE + 0x0469)
74
75#define BIOS_BASE (0xf0000)
76#define BIOS_SIZE (0x10000)
77#define BIOS_COUNT (BIOS_SIZE/4)
78
79#define CMOS_REG (0x70)
80#define CMOS_DATA (0x71)
81#define BIOS_RESET (0x0f)
82#define BIOS_WARM (0x0a)
83
84#define PROCENTRY_FLAG_EN 0x01
85#define PROCENTRY_FLAG_BP 0x02
86#define IOAPICENTRY_FLAG_EN 0x01
87
88
89/* MP Floating Pointer Structure */
90typedef struct MPFPS {
91 char signature[4];
92 u_int32_t pap;
93 u_char length;
94 u_char spec_rev;
95 u_char checksum;
96 u_char mpfb1;
97 u_char mpfb2;
98 u_char mpfb3;
99 u_char mpfb4;
100 u_char mpfb5;
101} *mpfps_t;
102
103/* MP Configuration Table Header */
104typedef struct MPCTH {
105 char signature[4];
106 u_short base_table_length;
107 u_char spec_rev;
108 u_char checksum;
109 u_char oem_id[8];
110 u_char product_id[12];
a5f51ef3 111 u_int32_t oem_table_pointer;
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112 u_short oem_table_size;
113 u_short entry_count;
a5f51ef3 114 u_int32_t apic_address;
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115 u_short extended_table_length;
116 u_char extended_table_checksum;
117 u_char reserved;
118} *mpcth_t;
119
120
121typedef struct PROCENTRY {
122 u_char type;
123 u_char apic_id;
124 u_char apic_version;
125 u_char cpu_flags;
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126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
128 u_int32_t reserved1;
129 u_int32_t reserved2;
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130} *proc_entry_ptr;
131
132typedef struct BUSENTRY {
133 u_char type;
134 u_char bus_id;
135 char bus_type[6];
136} *bus_entry_ptr;
137
138typedef struct IOAPICENTRY {
139 u_char type;
140 u_char apic_id;
141 u_char apic_version;
142 u_char apic_flags;
a5f51ef3 143 u_int32_t apic_address;
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144} *io_apic_entry_ptr;
145
146typedef struct INTENTRY {
147 u_char type;
148 u_char int_type;
149 u_short int_flags;
150 u_char src_bus_id;
151 u_char src_bus_irq;
152 u_char dst_apic_id;
153 u_char dst_apic_int;
154} *int_entry_ptr;
155
156/* descriptions of MP basetable entries */
157typedef struct BASETABLE_ENTRY {
158 u_char type;
159 u_char length;
160 char name[16];
161} basetable_entry;
162
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163struct mptable_pos {
164 mpfps_t mp_fps;
165 mpcth_t mp_cth;
166 vm_size_t mp_cth_mapsz;
167};
168
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169/*
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
173 *
174 */
175#if defined(CHECK_POINTS)
176#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
178
179#define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
186
187#define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
189 (S), \
190 CHECK_READ(0x34), \
191 CHECK_READ(0x35), \
192 CHECK_READ(0x36), \
193 CHECK_READ(0x37), \
194 CHECK_READ(0x38), \
195 CHECK_READ(0x39));
196
197#else /* CHECK_POINTS */
198
199#define CHECK_INIT(D)
200#define CHECK_PRINT(S)
201
202#endif /* CHECK_POINTS */
203
204/*
205 * Values to send to the POST hardware.
206 */
207#define MP_BOOTADDRESS_POST 0x10
208#define MP_PROBE_POST 0x11
209#define MPTABLE_PASS1_POST 0x12
210
211#define MP_START_POST 0x13
212#define MP_ENABLE_POST 0x14
213#define MPTABLE_PASS2_POST 0x15
214
215#define START_ALL_APS_POST 0x16
216#define INSTALL_AP_TRAMP_POST 0x17
217#define START_AP_POST 0x18
218
219#define MP_ANNOUNCE_POST 0x19
220
221static int need_hyperthreading_fixup;
222static u_int logical_cpus;
223u_int logical_cpus_mask;
224
225/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226int current_postcode;
227
228/** XXX FIXME: what system files declare these??? */
229extern struct region_descriptor r_gdt, r_idt;
230
231int bsp_apic_ready = 0; /* flags useability of BSP apic */
232int mp_naps; /* # of Applications processors */
233int mp_nbusses; /* # of busses */
234#ifdef APIC_IO
235int mp_napics; /* # of IO APICs */
236#endif
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237vm_offset_t cpu_apic_address;
238#ifdef APIC_IO
239vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
240u_int32_t *io_apic_versions;
241#endif
242extern int nkpt;
243
244u_int32_t cpu_apic_versions[MAXCPU];
245int64_t tsc0_offset;
246extern int64_t tsc_offsets[];
247
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248extern u_long ebda_addr;
249
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250#ifdef APIC_IO
251struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
252#endif
253
254/*
255 * APIC ID logical/physical mapping structures.
256 * We oversize these to simplify boot-time config.
257 */
258int cpu_num_to_apic_id[NAPICID];
259#ifdef APIC_IO
260int io_num_to_apic_id[NAPICID];
261#endif
262int apic_id_to_logical[NAPICID];
263
264/* AP uses this during bootstrap. Do not staticize. */
265char *bootSTK;
266static int bootAP;
267
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268/*
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
271 * and so forth.
272 */
273
274#define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
276
277extern pt_entry_t *SMPpt;
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278
279struct pcb stoppcbs[MAXCPU];
280
281extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
282
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283/*
284 * Local data and functions.
285 */
286
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287static u_int boot_address;
288static u_int base_memory;
289static int mp_finish;
290
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291static void mp_enable(u_int boot_addr);
292
f804d15f 293static int mptable_probe(void);
0eaa8172 294static long mptable_search_sig(u_int32_t target, int count);
46d4e165 295static void mptable_hyperthread_fixup(u_int id_mask);
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296static void mptable_pass1(struct mptable_pos *);
297static int mptable_pass2(struct mptable_pos *);
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298static void mptable_default(int type);
299static void mptable_fix(void);
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300static void mptable_map(struct mptable_pos *, vm_paddr_t);
301static void mptable_unmap(struct mptable_pos *);
0eaa8172 302
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303#ifdef APIC_IO
304static void setup_apic_irq_mapping(void);
305static int apic_int_is_bus_type(int intr, int bus_type);
306#endif
307static int start_all_aps(u_int boot_addr);
bfc09ba0 308#if 0
46d4e165 309static void install_ap_tramp(u_int boot_addr);
bfc09ba0 310#endif
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311static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
312static int smitest(void);
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313
314static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
315cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
316SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
317static u_int bootMP_size;
318
319/*
320 * Calculate usable address in base memory for AP trampoline code.
321 */
322u_int
323mp_bootaddress(u_int basemem)
324{
325 POSTCODE(MP_BOOTADDRESS_POST);
326
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327 base_memory = basemem;
328
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329 bootMP_size = mptramp_end - mptramp_start;
330 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
331 if (((basemem * 1024) - boot_address) < bootMP_size)
332 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
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333 /* 3 levels of page table pages */
334 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
335
336 return mptramp_pagetables;
337}
338
339
340/*
341 * Look for an Intel MP spec table (ie, SMP capable hardware).
342 */
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343static int
344mptable_probe(void)
46d4e165 345{
3a918cfd 346 long x;
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347 u_int32_t target;
348
349 /*
350 * Make sure our SMPpt[] page table is big enough to hold all the
351 * mappings we need.
352 */
353 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
354
355 POSTCODE(MP_PROBE_POST);
356
357 /* see if EBDA exists */
927c4c1f 358 if (ebda_addr != 0) {
46d4e165 359 /* search first 1K of EBDA */
927c4c1f 360 target = (u_int32_t)ebda_addr;
0eaa8172 361 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
351254e7 362 return x;
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363 } else {
364 /* last 1K of base memory, effective 'top of base' passed in */
351254e7 365 target = (u_int32_t)(base_memory - 0x400);
0eaa8172 366 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
351254e7 367 return x;
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368 }
369
370 /* search the BIOS */
351254e7 371 target = (u_int32_t)BIOS_BASE;
0eaa8172 372 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
351254e7 373 return x;
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374
375 /* nothing found */
46d4e165 376 return 0;
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377}
378
379
380/*
381 * Startup the SMP processors.
382 */
383void
384mp_start(void)
385{
386 POSTCODE(MP_START_POST);
a0679cc7 387 mp_enable(boot_address);
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388}
389
390
391/*
392 * Print various information about the SMP system hardware and setup.
393 */
394void
395mp_announce(void)
396{
397 int x;
398
399 POSTCODE(MP_ANNOUNCE_POST);
400
401 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
402 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
403 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
bfc09ba0 404 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
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405 for (x = 1; x <= mp_naps; ++x) {
406 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
407 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
bfc09ba0 408 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
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409 }
410
411#if defined(APIC_IO)
412 for (x = 0; x < mp_napics; ++x) {
413 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
414 kprintf(", version: 0x%08x", io_apic_versions[x]);
bcdeeecd 415 kprintf(", at 0x%08lx\n", io_apic_address[x]);
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416 }
417#else
418 kprintf(" Warning: APIC I/O disabled\n");
419#endif /* APIC_IO */
420}
421
422/*
423 * AP cpu's call this to sync up protected mode.
424 *
ec073ddc 425 * WARNING! %gs is not set up on entry. This routine sets up %gs.
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426 */
427void
428init_secondary(void)
429{
430 int gsel_tss;
431 int x, myid = bootAP;
432 u_int64_t msr, cr0;
433 struct mdglobaldata *md;
434 struct privatespace *ps;
435
436 ps = &CPU_prvspace[myid];
437
438 gdt_segs[GPROC0_SEL].ssd_base =
439 (long) &ps->mdglobaldata.gd_common_tss;
440 ps->mdglobaldata.mi.gd_prvspace = ps;
441
442 /* We fill the 32-bit segment descriptors */
443 for (x = 0; x < NGDT; x++) {
444 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
445 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
446 }
447 /* And now a 64-bit one */
448 ssdtosyssd(&gdt_segs[GPROC0_SEL],
449 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
450
451 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
452 r_gdt.rd_base = (long) &gdt[myid * NGDT];
453 lgdt(&r_gdt); /* does magic intra-segment return */
454
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455 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
456 wrmsr(MSR_FSBASE, 0); /* User value */
457 wrmsr(MSR_GSBASE, (u_int64_t)ps);
458 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
459
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460 lidt(&r_idt);
461
462#if 0
463 lldt(_default_ldt);
464 mdcpu->gd_currentldt = _default_ldt;
465#endif
466
467 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
468 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
469
470 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
471
472 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
473#if 0 /* JG XXX */
474 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
475#endif
476 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
477 md->gd_common_tssd = *md->gd_tss_gdt;
478#if 0 /* JG XXX */
479 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
480#endif
481 ltr(gsel_tss);
482
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483 /*
484 * Set to a known state:
485 * Set by mpboot.s: CR0_PG, CR0_PE
486 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
487 */
488 cr0 = rcr0();
489 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
490 load_cr0(cr0);
491
492 /* Set up the fast syscall stuff */
493 msr = rdmsr(MSR_EFER) | EFER_SCE;
494 wrmsr(MSR_EFER, msr);
495 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
496 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
497 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
498 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
499 wrmsr(MSR_STAR, msr);
500 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
501
502 pmap_set_opt(); /* PSE/4MB pages, etc */
503#if JGXXX
504 /* Initialize the PAT MSR. */
505 pmap_init_pat();
506#endif
507
508 /* set up CPU registers and state */
509 cpu_setregs();
510
511 /* set up SSE/NX registers */
512 initializecpu();
513
514 /* set up FPU state on the AP */
515 npxinit(__INITIAL_NPXCW__);
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516
517 /* disable the APIC, just to be SURE */
518 lapic->svr &= ~APIC_SVR_ENABLE;
519
520 /* data returned to BSP */
521 cpu_apic_versions[0] = lapic->version;
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522}
523
524/*******************************************************************
525 * local functions and data
526 */
527
528/*
529 * start the SMP system
530 */
531static void
532mp_enable(u_int boot_addr)
533{
534 int x;
535#if defined(APIC_IO)
536 int apic;
537 u_int ux;
538#endif /* APIC_IO */
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539 vm_paddr_t mpfps_paddr;
540 struct mptable_pos mpt;
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541
542 POSTCODE(MP_ENABLE_POST);
543
f804d15f 544 mpfps_paddr = mptable_probe();
91f1c7a4 545 if (mpfps_paddr == 0)
f804d15f 546 panic("mp_enable: mptable_probe failed\n");
f592025a 547
91f1c7a4 548 mptable_map(&mpt, mpfps_paddr);
46d4e165 549
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550 /*
551 * We can safely map physical memory into SMPpt after
552 * mptable_pass1() completes.
553 */
91f1c7a4 554 mptable_pass1(&mpt);
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555
556 if (cpu_apic_address == 0)
f592025a 557 panic("mp_enable: no local apic!\n");
9ad60dda 558
46d4e165 559 /* examine the MP table for needed info, uses physical addresses */
91f1c7a4 560 x = mptable_pass2(&mpt);
46d4e165 561
91f1c7a4 562 mptable_unmap(&mpt);
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563
564 /* can't process default configs till the CPU APIC is pmapped */
565 if (x)
0eaa8172 566 mptable_default(x);
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567
568 /* post scan cleanup */
0eaa8172 569 mptable_fix();
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570
571#if defined(APIC_IO)
572
573 setup_apic_irq_mapping();
574
575 /* fill the LOGICAL io_apic_versions table */
576 for (apic = 0; apic < mp_napics; ++apic) {
577 ux = io_apic_read(apic, IOAPIC_VER);
578 io_apic_versions[apic] = ux;
579 io_apic_set_id(apic, IO_TO_ID(apic));
580 }
581
582 /* program each IO APIC in the system */
583 for (apic = 0; apic < mp_napics; ++apic)
584 if (io_apic_setup(apic) < 0)
585 panic("IO APIC setup failure");
586
587#endif /* APIC_IO */
588
589 /*
590 * These are required for SMP operation
591 */
592
593 /* install a 'Spurious INTerrupt' vector */
594 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
a4f18b62 595 SDT_SYSIGT, SEL_KPL, 0);
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596
597 /* install an inter-CPU IPI for TLB invalidation */
598 setidt(XINVLTLB_OFFSET, Xinvltlb,
a4f18b62 599 SDT_SYSIGT, SEL_KPL, 0);
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600
601 /* install an inter-CPU IPI for IPIQ messaging */
602 setidt(XIPIQ_OFFSET, Xipiq,
a4f18b62 603 SDT_SYSIGT, SEL_KPL, 0);
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604
605 /* install a timer vector */
606 setidt(XTIMER_OFFSET, Xtimer,
a4f18b62 607 SDT_SYSIGT, SEL_KPL, 0);
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608
609 /* install an inter-CPU IPI for CPU stop/restart */
610 setidt(XCPUSTOP_OFFSET, Xcpustop,
a4f18b62 611 SDT_SYSIGT, SEL_KPL, 0);
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612
613 /* start each Application Processor */
614 start_all_aps(boot_addr);
615}
616
617
618/*
619 * look for the MP spec signature
620 */
621
622/* string defined by the Intel MP Spec as identifying the MP table */
623#define MP_SIG 0x5f504d5f /* _MP_ */
624#define NEXT(X) ((X) += 4)
3a918cfd 625static long
0eaa8172 626mptable_search_sig(u_int32_t target, int count)
46d4e165 627{
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628 vm_size_t map_size;
629 u_int32_t *addr;
630 int x, ret;
46d4e165 631
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632 KKASSERT(target != 0);
633
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634 map_size = count * sizeof(u_int32_t);
635 addr = pmap_mapdev((vm_paddr_t)target, map_size);
46d4e165 636
351254e7 637 ret = 0;
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638 for (x = 0; x < count; NEXT(x)) {
639 if (addr[x] == MP_SIG) {
640 /* make array index a byte index */
641 ret = target + (x * sizeof(u_int32_t));
642 break;
643 }
644 }
351254e7 645
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646 pmap_unmapdev((vm_offset_t)addr, map_size);
647 return ret;
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648}
649
650
651static basetable_entry basetable_entry_types[] =
652{
653 {0, 20, "Processor"},
654 {1, 8, "Bus"},
655 {2, 8, "I/O APIC"},
656 {3, 8, "I/O INT"},
657 {4, 8, "Local INT"}
658};
659
660typedef struct BUSDATA {
661 u_char bus_id;
662 enum busTypes bus_type;
663} bus_datum;
664
665typedef struct INTDATA {
666 u_char int_type;
667 u_short int_flags;
668 u_char src_bus_id;
669 u_char src_bus_irq;
670 u_char dst_apic_id;
671 u_char dst_apic_int;
672 u_char int_vector;
673} io_int, local_int;
674
675typedef struct BUSTYPENAME {
676 u_char type;
677 char name[7];
678} bus_type_name;
679
680static bus_type_name bus_type_table[] =
681{
682 {CBUS, "CBUS"},
683 {CBUSII, "CBUSII"},
684 {EISA, "EISA"},
685 {MCA, "MCA"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {ISA, "ISA"},
688 {MCA, "MCA"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {PCI, "PCI"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
699 {XPRESS, "XPRESS"},
700 {UNKNOWN_BUSTYPE, "---"}
701};
702/* from MP spec v1.4, table 5-1 */
703static int default_data[7][5] =
704{
705/* nbus, id0, type0, id1, type1 */
706 {1, 0, ISA, 255, 255},
707 {1, 0, EISA, 255, 255},
708 {1, 0, EISA, 255, 255},
709 {1, 0, MCA, 255, 255},
710 {2, 0, ISA, 1, PCI},
711 {2, 0, EISA, 1, PCI},
712 {2, 0, MCA, 1, PCI}
713};
714
715
716/* the bus data */
717static bus_datum *bus_data;
718
719#ifdef APIC_IO
720/* the IO INT data, one entry per possible APIC INTerrupt */
721static io_int *io_apic_ints;
722static int nintrs;
723#endif
724
725static int processor_entry (proc_entry_ptr entry, int cpu);
726static int bus_entry (bus_entry_ptr entry, int bus);
727#ifdef APIC_IO
728static int io_apic_entry (io_apic_entry_ptr entry, int apic);
729static int int_entry (int_entry_ptr entry, int intr);
730#endif
731static int lookup_bus_type (char *name);
732
733
734/*
735 * 1st pass on motherboard's Intel MP specification table.
736 *
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737 * determines:
738 * cpu_apic_address (common to all CPUs)
739 * io_apic_address[N]
740 * mp_naps
741 * mp_nbusses
742 * mp_napics
743 * nintrs
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744 * need_hyperthreading_fixup
745 * logical_cpus
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746 */
747static void
91f1c7a4 748mptable_pass1(struct mptable_pos *mpt)
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749{
750#ifdef APIC_IO
751 int x;
752#endif
91f1c7a4 753 mpfps_t fps;
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754 mpcth_t cth;
755 int totalSize;
756 void* position;
757 int count;
758 int type;
759 u_int id_mask;
760
761 POSTCODE(MPTABLE_PASS1_POST);
762
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763 fps = mpt->mp_fps;
764 KKASSERT(fps != NULL);
9ad60dda 765
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766#ifdef APIC_IO
767 /* clear various tables */
768 for (x = 0; x < NAPICID; ++x) {
769 io_apic_address[x] = ~0; /* IO APIC address table */
770 }
771#endif
772
773 /* init everything to empty */
774 mp_naps = 0;
775 mp_nbusses = 0;
776#ifdef APIC_IO
777 mp_napics = 0;
778 nintrs = 0;
779#endif
780 id_mask = 0;
781
782 /* check for use of 'default' configuration */
91f1c7a4 783 if (fps->mpfb1 != 0) {
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784 /* use default addresses */
785 cpu_apic_address = DEFAULT_APIC_BASE;
786#ifdef APIC_IO
787 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
788#endif
789
790 /* fill in with defaults */
791 mp_naps = 2; /* includes BSP */
91f1c7a4 792 mp_nbusses = default_data[fps->mpfb1 - 1][0];
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793#if defined(APIC_IO)
794 mp_napics = 1;
795 nintrs = 16;
796#endif /* APIC_IO */
797 }
798 else {
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799 cth = mpt->mp_cth;
800 if (cth == NULL)
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801 panic("MP Configuration Table Header MISSING!");
802
803 cpu_apic_address = (vm_offset_t) cth->apic_address;
804
805 /* walk the table, recording info of interest */
806 totalSize = cth->base_table_length - sizeof(struct MPCTH);
807 position = (u_char *) cth + sizeof(struct MPCTH);
808 count = cth->entry_count;
809
810 while (count--) {
811 switch (type = *(u_char *) position) {
812 case 0: /* processor_entry */
813 if (((proc_entry_ptr)position)->cpu_flags
814 & PROCENTRY_FLAG_EN) {
815 ++mp_naps;
816 id_mask |= 1 <<
817 ((proc_entry_ptr)position)->apic_id;
818 }
819 break;
820 case 1: /* bus_entry */
821 ++mp_nbusses;
822 break;
823 case 2: /* io_apic_entry */
824#ifdef APIC_IO
825 if (((io_apic_entry_ptr)position)->apic_flags
826 & IOAPICENTRY_FLAG_EN)
827 io_apic_address[mp_napics++] =
828 (vm_offset_t)((io_apic_entry_ptr)
829 position)->apic_address;
830#endif
831 break;
832 case 3: /* int_entry */
833#ifdef APIC_IO
834 ++nintrs;
835#endif
836 break;
837 case 4: /* int_entry */
838 break;
839 default:
840 panic("mpfps Base Table HOSED!");
841 /* NOTREACHED */
842 }
843
844 totalSize -= basetable_entry_types[type].length;
845 position = (uint8_t *)position +
846 basetable_entry_types[type].length;
847 }
848 }
849
850 /* qualify the numbers */
851 if (mp_naps > MAXCPU) {
852 kprintf("Warning: only using %d of %d available CPUs!\n",
853 MAXCPU, mp_naps);
854 mp_naps = MAXCPU;
855 }
856
857 /* See if we need to fixup HT logical CPUs. */
858 mptable_hyperthread_fixup(id_mask);
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859
860 --mp_naps; /* subtract the BSP */
861}
862
863
864/*
865 * 2nd pass on motherboard's Intel MP specification table.
866 *
867 * sets:
0ecea546 868 * logical_cpus_mask
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869 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
870 * CPU_TO_ID(N), logical CPU to APIC ID table
871 * IO_TO_ID(N), logical IO to APIC ID table
872 * bus_data[N]
873 * io_apic_ints[N]
874 */
875static int
91f1c7a4 876mptable_pass2(struct mptable_pos *mpt)
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877{
878 struct PROCENTRY proc;
879 int x;
91f1c7a4 880 mpfps_t fps;
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881 mpcth_t cth;
882 int totalSize;
883 void* position;
884 int count;
885 int type;
886 int apic, bus, cpu, intr;
887 int i;
888
889 POSTCODE(MPTABLE_PASS2_POST);
890
91f1c7a4
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891 fps = mpt->mp_fps;
892 KKASSERT(fps != NULL);
893
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894 /* Initialize fake proc entry for use with HT fixup. */
895 bzero(&proc, sizeof(proc));
896 proc.type = 0;
897 proc.cpu_flags = PROCENTRY_FLAG_EN;
898
899#ifdef APIC_IO
900 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
901 M_DEVBUF, M_WAITOK);
902 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
903 M_DEVBUF, M_WAITOK | M_ZERO);
904 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
905 M_DEVBUF, M_WAITOK);
906#endif
907 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
908 M_DEVBUF, M_WAITOK);
909
910#ifdef APIC_IO
911 for (i = 0; i < mp_napics; i++) {
912 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
913 }
914#endif
915
916 /* clear various tables */
917 for (x = 0; x < NAPICID; ++x) {
918 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
919#ifdef APIC_IO
920 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
921 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
922#endif
923 }
924
925 /* clear bus data table */
926 for (x = 0; x < mp_nbusses; ++x)
927 bus_data[x].bus_id = 0xff;
928
929#ifdef APIC_IO
930 /* clear IO APIC INT table */
931 for (x = 0; x < (nintrs + 1); ++x) {
932 io_apic_ints[x].int_type = 0xff;
933 io_apic_ints[x].int_vector = 0xff;
934 }
935#endif
936
46d4e165 937 /* record whether PIC or virtual-wire mode */
91f1c7a4 938 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
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939
940 /* check for use of 'default' configuration */
91f1c7a4
MN
941 if (fps->mpfb1 != 0)
942 return fps->mpfb1; /* return default configuration type */
46d4e165 943
91f1c7a4
MN
944 cth = mpt->mp_cth;
945 if (cth == NULL)
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946 panic("MP Configuration Table Header MISSING!");
947
948 /* walk the table, recording info of interest */
949 totalSize = cth->base_table_length - sizeof(struct MPCTH);
950 position = (u_char *) cth + sizeof(struct MPCTH);
951 count = cth->entry_count;
952 apic = bus = intr = 0;
953 cpu = 1; /* pre-count the BSP */
954
955 while (count--) {
956 switch (type = *(u_char *) position) {
957 case 0:
958 if (processor_entry(position, cpu))
959 ++cpu;
960
961 if (need_hyperthreading_fixup) {
962 /*
963 * Create fake mptable processor entries
964 * and feed them to processor_entry() to
965 * enumerate the logical CPUs.
966 */
967 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
968 for (i = 1; i < logical_cpus; i++) {
969 proc.apic_id++;
970 processor_entry(&proc, cpu);
971 logical_cpus_mask |= (1 << cpu);
972 cpu++;
973 }
974 }
975 break;
976 case 1:
977 if (bus_entry(position, bus))
978 ++bus;
979 break;
980 case 2:
981#ifdef APIC_IO
982 if (io_apic_entry(position, apic))
983 ++apic;
984#endif
985 break;
986 case 3:
987#ifdef APIC_IO
988 if (int_entry(position, intr))
989 ++intr;
990#endif
991 break;
992 case 4:
993 /* int_entry(position); */
994 break;
995 default:
996 panic("mpfps Base Table HOSED!");
997 /* NOTREACHED */
998 }
999
1000 totalSize -= basetable_entry_types[type].length;
1001 position = (uint8_t *)position + basetable_entry_types[type].length;
1002 }
1003
bfa17615 1004 if (CPU_TO_ID(0) < 0)
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1005 panic("NO BSP found!");
1006
1007 /* report fact that its NOT a default configuration */
1008 return 0;
1009}
1010
91f1c7a4 1011
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1012/*
1013 * Check if we should perform a hyperthreading "fix-up" to
1014 * enumerate any logical CPU's that aren't already listed
1015 * in the table.
1016 *
1017 * XXX: We assume that all of the physical CPUs in the
1018 * system have the same number of logical CPUs.
1019 *
1020 * XXX: We assume that APIC ID's are allocated such that
1021 * the APIC ID's for a physical processor are aligned
1022 * with the number of logical CPU's in the processor.
1023 */
1024static void
1025mptable_hyperthread_fixup(u_int id_mask)
1026{
1027 u_int i, id;
1028
1029 /* Nothing to do if there is no HTT support. */
1030 if ((cpu_feature & CPUID_HTT) == 0)
1031 return;
1032 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1033 if (logical_cpus <= 1)
1034 return;
1035
1036 /*
1037 * For each APIC ID of a CPU that is set in the mask,
1038 * scan the other candidate APIC ID's for this
1039 * physical processor. If any of those ID's are
1040 * already in the table, then kill the fixup.
1041 */
1042 for (id = 0; id <= MAXCPU; id++) {
1043 if ((id_mask & 1 << id) == 0)
1044 continue;
1045 /* First, make sure we are on a logical_cpus boundary. */
1046 if (id % logical_cpus != 0)
1047 return;
1048 for (i = id + 1; i < id + logical_cpus; i++)
1049 if ((id_mask & 1 << i) != 0)
1050 return;
1051 }
1052
1053 /*
1054 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1055 * mp_naps right now.
1056 */
1057 need_hyperthreading_fixup = 1;
1058 mp_naps *= logical_cpus;
1059}
1060
91f1c7a4
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1061static void
1062mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1063{
1064 mpfps_t fps = NULL;
1065 mpcth_t cth = NULL;
1066 vm_size_t cth_mapsz = 0;
1067
1068 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1069 if (fps->pap != 0) {
1070 /*
1071 * Map configuration table header to get
1072 * the base table size
1073 */
1074 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1075 cth_mapsz = cth->base_table_length;
1076 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1077
1078 /*
1079 * Map the base table
1080 */
1081 cth = pmap_mapdev(fps->pap, cth_mapsz);
1082 }
1083
1084 mpt->mp_fps = fps;
1085 mpt->mp_cth = cth;
1086 mpt->mp_cth_mapsz = cth_mapsz;
1087}
1088
1089static void
1090mptable_unmap(struct mptable_pos *mpt)
1091{
1092 if (mpt->mp_cth != NULL) {
1093 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1094 mpt->mp_cth = NULL;
1095 mpt->mp_cth_mapsz = 0;
1096 }
1097 if (mpt->mp_fps != NULL) {
1098 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1099 mpt->mp_fps = NULL;
1100 }
1101}
1102
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1103#ifdef APIC_IO
1104
1105void
1106assign_apic_irq(int apic, int intpin, int irq)
1107{
1108 int x;
1109
1110 if (int_to_apicintpin[irq].ioapic != -1)
1111 panic("assign_apic_irq: inconsistent table");
1112
1113 int_to_apicintpin[irq].ioapic = apic;
1114 int_to_apicintpin[irq].int_pin = intpin;
1115 int_to_apicintpin[irq].apic_address = ioapic[apic];
1116 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1117
1118 for (x = 0; x < nintrs; x++) {
1119 if ((io_apic_ints[x].int_type == 0 ||
1120 io_apic_ints[x].int_type == 3) &&
1121 io_apic_ints[x].int_vector == 0xff &&
1122 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1123 io_apic_ints[x].dst_apic_int == intpin)
1124 io_apic_ints[x].int_vector = irq;
1125 }
1126}
1127
1128void
1129revoke_apic_irq(int irq)
1130{
1131 int x;
1132 int oldapic;
1133 int oldintpin;
1134
1135 if (int_to_apicintpin[irq].ioapic == -1)
1136 panic("revoke_apic_irq: inconsistent table");
1137
1138 oldapic = int_to_apicintpin[irq].ioapic;
1139 oldintpin = int_to_apicintpin[irq].int_pin;
1140
1141 int_to_apicintpin[irq].ioapic = -1;
1142 int_to_apicintpin[irq].int_pin = 0;
1143 int_to_apicintpin[irq].apic_address = NULL;
1144 int_to_apicintpin[irq].redirindex = 0;
1145
1146 for (x = 0; x < nintrs; x++) {
1147 if ((io_apic_ints[x].int_type == 0 ||
1148 io_apic_ints[x].int_type == 3) &&
1149 io_apic_ints[x].int_vector != 0xff &&
1150 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1151 io_apic_ints[x].dst_apic_int == oldintpin)
1152 io_apic_ints[x].int_vector = 0xff;
1153 }
1154}
1155
1156/*
1157 * Allocate an IRQ
1158 */
1159static void
1160allocate_apic_irq(int intr)
1161{
1162 int apic;
1163 int intpin;
1164 int irq;
1165
1166 if (io_apic_ints[intr].int_vector != 0xff)
1167 return; /* Interrupt handler already assigned */
1168
1169 if (io_apic_ints[intr].int_type != 0 &&
1170 (io_apic_ints[intr].int_type != 3 ||
1171 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1172 io_apic_ints[intr].dst_apic_int == 0)))
1173 return; /* Not INT or ExtInt on != (0, 0) */
1174
1175 irq = 0;
1176 while (irq < APIC_INTMAPSIZE &&
1177 int_to_apicintpin[irq].ioapic != -1)
1178 irq++;
1179
1180 if (irq >= APIC_INTMAPSIZE)
1181 return; /* No free interrupt handlers */
1182
1183 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1184 intpin = io_apic_ints[intr].dst_apic_int;
1185
1186 assign_apic_irq(apic, intpin, irq);
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1187}
1188
1189
1190static void
1191swap_apic_id(int apic, int oldid, int newid)
1192{
1193 int x;
1194 int oapic;
1195
1196
1197 if (oldid == newid)
1198 return; /* Nothing to do */
1199
1200 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1201 apic, oldid, newid);
1202
1203 /* Swap physical APIC IDs in interrupt entries */
1204 for (x = 0; x < nintrs; x++) {
1205 if (io_apic_ints[x].dst_apic_id == oldid)
1206 io_apic_ints[x].dst_apic_id = newid;
1207 else if (io_apic_ints[x].dst_apic_id == newid)
1208 io_apic_ints[x].dst_apic_id = oldid;
1209 }
1210
1211 /* Swap physical APIC IDs in IO_TO_ID mappings */
1212 for (oapic = 0; oapic < mp_napics; oapic++)
1213 if (IO_TO_ID(oapic) == newid)
1214 break;
1215
1216 if (oapic < mp_napics) {
1217 kprintf("Changing APIC ID for IO APIC #%d from "
1218 "%d to %d in MP table\n",
1219 oapic, newid, oldid);
1220 IO_TO_ID(oapic) = oldid;
1221 }
1222 IO_TO_ID(apic) = newid;
1223}
1224
1225
1226static void
1227fix_id_to_io_mapping(void)
1228{
1229 int x;
1230
1231 for (x = 0; x < NAPICID; x++)
1232 ID_TO_IO(x) = -1;
1233
1234 for (x = 0; x <= mp_naps; x++)
1235 if (CPU_TO_ID(x) < NAPICID)
1236 ID_TO_IO(CPU_TO_ID(x)) = x;
1237
1238 for (x = 0; x < mp_napics; x++)
1239 if (IO_TO_ID(x) < NAPICID)
1240 ID_TO_IO(IO_TO_ID(x)) = x;
1241}
1242
1243
1244static int
1245first_free_apic_id(void)
1246{
1247 int freeid, x;
1248
1249 for (freeid = 0; freeid < NAPICID; freeid++) {
1250 for (x = 0; x <= mp_naps; x++)
1251 if (CPU_TO_ID(x) == freeid)
1252 break;
1253 if (x <= mp_naps)
1254 continue;
1255 for (x = 0; x < mp_napics; x++)
1256 if (IO_TO_ID(x) == freeid)
1257 break;
1258 if (x < mp_napics)
1259 continue;
1260 return freeid;
1261 }
1262 return freeid;
1263}
1264
1265
1266static int
1267io_apic_id_acceptable(int apic, int id)
1268{
1269 int cpu; /* Logical CPU number */
1270 int oapic; /* Logical IO APIC number for other IO APIC */
1271
1272 if (id >= NAPICID)
1273 return 0; /* Out of range */
1274
1275 for (cpu = 0; cpu <= mp_naps; cpu++)
1276 if (CPU_TO_ID(cpu) == id)
1277 return 0; /* Conflict with CPU */
1278
1279 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1280 if (IO_TO_ID(oapic) == id)
1281 return 0; /* Conflict with other APIC */
1282
1283 return 1; /* ID is acceptable for IO APIC */
1284}
1285
1286static
1287io_int *
1288io_apic_find_int_entry(int apic, int pin)
1289{
1290 int x;
1291
1292 /* search each of the possible INTerrupt sources */
1293 for (x = 0; x < nintrs; ++x) {
1294 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1295 (pin == io_apic_ints[x].dst_apic_int))
1296 return (&io_apic_ints[x]);
1297 }
1298 return NULL;
1299}
1300
1301#endif
1302
1303/*
1304 * parse an Intel MP specification table
1305 */
1306static void
0eaa8172 1307mptable_fix(void)
46d4e165
JG
1308{
1309 int x;
1310#ifdef APIC_IO
1311 int id;
1312 int apic; /* IO APIC unit number */
1313 int freeid; /* Free physical APIC ID */
1314 int physid; /* Current physical IO APIC ID */
1315 io_int *io14;
1316#endif
1317 int bus_0 = 0; /* Stop GCC warning */
1318 int bus_pci = 0; /* Stop GCC warning */
1319 int num_pci_bus;
1320
1321 /*
1322 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1323 * did it wrong. The MP spec says that when more than 1 PCI bus
1324 * exists the BIOS must begin with bus entries for the PCI bus and use
1325 * actual PCI bus numbering. This implies that when only 1 PCI bus
1326 * exists the BIOS can choose to ignore this ordering, and indeed many
1327 * MP motherboards do ignore it. This causes a problem when the PCI
1328 * sub-system makes requests of the MP sub-system based on PCI bus
1329 * numbers. So here we look for the situation and renumber the
1330 * busses and associated INTs in an effort to "make it right".
1331 */
1332
1333 /* find bus 0, PCI bus, count the number of PCI busses */
1334 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1335 if (bus_data[x].bus_id == 0) {
1336 bus_0 = x;
1337 }
1338 if (bus_data[x].bus_type == PCI) {
1339 ++num_pci_bus;
1340 bus_pci = x;
1341 }
1342 }
1343 /*
1344 * bus_0 == slot of bus with ID of 0
1345 * bus_pci == slot of last PCI bus encountered
1346 */
1347
1348 /* check the 1 PCI bus case for sanity */
1349 /* if it is number 0 all is well */
1350 if (num_pci_bus == 1 &&
1351 bus_data[bus_pci].bus_id != 0) {
1352
1353 /* mis-numbered, swap with whichever bus uses slot 0 */
1354
1355 /* swap the bus entry types */
1356 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1357 bus_data[bus_0].bus_type = PCI;
1358
1359#ifdef APIC_IO
1360 /* swap each relavant INTerrupt entry */
1361 id = bus_data[bus_pci].bus_id;
1362 for (x = 0; x < nintrs; ++x) {
1363 if (io_apic_ints[x].src_bus_id == id) {
1364 io_apic_ints[x].src_bus_id = 0;
1365 }
1366 else if (io_apic_ints[x].src_bus_id == 0) {
1367 io_apic_ints[x].src_bus_id = id;
1368 }
1369 }
1370#endif
1371 }
1372
1373#ifdef APIC_IO
1374 /* Assign IO APIC IDs.
1375 *
1376 * First try the existing ID. If a conflict is detected, try
1377 * the ID in the MP table. If a conflict is still detected, find
1378 * a free id.
1379 *
1380 * We cannot use the ID_TO_IO table before all conflicts has been
1381 * resolved and the table has been corrected.
1382 */
1383 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1384
1385 /* First try to use the value set by the BIOS */
1386 physid = io_apic_get_id(apic);
1387 if (io_apic_id_acceptable(apic, physid)) {
1388 if (IO_TO_ID(apic) != physid)
1389 swap_apic_id(apic, IO_TO_ID(apic), physid);
1390 continue;
1391 }
1392
1393 /* Then check if the value in the MP table is acceptable */
1394 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1395 continue;
1396
1397 /* Last resort, find a free APIC ID and use it */
1398 freeid = first_free_apic_id();
1399 if (freeid >= NAPICID)
1400 panic("No free physical APIC IDs found");
1401
1402 if (io_apic_id_acceptable(apic, freeid)) {
1403 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1404 continue;
1405 }
1406 panic("Free physical APIC ID not usable");
1407 }
1408 fix_id_to_io_mapping();
1409#endif
1410
1411#ifdef APIC_IO
1412 /* detect and fix broken Compaq MP table */
1413 if (apic_int_type(0, 0) == -1) {
1414 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1415 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1416 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1417 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1418 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1419 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1420 nintrs++;
1421 } else if (apic_int_type(0, 0) == 0) {
1422 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1423 for (x = 0; x < nintrs; ++x)
1424 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1425 (0 == io_apic_ints[x].dst_apic_int)) {
1426 io_apic_ints[x].int_type = 3;
1427 io_apic_ints[x].int_vector = 0xff;
1428 break;
1429 }
1430 }
1431
1432 /*
1433 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1434 * controllers universally come in pairs. If IRQ 14 is specified
1435 * as an ISA interrupt, then IRQ 15 had better be too.
1436 *
1437 * [ Shuttle XPC / AMD Athlon X2 ]
1438 * The MPTable is missing an entry for IRQ 15. Note that the
1439 * ACPI table has an entry for both 14 and 15.
1440 */
1441 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1442 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1443 io14 = io_apic_find_int_entry(0, 14);
1444 io_apic_ints[nintrs] = *io14;
1445 io_apic_ints[nintrs].src_bus_irq = 15;
1446 io_apic_ints[nintrs].dst_apic_int = 15;
1447 nintrs++;
1448 }
1449#endif
1450}
1451
1452#ifdef APIC_IO
1453
1454/* Assign low level interrupt handlers */
1455static void
1456setup_apic_irq_mapping(void)
1457{
1458 int x;
1459 int int_vector;
1460
1461 /* Clear array */
1462 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1463 int_to_apicintpin[x].ioapic = -1;
1464 int_to_apicintpin[x].int_pin = 0;
1465 int_to_apicintpin[x].apic_address = NULL;
1466 int_to_apicintpin[x].redirindex = 0;
1467 }
1468
1469 /* First assign ISA/EISA interrupts */
1470 for (x = 0; x < nintrs; x++) {
1471 int_vector = io_apic_ints[x].src_bus_irq;
1472 if (int_vector < APIC_INTMAPSIZE &&
1473 io_apic_ints[x].int_vector == 0xff &&
1474 int_to_apicintpin[int_vector].ioapic == -1 &&
1475 (apic_int_is_bus_type(x, ISA) ||
1476 apic_int_is_bus_type(x, EISA)) &&
1477 io_apic_ints[x].int_type == 0) {
1478 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1479 io_apic_ints[x].dst_apic_int,
1480 int_vector);
1481 }
1482 }
1483
1484 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1485 for (x = 0; x < nintrs; x++) {
1486 if (io_apic_ints[x].dst_apic_int == 0 &&
1487 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1488 io_apic_ints[x].int_vector == 0xff &&
1489 int_to_apicintpin[0].ioapic == -1 &&
1490 io_apic_ints[x].int_type == 3) {
1491 assign_apic_irq(0, 0, 0);
1492 break;
1493 }
1494 }
662f60ef
SZ
1495
1496 /* Assign PCI interrupts */
1497 for (x = 0; x < nintrs; ++x) {
1498 if (io_apic_ints[x].int_type == 0 &&
1499 io_apic_ints[x].int_vector == 0xff &&
1500 apic_int_is_bus_type(x, PCI))
1501 allocate_apic_irq(x);
1502 }
46d4e165
JG
1503}
1504
1505#endif
1506
1507static int
1508processor_entry(proc_entry_ptr entry, int cpu)
1509{
bfa17615
MN
1510 KKASSERT(cpu > 0);
1511
46d4e165
JG
1512 /* check for usability */
1513 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1514 return 0;
1515
1516 if(entry->apic_id >= NAPICID)
1517 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1518 /* check for BSP flag */
1519 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
46d4e165
JG
1520 CPU_TO_ID(0) = entry->apic_id;
1521 ID_TO_CPU(entry->apic_id) = 0;
1522 return 0; /* its already been counted */
1523 }
1524
1525 /* add another AP to list, if less than max number of CPUs */
1526 else if (cpu < MAXCPU) {
1527 CPU_TO_ID(cpu) = entry->apic_id;
1528 ID_TO_CPU(entry->apic_id) = cpu;
1529 return 1;
1530 }
1531
1532 return 0;
1533}
1534
1535
1536static int
1537bus_entry(bus_entry_ptr entry, int bus)
1538{
1539 int x;
1540 char c, name[8];
1541
1542 /* encode the name into an index */
1543 for (x = 0; x < 6; ++x) {
1544 if ((c = entry->bus_type[x]) == ' ')
1545 break;
1546 name[x] = c;
1547 }
1548 name[x] = '\0';
1549
1550 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1551 panic("unknown bus type: '%s'", name);
1552
1553 bus_data[bus].bus_id = entry->bus_id;
1554 bus_data[bus].bus_type = x;
1555
1556 return 1;
1557}
1558
1559#ifdef APIC_IO
1560
1561static int
1562io_apic_entry(io_apic_entry_ptr entry, int apic)
1563{
1564 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1565 return 0;
1566
1567 IO_TO_ID(apic) = entry->apic_id;
1568 if (entry->apic_id < NAPICID)
1569 ID_TO_IO(entry->apic_id) = apic;
1570
1571 return 1;
1572}
1573
1574#endif
1575
1576static int
1577lookup_bus_type(char *name)
1578{
1579 int x;
1580
1581 for (x = 0; x < MAX_BUSTYPE; ++x)
1582 if (strcmp(bus_type_table[x].name, name) == 0)
1583 return bus_type_table[x].type;
1584
1585 return UNKNOWN_BUSTYPE;
1586}
1587
1588#ifdef APIC_IO
1589
1590static int
1591int_entry(int_entry_ptr entry, int intr)
1592{
1593 int apic;
1594
1595 io_apic_ints[intr].int_type = entry->int_type;
1596 io_apic_ints[intr].int_flags = entry->int_flags;
1597 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1598 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1599 if (entry->dst_apic_id == 255) {
1600 /* This signal goes to all IO APICS. Select an IO APIC
1601 with sufficient number of interrupt pins */
1602 for (apic = 0; apic < mp_napics; apic++)
1603 if (((io_apic_read(apic, IOAPIC_VER) &
1604 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1605 entry->dst_apic_int)
1606 break;
1607 if (apic < mp_napics)
1608 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1609 else
1610 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1611 } else
1612 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1613 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1614
1615 return 1;
1616}
1617
1618static int
1619apic_int_is_bus_type(int intr, int bus_type)
1620{
1621 int bus;
1622
1623 for (bus = 0; bus < mp_nbusses; ++bus)
1624 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1625 && ((int) bus_data[bus].bus_type == bus_type))
1626 return 1;
1627
1628 return 0;
1629}
1630
1631/*
1632 * Given a traditional ISA INT mask, return an APIC mask.
1633 */
1634u_int
1635isa_apic_mask(u_int isa_mask)
1636{
1637 int isa_irq;
1638 int apic_pin;
1639
1640#if defined(SKIP_IRQ15_REDIRECT)
1641 if (isa_mask == (1 << 15)) {
1642 kprintf("skipping ISA IRQ15 redirect\n");
1643 return isa_mask;
1644 }
1645#endif /* SKIP_IRQ15_REDIRECT */
1646
1647 isa_irq = ffs(isa_mask); /* find its bit position */
1648 if (isa_irq == 0) /* doesn't exist */
1649 return 0;
1650 --isa_irq; /* make it zero based */
1651
1652 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1653 if (apic_pin == -1)
1654 return 0;
1655
1656 return (1 << apic_pin); /* convert pin# to a mask */
1657}
1658
1659/*
1660 * Determine which APIC pin an ISA/EISA INT is attached to.
1661 */
1662#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1663#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1664#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1665#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1666
1667#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1668int
1669isa_apic_irq(int isa_irq)
1670{
1671 int intr;
1672
1673 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1674 if (INTTYPE(intr) == 0) { /* standard INT */
1675 if (SRCBUSIRQ(intr) == isa_irq) {
1676 if (apic_int_is_bus_type(intr, ISA) ||
1677 apic_int_is_bus_type(intr, EISA)) {
1678 if (INTIRQ(intr) == 0xff)
1679 return -1; /* unassigned */
1680 return INTIRQ(intr); /* found */
1681 }
1682 }
1683 }
1684 }
1685 return -1; /* NOT found */
1686}
1687
1688
1689/*
1690 * Determine which APIC pin a PCI INT is attached to.
1691 */
1692#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1693#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1694#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1695int
1696pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1697{
1698 int intr;
1699
1700 --pciInt; /* zero based */
1701
1702 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1703 if ((INTTYPE(intr) == 0) /* standard INT */
1704 && (SRCBUSID(intr) == pciBus)
1705 && (SRCBUSDEVICE(intr) == pciDevice)
1706 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1707 if (apic_int_is_bus_type(intr, PCI)) {
662f60ef
SZ
1708 if (INTIRQ(intr) == 0xff) {
1709 kprintf("IOAPIC: pci_apic_irq() "
1710 "failed\n");
46d4e165 1711 return -1; /* unassigned */
662f60ef 1712 }
46d4e165
JG
1713 return INTIRQ(intr); /* exact match */
1714 }
1715 }
1716 }
1717
1718 return -1; /* NOT found */
1719}
1720
1721int
1722next_apic_irq(int irq)
1723{
1724 int intr, ointr;
1725 int bus, bustype;
1726
1727 bus = 0;
1728 bustype = 0;
1729 for (intr = 0; intr < nintrs; intr++) {
1730 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1731 continue;
1732 bus = SRCBUSID(intr);
1733 bustype = apic_bus_type(bus);
1734 if (bustype != ISA &&
1735 bustype != EISA &&
1736 bustype != PCI)
1737 continue;
1738 break;
1739 }
1740 if (intr >= nintrs) {
1741 return -1;
1742 }
1743 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1744 if (INTTYPE(ointr) != 0)
1745 continue;
1746 if (bus != SRCBUSID(ointr))
1747 continue;
1748 if (bustype == PCI) {
1749 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1750 continue;
1751 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1752 continue;
1753 }
1754 if (bustype == ISA || bustype == EISA) {
1755 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1756 continue;
1757 }
1758 if (INTPIN(intr) == INTPIN(ointr))
1759 continue;
1760 break;
1761 }
1762 if (ointr >= nintrs) {
1763 return -1;
1764 }
1765 return INTIRQ(ointr);
1766}
1767#undef SRCBUSLINE
1768#undef SRCBUSDEVICE
1769#undef SRCBUSID
1770#undef SRCBUSIRQ
1771
1772#undef INTPIN
1773#undef INTIRQ
1774#undef INTAPIC
1775#undef INTTYPE
1776
1777#endif
1778
1779/*
1780 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1781 *
1782 * XXX FIXME:
1783 * Exactly what this means is unclear at this point. It is a solution
1784 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1785 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1786 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1787 * option.
1788 */
1789int
1790undirect_isa_irq(int rirq)
1791{
1792#if defined(READY)
1793 if (bootverbose)
1794 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1795 /** FIXME: tickle the MB redirector chip */
1796 return /* XXX */;
1797#else
1798 if (bootverbose)
1799 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1800 return 0;
1801#endif /* READY */
1802}
1803
1804
1805/*
1806 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1807 */
1808int
1809undirect_pci_irq(int rirq)
1810{
1811#if defined(READY)
1812 if (bootverbose)
1813 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1814
1815 /** FIXME: tickle the MB redirector chip */
1816 return /* XXX */;
1817#else
1818 if (bootverbose)
1819 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1820 rirq);
1821 return 0;
1822#endif /* READY */
1823}
1824
1825
1826/*
1827 * given a bus ID, return:
1828 * the bus type if found
1829 * -1 if NOT found
1830 */
1831int
1832apic_bus_type(int id)
1833{
1834 int x;
1835
1836 for (x = 0; x < mp_nbusses; ++x)
1837 if (bus_data[x].bus_id == id)
1838 return bus_data[x].bus_type;
1839
1840 return -1;
1841}
1842
1843#ifdef APIC_IO
1844
1845/*
1846 * given a LOGICAL APIC# and pin#, return:
1847 * the associated src bus ID if found
1848 * -1 if NOT found
1849 */
1850int
1851apic_src_bus_id(int apic, int pin)
1852{
1853 int x;
1854
1855 /* search each of the possible INTerrupt sources */
1856 for (x = 0; x < nintrs; ++x)
1857 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1858 (pin == io_apic_ints[x].dst_apic_int))
1859 return (io_apic_ints[x].src_bus_id);
1860
1861 return -1; /* NOT found */
1862}
1863
1864/*
1865 * given a LOGICAL APIC# and pin#, return:
1866 * the associated src bus IRQ if found
1867 * -1 if NOT found
1868 */
1869int
1870apic_src_bus_irq(int apic, int pin)
1871{
1872 int x;
1873
1874 for (x = 0; x < nintrs; x++)
1875 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1876 (pin == io_apic_ints[x].dst_apic_int))
1877 return (io_apic_ints[x].src_bus_irq);
1878
1879 return -1; /* NOT found */
1880}
1881
1882
1883/*
1884 * given a LOGICAL APIC# and pin#, return:
1885 * the associated INTerrupt type if found
1886 * -1 if NOT found
1887 */
1888int
1889apic_int_type(int apic, int pin)
1890{
1891 int x;
1892
1893 /* search each of the possible INTerrupt sources */
1894 for (x = 0; x < nintrs; ++x) {
1895 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1896 (pin == io_apic_ints[x].dst_apic_int))
1897 return (io_apic_ints[x].int_type);
1898 }
1899 return -1; /* NOT found */
1900}
1901
1902/*
1903 * Return the IRQ associated with an APIC pin
1904 */
1905int
1906apic_irq(int apic, int pin)
1907{
1908 int x;
1909 int res;
1910
1911 for (x = 0; x < nintrs; ++x) {
1912 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1913 (pin == io_apic_ints[x].dst_apic_int)) {
1914 res = io_apic_ints[x].int_vector;
1915 if (res == 0xff)
1916 return -1;
1917 if (apic != int_to_apicintpin[res].ioapic)
1918 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1919 if (pin != int_to_apicintpin[res].int_pin)
1920 panic("apic_irq inconsistent table (2)");
1921 return res;
1922 }
1923 }
1924 return -1;
1925}
1926
1927
1928/*
1929 * given a LOGICAL APIC# and pin#, return:
1930 * the associated trigger mode if found
1931 * -1 if NOT found
1932 */
1933int
1934apic_trigger(int apic, int pin)
1935{
1936 int x;
1937
1938 /* search each of the possible INTerrupt sources */
1939 for (x = 0; x < nintrs; ++x)
1940 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1941 (pin == io_apic_ints[x].dst_apic_int))
1942 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1943
1944 return -1; /* NOT found */
1945}
1946
1947
1948/*
1949 * given a LOGICAL APIC# and pin#, return:
1950 * the associated 'active' level if found
1951 * -1 if NOT found
1952 */
1953int
1954apic_polarity(int apic, int pin)
1955{
1956 int x;
1957
1958 /* search each of the possible INTerrupt sources */
1959 for (x = 0; x < nintrs; ++x)
1960 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1961 (pin == io_apic_ints[x].dst_apic_int))
1962 return (io_apic_ints[x].int_flags & 0x03);
1963
1964 return -1; /* NOT found */
1965}
1966
1967#endif
1968
1969/*
1970 * set data according to MP defaults
1971 * FIXME: probably not complete yet...
1972 */
1973static void
0eaa8172 1974mptable_default(int type)
46d4e165 1975{
bfa17615 1976 int ap_cpu_id, boot_cpu_id;
46d4e165
JG
1977#if defined(APIC_IO)
1978 int io_apic_id;
1979 int pin;
1980#endif /* APIC_IO */
1981
1982#if 0
1983 kprintf(" MP default config type: %d\n", type);
1984 switch (type) {
1985 case 1:
1986 kprintf(" bus: ISA, APIC: 82489DX\n");
1987 break;
1988 case 2:
1989 kprintf(" bus: EISA, APIC: 82489DX\n");
1990 break;
1991 case 3:
1992 kprintf(" bus: EISA, APIC: 82489DX\n");
1993 break;
1994 case 4:
1995 kprintf(" bus: MCA, APIC: 82489DX\n");
1996 break;
1997 case 5:
1998 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1999 break;
2000 case 6:
2001 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2002 break;
2003 case 7:
2004 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2005 break;
2006 default:
2007 kprintf(" future type\n");
2008 break;
2009 /* NOTREACHED */
2010 }
2011#endif /* 0 */
2012
2013 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2014 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2015
2016 /* BSP */
2017 CPU_TO_ID(0) = boot_cpu_id;
2018 ID_TO_CPU(boot_cpu_id) = 0;
2019
2020 /* one and only AP */
2021 CPU_TO_ID(1) = ap_cpu_id;
2022 ID_TO_CPU(ap_cpu_id) = 1;
2023
2024#if defined(APIC_IO)
2025 /* one and only IO APIC */
2026 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2027
2028 /*
2029 * sanity check, refer to MP spec section 3.6.6, last paragraph
2030 * necessary as some hardware isn't properly setting up the IO APIC
2031 */
2032#if defined(REALLY_ANAL_IOAPICID_VALUE)
2033 if (io_apic_id != 2) {
2034#else
2035 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2036#endif /* REALLY_ANAL_IOAPICID_VALUE */
2037 io_apic_set_id(0, 2);
2038 io_apic_id = 2;
2039 }
2040 IO_TO_ID(0) = io_apic_id;
2041 ID_TO_IO(io_apic_id) = 0;
2042#endif /* APIC_IO */
2043
2044 /* fill out bus entries */
2045 switch (type) {
2046 case 1:
2047 case 2:
2048 case 3:
2049 case 4:
2050 case 5:
2051 case 6:
2052 case 7:
2053 bus_data[0].bus_id = default_data[type - 1][1];
2054 bus_data[0].bus_type = default_data[type - 1][2];
2055 bus_data[1].bus_id = default_data[type - 1][3];
2056 bus_data[1].bus_type = default_data[type - 1][4];
2057 break;
2058
2059 /* case 4: case 7: MCA NOT supported */
2060 default: /* illegal/reserved */
2061 panic("BAD default MP config: %d", type);
2062 /* NOTREACHED */
2063 }
2064
2065#if defined(APIC_IO)
2066 /* general cases from MP v1.4, table 5-2 */
2067 for (pin = 0; pin < 16; ++pin) {
2068 io_apic_ints[pin].int_type = 0;
2069 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2070 io_apic_ints[pin].src_bus_id = 0;
2071 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2072 io_apic_ints[pin].dst_apic_id = io_apic_id;
2073 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2074 }
2075
2076 /* special cases from MP v1.4, table 5-2 */
2077 if (type == 2) {
2078 io_apic_ints[2].int_type = 0xff; /* N/C */
2079 io_apic_ints[13].int_type = 0xff; /* N/C */
2080#if !defined(APIC_MIXED_MODE)
2081 /** FIXME: ??? */
2082 panic("sorry, can't support type 2 default yet");
2083#endif /* APIC_MIXED_MODE */
2084 }
2085 else
2086 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2087
2088 if (type == 7)
2089 io_apic_ints[0].int_type = 0xff; /* N/C */
2090 else
2091 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2092#endif /* APIC_IO */
2093}
2094
2095/*
2096 * Map a physical memory address representing I/O into KVA. The I/O
2097 * block is assumed not to cross a page boundary.
2098 */
2099void *
2100permanent_io_mapping(vm_paddr_t pa)
2101{
46d4e165
JG
2102 KKASSERT(pa < 0x100000000LL);
2103
403c36ea 2104 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
46d4e165
JG
2105}
2106
2107/*
2108 * start each AP in our list
2109 */
2110static int
2111start_all_aps(u_int boot_addr)
2112{
2113 vm_offset_t va = boot_address + KERNBASE;
2114 u_int64_t *pt4, *pt3, *pt2;
2115 int x, i, pg;
2116 int shift;
bb467734
MD
2117 int smicount;
2118 int smibest;
2119 int smilast;
46d4e165
JG
2120 u_char mpbiosreason;
2121 u_long mpbioswarmvec;
2122 struct mdglobaldata *gd;
2123 struct privatespace *ps;
46d4e165
JG
2124
2125 POSTCODE(START_ALL_APS_POST);
2126
2127 /* Initialize BSP's local APIC */
2128 apic_initialize(TRUE);
2129 bsp_apic_ready = 1;
2130
2131 /* install the AP 1st level boot code */
2132 pmap_kenter(va, boot_address);
bfc09ba0 2133 cpu_invlpg((void *)va); /* JG XXX */
46d4e165
JG
2134 bcopy(mptramp_start, (void *)va, bootMP_size);
2135
2136 /* Locate the page tables, they'll be below the trampoline */
2137 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2138 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2139 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2140
2141 /* Create the initial 1GB replicated page tables */
2142 for (i = 0; i < 512; i++) {
2143 /* Each slot of the level 4 pages points to the same level 3 page */
2144 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2145 pt4[i] |= PG_V | PG_RW | PG_U;
2146
2147 /* Each slot of the level 3 pages points to the same level 2 page */
2148 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2149 pt3[i] |= PG_V | PG_RW | PG_U;
2150
2151 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2152 pt2[i] = i * (2 * 1024 * 1024);
2153 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2154 }
2155
2156 /* save the current value of the warm-start vector */
2157 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2158 outb(CMOS_REG, BIOS_RESET);
2159 mpbiosreason = inb(CMOS_DATA);
2160
2161 /* setup a vector to our boot code */
2162 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2163 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2164 outb(CMOS_REG, BIOS_RESET);
2165 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2166
bb467734
MD
2167 /*
2168 * If we have a TSC we can figure out the SMI interrupt rate.
2169 * The SMI does not necessarily use a constant rate. Spend
2170 * up to 250ms trying to figure it out.
2171 */
2172 smibest = 0;
2173 if (cpu_feature & CPUID_TSC) {
2174 set_apic_timer(275000);
2175 smilast = read_apic_timer();
2176 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2177 smicount = smitest();
2178 if (smibest == 0 || smilast - smicount < smibest)
2179 smibest = smilast - smicount;
2180 smilast = smicount;
2181 }
2182 if (smibest > 250000)
2183 smibest = 0;
2184 if (smibest) {
2185 smibest = smibest * (int64_t)1000000 /
2186 get_apic_timer_frequency();
2187 }
2188 }
2189 if (smibest)
2190 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2191 1000000 / smibest, smibest);
2192
46d4e165
JG
2193 /* start each AP */
2194 for (x = 1; x <= mp_naps; ++x) {
2195
2196 /* This is a bit verbose, it will go away soon. */
2197
2198 /* first page of AP's private space */
b2b3ffcd 2199 pg = x * x86_64_btop(sizeof(struct privatespace));
46d4e165
JG
2200
2201 /* allocate new private data page(s) */
2202 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2203 MDGLOBALDATA_BASEALLOC_SIZE);
46d4e165
JG
2204
2205 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2206 bzero(gd, sizeof(*gd));
2207 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2208
2209 /* prime data page for it to use */
2210 mi_gdinit(&gd->mi, x);
2211 cpu_gdinit(gd, x);
2212 gd->gd_CMAP1 = &SMPpt[pg + 0];
2213 gd->gd_CMAP2 = &SMPpt[pg + 1];
2214 gd->gd_CMAP3 = &SMPpt[pg + 2];
2215 gd->gd_PMAP1 = &SMPpt[pg + 3];
2216 gd->gd_CADDR1 = ps->CPAGE1;
2217 gd->gd_CADDR2 = ps->CPAGE2;
2218 gd->gd_CADDR3 = ps->CPAGE3;
bfc09ba0 2219 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
46d4e165
JG
2220 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2221 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2222
2223 /* setup a vector to our boot code */
2224 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2225 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2226 outb(CMOS_REG, BIOS_RESET);
2227 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2228
2229 /*
2230 * Setup the AP boot stack
2231 */
2232 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2233 bootAP = x;
2234
2235 /* attempt to start the Application Processor */
2236 CHECK_INIT(99); /* setup checkpoints */
bb467734 2237 if (!start_ap(gd, boot_addr, smibest)) {
46d4e165
JG
2238 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2239 CHECK_PRINT("trace"); /* show checkpoints */
2240 /* better panic as the AP may be running loose */
2241 kprintf("panic y/n? [y] ");
2242 if (cngetc() != 'n')
2243 panic("bye-bye");
2244 }
2245 CHECK_PRINT("trace"); /* show checkpoints */
2246
2247 /* record its version info */
2248 cpu_apic_versions[x] = cpu_apic_versions[0];
2249 }
2250
2251 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2252 ncpus = x;
2253
2254 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2255 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2256 ;
2257 --shift;
2258 ncpus2_shift = shift;
2259 ncpus2 = 1 << shift;
2260 ncpus2_mask = ncpus2 - 1;
2261
2262 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2263 if ((1 << shift) < ncpus)
2264 ++shift;
2265 ncpus_fit = 1 << shift;
2266 ncpus_fit_mask = ncpus_fit - 1;
2267
2268 /* build our map of 'other' CPUs */
2269 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2270 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2271 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2272
2273 /* fill in our (BSP) APIC version */
2274 cpu_apic_versions[0] = lapic->version;
2275
2276 /* restore the warmstart vector */
2277 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2278 outb(CMOS_REG, BIOS_RESET);
2279 outb(CMOS_DATA, mpbiosreason);
2280
2281 /*
2282 * NOTE! The idlestack for the BSP was setup by locore. Finish
2283 * up, clean out the P==V mapping we did earlier.
2284 */
46d4e165
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2285 pmap_set_opt();
2286
2287 /* number of APs actually started */
2288 return ncpus - 1;
2289}
2290
2291
2292/*
2293 * load the 1st level AP boot code into base memory.
2294 */
2295
2296/* targets for relocation */
2297extern void bigJump(void);
2298extern void bootCodeSeg(void);
2299extern void bootDataSeg(void);
2300extern void MPentry(void);
2301extern u_int MP_GDT;
2302extern u_int mp_gdtbase;
2303
bfc09ba0
MD
2304#if 0
2305
46d4e165
JG
2306static void
2307install_ap_tramp(u_int boot_addr)
2308{
2309 int x;
2310 int size = *(int *) ((u_long) & bootMP_size);
2311 u_char *src = (u_char *) ((u_long) bootMP);
2312 u_char *dst = (u_char *) boot_addr + KERNBASE;
2313 u_int boot_base = (u_int) bootMP;
2314 u_int8_t *dst8;
2315 u_int16_t *dst16;
2316 u_int32_t *dst32;
2317
2318 POSTCODE(INSTALL_AP_TRAMP_POST);
2319
2320 for (x = 0; x < size; ++x)
2321 *dst++ = *src++;
2322
2323 /*
2324 * modify addresses in code we just moved to basemem. unfortunately we
2325 * need fairly detailed info about mpboot.s for this to work. changes
2326 * to mpboot.s might require changes here.
2327 */
2328
2329 /* boot code is located in KERNEL space */
2330 dst = (u_char *) boot_addr + KERNBASE;
2331
2332 /* modify the lgdt arg */
2333 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2334 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2335
2336 /* modify the ljmp target for MPentry() */
2337 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2338 *dst32 = ((u_int) MPentry - KERNBASE);
2339
2340 /* modify the target for boot code segment */
2341 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2342 dst8 = (u_int8_t *) (dst16 + 1);
2343 *dst16 = (u_int) boot_addr & 0xffff;
2344 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2345
2346 /* modify the target for boot data segment */
2347 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2348 dst8 = (u_int8_t *) (dst16 + 1);
2349 *dst16 = (u_int) boot_addr & 0xffff;
2350 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2351}
2352
bfc09ba0 2353#endif
46d4e165
JG
2354
2355/*
bb467734 2356 * This function starts the AP (application processor) identified
46d4e165
JG
2357 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2358 * to accomplish this. This is necessary because of the nuances
2359 * of the different hardware we might encounter. It ain't pretty,
2360 * but it seems to work.
2361 *
2362 * NOTE: eventually an AP gets to ap_init(), which is called just
2363 * before the AP goes into the LWKT scheduler's idle loop.
2364 */
2365static int
bb467734 2366start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
46d4e165
JG
2367{
2368 int physical_cpu;
2369 int vector;
2370 u_long icr_lo, icr_hi;
2371
2372 POSTCODE(START_AP_POST);
2373
2374 /* get the PHYSICAL APIC ID# */
2375 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2376
2377 /* calculate the vector */
2378 vector = (boot_addr >> 12) & 0xff;
2379
bb467734
MD
2380 /* We don't want anything interfering */
2381 cpu_disable_intr();
2382
46d4e165
JG
2383 /* Make sure the target cpu sees everything */
2384 wbinvd();
2385
2386 /*
bb467734
MD
2387 * Try to detect when a SMI has occurred, wait up to 200ms.
2388 *
2389 * If a SMI occurs during an AP reset but before we issue
2390 * the STARTUP command, the AP may brick. To work around
2391 * this problem we hold off doing the AP startup until
2392 * after we have detected the SMI. Hopefully another SMI
2393 * will not occur before we finish the AP startup.
2394 *
2395 * Retries don't seem to help. SMIs have a window of opportunity
2396 * and if USB->legacy keyboard emulation is enabled in the BIOS
2397 * the interrupt rate can be quite high.
2398 *
2399 * NOTE: Don't worry about the L1 cache load, it might bloat
2400 * ldelta a little but ndelta will be so huge when the SMI
2401 * occurs the detection logic will still work fine.
2402 */
2403 if (smibest) {
2404 set_apic_timer(200000);
2405 smitest();
2406 }
2407
2408 /*
46d4e165
JG
2409 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2410 * and running the target CPU. OR this INIT IPI might be latched (P5
2411 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2412 * ignored.
bb467734
MD
2413 *
2414 * see apic/apicreg.h for icr bit definitions.
2415 *
2416 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
46d4e165
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2417 */
2418
bb467734
MD
2419 /*
2420 * Setup the address for the target AP. We can setup
2421 * icr_hi once and then just trigger operations with
2422 * icr_lo.
2423 */
46d4e165
JG
2424 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2425 icr_hi |= (physical_cpu << 24);
46d4e165 2426 icr_lo = lapic->icr_lo & 0xfff00000;
bb467734 2427 lapic->icr_hi = icr_hi;
46d4e165 2428
bb467734
MD
2429 /*
2430 * Do an INIT IPI: assert RESET
2431 *
2432 * Use edge triggered mode to assert INIT
2433 */
2434 lapic->icr_lo = icr_lo | 0x00004500;
46d4e165
JG
2435 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2436 /* spin */ ;
2437
bb467734
MD
2438 /*
2439 * The spec calls for a 10ms delay but we may have to use a
2440 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2441 * interrupt. We have other loops here too and dividing by 2
2442 * doesn't seem to be enough even after subtracting 350us,
2443 * so we divide by 4.
2444 *
2445 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2446 * interrupt was detected we use the full 10ms.
2447 */
2448 if (smibest == 0)
2449 u_sleep(10000);
2450 else if (smibest < 150 * 4 + 350)
2451 u_sleep(150);
2452 else if ((smibest - 350) / 4 < 10000)
2453 u_sleep((smibest - 350) / 4);
2454 else
2455 u_sleep(10000);
46d4e165 2456
bb467734
MD
2457 /*
2458 * Do an INIT IPI: deassert RESET
2459 *
2460 * Use level triggered mode to deassert. It is unclear
2461 * why we need to do this.
2462 */
2463 lapic->icr_lo = icr_lo | 0x00008500;
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2464 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2465 /* spin */ ;
bb467734 2466 u_sleep(150); /* wait 150us */
46d4e165
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2467
2468 /*
bb467734 2469 * Next we do a STARTUP IPI: the previous INIT IPI might still be
46d4e165
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2470 * latched, (P5 bug) this 1st STARTUP would then terminate
2471 * immediately, and the previously started INIT IPI would continue. OR
2472 * the previous INIT IPI has already run. and this STARTUP IPI will
2473 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2474 * will run.
2475 */
46d4e165
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2476 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2477 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2478 /* spin */ ;
2479 u_sleep(200); /* wait ~200uS */
2480
2481 /*
bb467734 2482 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
46d4e165
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2483 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2484 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2485 * recognized after hardware RESET or INIT IPI.
2486 */
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2487 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2488 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2489 /* spin */ ;
bb467734
MD
2490
2491 /* Resume normal operation */
2492 cpu_enable_intr();
46d4e165
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2493
2494 /* wait for it to start, see ap_init() */
2495 set_apic_timer(5000000);/* == 5 seconds */
2496 while (read_apic_timer()) {
2497 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2498 return 1; /* return SUCCESS */
2499 }
bb467734 2500
46d4e165
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2501 return 0; /* return FAILURE */
2502}
2503
bb467734
MD
2504static
2505int
2506smitest(void)
2507{
2508 int64_t ltsc;
2509 int64_t ntsc;
2510 int64_t ldelta;
2511 int64_t ndelta;
2512 int count;
2513
2514 ldelta = 0;
2515 ndelta = 0;
2516 while (read_apic_timer()) {
2517 ltsc = rdtsc();
2518 for (count = 0; count < 100; ++count)
2519 ntsc = rdtsc(); /* force loop to occur */
2520 if (ldelta) {
2521 ndelta = ntsc - ltsc;
2522 if (ldelta > ndelta)
2523 ldelta = ndelta;
2524 if (ndelta > ldelta * 2)
2525 break;
2526 } else {
2527 ldelta = ntsc - ltsc;
2528 }
2529 }
2530 return(read_apic_timer());
2531}
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2532
2533/*
2534 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2535 *
2536 * If for some reason we were unable to start all cpus we cannot safely
2537 * use broadcast IPIs.
2538 */
2539void
2540smp_invltlb(void)
2541{
2542#ifdef SMP
2543 if (smp_startup_mask == smp_active_mask) {
2544 all_but_self_ipi(XINVLTLB_OFFSET);
2545 } else {
2546 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2547 APIC_DELMODE_FIXED);
2548 }
2549#endif
2550}
2551
2552/*
2553 * When called the executing CPU will send an IPI to all other CPUs
2554 * requesting that they halt execution.
2555 *
2556 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2557 *
2558 * - Signals all CPUs in map to stop.
2559 * - Waits for each to stop.
2560 *
2561 * Returns:
2562 * -1: error
2563 * 0: NA
2564 * 1: ok
2565 *
2566 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2567 * from executing at same time.
2568 */
2569int
2570stop_cpus(u_int map)
2571{
2572 map &= smp_active_mask;
2573
2574 /* send the Xcpustop IPI to all CPUs in map */
2575 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2576
2577 while ((stopped_cpus & map) != map)
2578 /* spin */ ;
2579
2580 return 1;
2581}
2582
2583
2584/*
2585 * Called by a CPU to restart stopped CPUs.
2586 *
2587 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2588 *
2589 * - Signals all CPUs in map to restart.
2590 * - Waits for each to restart.
2591 *
2592 * Returns:
2593 * -1: error
2594 * 0: NA
2595 * 1: ok
2596 */
2597int
2598restart_cpus(u_int map)
2599{
2600 /* signal other cpus to restart */
2601 started_cpus = map & smp_active_mask;
2602
2603 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2604 /* spin */ ;
2605
2606 return 1;
2607}
2608
2609/*
2610 * This is called once the mpboot code has gotten us properly relocated
2611 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2612 * and when it returns the scheduler will call the real cpu_idle() main
2613 * loop for the idlethread. Interrupts are disabled on entry and should
2614 * remain disabled at return.
2615 */
2616void
2617ap_init(void)
2618{
2619 u_int apic_id;
2620
2621 /*
2622 * Adjust smp_startup_mask to signal the BSP that we have started
2623 * up successfully. Note that we do not yet hold the BGL. The BSP
2624 * is waiting for our signal.
2625 *
2626 * We can't set our bit in smp_active_mask yet because we are holding
2627 * interrupts physically disabled and remote cpus could deadlock
2628 * trying to send us an IPI.
2629 */
2630 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2631 cpu_mfence();
2632
2633 /*
2634 * Interlock for finalization. Wait until mp_finish is non-zero,
2635 * then get the MP lock.
2636 *
2637 * Note: We are in a critical section.
2638 *
2639 * Note: We have to synchronize td_mpcount to our desired MP state
2640 * before calling cpu_try_mplock().
2641 *
2642 * Note: we are the idle thread, we can only spin.
2643 *
2644 * Note: The load fence is memory volatile and prevents the compiler
2645 * from improperly caching mp_finish, and the cpu from improperly
2646 * caching it.
2647 */
2648 while (mp_finish == 0)
2649 cpu_lfence();
2650 ++curthread->td_mpcount;
2651 while (cpu_try_mplock() == 0)
2652 ;
2653
2654 if (cpu_feature & CPUID_TSC) {
2655 /*
2656 * The BSP is constantly updating tsc0_offset, figure out the
2657 * relative difference to synchronize ktrdump.
2658 */
2659 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2660 }
2661
2662 /* BSP may have changed PTD while we're waiting for the lock */
2663 cpu_invltlb();
2664
2665#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2666 lidt(&r_idt);
2667#endif
2668
2669 /* Build our map of 'other' CPUs. */
2670 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2671
2672 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2673
2674 /* A quick check from sanity claus */
2675 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2676 if (mycpu->gd_cpuid != apic_id) {
2677 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2678 kprintf("SMP: apic_id = %d\n", apic_id);
2679#if JGXXX
2680 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2681#endif
2682 panic("cpuid mismatch! boom!!");
2683 }
2684
2685 /* Initialize AP's local APIC for irq's */
2686 apic_initialize(FALSE);
2687
2688 /* Set memory range attributes for this CPU to match the BSP */
2689 mem_range_AP_init();
2690
2691 /*
2692 * Once we go active we must process any IPIQ messages that may
2693 * have been queued, because no actual IPI will occur until we
2694 * set our bit in the smp_active_mask. If we don't the IPI
2695 * message interlock could be left set which would also prevent
2696 * further IPIs.
2697 *
2698 * The idle loop doesn't expect the BGL to be held and while
2699 * lwkt_switch() normally cleans things up this is a special case
2700 * because we returning almost directly into the idle loop.
2701 *
2702 * The idle thread is never placed on the runq, make sure
2703 * nothing we've done put it there.
2704 */
2705 KKASSERT(curthread->td_mpcount == 1);
2706 smp_active_mask |= 1 << mycpu->gd_cpuid;
2707
2708 /*
2709 * Enable interrupts here. idle_restore will also do it, but
2710 * doing it here lets us clean up any strays that got posted to
2711 * the CPU during the AP boot while we are still in a critical
2712 * section.
2713 */
2714 __asm __volatile("sti; pause; pause"::);
2715 mdcpu->gd_fpending = 0;
46d4e165
JG
2716
2717 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2718 lwkt_process_ipiq();
2719
2720 /*
2721 * Releasing the mp lock lets the BSP finish up the SMP init
2722 */
2723 rel_mplock();
2724 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2725}
2726
2727/*
2728 * Get SMP fully working before we start initializing devices.
2729 */
2730static
2731void
2732ap_finish(void)
2733{
2734 mp_finish = 1;
2735 if (bootverbose)
2736 kprintf("Finish MP startup\n");
2737 if (cpu_feature & CPUID_TSC)
2738 tsc0_offset = rdtsc();
2739 tsc_offsets[0] = 0;
2740 rel_mplock();
2741 while (smp_active_mask != smp_startup_mask) {
2742 cpu_lfence();
2743 if (cpu_feature & CPUID_TSC)
2744 tsc0_offset = rdtsc();
2745 }
2746 while (try_mplock() == 0)
2747 ;
2748 if (bootverbose)
2749 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2750}
2751
2752SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2753
2754void
2755cpu_send_ipiq(int dcpu)
2756{
2757 if ((1 << dcpu) & smp_active_mask)
2758 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2759}
2760
2761#if 0 /* single_apic_ipi_passive() not working yet */
2762/*
2763 * Returns 0 on failure, 1 on success
2764 */
2765int
2766cpu_send_ipiq_passive(int dcpu)
2767{
2768 int r = 0;
2769 if ((1 << dcpu) & smp_active_mask) {
2770 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2771 APIC_DELMODE_FIXED);
2772 }
2773 return(r);
2774}
2775#endif
2776