i386: Split mpapic.c into lapic.c and ioapic.c
[dragonfly.git] / sys / platform / pc32 / apic / lapic.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
b12a1521 30#include <sys/kernel.h>
23b08e03 31#include <sys/bus.h>
e0918665 32#include <sys/machintr.h>
72740893 33#include <machine/globaldata.h>
984263bc 34#include <machine/smp.h>
90e8a35b 35#include <machine/cputypes.h>
d595a6c0 36#include <machine/md_var.h>
ad52b37b 37#include <machine/pmap.h>
a9295349 38#include <machine_base/apic/mpapic.h>
929c940f 39#include <machine_base/apic/ioapic_abi.h>
984263bc 40#include <machine/segments.h>
96728c05 41#include <sys/thread2.h>
984263bc 42
87cf6827 43#include <machine/intr_machdep.h>
984263bc 44
ad52b37b
SZ
45/* XXX */
46extern pt_entry_t *SMPpt;
47
b52c8db0 48static void lapic_timer_calibrate(void);
086575e9 49static void lapic_timer_set_divisor(int);
a9e511df 50static void lapic_timer_fixup_handler(void *);
76c58571 51static void lapic_timer_restart_handler(void *);
c5b8324c 52
78ea5a2a
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53void lapic_timer_process(void);
54void lapic_timer_process_frame(struct intrframe *);
c5b8324c 55
ef612539 56static int lapic_timer_enable = 1;
c5b8324c 57TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 58
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59static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
60static void lapic_timer_intr_enable(struct cputimer_intr *);
61static void lapic_timer_intr_restart(struct cputimer_intr *);
62static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
63
64static struct cputimer_intr lapic_cputimer_intr = {
65 .freq = 0,
66 .reload = lapic_timer_intr_reload,
67 .enable = lapic_timer_intr_enable,
68 .config = cputimer_intr_default_config,
69 .restart = lapic_timer_intr_restart,
70 .pmfixup = lapic_timer_intr_pmfixup,
71 .initclock = cputimer_intr_default_initclock,
72 .next = SLIST_ENTRY_INITIALIZER,
73 .name = "lapic",
74 .type = CPUTIMER_INTR_LAPIC,
75 .prio = CPUTIMER_INTR_PRIO_LAPIC,
76 .caps = CPUTIMER_INTR_CAP_NONE
77};
78
086575e9
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79static int lapic_timer_divisor_idx = -1;
80static const uint32_t lapic_timer_divisors[] = {
81 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
82 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
83};
c157ff7a 84#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
086575e9 85
984263bc 86/*
d99d4acb 87 * Enable LAPIC, configure interrupts.
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88 */
89void
5ddeabb9 90lapic_init(boolean_t bsp)
984263bc 91{
78ea5a2a 92 uint32_t timer;
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93 u_int temp;
94
9d6bf2df 95 /*
dbfb3a5a
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96 * Install vectors
97 *
98 * Since IDT is shared between BSP and APs, these vectors
99 * only need to be installed once; we do it on BSP.
100 */
101 if (bsp) {
102 /* Install a 'Spurious INTerrupt' vector */
103 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
104 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
105
106 /* Install an inter-CPU IPI for TLB invalidation */
107 setidt(XINVLTLB_OFFSET, Xinvltlb,
108 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
109
110 /* Install an inter-CPU IPI for IPIQ messaging */
111 setidt(XIPIQ_OFFSET, Xipiq,
112 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
113
114 /* Install a timer vector */
115 setidt(XTIMER_OFFSET, Xtimer,
116 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
117
118 /* Install an inter-CPU IPI for CPU stop/restart */
119 setidt(XCPUSTOP_OFFSET, Xcpustop,
120 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
121 }
122
123 /*
d99d4acb 124 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
97359a5b
MD
125 * aggregate interrupt input from the 8259. The INTA cycle
126 * will be routed to the external controller (the 8259) which
127 * is expected to supply the vector.
128 *
129 * Must be setup edge triggered, active high.
130 *
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131 * Disable LINT0 on BSP, if I/O APIC is enabled.
132 *
d99d4acb 133 * Disable LINT0 on the APs. It doesn't matter what delivery
97359a5b 134 * mode we use because we leave it masked.
9d6bf2df 135 */
984263bc 136 temp = lapic.lvt_lint0;
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137 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
138 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
4d08e038 139 if (bsp) {
9d6bf2df 140 temp |= APIC_LVT_DM_EXTINT;
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141 if (apic_io_enable)
142 temp |= APIC_LVT_MASKED;
143 } else {
97359a5b 144 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
4d08e038 145 }
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146 lapic.lvt_lint0 = temp;
147
9d6bf2df 148 /*
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149 * Setup LINT1 as NMI.
150 *
151 * Must be setup edge trigger, active high.
152 *
153 * Enable LINT1 on BSP, if I/O APIC is enabled.
154 *
155 * Disable LINT1 on the APs.
9d6bf2df 156 */
984263bc 157 temp = lapic.lvt_lint1;
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158 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
159 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
160 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
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161 if (bsp && apic_io_enable)
162 temp &= ~APIC_LVT_MASKED;
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163 lapic.lvt_lint1 = temp;
164
d9eea1a5 165 /*
d99d4acb 166 * Mask the LAPIC error interrupt, LAPIC performance counter
78ea5a2a 167 * interrupt.
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168 */
169 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
170 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
78ea5a2a 171
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172 /*
173 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
174 */
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175 timer = lapic.lvt_timer;
176 timer &= ~APIC_LVTT_VECTOR;
177 timer |= XTIMER_OFFSET;
178 timer |= APIC_LVTT_MASKED;
179 lapic.lvt_timer = timer;
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180
181 /*
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182 * Set the Task Priority Register as needed. At the moment allow
183 * interrupts on all cpus (the APs will remain CLId until they are
184 * ready to deal). We could disable all but IPIs by setting
84bf7d5a 185 * temp |= TPR_IPI for cpu != 0.
d9eea1a5 186 */
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187 temp = lapic.tpr;
188 temp &= ~APIC_TPR_PRIO; /* clear priority field */
30c5f287
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189#ifdef SMP /* APIC-IO */
190if (!apic_io_enable) {
191#endif
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192 /*
193 * If we are NOT running the IO APICs, the LAPIC will only be used
194 * for IPIs. Set the TPR to prevent any unintentional interrupts.
195 */
84bf7d5a 196 temp |= TPR_IPI;
30c5f287
MN
197#ifdef SMP /* APIC-IO */
198}
97359a5b 199#endif
8a8d5d85 200
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201 lapic.tpr = temp;
202
97359a5b 203 /*
d99d4acb 204 * Enable the LAPIC
97359a5b 205 */
984263bc 206 temp = lapic.svr;
d99d4acb 207 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
97359a5b 208 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 209
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210 /*
211 * Set the spurious interrupt vector. The low 4 bits of the vector
212 * must be 1111.
213 */
214 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 215 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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216 temp &= ~APIC_SVR_VECTOR;
217 temp |= XSPURIOUSINT_OFFSET;
984263bc 218
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219 lapic.svr = temp;
220
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221 /*
222 * Pump out a few EOIs to clean out interrupts that got through
223 * before we were able to set the TPR.
224 */
225 lapic.eoi = 0;
226 lapic.eoi = 0;
227 lapic.eoi = 0;
228
c5b8324c 229 if (bsp) {
b52c8db0 230 lapic_timer_calibrate();
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231 if (lapic_timer_enable) {
232 cputimer_intr_register(&lapic_cputimer_intr);
233 cputimer_intr_select(&lapic_cputimer_intr, 0);
234 }
c5b8324c 235 } else {
086575e9 236 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 237 }
b52c8db0 238
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239 if (bootverbose)
240 apic_dump("apic_initialize()");
241}
242
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243static void
244lapic_timer_set_divisor(int divisor_idx)
245{
246 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
247 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
248}
249
250static void
251lapic_timer_oneshot(u_int count)
252{
253 uint32_t value;
254
255 value = lapic.lvt_timer;
256 value &= ~APIC_LVTT_PERIODIC;
257 lapic.lvt_timer = value;
258 lapic.icr_timer = count;
259}
260
261static void
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262lapic_timer_oneshot_quick(u_int count)
263{
264 lapic.icr_timer = count;
265}
266
267static void
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268lapic_timer_calibrate(void)
269{
47bdf646 270 sysclock_t value;
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271
272 /* Try to calibrate the local APIC timer. */
273 for (lapic_timer_divisor_idx = 0;
274 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
275 lapic_timer_divisor_idx++) {
276 lapic_timer_set_divisor(lapic_timer_divisor_idx);
277 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
278 DELAY(2000000);
279 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
280 if (value != APIC_TIMER_MAX_COUNT)
281 break;
282 }
283 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
284 panic("lapic: no proper timer divisor?!\n");
ef612539 285 lapic_cputimer_intr.freq = value / 2;
b52c8db0 286
47bdf646 287 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 288 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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289}
290
c5b8324c
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291static void
292lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
293{
294 sysclock_t count;
295
296 gd->gd_timer_running = 0;
297
298 count = sys_cputimer->count();
299 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
300 systimer_intr(&count, 0, frame);
301}
302
78ea5a2a
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303void
304lapic_timer_process(void)
305{
ae48d6cd 306 lapic_timer_process_oncpu(mycpu, NULL);
78ea5a2a
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307}
308
309void
310lapic_timer_process_frame(struct intrframe *frame)
311{
ae48d6cd 312 lapic_timer_process_oncpu(mycpu, frame);
b12a1521
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313}
314
c5b8324c 315static void
ef612539 316lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
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317{
318 struct globaldata *gd = mycpu;
319
ef612539 320 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
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321 if (reload < 2)
322 reload = 2;
323
324 if (gd->gd_timer_running) {
325 if (reload < lapic.ccr_timer)
326 lapic_timer_oneshot_quick(reload);
327 } else {
328 gd->gd_timer_running = 1;
329 lapic_timer_oneshot_quick(reload);
330 }
331}
332
ef612539
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333static void
334lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
6198c499
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335{
336 uint32_t timer;
337
338 timer = lapic.lvt_timer;
339 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
340 lapic.lvt_timer = timer;
a9e511df
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341
342 lapic_timer_fixup_handler(NULL);
343}
344
345static void
76c58571 346lapic_timer_fixup_handler(void *arg)
a9e511df 347{
76c58571
SZ
348 int *started = arg;
349
350 if (started != NULL)
351 *started = 0;
352
90e8a35b 353 if (cpu_vendor_id == CPU_VENDOR_AMD) {
a9e511df
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354 /*
355 * Detect the presence of C1E capability mostly on latest
356 * dual-cores (or future) k8 family. This feature renders
357 * the local APIC timer dead, so we disable it by reading
358 * the Interrupt Pending Message register and clearing both
359 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
360 *
361 * Reference:
362 * "BIOS and Kernel Developer's Guide for AMD NPT
363 * Family 0Fh Processors"
364 * #32559 revision 3.00
365 */
366 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
367 (cpu_id & 0x0fff0000) >= 0x00040000) {
368 uint64_t msr;
369
370 msr = rdmsr(0xc0010055);
371 if (msr & 0x18000000) {
372 struct globaldata *gd = mycpu;
373
374 kprintf("cpu%d: AMD C1E detected\n",
375 gd->gd_cpuid);
376 wrmsr(0xc0010055, msr & ~0x18000000ULL);
377
378 /*
379 * We are kinda stalled;
380 * kick start again.
381 */
382 gd->gd_timer_running = 1;
383 lapic_timer_oneshot_quick(2);
76c58571
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384
385 if (started != NULL)
386 *started = 1;
a9e511df
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387 }
388 }
389 }
390}
391
76c58571
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392static void
393lapic_timer_restart_handler(void *dummy __unused)
394{
395 int started;
396
397 lapic_timer_fixup_handler(&started);
398 if (!started) {
399 struct globaldata *gd = mycpu;
400
401 gd->gd_timer_running = 1;
402 lapic_timer_oneshot_quick(2);
403 }
404}
405
a9e511df
SZ
406/*
407 * This function is called only by ACPI-CA code currently:
408 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
409 * module controls PM. So once ACPI-CA is attached, we try
410 * to apply the fixup to prevent LAPIC timer from hanging.
411 */
ef612539
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412static void
413lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 414{
ef612539
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415 lwkt_send_ipiq_mask(smp_active_mask,
416 lapic_timer_fixup_handler, NULL);
6198c499
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417}
418
ef612539
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419static void
420lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 421{
76c58571
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422 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
423}
424
b52c8db0 425
984263bc
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426/*
427 * dump contents of local APIC registers
428 */
429void
430apic_dump(char* str)
431{
26be20a0
SW
432 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
433 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
984263bc
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434 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
435}
436
984263bc
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437/*
438 * Inter Processor Interrupt functions.
439 */
440
984263bc
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441/*
442 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
443 *
444 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
445 * vector is any valid SYSTEM INT vector
446 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
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447 *
448 * A backlog of requests can create a deadlock between cpus. To avoid this
449 * we have to be able to accept IPIs at the same time we are trying to send
450 * them. The critical section prevents us from attempting to send additional
451 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
452 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
453 * to occur but fortunately it does not happen too often.
984263bc 454 */
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455int
456apic_ipi(int dest_type, int vector, int delivery_mode)
457{
458 u_long icr_lo;
459
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460 crit_enter();
461 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
462 unsigned int eflags = read_eflags();
463 cpu_enable_intr();
cfaeae2a 464 DEBUG_PUSH_INFO("apic_ipi");
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465 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
466 lwkt_process_ipiq();
467 }
cfaeae2a 468 DEBUG_POP_INFO();
96728c05 469 write_eflags(eflags);
984263bc 470 }
984263bc 471
9d6bf2df 472 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 473 delivery_mode | vector;
984263bc 474 lapic.icr_lo = icr_lo;
96728c05 475 crit_exit();
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476 return 0;
477}
478
41a01a4d
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479void
480single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
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481{
482 u_long icr_lo;
483 u_long icr_hi;
984263bc 484
41a01a4d 485 crit_enter();
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486 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
487 unsigned int eflags = read_eflags();
488 cpu_enable_intr();
cfaeae2a 489 DEBUG_PUSH_INFO("single_apic_ipi");
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490 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
491 lwkt_process_ipiq();
492 }
cfaeae2a 493 DEBUG_POP_INFO();
96728c05 494 write_eflags(eflags);
984263bc 495 }
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496 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
497 icr_hi |= (CPU_TO_ID(cpu) << 24);
498 lapic.icr_hi = icr_hi;
499
b2f93ae9 500 /* build ICR_LOW */
9d6bf2df 501 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
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502 | APIC_DEST_DESTFLD | delivery_mode | vector;
503
504 /* write APIC ICR */
505 lapic.icr_lo = icr_lo;
41a01a4d 506 crit_exit();
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507}
508
41a01a4d
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509#if 0
510
511/*
512 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
513 *
514 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
515 * to the target, and the scheduler does not 'poll' for IPI messages.
516 */
517int
518single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
519{
520 u_long icr_lo;
521 u_long icr_hi;
522
523 crit_enter();
524 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
525 crit_exit();
526 return(0);
527 }
528 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
529 icr_hi |= (CPU_TO_ID(cpu) << 24);
530 lapic.icr_hi = icr_hi;
531
532 /* build IRC_LOW */
533 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
534 | APIC_DEST_DESTFLD | delivery_mode | vector;
535
536 /* write APIC ICR */
537 lapic.icr_lo = icr_lo;
538 crit_exit();
539 return(1);
540}
541
542#endif
543
984263bc
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544/*
545 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
546 *
96728c05
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547 * target is a bitmask of destination cpus. Vector is any
548 * valid system INT vector. Delivery mode may be either
549 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 550 */
41a01a4d 551void
da23a592 552selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
984263bc 553{
96728c05
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554 crit_enter();
555 while (target) {
da23a592
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556 int n = BSFCPUMASK(target);
557 target &= ~CPUMASK(n);
41a01a4d 558 single_apic_ipi(n, vector, delivery_mode);
96728c05
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559 }
560 crit_exit();
984263bc 561}
984263bc 562
984263bc
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563/*
564 * Timer code, in development...
565 * - suggested by rgrimes@gndrsh.aac.dev.com
566 */
bb467734
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567int
568get_apic_timer_frequency(void)
569{
570 return(lapic_cputimer_intr.freq);
571}
984263bc 572
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573/*
574 * Load a 'downcount time' in uSeconds.
575 */
576void
2942ed63 577set_apic_timer(int us)
984263bc 578{
2942ed63 579 u_int count;
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580
581 /*
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582 * When we reach here, lapic timer's frequency
583 * must have been calculated as well as the
584 * divisor (lapic.dcr_timer is setup during the
585 * divisor calculation).
984263bc 586 */
ef612539 587 KKASSERT(lapic_cputimer_intr.freq != 0 &&
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588 lapic_timer_divisor_idx >= 0);
589
ef612539 590 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 591 lapic_timer_oneshot(count);
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592}
593
594
595/*
596 * Read remaining time in timer.
597 */
598int
599read_apic_timer(void)
600{
601#if 0
602 /** XXX FIXME: we need to return the actual remaining time,
603 * for now we just return the remaining count.
604 */
605#else
606 return lapic.ccr_timer;
607#endif
608}
609
610
611/*
612 * Spin-style delay, set delay time in uS, spin till it drains.
613 */
614void
615u_sleep(int count)
616{
617 set_apic_timer(count);
618 while (read_apic_timer())
619 /* spin */ ;
620}
ad52b37b 621
11bae9b8 622int
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623lapic_unused_apic_id(int start)
624{
625 int i;
626
627 for (i = start; i < NAPICID; ++i) {
628 if (ID_TO_CPU(i) == -1)
629 return i;
630 }
631 return NAPICID;
632}
633
ad52b37b 634void
84cc808b 635lapic_map(vm_offset_t lapic_addr)
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636{
637 /* Local apic is mapped on last page */
638 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
639 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
640
d557216f 641 kprintf("lapic: at %p\n", (void *)lapic_addr);
ad52b37b 642}
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643
644static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
645 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
646
647void
648lapic_config(void)
649{
650 struct lapic_enumerator *e;
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651 int error, i;
652
653 for (i = 0; i < NAPICID; ++i)
654 ID_TO_CPU(i) = -1;
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655
656 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
657 error = e->lapic_probe(e);
658 if (!error)
659 break;
660 }
661 if (e == NULL)
662 panic("can't config lapic\n");
663
664 e->lapic_enumerate(e);
665}
666
667void
668lapic_enumerator_register(struct lapic_enumerator *ne)
669{
670 struct lapic_enumerator *e;
671
672 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
673 if (e->lapic_prio < ne->lapic_prio) {
674 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
675 return;
676 }
677 }
678 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
679}