AHCI - Intel fixes, error processing fixes.
[dragonfly.git] / sys / dev / disk / ahci / ahci.c
CommitLineData
258223a3
MD
1/*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 *
17 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
18 *
19 * This code is derived from software contributed to The DragonFly Project
20 * by Matthew Dillon <dillon@backplane.com>
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * 2. Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * 3. Neither the name of The DragonFly Project nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific, prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
39 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
40 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
41 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
46 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * SUCH DAMAGE.
48 *
49 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
50 */
51
52#include "ahci.h"
53
f4553de1 54void ahci_port_interrupt_enable(struct ahci_port *ap);
258223a3
MD
55
56int ahci_load_prdt(struct ahci_ccb *);
57void ahci_unload_prdt(struct ahci_ccb *);
58static void ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs,
59 int nsegs, int error);
258223a3 60void ahci_start(struct ahci_ccb *);
17eab71e 61int ahci_port_softreset(struct ahci_port *ap);
1980eff3 62int ahci_port_hardreset(struct ahci_port *ap, int hard);
cf5f3a81 63void ahci_port_hardstop(struct ahci_port *ap);
258223a3 64
831bc9e3 65static void ahci_ata_cmd_timeout_unserialized(void *);
831bc9e3 66void ahci_check_active_timeouts(struct ahci_port *ap);
258223a3 67
831bc9e3
MD
68void ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at);
69void ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at);
4c339a5f
MD
70void ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb);
71void ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t mask);
258223a3 72
12feb904 73int ahci_port_read_ncq_error(struct ahci_port *, int);
258223a3
MD
74
75struct ahci_dmamem *ahci_dmamem_alloc(struct ahci_softc *, bus_dma_tag_t tag);
76void ahci_dmamem_free(struct ahci_softc *, struct ahci_dmamem *);
77static void ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error);
78
12feb904
MD
79static void ahci_dummy_done(struct ata_xfer *xa);
80static void ahci_empty_done(struct ahci_ccb *ccb);
81static void ahci_ata_cmd_done(struct ahci_ccb *ccb);
258223a3 82
fd8bd957
MD
83/*
84 * Initialize the global AHCI hardware. This code does not set up any of
85 * its ports.
86 */
258223a3
MD
87int
88ahci_init(struct ahci_softc *sc)
89{
12feb904 90 u_int32_t cap, pi, pleft;
831bc9e3
MD
91 int i;
92 struct ahci_port *ap;
258223a3
MD
93
94 DPRINTF(AHCI_D_VERBOSE, " GHC 0x%b",
95 ahci_read(sc, AHCI_REG_GHC), AHCI_FMT_GHC);
96
97 /* save BIOS initialised parameters, enable staggered spin up */
98 cap = ahci_read(sc, AHCI_REG_CAP);
99 cap &= AHCI_REG_CAP_SMPS;
100 cap |= AHCI_REG_CAP_SSS;
101 pi = ahci_read(sc, AHCI_REG_PI);
102
831bc9e3
MD
103 /*
104 * This is a hack that currently does not appear to have
105 * a significant effect, but I noticed the port registers
106 * do not appear to be completely cleared after the host
107 * controller is reset.
12feb904
MD
108 *
109 * Use a temporary ap structure so we can call ahci_pwrite().
831bc9e3
MD
110 */
111 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO);
112 ap->ap_sc = sc;
12feb904
MD
113 pleft = pi;
114 for (i = 0; i < AHCI_MAX_PORTS; ++i) {
115 if (pleft == 0)
116 break;
831bc9e3
MD
117 if ((pi & (1 << i)) == 0)
118 continue;
119 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
120 AHCI_PORT_REGION(i), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) {
121 device_printf(sc->sc_dev, "can't map port\n");
122 return (1);
123 }
124 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED |
125 AHCI_PREG_SCTL_DET_DISABLE);
126 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
127 ahci_pwrite(ap, AHCI_PREG_IE, 0);
12feb904 128 ahci_write(ap->ap_sc, AHCI_REG_IS, 1 << i);
831bc9e3 129 ahci_pwrite(ap, AHCI_PREG_CMD, 0);
12feb904
MD
130 ahci_pwrite(ap, AHCI_PREG_IS, -1);
131 sc->sc_portmask |= (1 << i);
132 pleft &= ~(1 << i);
831bc9e3 133 }
12feb904 134 sc->sc_numports = i;
831bc9e3 135 kfree(ap, M_DEVBUF);
831bc9e3 136
17eab71e
MD
137 /*
138 * Unconditionally reset the controller, do not conditionalize on
139 * trying to figure it if it was previously active or not.
831bc9e3
MD
140 *
141 * NOTE BRICKS (1)
142 *
143 * If you have a port multiplier and it does not have a device
144 * in target 0, and it probes normally, but a later operation
145 * mis-probes a target behind that PM, it is possible for the
146 * port to brick such that only (a) a power cycle of the host
147 * or (b) placing a device in target 0 will fix the problem.
148 * Power cycling the PM has no effect (it works fine on another
149 * host port). This issue is unrelated to CLO.
17eab71e
MD
150 */
151 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_HR);
831bc9e3
MD
152 if (ahci_wait_ne(sc, AHCI_REG_GHC,
153 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) {
17eab71e
MD
154 device_printf(sc->sc_dev,
155 "unable to reset controller\n");
156 return (1);
258223a3 157 }
831bc9e3 158 ahci_os_sleep(100);
258223a3
MD
159
160 /* enable ahci (global interrupts disabled) */
161 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE);
162
163 /* restore parameters */
164 ahci_write(sc, AHCI_REG_CAP, cap);
165 ahci_write(sc, AHCI_REG_PI, pi);
166
167 return (0);
168}
169
fd8bd957
MD
170/*
171 * Allocate and initialize an AHCI port.
172 */
258223a3
MD
173int
174ahci_port_alloc(struct ahci_softc *sc, u_int port)
175{
1980eff3
MD
176 struct ahci_port *ap;
177 struct ata_port *at;
178 struct ahci_ccb *ccb;
179 u_int64_t dva;
180 u_int32_t cmd;
12feb904 181 u_int32_t data;
1980eff3
MD
182 struct ahci_cmd_hdr *hdr;
183 struct ahci_cmd_table *table;
258223a3
MD
184 int rc = ENOMEM;
185 int error;
186 int i;
187
188 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO);
12feb904 189 ap->ap_err_scratch = kmalloc(512, M_DEVBUF, M_WAITOK | M_ZERO);
258223a3
MD
190
191 ksnprintf(ap->ap_name, sizeof(ap->ap_name), "%s%d.%d",
192 device_get_name(sc->sc_dev),
193 device_get_unit(sc->sc_dev),
194 port);
195 sc->sc_ports[port] = ap;
196
1980eff3
MD
197 /*
198 * Allocate enough so we never have to reallocate, it makes
199 * it easier.
200 *
201 * ap_pmcount will be reduced by the scan if we encounter the
202 * port multiplier port prior to target 15.
203 */
204 if (ap->ap_ata == NULL) {
205 ap->ap_ata = kmalloc(sizeof(*ap->ap_ata) * AHCI_MAX_PMPORTS,
206 M_DEVBUF, M_INTWAIT | M_ZERO);
207 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) {
208 at = &ap->ap_ata[i];
209 at->at_ahci_port = ap;
210 at->at_target = i;
3209f581 211 at->at_probe = ATA_PROBE_NEED_INIT;
831bc9e3 212 at->at_features |= ATA_PORT_F_RESCAN;
1980eff3
MD
213 ksnprintf(at->at_name, sizeof(at->at_name),
214 "%s.%d", ap->ap_name, i);
215 }
216 }
258223a3
MD
217 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
218 AHCI_PORT_REGION(port), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) {
219 device_printf(sc->sc_dev,
220 "unable to create register window for port %d\n",
221 port);
222 goto freeport;
223 }
224
225 ap->ap_sc = sc;
226 ap->ap_num = port;
3209f581 227 ap->ap_probe = ATA_PROBE_NEED_INIT;
258223a3
MD
228 TAILQ_INIT(&ap->ap_ccb_free);
229 TAILQ_INIT(&ap->ap_ccb_pending);
230 lockinit(&ap->ap_ccb_lock, "ahcipo", 0, 0);
231
232 /* Disable port interrupts */
233 ahci_pwrite(ap, AHCI_PREG_IE, 0);
831bc9e3 234 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
258223a3 235
17eab71e
MD
236 /*
237 * Sec 10.1.2 - deinitialise port if it is already running
238 */
258223a3
MD
239 cmd = ahci_pread(ap, AHCI_PREG_CMD);
240 if ((cmd & (AHCI_PREG_CMD_ST | AHCI_PREG_CMD_CR |
17eab71e 241 AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_FR)) ||
258223a3
MD
242 (ahci_pread(ap, AHCI_PREG_SCTL) & AHCI_PREG_SCTL_DET)) {
243 int r;
244
245 r = ahci_port_stop(ap, 1);
246 if (r) {
247 device_printf(sc->sc_dev,
248 "unable to disable %s, ignoring port %d\n",
249 ((r == 2) ? "CR" : "FR"), port);
250 rc = ENXIO;
251 goto freeport;
252 }
253
254 /* Write DET to zero */
cf5f3a81 255 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
258223a3
MD
256 }
257
258 /* Allocate RFIS */
259 ap->ap_dmamem_rfis = ahci_dmamem_alloc(sc, sc->sc_tag_rfis);
260 if (ap->ap_dmamem_rfis == NULL) {
cf5f3a81 261 kprintf("%s: NORFIS\n", PORTNAME(ap));
258223a3
MD
262 goto nomem;
263 }
264
265 /* Setup RFIS base address */
266 ap->ap_rfis = (struct ahci_rfis *) AHCI_DMA_KVA(ap->ap_dmamem_rfis);
267 dva = AHCI_DMA_DVA(ap->ap_dmamem_rfis);
268 ahci_pwrite(ap, AHCI_PREG_FBU, (u_int32_t)(dva >> 32));
269 ahci_pwrite(ap, AHCI_PREG_FB, (u_int32_t)dva);
270
831bc9e3
MD
271 /* Clear SERR before starting FIS reception or ST or anything */
272 ahci_flush_tfd(ap);
273 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
274
258223a3
MD
275 /* Enable FIS reception and activate port. */
276 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1980eff3 277 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA);
258223a3
MD
278 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD | AHCI_PREG_CMD_SUD;
279 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE);
280
281 /* Check whether port activated. Skip it if not. */
282 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
283 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
cf5f3a81 284 kprintf("%s: NOT-ACTIVATED\n", PORTNAME(ap));
258223a3
MD
285 rc = ENXIO;
286 goto freeport;
287 }
288
289 /* Allocate a CCB for each command slot */
290 ap->ap_ccbs = kmalloc(sizeof(struct ahci_ccb) * sc->sc_ncmds, M_DEVBUF,
291 M_WAITOK | M_ZERO);
292 if (ap->ap_ccbs == NULL) {
293 device_printf(sc->sc_dev,
294 "unable to allocate command list for port %d\n",
295 port);
296 goto freeport;
297 }
298
299 /* Command List Structures and Command Tables */
300 ap->ap_dmamem_cmd_list = ahci_dmamem_alloc(sc, sc->sc_tag_cmdh);
301 ap->ap_dmamem_cmd_table = ahci_dmamem_alloc(sc, sc->sc_tag_cmdt);
302 if (ap->ap_dmamem_cmd_table == NULL ||
303 ap->ap_dmamem_cmd_list == NULL) {
304nomem:
305 device_printf(sc->sc_dev,
306 "unable to allocate DMA memory for port %d\n",
307 port);
308 goto freeport;
309 }
310
311 /* Setup command list base address */
312 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_list);
313 ahci_pwrite(ap, AHCI_PREG_CLBU, (u_int32_t)(dva >> 32));
314 ahci_pwrite(ap, AHCI_PREG_CLB, (u_int32_t)dva);
315
316 /* Split CCB allocation into CCBs and assign to command header/table */
317 hdr = AHCI_DMA_KVA(ap->ap_dmamem_cmd_list);
318 table = AHCI_DMA_KVA(ap->ap_dmamem_cmd_table);
319 for (i = 0; i < sc->sc_ncmds; i++) {
320 ccb = &ap->ap_ccbs[i];
321
322 error = bus_dmamap_create(sc->sc_tag_data, BUS_DMA_ALLOCNOW,
323 &ccb->ccb_dmamap);
324 if (error) {
325 device_printf(sc->sc_dev,
326 "unable to create dmamap for port %d "
327 "ccb %d\n", port, i);
328 goto freeport;
329 }
330
331 callout_init(&ccb->ccb_timeout);
332 ccb->ccb_slot = i;
333 ccb->ccb_port = ap;
334 ccb->ccb_cmd_hdr = &hdr[i];
335 ccb->ccb_cmd_table = &table[i];
336 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_table) +
337 ccb->ccb_slot * sizeof(struct ahci_cmd_table);
338 ccb->ccb_cmd_hdr->ctba_hi = htole32((u_int32_t)(dva >> 32));
339 ccb->ccb_cmd_hdr->ctba_lo = htole32((u_int32_t)dva);
340
341 ccb->ccb_xa.fis =
342 (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis;
343 ccb->ccb_xa.packetcmd = ccb->ccb_cmd_table->acmd;
344 ccb->ccb_xa.tag = i;
345
258223a3 346 ccb->ccb_xa.state = ATA_S_COMPLETE;
1067474a
MD
347
348 /*
349 * CCB[1] is the error CCB and is not get or put. It is
350 * also used for probing. Numerous HBAs only load the
351 * signature from CCB[1] so it MUST be used for the second
352 * FIS.
353 */
354 if (i == 1)
355 ap->ap_err_ccb = ccb;
356 else
357 ahci_put_ccb(ccb);
258223a3
MD
358 }
359
12feb904
MD
360 /*
361 * Wait for ICC change to complete
362 */
258223a3
MD
363 ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_ICC);
364
fd8bd957 365 /*
12feb904
MD
366 * Calculate the interrupt mask
367 */
368 data = AHCI_PREG_IE_TFEE | AHCI_PREG_IE_HBFE |
369 AHCI_PREG_IE_IFE | AHCI_PREG_IE_OFE |
370 AHCI_PREG_IE_DPE | AHCI_PREG_IE_UFE |
371 AHCI_PREG_IE_PCE | AHCI_PREG_IE_PRCE |
372 AHCI_PREG_IE_DHRE | AHCI_PREG_IE_SDBE;
373 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
374 data |= AHCI_PREG_IE_IPME;
375#ifdef AHCI_COALESCE
376 if (sc->sc_ccc_ports & (1 << port)
377 data &= ~(AHCI_PREG_IE_SDBE | AHCI_PREG_IE_DHRE);
378#endif
379 ap->ap_intmask = data;
380
381 /*
f4553de1
MD
382 * Start the port. The helper thread will call ahci_port_init()
383 * so the ports can all be started in parallel. A failure by
384 * ahci_port_init() does not deallocate the port since we still
385 * want hot-plug events.
fd8bd957 386 */
f4553de1 387 ahci_os_start_port(ap);
fd8bd957
MD
388 return(0);
389freeport:
390 ahci_port_free(sc, port);
fd8bd957
MD
391 return (rc);
392}
393
394/*
395 * [re]initialize an idle port. No CCBs should be active.
396 *
397 * This function is called during the initial port allocation sequence
398 * and is also called on hot-plug insertion. We take no chances and
399 * use a portreset instead of a softreset.
400 *
22181ab7
MD
401 * This function is the only way to move a failed port back to active
402 * status.
403 *
fd8bd957
MD
404 * Returns 0 if a device is successfully detected.
405 */
406int
12feb904 407ahci_port_init(struct ahci_port *ap)
fd8bd957 408{
fd8bd957 409 /*
12feb904 410 * Register [re]initialization
fd8bd957 411 */
12feb904 412 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
1980eff3 413 ahci_pwrite(ap, AHCI_PREG_SNTF, -1);
12feb904
MD
414 ap->ap_probe = ATA_PROBE_NEED_HARD_RESET;
415 ap->ap_pmcount = 0;
416 ahci_port_interrupt_enable(ap);
417 return (0);
258223a3
MD
418}
419
fd8bd957 420/*
f4553de1
MD
421 * Enable or re-enable interrupts on a port.
422 *
423 * This routine is called from the port initialization code or from the
424 * helper thread as the real interrupt may be forced to turn off certain
425 * interrupt sources.
426 */
427void
428ahci_port_interrupt_enable(struct ahci_port *ap)
429{
12feb904 430 ahci_pwrite(ap, AHCI_PREG_IE, ap->ap_intmask);
f4553de1
MD
431}
432
433/*
3209f581
MD
434 * Run the port / target state machine from a main context.
435 *
436 * The state machine for the port is always run.
437 *
438 * If atx is non-NULL run the state machine for a particular target.
439 * If atx is NULL run the state machine for all targets.
440 */
441void
831bc9e3 442ahci_port_state_machine(struct ahci_port *ap, int initial)
3209f581
MD
443{
444 struct ata_port *at;
445 u_int32_t data;
446 int target;
447 int didsleep;
831bc9e3 448 int loop;
3209f581 449
831bc9e3
MD
450 /*
451 * State machine for port. Note that CAM is not yet associated
452 * during the initial parallel probe and the port's probe state
453 * will not get past ATA_PROBE_NEED_IDENT.
454 */
c408a8b3 455 {
1067474a
MD
456 if (initial == 0 && ap->ap_probe <= ATA_PROBE_NEED_HARD_RESET) {
457 kprintf("%s: Waiting 10 seconds on insertion\n",
458 PORTNAME(ap));
459 ahci_os_sleep(10000);
460 initial = 1;
3209f581 461 }
1067474a 462 if (ap->ap_probe == ATA_PROBE_NEED_INIT)
12feb904 463 ahci_port_init(ap);
3209f581
MD
464 if (ap->ap_probe == ATA_PROBE_NEED_HARD_RESET)
465 ahci_port_reset(ap, NULL, 1);
466 if (ap->ap_probe == ATA_PROBE_NEED_SOFT_RESET)
467 ahci_port_reset(ap, NULL, 0);
468 if (ap->ap_probe == ATA_PROBE_NEED_IDENT)
469 ahci_cam_probe(ap, NULL);
470 }
471 if (ap->ap_type != ATA_PORT_T_PM) {
472 if (ap->ap_probe == ATA_PROBE_FAILED) {
473 ahci_cam_changed(ap, NULL, 0);
f4553de1 474 } else if (ap->ap_probe >= ATA_PROBE_NEED_IDENT) {
3209f581
MD
475 ahci_cam_changed(ap, NULL, 1);
476 }
477 return;
478 }
479
831bc9e3
MD
480 /*
481 * Port Multiplier state machine.
482 *
483 * Get a mask of changed targets and combine with any runnable
484 * states already present.
485 */
486 for (loop = 0; ;++loop) {
2cc2e845 487 if (ahci_pm_read(ap, 15, SATA_PMREG_EINFO, &data)) {
3209f581
MD
488 kprintf("%s: PM unable to read hot-plug bitmap\n",
489 PORTNAME(ap));
490 break;
491 }
3209f581
MD
492
493 /*
831bc9e3
MD
494 * Do at least one loop, then stop if no more state changes
495 * have occured. The PM might not generate a new
496 * notification until we clear the entire bitmap.
3209f581 497 */
831bc9e3 498 if (loop && data == 0)
3209f581
MD
499 break;
500
501 /*
502 * New devices showing up in the bitmap require some spin-up
503 * time before we start probing them. Reset didsleep. The
504 * first new device we detect will sleep before probing.
831bc9e3
MD
505 *
506 * This only applies to devices whos change bit is set in
507 * the data, and does not apply to the initial boot-time
508 * probe.
3209f581
MD
509 */
510 didsleep = 0;
511
512 for (target = 0; target < ap->ap_pmcount; ++target) {
513 at = &ap->ap_ata[target];
514
515 /*
516 * Check the target state for targets behind the PM
517 * which have changed state. This will adjust
518 * at_probe and set ATA_PORT_F_RESCAN
519 *
1067474a 520 * We want to wait at least 10 seconds before probing
3209f581
MD
521 * a newly inserted device. If the check status
522 * indicates a device is present and in need of a
523 * hard reset, we make sure we have slept before
524 * continuing.
831bc9e3 525 *
1067474a
MD
526 * We also need to wait at least 1 second for the
527 * PHY state to change after insertion, if we
528 * haven't already waited the 10 seconds.
529 *
831bc9e3
MD
530 * NOTE: When pm_check_good finds a good port it
531 * typically starts us in probe state
532 * NEED_HARD_RESET rather than INIT.
3209f581
MD
533 */
534 if (data & (1 << target)) {
1067474a
MD
535 if (initial == 0 && didsleep == 0)
536 ahci_os_sleep(1000);
3209f581 537 ahci_pm_check_good(ap, target);
831bc9e3
MD
538 if (initial == 0 && didsleep == 0 &&
539 at->at_probe <= ATA_PROBE_NEED_HARD_RESET
540 ) {
541 didsleep = 1;
121d8e75
MD
542 kprintf("%s: Waiting 10 seconds on insertion\n", PORTNAME(ap));
543 ahci_os_sleep(10000);
831bc9e3
MD
544 }
545 }
546
547 /*
548 * Report hot-plug events before the probe state
549 * really gets hot. Only actual events are reported
550 * here to reduce spew.
551 */
552 if (data & (1 << target)) {
553 kprintf("%s: HOTPLUG (PM) - ", ATANAME(ap, at));
554 switch(at->at_probe) {
555 case ATA_PROBE_NEED_INIT:
556 case ATA_PROBE_NEED_HARD_RESET:
557 kprintf("Device inserted\n");
558 break;
559 case ATA_PROBE_FAILED:
560 kprintf("Device removed\n");
561 break;
562 default:
563 kprintf("Device probe in progress\n");
564 break;
3209f581
MD
565 }
566 }
567
568 /*
831bc9e3
MD
569 * Run through the state machine as necessary if
570 * the port is not marked failed.
571 *
572 * The state machine may stop at NEED_IDENT if
573 * CAM is not yet attached.
574 *
575 * Acquire exclusive access to the port while we
576 * are doing this. This prevents command-completion
577 * from queueing commands for non-polled targets
578 * inbetween our probe steps. We need to do this
579 * because the reset probes can generate severe PHY
580 * and protocol errors and soft-brick the port.
3209f581 581 */
831bc9e3
MD
582 if (at->at_probe != ATA_PROBE_FAILED &&
583 at->at_probe != ATA_PROBE_GOOD) {
584 ahci_beg_exclusive_access(ap, at);
3209f581 585 if (at->at_probe == ATA_PROBE_NEED_INIT)
12feb904 586 ahci_pm_port_init(ap, at);
3209f581
MD
587 if (at->at_probe == ATA_PROBE_NEED_HARD_RESET)
588 ahci_port_reset(ap, at, 1);
589 if (at->at_probe == ATA_PROBE_NEED_SOFT_RESET)
590 ahci_port_reset(ap, at, 0);
591 if (at->at_probe == ATA_PROBE_NEED_IDENT)
592 ahci_cam_probe(ap, at);
831bc9e3 593 ahci_end_exclusive_access(ap, at);
3209f581
MD
594 }
595
596 /*
831bc9e3 597 * Add or remove from CAM
3209f581
MD
598 */
599 if (at->at_features & ATA_PORT_F_RESCAN) {
600 at->at_features &= ~ATA_PORT_F_RESCAN;
601 if (at->at_probe == ATA_PROBE_FAILED) {
602 ahci_cam_changed(ap, at, 0);
f4553de1 603 } else if (at->at_probe >= ATA_PROBE_NEED_IDENT) {
3209f581
MD
604 ahci_cam_changed(ap, at, 1);
605 }
606 }
3560ed94
MD
607 data &= ~(1 << target);
608 }
609 if (data) {
610 kprintf("%s: WARNING (PM): extra bits set in "
611 "EINFO: %08x\n", PORTNAME(ap), data);
612 while (target < AHCI_MAX_PMPORTS) {
613 ahci_pm_check_good(ap, target);
614 ++target;
615 }
3209f581
MD
616 }
617 }
618}
619
620
621/*
fd8bd957
MD
622 * De-initialize and detach a port.
623 */
258223a3
MD
624void
625ahci_port_free(struct ahci_softc *sc, u_int port)
626{
627 struct ahci_port *ap = sc->sc_ports[port];
628 struct ahci_ccb *ccb;
629
17eab71e
MD
630 /*
631 * Ensure port is disabled and its interrupts are all flushed.
632 */
258223a3 633 if (ap->ap_sc) {
17eab71e 634 ahci_port_stop(ap, 1);
f4553de1 635 ahci_os_stop_port(ap);
258223a3
MD
636 ahci_pwrite(ap, AHCI_PREG_CMD, 0);
637 ahci_pwrite(ap, AHCI_PREG_IE, 0);
638 ahci_pwrite(ap, AHCI_PREG_IS, ahci_pread(ap, AHCI_PREG_IS));
639 ahci_write(sc, AHCI_REG_IS, 1 << port);
640 }
641
642 if (ap->ap_ccbs) {
643 while ((ccb = ahci_get_ccb(ap)) != NULL) {
644 if (ccb->ccb_dmamap) {
645 bus_dmamap_destroy(sc->sc_tag_data,
646 ccb->ccb_dmamap);
647 ccb->ccb_dmamap = NULL;
648 }
649 }
1067474a
MD
650 if ((ccb = ap->ap_err_ccb) != NULL) {
651 if (ccb->ccb_dmamap) {
652 bus_dmamap_destroy(sc->sc_tag_data,
653 ccb->ccb_dmamap);
654 ccb->ccb_dmamap = NULL;
655 }
656 ap->ap_err_ccb = NULL;
657 }
258223a3
MD
658 kfree(ap->ap_ccbs, M_DEVBUF);
659 ap->ap_ccbs = NULL;
660 }
661
662 if (ap->ap_dmamem_cmd_list) {
663 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_list);
664 ap->ap_dmamem_cmd_list = NULL;
665 }
666 if (ap->ap_dmamem_rfis) {
667 ahci_dmamem_free(sc, ap->ap_dmamem_rfis);
668 ap->ap_dmamem_rfis = NULL;
669 }
670 if (ap->ap_dmamem_cmd_table) {
671 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_table);
672 ap->ap_dmamem_cmd_table = NULL;
673 }
1980eff3
MD
674 if (ap->ap_ata) {
675 kfree(ap->ap_ata, M_DEVBUF);
676 ap->ap_ata = NULL;
677 }
12feb904
MD
678 if (ap->ap_err_scratch) {
679 kfree(ap->ap_err_scratch, M_DEVBUF);
680 ap->ap_err_scratch = NULL;
681 }
258223a3
MD
682
683 /* bus_space(9) says we dont free the subregions handle */
684
685 kfree(ap, M_DEVBUF);
686 sc->sc_ports[port] = NULL;
687}
688
fd8bd957
MD
689/*
690 * Start high-level command processing on the port
691 */
258223a3 692int
17eab71e 693ahci_port_start(struct ahci_port *ap)
258223a3 694{
12feb904 695 u_int32_t r, s, is, tfd;
258223a3 696
17eab71e
MD
697 /*
698 * FRE must be turned on before ST. Wait for FR to go active
699 * before turning on ST. The spec doesn't seem to think this
700 * is necessary but waiting here avoids an on-off race in the
701 * ahci_port_stop() code.
702 */
12feb904 703 r = ahci_pread(ap, AHCI_PREG_CMD);
17eab71e
MD
704 if ((r & AHCI_PREG_CMD_FRE) == 0) {
705 r |= AHCI_PREG_CMD_FRE;
706 ahci_pwrite(ap, AHCI_PREG_CMD, r);
707 }
708 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) {
709 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) {
710 kprintf("%s: Cannot start FIS reception\n",
711 PORTNAME(ap));
712 return (2);
713 }
714 }
715
716 /*
717 * Turn on ST, wait for CR to come up.
718 */
719 r |= AHCI_PREG_CMD_ST;
258223a3 720 ahci_pwrite(ap, AHCI_PREG_CMD, r);
17eab71e 721 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) {
8bf6a3ff
MD
722 s = ahci_pread(ap, AHCI_PREG_SERR);
723 is = ahci_pread(ap, AHCI_PREG_IS);
724 tfd = ahci_pread(ap, AHCI_PREG_TFD);
1980eff3 725 kprintf("%s: Cannot start command DMA\n"
1980eff3 726 "NCMP=%b NSERR=%b\n"
12feb904
MD
727 "NEWIS=%b\n"
728 "NEWTFD=%b\n",
1980eff3 729 PORTNAME(ap),
1980eff3 730 r, AHCI_PFMT_CMD, s, AHCI_PFMT_SERR,
12feb904
MD
731 is, AHCI_PFMT_IS,
732 tfd, AHCI_PFMT_TFD_STS);
17eab71e
MD
733 return (1);
734 }
258223a3
MD
735
736#ifdef AHCI_COALESCE
17eab71e
MD
737 /*
738 * (Re-)enable coalescing on the port.
739 */
258223a3
MD
740 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) {
741 ap->ap_sc->sc_ccc_ports_cur |= (1 << ap->ap_num);
742 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS,
743 ap->ap_sc->sc_ccc_ports_cur);
744 }
745#endif
746
258223a3
MD
747 return (0);
748}
749
fd8bd957
MD
750/*
751 * Stop high-level command processing on a port
4c339a5f
MD
752 *
753 * WARNING! If the port is stopped while CR is still active our saved
754 * CI/SACT will race any commands completed by the command
755 * processor prior to being able to stop. Thus we never call
756 * this function unless we intend to dispose of any remaining
757 * active commands. In particular, this complicates the timeout
758 * code.
fd8bd957 759 */
258223a3
MD
760int
761ahci_port_stop(struct ahci_port *ap, int stop_fis_rx)
762{
12feb904 763 u_int32_t r;
258223a3
MD
764
765#ifdef AHCI_COALESCE
17eab71e
MD
766 /*
767 * Disable coalescing on the port while it is stopped.
768 */
258223a3
MD
769 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) {
770 ap->ap_sc->sc_ccc_ports_cur &= ~(1 << ap->ap_num);
771 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS,
772 ap->ap_sc->sc_ccc_ports_cur);
773 }
774#endif
775
17eab71e
MD
776 /*
777 * Turn off ST, then wait for CR to go off.
778 */
258223a3
MD
779 r = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
780 r &= ~AHCI_PREG_CMD_ST;
258223a3
MD
781 ahci_pwrite(ap, AHCI_PREG_CMD, r);
782
17eab71e
MD
783 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) {
784 kprintf("%s: Port bricked, unable to stop (ST)\n",
785 PORTNAME(ap));
258223a3 786 return (1);
17eab71e 787 }
258223a3 788
1980eff3 789#if 0
17eab71e
MD
790 /*
791 * Turn off FRE, then wait for FR to go off. FRE cannot
792 * be turned off until CR transitions to 0.
793 */
1980eff3
MD
794 if ((r & AHCI_PREG_CMD_FR) == 0) {
795 kprintf("%s: FR stopped, clear FRE for next start\n",
796 PORTNAME(ap));
797 stop_fis_rx = 2;
798 }
799#endif
17eab71e
MD
800 if (stop_fis_rx) {
801 r &= ~AHCI_PREG_CMD_FRE;
802 ahci_pwrite(ap, AHCI_PREG_CMD, r);
803 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) {
804 kprintf("%s: Port bricked, unable to stop (FRE)\n",
805 PORTNAME(ap));
806 return (2);
807 }
808 }
258223a3
MD
809
810 return (0);
811}
812
fd8bd957
MD
813/*
814 * AHCI command list override -> forcibly clear TFD.STS.{BSY,DRQ}
815 */
258223a3
MD
816int
817ahci_port_clo(struct ahci_port *ap)
818{
819 struct ahci_softc *sc = ap->ap_sc;
820 u_int32_t cmd;
821
822 /* Only attempt CLO if supported by controller */
823 if ((ahci_read(sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) == 0)
824 return (1);
825
826 /* Issue CLO */
827 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
258223a3
MD
828 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_CLO);
829
830 /* Wait for completion */
831 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CLO)) {
832 kprintf("%s: CLO did not complete\n", PORTNAME(ap));
833 return (1);
834 }
835
836 return (0);
837}
838
fd8bd957 839/*
1980eff3
MD
840 * Reset a port.
841 *
842 * If hard is 0 perform a softreset of the port.
843 * If hard is 1 perform a hard reset of the port.
844 * If hard is 2 perform a hard reset of the port and cycle the phy.
845 *
846 * If at is non-NULL an indirect port via a port-multiplier is being
847 * reset, otherwise a direct port is being reset.
17eab71e 848 *
1980eff3 849 * NOTE: Indirect ports can only be soft-reset.
17eab71e
MD
850 */
851int
1980eff3 852ahci_port_reset(struct ahci_port *ap, struct ata_port *at, int hard)
17eab71e
MD
853{
854 int rc;
855
856 if (hard) {
1980eff3
MD
857 if (at)
858 rc = ahci_pm_hardreset(ap, at->at_target, hard);
859 else
860 rc = ahci_port_hardreset(ap, hard);
17eab71e 861 } else {
1980eff3
MD
862 if (at)
863 rc = ahci_pm_softreset(ap, at->at_target);
864 else
865 rc = ahci_port_softreset(ap);
17eab71e
MD
866 }
867 return(rc);
868}
869
870/*
fd8bd957
MD
871 * AHCI soft reset, Section 10.4.1
872 *
1980eff3
MD
873 * (at) will be NULL when soft-resetting a directly-attached device, and
874 * non-NULL when soft-resetting a device through a port multiplier.
875 *
fd8bd957 876 * This function keeps port communications intact and attempts to generate
1980eff3 877 * a reset to the connected device using device commands.
fd8bd957 878 */
258223a3
MD
879int
880ahci_port_softreset(struct ahci_port *ap)
881{
1980eff3
MD
882 struct ahci_ccb *ccb = NULL;
883 struct ahci_cmd_hdr *cmd_slot;
884 u_int8_t *fis;
3209f581 885 int error;
1980eff3 886
3209f581 887 error = EIO;
1980eff3 888
074579df
MD
889 if (bootverbose) {
890 kprintf("%s: START SOFTRESET %b\n", PORTNAME(ap),
891 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD);
892 }
258223a3
MD
893
894 DPRINTF(AHCI_D_VERBOSE, "%s: soft reset\n", PORTNAME(ap));
895
896 crit_enter();
1980eff3
MD
897 ap->ap_flags |= AP_F_IN_RESET;
898 ap->ap_state = AP_S_NORMAL;
258223a3 899
1980eff3
MD
900 /*
901 * Remember port state in cmd (main to restore start/stop)
902 *
903 * Idle port.
904 */
258223a3
MD
905 if (ahci_port_stop(ap, 0)) {
906 kprintf("%s: failed to stop port, cannot softreset\n",
907 PORTNAME(ap));
908 goto err;
909 }
cf5f3a81
MD
910
911 /*
1980eff3 912 * Request CLO if device appears hung.
cf5f3a81 913 */
258223a3 914 if (ahci_pread(ap, AHCI_PREG_TFD) &
1980eff3 915 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
258223a3
MD
916 ahci_port_clo(ap);
917 }
918
1980eff3
MD
919 /*
920 * This is an attempt to clear errors so a new signature will
921 * be latched. It isn't working properly. XXX
922 */
cf5f3a81 923 ahci_flush_tfd(ap);
1980eff3 924 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
258223a3
MD
925
926 /* Restart port */
17eab71e 927 if (ahci_port_start(ap)) {
258223a3
MD
928 kprintf("%s: failed to start port, cannot softreset\n",
929 PORTNAME(ap));
930 goto err;
931 }
932
933 /* Check whether CLO worked */
934 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1980eff3 935 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
258223a3
MD
936 kprintf("%s: CLO %s, need port reset\n",
937 PORTNAME(ap),
938 (ahci_read(ap->ap_sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO)
939 ? "failed" : "unsupported");
3209f581 940 error = EBUSY;
258223a3
MD
941 goto err;
942 }
943
cec85a37
MD
944 /*
945 * Prep first D2H command with SRST feature & clear busy/reset flags
946 *
947 * It is unclear which other fields in the FIS are used. Just zero
948 * everything.
1067474a
MD
949 *
950 * NOTE! This CCB is used for both the first and second commands.
951 * The second command must use CCB slot 1 to properly load
952 * the signature.
cec85a37 953 */
258223a3 954 ccb = ahci_get_err_ccb(ap);
12feb904
MD
955 ccb->ccb_xa.complete = ahci_dummy_done;
956 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_EXCLUSIVE;
1067474a 957 KKASSERT(ccb->ccb_slot == 1);
1980eff3 958 ccb->ccb_xa.at = NULL;
258223a3 959 cmd_slot = ccb->ccb_cmd_hdr;
258223a3
MD
960
961 fis = ccb->ccb_cmd_table->cfis;
cec85a37 962 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1980eff3
MD
963 fis[0] = ATA_FIS_TYPE_H2D;
964 fis[15] = ATA_FIS_CONTROL_SRST|ATA_FIS_CONTROL_4BIT;
258223a3
MD
965
966 cmd_slot->prdtl = 0;
967 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
968 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_C); /* Clear busy on OK */
969 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_R); /* Reset */
258223a3
MD
970
971 ccb->ccb_xa.state = ATA_S_PENDING;
12feb904 972
831bc9e3 973 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) {
5f8c1efd 974 kprintf("%s: First FIS failed\n", PORTNAME(ap));
258223a3 975 goto err;
cec85a37 976 }
258223a3 977
cec85a37 978 /*
831bc9e3
MD
979 * WARNING! TIME SENSITIVE SPACE! WARNING!
980 *
981 * The two FISes are supposed to be back to back. Don't issue other
982 * commands or even delay if we can help it.
1980eff3 983 */
1980eff3
MD
984
985 /*
cec85a37
MD
986 * Prep second D2H command to read status and complete reset sequence
987 * AHCI 10.4.1 and "Serial ATA Revision 2.6". I can't find the ATA
988 * Rev 2.6 and it is unclear how the second FIS should be set up
989 * from the AHCI document.
990 *
b089d0bf 991 * Give the device 3ms before sending the second FIS.
cec85a37
MD
992 *
993 * It is unclear which other fields in the FIS are used. Just zero
994 * everything.
995 */
12feb904
MD
996 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_AUTOSENSE | ATA_F_EXCLUSIVE;
997
cec85a37 998 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1980eff3
MD
999 fis[0] = ATA_FIS_TYPE_H2D;
1000 fis[15] = ATA_FIS_CONTROL_4BIT;
258223a3
MD
1001
1002 cmd_slot->prdtl = 0;
1003 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
258223a3
MD
1004
1005 ccb->ccb_xa.state = ATA_S_PENDING;
831bc9e3 1006 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) {
5f8c1efd 1007 kprintf("%s: Second FIS failed\n", PORTNAME(ap));
258223a3 1008 goto err;
cec85a37 1009 }
258223a3 1010
1980eff3
MD
1011 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1012 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
258223a3
MD
1013 kprintf("%s: device didn't come ready after reset, TFD: 0x%b\n",
1014 PORTNAME(ap),
1015 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS);
3209f581 1016 error = EBUSY;
258223a3
MD
1017 goto err;
1018 }
3209f581 1019 ahci_os_sleep(10);
258223a3 1020
fd8bd957
MD
1021 /*
1022 * If the softreset is trying to clear a BSY condition after a
1023 * normal portreset we assign the port type.
1024 *
1025 * If the softreset is being run first as part of the ccb error
1026 * processing code then report if the device signature changed
1027 * unexpectedly.
1028 */
1980eff3
MD
1029 if (ap->ap_type == ATA_PORT_T_NONE) {
1030 ap->ap_type = ahci_port_signature_detect(ap, NULL);
fd8bd957 1031 } else {
1980eff3
MD
1032 if (ahci_port_signature_detect(ap, NULL) != ap->ap_type) {
1033 kprintf("%s: device signature unexpectedly "
1034 "changed\n", PORTNAME(ap));
3209f581 1035 error = EBUSY; /* XXX */
fd8bd957
MD
1036 }
1037 }
3209f581 1038 error = 0;
1980eff3 1039
3209f581 1040 ahci_os_sleep(3);
258223a3
MD
1041err:
1042 if (ccb != NULL) {
258223a3 1043 ahci_put_err_ccb(ccb);
1980eff3
MD
1044
1045 /*
1046 * If the target is busy use CLO to clear the busy
1047 * condition. The BSY should be cleared on the next
1048 * start.
1049 */
1050 if (ahci_pread(ap, AHCI_PREG_TFD) &
1051 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1052 ahci_port_clo(ap);
1053 }
258223a3
MD
1054 }
1055
cf5f3a81
MD
1056 /*
1057 * If we failed to softreset make the port quiescent, otherwise
1058 * make sure the port's start/stop state matches what it was on
1059 * entry.
1980eff3
MD
1060 *
1061 * Don't kill the port if the softreset is on a port multiplier
1062 * target, that would kill all the targets!
cf5f3a81 1063 */
3209f581 1064 if (error) {
cf5f3a81 1065 ahci_port_hardstop(ap);
3209f581 1066 /* ap_probe set to failed */
cf5f3a81 1067 } else {
3209f581 1068 ap->ap_probe = ATA_PROBE_NEED_IDENT;
12feb904 1069 ap->ap_pmcount = 1;
4c339a5f 1070 ahci_port_start(ap);
cf5f3a81 1071 }
3209f581 1072 ap->ap_flags &= ~AP_F_IN_RESET;
258223a3
MD
1073 crit_exit();
1074
074579df
MD
1075 if (bootverbose)
1076 kprintf("%s: END SOFTRESET\n", PORTNAME(ap));
1980eff3 1077
3209f581 1078 return (error);
258223a3
MD
1079}
1080
fd8bd957
MD
1081/*
1082 * AHCI port reset, Section 10.4.2
1083 *
1084 * This function does a hard reset of the port. Note that the device
1085 * connected to the port could still end-up hung.
1086 */
258223a3 1087int
1980eff3 1088ahci_port_hardreset(struct ahci_port *ap, int hard)
258223a3 1089{
1980eff3 1090 u_int32_t cmd, r;
12feb904 1091 u_int32_t data;
3209f581 1092 int error;
1980eff3 1093 int loop;
258223a3 1094
12feb904
MD
1095 if (bootverbose)
1096 kprintf("%s: START HARDRESET\n", PORTNAME(ap));
1980eff3
MD
1097 ap->ap_flags |= AP_F_IN_RESET;
1098
1099 /*
1100 * Idle the port,
1101 */
258223a3 1102 ahci_port_stop(ap, 0);
cf5f3a81
MD
1103 ap->ap_state = AP_S_NORMAL;
1104
1105 /*
1980eff3
MD
1106 * The port may have been quiescent with its SUD bit cleared, so
1107 * set the SUD (spin up device).
cf5f3a81
MD
1108 */
1109 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1110 cmd |= AHCI_PREG_CMD_SUD;
1111 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
258223a3 1112
1980eff3
MD
1113 /*
1114 * Perform device detection. Cycle the PHY off, wait 10ms.
1115 * This simulates the SATA cable being physically unplugged.
1067474a
MD
1116 *
1117 * NOTE: hard reset mode 2 (cycling the PHY) is not reliable
1118 * and not currently used.
1980eff3
MD
1119 */
1120 ap->ap_type = ATA_PORT_T_NONE;
1121
1122 r = AHCI_PREG_SCTL_IPM_DISABLED;
1123 if (hard == 2)
1124 r |= AHCI_PREG_SCTL_DET_DISABLE;
1125 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
3209f581 1126 ahci_os_sleep(10);
258223a3 1127
1980eff3
MD
1128 /*
1129 * Start transmitting COMRESET. COMRESET must be sent for at
1130 * least 1ms.
1131 */
1132 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT;
074579df 1133 if (AhciForceGen1 & (1 << ap->ap_num))
258223a3 1134 r |= AHCI_PREG_SCTL_SPD_GEN1;
074579df 1135 else
258223a3 1136 r |= AHCI_PREG_SCTL_SPD_ANY;
258223a3 1137 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
831bc9e3
MD
1138
1139 /*
1140 * Through trial and error it seems to take around 100ms
1141 * for the detect logic to settle down. If this is too
1142 * short the softreset code will fail.
1143 */
1144 ahci_os_sleep(100);
cf5f3a81
MD
1145
1146 /*
1147 * Only SERR_DIAG_X needs to be cleared for TFD updates, but
1148 * since we are hard-resetting the port we might as well clear
1149 * the whole enchillada
1150 */
1151 ahci_flush_tfd(ap);
1152 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
258223a3
MD
1153 r &= ~AHCI_PREG_SCTL_DET_INIT;
1154 r |= AHCI_PREG_SCTL_DET_NONE;
1155 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
258223a3 1156
1980eff3
MD
1157 /*
1158 * Try to determine if there is a device on the port.
1159 *
1160 * Give the device 3/10 second to at least be detected.
1161 * If we fail clear PRCS (phy detect) since we may cycled
1162 * the phy and probably caused another PRCS interrupt.
1163 */
76497a9c
MD
1164 loop = 300;
1165 while (loop > 0) {
1980eff3
MD
1166 r = ahci_pread(ap, AHCI_PREG_SSTS);
1167 if (r & AHCI_PREG_SSTS_DET)
1168 break;
76497a9c 1169 loop -= ahci_os_softsleep();
1980eff3
MD
1170 }
1171 if (loop == 0) {
1172 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS);
074579df
MD
1173 if (bootverbose) {
1174 kprintf("%s: Port appears to be unplugged\n",
1175 PORTNAME(ap));
1176 }
3209f581 1177 error = ENODEV;
12feb904 1178 goto done;
1980eff3
MD
1179 }
1180
1181 /*
1182 * There is something on the port. Give the device 3 seconds
1183 * to fully negotiate.
1184 */
12feb904 1185 if (ahci_pwait_eq(ap, 3000, AHCI_PREG_SSTS,
1980eff3 1186 AHCI_PREG_SSTS_DET, AHCI_PREG_SSTS_DET_DEV)) {
074579df
MD
1187 if (bootverbose) {
1188 kprintf("%s: Device may be powered down\n",
1189 PORTNAME(ap));
1190 }
3209f581 1191 error = ENODEV;
12feb904 1192 goto pmdetect;
258223a3
MD
1193 }
1194
cec85a37 1195 /*
12feb904
MD
1196 * We got something that definitely looks like a device. Give
1197 * the device time to send us its first D2H FIS. Waiting for
1198 * BSY to clear accomplishes this.
1980eff3 1199 *
12feb904
MD
1200 * NOTE that a port multiplier may or may not clear BSY here,
1201 * depending on what is sitting in target 0 behind it.
1980eff3
MD
1202 */
1203 ahci_flush_tfd(ap);
1980eff3 1204
12feb904
MD
1205 if (ahci_pwait_clr_to(ap, 3000, AHCI_PREG_TFD,
1206 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
831bc9e3 1207 error = EBUSY;
12feb904
MD
1208 } else {
1209 error = 0;
1980eff3
MD
1210 }
1211
12feb904 1212pmdetect:
1980eff3 1213 /*
12feb904
MD
1214 * Do the PM port probe regardless of how things turned out on
1215 * the BSY check.
1980eff3 1216 */
12feb904
MD
1217 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SPM)
1218 error = ahci_pm_port_probe(ap, error);
1980eff3 1219
12feb904 1220done:
1980eff3 1221 /*
12feb904 1222 * Finish up.
1980eff3 1223 */
12feb904
MD
1224 switch(error) {
1225 case 0:
1226 /*
1227 * All good, make sure the port is running and set the
1228 * probe state. Ignore the signature junk (it's unreliable)
1229 * until we get to the softreset code.
1230 */
1231 if (ahci_port_start(ap)) {
1232 kprintf("%s: failed to start command DMA on port, "
1233 "disabling\n", PORTNAME(ap));
1234 error = EBUSY;
1235 goto done;
1980eff3 1236 }
12feb904
MD
1237 if (ap->ap_type == ATA_PORT_T_PM)
1238 ap->ap_probe = ATA_PROBE_GOOD;
1239 else
1240 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET;
1241 break;
1242 case ENODEV:
1243 /*
1244 * Normal device probe failure
1245 */
1246 data = ahci_pread(ap, AHCI_PREG_SSTS);
1980eff3 1247
12feb904
MD
1248 switch(data & AHCI_PREG_SSTS_DET) {
1249 case AHCI_PREG_SSTS_DET_DEV_NE:
1250 kprintf("%s: Device not communicating\n",
1251 PORTNAME(ap));
1252 break;
1253 case AHCI_PREG_SSTS_DET_PHYOFFLINE:
1254 kprintf("%s: PHY offline\n",
1255 PORTNAME(ap));
1256 break;
1257 default:
1258 kprintf("%s: No device detected\n",
1259 PORTNAME(ap));
1260 break;
1261 }
1262 ahci_port_hardstop(ap);
1263 break;
1264 default:
1265 /*
1266 * Abnormal probe (EBUSY)
1267 */
1268 kprintf("%s: Device on port is bricked\n",
3209f581 1269 PORTNAME(ap));
12feb904
MD
1270 ahci_port_hardstop(ap);
1271#if 0
1272 rc = ahci_port_reset(ap, atx, 0);
1273 if (rc) {
1274 kprintf("%s: Unable unbrick device\n",
1275 PORTNAME(ap));
1276 } else {
1277 kprintf("%s: Successfully unbricked\n",
1278 PORTNAME(ap));
1067474a 1279 }
12feb904
MD
1280#endif
1281 break;
3209f581 1282 }
3209f581 1283
1980eff3 1284 /*
12feb904 1285 * Clean up
1980eff3 1286 */
12feb904
MD
1287 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
1288 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS);
1289
1290 ap->ap_flags &= ~AP_F_IN_RESET;
1980eff3 1291
12feb904
MD
1292 if (bootverbose)
1293 kprintf("%s: END HARDRESET %d\n", PORTNAME(ap), error);
1294 return (error);
cf5f3a81
MD
1295}
1296
1297/*
1298 * Hard-stop on hot-swap device removal. See 10.10.1
1299 *
1300 * Place the port in a mode that will allow it to detect hot-swap insertions.
1301 * This is a bit imprecise because just setting-up SCTL to DET_INIT doesn't
1302 * seem to do the job.
1303 */
1304void
1305ahci_port_hardstop(struct ahci_port *ap)
1306{
76497a9c 1307 struct ahci_ccb *ccb;
1980eff3 1308 struct ata_port *at;
cf5f3a81
MD
1309 u_int32_t r;
1310 u_int32_t cmd;
76497a9c 1311 int slot;
1980eff3 1312 int i;
cf5f3a81
MD
1313
1314 /*
1315 * Stop the port. We can't modify things like SUD if the port
1316 * is running.
1317 */
1318 ap->ap_state = AP_S_FATAL_ERROR;
1980eff3
MD
1319 ap->ap_probe = ATA_PROBE_FAILED;
1320 ap->ap_type = ATA_PORT_T_NONE;
cf5f3a81
MD
1321 ahci_port_stop(ap, 0);
1322 cmd = ahci_pread(ap, AHCI_PREG_CMD);
1323
1324 /*
1980eff3
MD
1325 * Clean up AT sub-ports on SATA port.
1326 */
1327 for (i = 0; ap->ap_ata && i < AHCI_MAX_PMPORTS; ++i) {
1328 at = &ap->ap_ata[i];
1329 at->at_type = ATA_PORT_T_NONE;
3209f581 1330 at->at_probe = ATA_PROBE_FAILED;
1980eff3
MD
1331 }
1332
1333 /*
1334 * Turn off port-multiplier control bit
1335 */
1336 if (cmd & AHCI_PREG_CMD_PMA) {
1337 cmd &= ~AHCI_PREG_CMD_PMA;
1338 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1339 }
1340
1341 /*
cf5f3a81
MD
1342 * Make sure FRE is active. There isn't anything we can do if it
1343 * fails so just ignore errors.
1344 */
1345 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
1346 cmd |= AHCI_PREG_CMD_FRE;
1347 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1348 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0)
1349 ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR);
1350 }
1351
1352 /*
1353 * 10.10.3 DET must be set to 0 before setting SUD to 0.
1354 * 10.10.1 place us in the Listen state.
1355 *
1356 * Deactivating SUD only applies if the controller supports SUD.
1357 */
1358 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
3209f581 1359 ahci_os_sleep(1);
cf5f3a81
MD
1360 if (cmd & AHCI_PREG_CMD_SUD) {
1361 cmd &= ~AHCI_PREG_CMD_SUD;
1362 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1363 }
3209f581 1364 ahci_os_sleep(1);
cf5f3a81
MD
1365
1366 /*
1367 * Transition su to the spin-up state. HVA shall send COMRESET and
1368 * begin initialization sequence (whatever that means).
1369 *
1370 * This only applies if the controller supports SUD.
1371 */
1372 cmd |= AHCI_PREG_CMD_SUD;
258223a3 1373 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
3209f581 1374 ahci_os_sleep(1);
258223a3 1375
cf5f3a81
MD
1376 /*
1377 * Transition us to the Reset state. Theoretically we send a
1378 * continuous stream of COMRESETs in this state.
1379 */
1380 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT;
1381 if (AhciForceGen1 & (1 << ap->ap_num)) {
1382 kprintf("%s: Force 1.5Gbits\n", PORTNAME(ap));
1383 r |= AHCI_PREG_SCTL_SPD_GEN1;
1384 } else {
1385 r |= AHCI_PREG_SCTL_SPD_ANY;
1386 }
1387 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
3209f581 1388 ahci_os_sleep(1);
cf5f3a81
MD
1389
1390 /*
1391 * Flush SERR_DIAG_X so the TFD can update.
1392 */
1393 ahci_flush_tfd(ap);
1394
1395 /*
76497a9c
MD
1396 * Clean out pending ccbs
1397 */
1398 while (ap->ap_active) {
1399 slot = ffs(ap->ap_active) - 1;
1400 ap->ap_active &= ~(1 << slot);
1401 ap->ap_expired &= ~(1 << slot);
1402 --ap->ap_active_cnt;
1403 ccb = &ap->ap_ccbs[slot];
1404 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) {
1405 callout_stop(&ccb->ccb_timeout);
1406 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING;
1407 }
1408 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED |
1409 ATA_F_TIMEOUT_EXPIRED);
1410 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1411 ccb->ccb_done(ccb);
1412 ccb->ccb_xa.complete(&ccb->ccb_xa);
1413 }
1414 while (ap->ap_sactive) {
1415 slot = ffs(ap->ap_sactive) - 1;
1416 ap->ap_sactive &= ~(1 << slot);
1417 ap->ap_expired &= ~(1 << slot);
1418 ccb = &ap->ap_ccbs[slot];
1419 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) {
1420 callout_stop(&ccb->ccb_timeout);
1421 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING;
1422 }
1423 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED |
1424 ATA_F_TIMEOUT_EXPIRED);
1425 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1426 ccb->ccb_done(ccb);
1427 ccb->ccb_xa.complete(&ccb->ccb_xa);
1428 }
1429 KKASSERT(ap->ap_active_cnt == 0);
1430
1431 while ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) != NULL) {
1432 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
1433 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1434 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_DESIRED;
1435 ccb->ccb_done(ccb);
1436 ccb->ccb_xa.complete(&ccb->ccb_xa);
1437 }
1438
1439 /*
cf5f3a81
MD
1440 * Leave us in COMRESET (both SUD and INIT active), the HBA should
1441 * hopefully send us a DIAG_X-related interrupt if it receives
1442 * a COMINIT, and if not that then at least a Phy transition
1443 * interrupt.
1444 *
1445 * If we transition INIT from 1->0 to begin the initalization
1446 * sequence it is unclear if that sequence will remain active
1447 * until the next device insertion.
1448 *
1449 * If we go back to the listen state it is unclear if the
1450 * device will actually send us a COMINIT, since we aren't
1451 * sending any COMRESET's
1452 */
1453 /* NOP */
1454}
1455
1456/*
c408a8b3
MD
1457 * We can't loop on the X bit, a continuous COMINIT received will make
1458 * it loop forever. Just assume one event has built up and clear X
1459 * so the task file descriptor can update.
cf5f3a81
MD
1460 */
1461void
1462ahci_flush_tfd(struct ahci_port *ap)
1463{
1464 u_int32_t r;
1465
1466 r = ahci_pread(ap, AHCI_PREG_SERR);
c408a8b3 1467 if (r & AHCI_PREG_SERR_DIAG_X)
1980eff3 1468 ahci_pwrite(ap, AHCI_PREG_SERR, AHCI_PREG_SERR_DIAG_X);
258223a3
MD
1469}
1470
fd8bd957
MD
1471/*
1472 * Figure out what type of device is connected to the port, ATAPI or
1473 * DISK.
1474 */
1475int
1980eff3 1476ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at)
fd8bd957
MD
1477{
1478 u_int32_t sig;
1479
1480 sig = ahci_pread(ap, AHCI_PREG_SIG);
074579df
MD
1481 if (bootverbose)
1482 kprintf("%s: sig %08x\n", ATANAME(ap, at), sig);
fd8bd957
MD
1483 if ((sig & 0xffff0000) == (SATA_SIGNATURE_ATAPI & 0xffff0000)) {
1484 return(ATA_PORT_T_ATAPI);
1980eff3
MD
1485 } else if ((sig & 0xffff0000) ==
1486 (SATA_SIGNATURE_PORT_MULTIPLIER & 0xffff0000)) {
1980eff3 1487 return(ATA_PORT_T_PM);
fd8bd957
MD
1488 } else {
1489 return(ATA_PORT_T_DISK);
1490 }
1491}
1492
1493/*
1494 * Load the DMA descriptor table for a CCB's buffer.
1495 */
258223a3
MD
1496int
1497ahci_load_prdt(struct ahci_ccb *ccb)
1498{
1499 struct ahci_port *ap = ccb->ccb_port;
1500 struct ahci_softc *sc = ap->ap_sc;
1501 struct ata_xfer *xa = &ccb->ccb_xa;
1502 struct ahci_prdt *prdt = ccb->ccb_cmd_table->prdt;
1503 bus_dmamap_t dmap = ccb->ccb_dmamap;
1504 struct ahci_cmd_hdr *cmd_slot = ccb->ccb_cmd_hdr;
1505 int error;
1506
1507 if (xa->datalen == 0) {
1508 ccb->ccb_cmd_hdr->prdtl = 0;
1509 return (0);
1510 }
1511
1512 error = bus_dmamap_load(sc->sc_tag_data, dmap,
1513 xa->data, xa->datalen,
1514 ahci_load_prdt_callback,
1515 &prdt,
1516 ((xa->flags & ATA_F_NOWAIT) ?
1517 BUS_DMA_NOWAIT : BUS_DMA_WAITOK));
1518 if (error != 0) {
1519 kprintf("%s: error %d loading dmamap\n", PORTNAME(ap), error);
1520 return (1);
1521 }
12feb904 1522#if 0
258223a3
MD
1523 if (xa->flags & ATA_F_PIO)
1524 prdt->flags |= htole32(AHCI_PRDT_FLAG_INTR);
12feb904 1525#endif
258223a3
MD
1526
1527 cmd_slot->prdtl = htole16(prdt - ccb->ccb_cmd_table->prdt + 1);
1528
1529 bus_dmamap_sync(sc->sc_tag_data, dmap,
1530 (xa->flags & ATA_F_READ) ?
1531 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1532
1533 return (0);
258223a3
MD
1534}
1535
1536/*
1537 * Callback from BUSDMA system to load the segment list. The passed segment
1538 * list is a temporary structure.
1539 */
1540static
1541void
1542ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, int nsegs,
1543 int error)
1544{
1545 struct ahci_prdt *prd = *(void **)info;
1546 u_int64_t addr;
1547
1548 KKASSERT(nsegs <= AHCI_MAX_PRDT);
1549
1550 while (nsegs) {
1551 addr = segs->ds_addr;
1552 prd->dba_hi = htole32((u_int32_t)(addr >> 32));
1553 prd->dba_lo = htole32((u_int32_t)addr);
258223a3
MD
1554 prd->flags = htole32(segs->ds_len - 1);
1555 --nsegs;
1556 if (nsegs)
1557 ++prd;
1558 ++segs;
1559 }
1560 *(void **)info = prd; /* return last valid segment */
1561}
1562
1563void
1564ahci_unload_prdt(struct ahci_ccb *ccb)
1565{
1566 struct ahci_port *ap = ccb->ccb_port;
1567 struct ahci_softc *sc = ap->ap_sc;
1568 struct ata_xfer *xa = &ccb->ccb_xa;
1569 bus_dmamap_t dmap = ccb->ccb_dmamap;
1570
1571 if (xa->datalen != 0) {
1572 bus_dmamap_sync(sc->sc_tag_data, dmap,
1573 (xa->flags & ATA_F_READ) ?
1574 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1575
1576 bus_dmamap_unload(sc->sc_tag_data, dmap);
1577
12feb904
MD
1578 if (ccb->ccb_cmd_hdr->prdbc == 0) {
1579 kprintf("%s: UNLOAD RESID WAS ZERO! tag=%d\n",
1580 ATANAME(ap, xa->at), ccb->ccb_slot);
1581 }
258223a3
MD
1582 if (ccb->ccb_xa.flags & ATA_F_NCQ)
1583 xa->resid = 0;
1584 else
1585 xa->resid = xa->datalen -
1586 le32toh(ccb->ccb_cmd_hdr->prdbc);
1587 }
1588}
1589
5f8c1efd
MD
1590/*
1591 * Start a command and poll for completion.
1592 *
3209f581
MD
1593 * timeout is in ms and only counts once the command gets on-chip.
1594 *
831bc9e3
MD
1595 * Returns ATA_S_* state, compare against ATA_S_COMPLETE to determine
1596 * that no error occured.
1597 *
5f8c1efd
MD
1598 * NOTE: If the caller specifies a NULL timeout function the caller is
1599 * responsible for clearing hardware state on failure, but we will
1600 * deal with removing the ccb from any pending queue.
1601 *
1602 * NOTE: NCQ should never be used with this function.
cf5f3a81
MD
1603 *
1604 * NOTE: If the port is in a failed state and stopped we do not try
1605 * to activate the ccb.
5f8c1efd 1606 */
258223a3 1607int
831bc9e3
MD
1608ahci_poll(struct ahci_ccb *ccb, int timeout,
1609 void (*timeout_fn)(struct ahci_ccb *))
258223a3 1610{
5f8c1efd 1611 struct ahci_port *ap = ccb->ccb_port;
258223a3 1612
cf5f3a81
MD
1613 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) {
1614 ccb->ccb_xa.state = ATA_S_ERROR;
831bc9e3 1615 return(ccb->ccb_xa.state);
cf5f3a81 1616 }
258223a3 1617 crit_enter();
12feb904
MD
1618#if 0
1619 kprintf("%s: Start command %02x tag=%d\n",
1620 ATANAME(ccb->ccb_port, ccb->ccb_xa.at),
1621 ccb->ccb_xa.fis->command, ccb->ccb_slot);
1622#endif
258223a3 1623 ahci_start(ccb);
1980eff3 1624
258223a3 1625 do {
f4553de1 1626 ahci_port_intr(ap, 1);
831bc9e3
MD
1627 switch(ccb->ccb_xa.state) {
1628 case ATA_S_ONCHIP:
1629 timeout -= ahci_os_softsleep();
1630 break;
1631 case ATA_S_PENDING:
1632 ahci_os_softsleep();
1633 ahci_check_active_timeouts(ap);
f4553de1 1634 break;
831bc9e3
MD
1635 default:
1636 crit_exit();
1637 return (ccb->ccb_xa.state);
f4553de1 1638 }
3209f581 1639 } while (timeout > 0);
5f8c1efd 1640
831bc9e3
MD
1641 kprintf("%s: Poll timeout slot %d CMD: %b TFD: 0x%b SERR: %b\n",
1642 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_slot,
1643 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD,
1644 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS,
1645 ahci_pread(ap, AHCI_PREG_SERR), AHCI_PFMT_SERR);
1646
1647 timeout_fn(ccb);
5f8c1efd 1648
258223a3
MD
1649 crit_exit();
1650
831bc9e3
MD
1651 return(ccb->ccb_xa.state);
1652}
1653
1654/*
1655 * When polling we have to check if the currently active CCB(s)
1656 * have timed out as the callout will be deadlocked while we
1657 * hold the port lock.
1658 */
1659void
1660ahci_check_active_timeouts(struct ahci_port *ap)
1661{
1662 struct ahci_ccb *ccb;
1663 u_int32_t mask;
1664 int tag;
1665
1666 mask = ap->ap_active | ap->ap_sactive;
1667 while (mask) {
1668 tag = ffs(mask) - 1;
1669 mask &= ~(1 << tag);
1670 ccb = &ap->ap_ccbs[tag];
1671 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_EXPIRED) {
1672 ahci_ata_cmd_timeout(ccb);
1673 }
1674 }
258223a3
MD
1675}
1676
3209f581
MD
1677static
1678__inline
1679void
1680ahci_start_timeout(struct ahci_ccb *ccb)
1681{
1682 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_DESIRED) {
1683 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_RUNNING;
1684 callout_reset(&ccb->ccb_timeout,
1685 (ccb->ccb_xa.timeout * hz + 999) / 1000,
1686 ahci_ata_cmd_timeout_unserialized, ccb);
1687 }
1688}
1689
258223a3
MD
1690void
1691ahci_start(struct ahci_ccb *ccb)
1692{
1693 struct ahci_port *ap = ccb->ccb_port;
1694 struct ahci_softc *sc = ap->ap_sc;
1695
1696 KKASSERT(ccb->ccb_xa.state == ATA_S_PENDING);
1697
1698 /* Zero transferred byte count before transfer */
1699 ccb->ccb_cmd_hdr->prdbc = 0;
1700
1701 /* Sync command list entry and corresponding command table entry */
1702 bus_dmamap_sync(sc->sc_tag_cmdh,
1703 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list),
1704 BUS_DMASYNC_PREWRITE);
1705 bus_dmamap_sync(sc->sc_tag_cmdt,
1706 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table),
1707 BUS_DMASYNC_PREWRITE);
1708
1709 /* Prepare RFIS area for write by controller */
1710 bus_dmamap_sync(sc->sc_tag_rfis,
1711 AHCI_DMA_MAP(ap->ap_dmamem_rfis),
1712 BUS_DMASYNC_PREREAD);
1713
4c339a5f
MD
1714 /*
1715 * There's no point trying to optimize this, it only shaves a few
1716 * nanoseconds so just queue the command and call our generic issue.
1717 */
1718 ahci_issue_pending_commands(ap, ccb);
258223a3
MD
1719}
1720
831bc9e3
MD
1721/*
1722 * While holding the port lock acquire exclusive access to the port.
1723 *
1724 * This is used when running the state machine to initialize and identify
1725 * targets over a port multiplier. Setting exclusive access prevents
1726 * ahci_port_intr() from activating any requests sitting on the pending
1727 * queue.
1728 */
1729void
1730ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at)
1731{
1732 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) == 0);
1733 ap->ap_flags |= AP_F_EXCLUSIVE_ACCESS;
1734 while (ap->ap_active || ap->ap_sactive) {
1735 ahci_port_intr(ap, 1);
1736 ahci_os_softsleep();
1737 }
1738}
1739
1740void
1741ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at)
1742{
1743 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) != 0);
1744 ap->ap_flags &= ~AP_F_EXCLUSIVE_ACCESS;
4c339a5f 1745 ahci_issue_pending_commands(ap, NULL);
831bc9e3
MD
1746}
1747
12feb904
MD
1748#if 0
1749
1750static void
1751fubar(struct ahci_ccb *ccb)
1752{
1753 struct ahci_port *ap = ccb->ccb_port;
1754 struct ahci_cmd_hdr *cmd;
1755 struct ahci_cmd_table *tab;
1756 struct ahci_prdt *prdt;
1757 int i;
1758
1759 kprintf("%s: ISSUE %02x\n",
1760 ATANAME(ap, ccb->ccb_xa.at),
1761 ccb->ccb_xa.fis->command);
1762 cmd = ccb->ccb_cmd_hdr;
1763 tab = ccb->ccb_cmd_table;
1764 prdt = ccb->ccb_cmd_table->prdt;
1765 kprintf("cmd flags=%04x prdtl=%d prdbc=%d ctba=%08x%08x\n",
1766 cmd->flags, cmd->prdtl, cmd->prdbc,
1767 cmd->ctba_hi, cmd->ctba_lo);
1768 for (i = 0; i < cmd->prdtl; ++i) {
1769 kprintf("\t%d dba=%08x%08x res=%08x flags=%08x\n",
1770 i, prdt->dba_hi, prdt->dba_lo, prdt->reserved,
1771 prdt->flags);
1772 }
1773 kprintf("tab\n");
1774}
1775
1776#endif
1777
4c339a5f
MD
1778/*
1779 * If ccb is not NULL enqueue and/or issue it.
1780 *
1781 * If ccb is NULL issue whatever we can from the queue. However, nothing
1782 * new is issued if the exclusive access flag is set or expired ccb's are
1783 * present.
1784 *
1785 * If existing commands are still active (ap_active/ap_sactive) we can only
1786 * issue matching new commands.
1787 */
258223a3 1788void
4c339a5f 1789ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb)
258223a3 1790{
4c339a5f
MD
1791 u_int32_t mask;
1792 int limit;
258223a3 1793
4c339a5f
MD
1794 /*
1795 * Enqueue the ccb.
1796 *
1797 * If just running the queue and in exclusive access mode we
1798 * just return. Also in this case if there are any expired ccb's
1799 * we want to clear the queue so the port can be safely stopped.
1800 */
1801 if (ccb) {
1802 TAILQ_INSERT_TAIL(&ap->ap_ccb_pending, ccb, ccb_entry);
1803 } else if ((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) || ap->ap_expired) {
831bc9e3 1804 return;
4c339a5f 1805 }
258223a3 1806
4c339a5f
MD
1807 /*
1808 * Pull the next ccb off the queue and run it if possible.
1809 */
1810 if ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) == NULL)
831bc9e3
MD
1811 return;
1812
12feb904
MD
1813 /*
1814 * Handle exclusivity requirements.
1815 *
1816 * ATA_F_EXCLUSIVE is used when we want to be the only command
1817 * running.
1818 *
1819 * ATA_F_AUTOSENSE is used when we want the D2H rfis loaded
1820 * back into the ccb on a normal (non-errored) command completion.
1821 * For example, for PM requests to target 15. Because the AHCI
1822 * spec does not stop the command processor and has only one rfis
1823 * area (for non-FBSS anyway), AUTOSENSE currently implies EXCLUSIVE.
1824 * Otherwise multiple completions can destroy the rfis data before
1825 * we have a chance to copy it.
1826 */
1827 if (ap->ap_active & ~ap->ap_expired) {
1828 /*
1829 * There may be multiple ccb's already running,
1830 * if any are running and ap_run_flags sets
1831 * one of these flags then we know only one is
1832 * running.
1833 *
1834 * XXX Current AUTOSENSE code forces exclusivity
1835 * to simplify the code.
1836 */
1837 if (ap->ap_run_flags &
1838 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) {
1839 return;
1840 }
1841
1842 if (ccb->ccb_xa.flags &
1843 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) {
1844 return;
1845 }
1846 }
1847
1848
4c339a5f 1849 if (ccb->ccb_xa.flags & ATA_F_NCQ) {
1980eff3 1850 /*
4c339a5f
MD
1851 * The next command is a NCQ command and can be issued as
1852 * long as currently active commands are not standard.
1980eff3 1853 */
4c339a5f 1854 if (ap->ap_active) {
1980eff3 1855 KKASSERT(ap->ap_active_cnt > 0);
4c339a5f
MD
1856 return;
1857 }
1858 KKASSERT(ap->ap_active_cnt == 0);
1859
1860 mask = 0;
1861 do {
1862 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
4c339a5f
MD
1863 mask |= 1 << ccb->ccb_slot;
1864 ccb->ccb_xa.state = ATA_S_ONCHIP;
12feb904
MD
1865 ahci_start_timeout(ccb);
1866 ap->ap_run_flags = ccb->ccb_xa.flags;
4c339a5f 1867 ccb = TAILQ_FIRST(&ap->ap_ccb_pending);
12feb904
MD
1868 } while (ccb && (ccb->ccb_xa.flags & ATA_F_NCQ) &&
1869 (ap->ap_run_flags &
1870 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0);
258223a3 1871
4c339a5f
MD
1872 ap->ap_sactive |= mask;
1873 ahci_pwrite(ap, AHCI_PREG_SACT, mask);
1874 ahci_pwrite(ap, AHCI_PREG_CI, mask);
1875 } else {
1980eff3 1876 /*
4c339a5f
MD
1877 * The next command is a standard command and can be issued
1878 * as long as currently active commands are not NCQ.
1879 *
1880 * We limit ourself to 1 command if we have a port multiplier,
1881 * (at least without FBSS support), otherwise timeouts on
1882 * one port can race completions on other ports (see
1883 * ahci_ata_cmd_timeout() for more information).
1884 *
1885 * If not on a port multiplier generally allow up to 4
1886 * standard commands to be enqueued. Remember that the
1887 * command processor will still process them sequentially.
1980eff3
MD
1888 */
1889 if (ap->ap_sactive)
258223a3 1890 return;
4c339a5f
MD
1891 if (ap->ap_type == ATA_PORT_T_PM)
1892 limit = 1;
1893 else if (ap->ap_sc->sc_ncmds > 4)
1894 limit = 4;
1895 else
1896 limit = 2;
258223a3 1897
4c339a5f
MD
1898 while (ap->ap_active_cnt < limit && ccb &&
1899 (ccb->ccb_xa.flags & ATA_F_NCQ) == 0) {
1900 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
12feb904
MD
1901#if 0
1902 fubar(ccb);
1903#endif
4c339a5f 1904 ap->ap_active |= 1 << ccb->ccb_slot;
1980eff3 1905 ap->ap_active_cnt++;
12feb904 1906 ap->ap_run_flags = ccb->ccb_xa.flags;
4c339a5f
MD
1907 ccb->ccb_xa.state = ATA_S_ONCHIP;
1908 ahci_pwrite(ap, AHCI_PREG_CI, 1 << ccb->ccb_slot);
12feb904 1909 ahci_start_timeout(ccb);
4c339a5f 1910 ccb = TAILQ_FIRST(&ap->ap_ccb_pending);
12feb904
MD
1911 if (ccb && (ccb->ccb_xa.flags &
1912 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE))) {
1913 break;
1914 }
1980eff3 1915 }
258223a3
MD
1916 }
1917}
1918
1919void
1920ahci_intr(void *arg)
1921{
f4553de1
MD
1922 struct ahci_softc *sc = arg;
1923 struct ahci_port *ap;
12feb904
MD
1924 u_int32_t is;
1925 u_int32_t ack;
f4553de1 1926 int port;
258223a3 1927
f4553de1
MD
1928 /*
1929 * Check if the master enable is up, and whether any interrupts are
1930 * pending.
1931 */
1932 if ((sc->sc_flags & AHCI_F_INT_GOOD) == 0)
1933 return;
258223a3 1934 is = ahci_read(sc, AHCI_REG_IS);
12feb904 1935 if (is == 0 || is == 0xffffffff) {
258223a3 1936 return;
12feb904
MD
1937 }
1938 is &= sc->sc_portmask;
258223a3
MD
1939
1940#ifdef AHCI_COALESCE
1941 /* Check coalescing interrupt first */
1942 if (is & sc->sc_ccc_mask) {
1943 DPRINTF(AHCI_D_INTR, "%s: command coalescing interrupt\n",
1944 DEVNAME(sc));
1945 is &= ~sc->sc_ccc_mask;
1946 is |= sc->sc_ccc_ports_cur;
1947 }
1948#endif
1949
f4553de1
MD
1950 /*
1951 * Process interrupts for each port in a non-blocking fashion.
12feb904
MD
1952 *
1953 * The global IS bit is forced on if any unmasked port interrupts
1954 * are pending, even if we clear.
f4553de1 1955 */
12feb904 1956 for (ack = 0; is; is &= ~(1 << port)) {
258223a3 1957 port = ffs(is) - 1;
12feb904
MD
1958 ack |= 1 << port;
1959
f4553de1 1960 ap = sc->sc_ports[port];
12feb904
MD
1961 if (ap == NULL)
1962 continue;
1963
1964 if (ahci_os_lock_port_nb(ap) == 0) {
1965 ahci_port_intr(ap, 0);
1966 ahci_os_unlock_port(ap);
1967 } else {
1968 ahci_pwrite(ap, AHCI_PREG_IE, 0);
1969 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT);
f4553de1 1970 }
258223a3 1971 }
258223a3
MD
1972 ahci_write(sc, AHCI_REG_IS, ack);
1973}
1974
f4553de1
MD
1975/*
1976 * Core called from helper thread.
1977 */
3209f581 1978void
f4553de1 1979ahci_port_thread_core(struct ahci_port *ap, int mask)
258223a3 1980{
f4553de1
MD
1981 /*
1982 * Process any expired timedouts.
1983 */
1984 ahci_os_lock_port(ap);
1985 if (mask & AP_SIGF_TIMEOUT) {
831bc9e3 1986 ahci_check_active_timeouts(ap);
f4553de1
MD
1987 }
1988
1989 /*
1990 * Process port interrupts which require a higher level of
1991 * intervention.
1992 */
1993 if (mask & AP_SIGF_PORTINT) {
1994 ahci_port_intr(ap, 1);
f4553de1 1995 ahci_port_interrupt_enable(ap);
831bc9e3 1996 ahci_os_unlock_port(ap);
12feb904
MD
1997 } else if (ap->ap_probe != ATA_PROBE_FAILED) {
1998 ahci_port_intr(ap, 1);
1999 ahci_port_interrupt_enable(ap);
2000 ahci_os_unlock_port(ap);
f4553de1
MD
2001 } else {
2002 ahci_os_unlock_port(ap);
2003 }
2004}
2005
2006/*
2007 * Core per-port interrupt handler.
2008 *
2009 * If blockable is 0 we cannot call ahci_os_sleep() at all and we can only
2010 * deal with normal command completions which do not require blocking.
2011 */
2012void
2013ahci_port_intr(struct ahci_port *ap, int blockable)
2014{
2015 struct ahci_softc *sc = ap->ap_sc;
2016 u_int32_t is, ci_saved, ci_masked;
2017 int slot;
2018 struct ahci_ccb *ccb = NULL;
2019 struct ata_port *ccb_at = NULL;
2020 volatile u_int32_t *active;
f4553de1
MD
2021 const u_int32_t blockable_mask = AHCI_PREG_IS_TFES |
2022 AHCI_PREG_IS_IFS |
2023 AHCI_PREG_IS_PCS |
2024 AHCI_PREG_IS_PRCS |
2025 AHCI_PREG_IS_HBFS |
2026 AHCI_PREG_IS_OFS |
2027 AHCI_PREG_IS_UFS;
2028
22181ab7
MD
2029 enum { NEED_NOTHING, NEED_RESTART, NEED_HOTPLUG_INSERT,
2030 NEED_HOTPLUG_REMOVE } need = NEED_NOTHING;
258223a3 2031
f4553de1
MD
2032 /*
2033 * All basic command completions are always processed.
2034 */
12feb904 2035 is = ahci_pread(ap, AHCI_PREG_IS);
cec07d75
MD
2036 if (is & AHCI_PREG_IS_DPS)
2037 ahci_pwrite(ap, AHCI_PREG_IS, is & AHCI_PREG_IS_DPS);
258223a3 2038
f4553de1
MD
2039 /*
2040 * If we can't block then we can't handle these here. Disable
2041 * the interrupts in question so we don't live-lock, the helper
2042 * thread will re-enable them.
2043 *
2044 * If the port is in a completely failed state we do not want
dbef6246 2045 * to drop through to failed-command-processing if blockable is 0,
f4553de1 2046 * just let the thread deal with it all.
dbef6246
MD
2047 *
2048 * Otherwise we fall through and still handle DHRS and any commands
2049 * which completed normally. Even if we are errored we haven't
2050 * stopped the port yet so CI/SACT are still good.
f4553de1
MD
2051 */
2052 if (blockable == 0) {
2053 if (ap->ap_state == AP_S_FATAL_ERROR) {
12feb904 2054 ahci_pwrite(ap, AHCI_PREG_IE, 0);
f4553de1
MD
2055 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT);
2056 return;
2057 }
2058 if (is & blockable_mask) {
12feb904 2059 ahci_pwrite(ap, AHCI_PREG_IE, 0);
f4553de1 2060 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT);
12feb904 2061 return;
f4553de1
MD
2062 }
2063 }
2064
3209f581 2065 /*
f4553de1 2066 * Either NCQ or non-NCQ commands will be active, never both.
3209f581 2067 */
258223a3 2068 if (ap->ap_sactive) {
258223a3
MD
2069 KKASSERT(ap->ap_active == 0);
2070 KKASSERT(ap->ap_active_cnt == 0);
2071 ci_saved = ahci_pread(ap, AHCI_PREG_SACT);
2072 active = &ap->ap_sactive;
2073 } else {
258223a3
MD
2074 ci_saved = ahci_pread(ap, AHCI_PREG_CI);
2075 active = &ap->ap_active;
2076 }
12feb904
MD
2077 KKASSERT(!(ap->ap_sactive && ap->ap_active));
2078#if 0
2079 kprintf("CHECK act=%08x/%08x sact=%08x/%08x\n",
2080 ap->ap_active, ahci_pread(ap, AHCI_PREG_CI),
2081 ap->ap_sactive, ahci_pread(ap, AHCI_PREG_SACT));
2082#endif
258223a3 2083
258223a3 2084 if (is & AHCI_PREG_IS_TFES) {
1980eff3 2085 /*
f4553de1
MD
2086 * Command failed (blockable).
2087 *
2088 * See AHCI 1.1 spec 6.2.2.1 and 6.2.2.2.
1980eff3
MD
2089 *
2090 * This stops command processing.
2091 */
2092 u_int32_t tfd, serr;
2093 int err_slot;
258223a3 2094
12feb904 2095process_error:
258223a3
MD
2096 tfd = ahci_pread(ap, AHCI_PREG_TFD);
2097 serr = ahci_pread(ap, AHCI_PREG_SERR);
2098
cf5f3a81 2099 /*
12feb904
MD
2100 * Load the error slot and restart command processing.
2101 * CLO if we need to. The error slot may not be valid.
2102 * MUST BE DONE BEFORE CLEARING ST!
2103 *
2104 * Cycle ST.
2105 *
2106 * It is unclear but we may have to clear SERR to reenable
2107 * error processing.
cf5f3a81 2108 */
12feb904
MD
2109 err_slot = AHCI_PREG_CMD_CCS(ahci_pread(ap, AHCI_PREG_CMD));
2110 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_TFES |
2111 AHCI_PREG_IS_PSS |
2112 AHCI_PREG_IS_DHRS |
2113 AHCI_PREG_IS_SDBS);
2114 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_PSS |
2115 AHCI_PREG_IS_DHRS | AHCI_PREG_IS_SDBS);
2116 ahci_pwrite(ap, AHCI_PREG_SERR, serr);
258223a3 2117 ahci_port_stop(ap, 0);
12feb904
MD
2118 ahci_os_hardsleep(10);
2119 if (tfd & (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
2120 kprintf("%s: Issuing CLO\n", PORTNAME(ap));
2121 ahci_port_clo(ap);
2122 }
2123 ahci_port_start(ap);
22181ab7 2124 need = NEED_RESTART;
258223a3 2125
12feb904
MD
2126 kprintf("%s: TFES slot %d ci_saved = %08x\n",
2127 PORTNAME(ap), err_slot, ci_saved);
2128
cf5f3a81 2129 /*
12feb904
MD
2130 * If we got an error on an error CCB just complete it
2131 * with an error. ci_saved has the mask to restart
2132 * (the err_ccb will be removed from it by finish_error).
cf5f3a81 2133 */
12feb904
MD
2134 if (ap->ap_flags & AP_F_ERR_CCB_RESERVED) {
2135 err_slot = ap->ap_err_ccb->ccb_slot;
2136 goto finish_error;
2137 }
258223a3 2138
12feb904
MD
2139 /*
2140 * If NCQ commands were active get the error slot from
2141 * the log page. NCQ is not supported for PM's so this
2142 * is a direct-attached target.
2143 *
2144 * Otherwise if no commands were active we have a problem.
2145 *
2146 * Otherwise if the error slot is bad we have a problem.
2147 *
2148 * Otherwise process the error for the slot.
2149 */
2150 if (ap->ap_sactive) {
2151 err_slot = ahci_port_read_ncq_error(ap, 0);
2152 } else if (ap->ap_active == 0) {
2153 kprintf("%s: TFES with no commands pending\n",
2154 PORTNAME(ap));
2155 err_slot = -1;
2156 } else if (err_slot < 0 || err_slot >= ap->ap_sc->sc_ncmds) {
2157 kprintf("%s: bad error slot %d\n",
2158 PORTNAME(ap), err_slot);
2159 err_slot = -1;
2160 } else {
2161 ccb = &ap->ap_ccbs[err_slot];
258223a3 2162
1980eff3 2163 /*
12feb904
MD
2164 * Validate the errored ccb. Note that ccb_at can
2165 * be NULL for direct-attached ccb's.
1980eff3 2166 *
12feb904 2167 * Copy received taskfile data from the RFIS.
1980eff3 2168 */
12feb904
MD
2169 if (ccb->ccb_xa.state == ATA_S_ONCHIP) {
2170 ccb_at = ccb->ccb_xa.at;
2171 memcpy(&ccb->ccb_xa.rfis, ap->ap_rfis->rfis,
2172 sizeof(struct ata_fis_d2h));
2173 kprintf("%s: Copying error rfis slot %d\n",
2174 ATANAME(ap, ccb_at), err_slot);
2175 } else {
2176 kprintf("%s: Cannot copy rfis, CCB slot "
2177 "%d is not on-chip (state=%d)\n",
2178 ATANAME(ap, ccb->ccb_xa.at),
2179 err_slot, ccb->ccb_xa.state);
2180 err_slot = -1;
258223a3 2181 }
258223a3
MD
2182 }
2183
2184 /*
12feb904
MD
2185 * If we could not determine the errored slot then
2186 * reset the port.
258223a3 2187 */
12feb904
MD
2188 if (err_slot < 0) {
2189 kprintf("%s: TFES: Unable to determine errored slot\n",
2190 PORTNAME(ap));
1980eff3
MD
2191 if (ap->ap_flags & AP_F_IN_RESET)
2192 goto fatal;
258223a3
MD
2193 goto failall;
2194 }
2195
12feb904
MD
2196 /*
2197 * Finish error on slot. We will restart ci_saved
2198 * commands except the errored slot which we generate
2199 * a failure for.
2200 */
2201finish_error:
2202 ccb = &ap->ap_ccbs[err_slot];
258223a3 2203 ci_saved &= ~(1 << err_slot);
258223a3
MD
2204 KKASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP);
2205 ccb->ccb_xa.state = ATA_S_ERROR;
1980eff3
MD
2206 } else if (is & AHCI_PREG_IS_DHRS) {
2207 /*
f4553de1
MD
2208 * Command posted D2H register FIS to the rfis (non-blocking).
2209 *
12feb904
MD
2210 * A normal completion with an error may set DHRS instead
2211 * of TFES. The CCS bits are only valid if ERR was set.
2212 * If ERR is set command processing was probably stopped.
8bf6a3ff 2213 *
12feb904
MD
2214 * If ERR was not set we can only copy-back data for
2215 * exclusive-mode commands because otherwise we won't know
2216 * which tag the rfis belonged to.
2217 *
2218 * err_slot must be read from the CCS before any other port
2219 * action, such as stopping the port.
2220 *
2221 * WARNING! This is not well documented in the AHCI spec.
2222 * It can be found in the state machine tables
2223 * but not in the explanations.
1980eff3 2224 */
12feb904
MD
2225 u_int32_t tfd;
2226 u_int32_t cmd;
2227 int err_slot;
2228
2229 tfd = ahci_pread(ap, AHCI_PREG_TFD);
2230 cmd = ahci_pread(ap, AHCI_PREG_CMD);
1980eff3 2231
12feb904
MD
2232 if ((tfd & AHCI_PREG_TFD_STS_ERR) &&
2233 (cmd & AHCI_PREG_CMD_CR) == 0) {
1980eff3 2234 err_slot = AHCI_PREG_CMD_CCS(
12feb904 2235 ahci_pread(ap, AHCI_PREG_CMD));
1980eff3 2236 ccb = &ap->ap_ccbs[err_slot];
12feb904
MD
2237 kprintf("%s: DHRS tfd=%b err_slot=%d cmd=%02x\n",
2238 PORTNAME(ap),
2239 tfd, AHCI_PFMT_TFD_STS,
2240 err_slot, ccb->ccb_xa.fis->command);
2241 goto process_error;
1980eff3 2242 }
12feb904
MD
2243 /*
2244 * NO ELSE... copy back is in the normal command completion
2245 * code and only if no error occured and ATA_F_AUTOSENSE
2246 * was set.
2247 */
cec07d75 2248 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_DHRS);
1980eff3
MD
2249 }
2250
2251 /*
f4553de1 2252 * Device notification to us (non-blocking)
1980eff3 2253 *
12feb904
MD
2254 * NOTE! On some parts notification bits can cause an IPMS
2255 * interrupt instead of a SDBS interrupt.
cec07d75 2256 *
12feb904
MD
2257 * NOTE! On some parts (e.g. VBOX, probably intel ICHx),
2258 * SDBS notifies us of the completion of a NCQ command
2259 * and DBS does not.
1980eff3 2260 */
12feb904 2261 if (is & (AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS)) {
1980eff3 2262 u_int32_t data;
cec07d75 2263
12feb904
MD
2264 ahci_pwrite(ap, AHCI_PREG_IS,
2265 AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS);
2266 if (sc->sc_cap & AHCI_REG_CAP_SSNTF) {
2267 data = ahci_pread(ap, AHCI_PREG_SNTF);
2268 if (data) {
2269 ahci_pwrite(ap, AHCI_PREG_IS,
2270 AHCI_PREG_IS_SDBS);
2271 kprintf("%s: NOTIFY %08x\n",
2272 PORTNAME(ap), data);
2273 ahci_pwrite(ap, AHCI_PREG_SERR,
2274 AHCI_PREG_SERR_DIAG_N);
2275 ahci_pwrite(ap, AHCI_PREG_SNTF, data);
2276 ahci_cam_changed(ap, NULL, -1);
2277 }
1980eff3 2278 }
12feb904 2279 is &= ~(AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS);
1980eff3 2280 }
3209f581
MD
2281
2282 /*
f4553de1
MD
2283 * Spurious IFS errors (blockable).
2284 *
3209f581
MD
2285 * Spurious IFS errors can occur while we are doing a reset
2286 * sequence through a PM. Try to recover if we are being asked
2287 * to ignore IFS errors during these periods.
2288 */
2289 if ((is & AHCI_PREG_IS_IFS) && (ap->ap_flags & AP_F_IGNORE_IFS)) {
1980eff3 2290 u_int32_t serr = ahci_pread(ap, AHCI_PREG_SERR);
3209f581
MD
2291 if ((ap->ap_flags & AP_F_IFS_IGNORED) == 0) {
2292 kprintf("%s: Ignoring IFS (XXX) (IS: %b, SERR: %b)\n",
2293 PORTNAME(ap),
2294 is, AHCI_PFMT_IS,
2295 serr, AHCI_PFMT_SERR);
2296 ap->ap_flags |= AP_F_IFS_IGNORED;
2297 }
2298 ap->ap_flags |= AP_F_IFS_OCCURED;
1980eff3
MD
2299 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
2300 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_IFS);
2301 is &= ~AHCI_PREG_IS_IFS;
2302 ahci_port_stop(ap, 0);
2303 ahci_port_start(ap);
12feb904
MD
2304 kprintf("%s: Spurious IFS error\n", PORTNAME(ap));
2305 goto failall;
2306 /* need = NEED_RESTART; */
258223a3
MD
2307 }
2308
2309 /*
f4553de1 2310 * Port change (hot-plug) (blockable).
258223a3
MD
2311 *
2312 * A PCS interrupt will occur on hot-plug once communication is
2313 * established.
2314 *
2315 * A PRCS interrupt will occur on hot-unplug (and possibly also
2316 * on hot-plug).
2317 *
22181ab7
MD
2318 * XXX We can then check the CPS (Cold Presence State) bit, if
2319 * supported, to determine if a device is plugged in or not and do
2320 * the right thing.
2321 *
2322 * WARNING: A PCS interrupt is cleared by clearing DIAG_X, and
2323 * can also occur if an unsolicited COMINIT is received.
2324 * If this occurs command processing is automatically
2325 * stopped (CR goes inactive) and the port must be stopped
2326 * and restarted.
258223a3
MD
2327 */
2328 if (is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)) {
12feb904
MD
2329 kprintf("%s: Transient Errors: %b\n",
2330 PORTNAME(ap), is, AHCI_PFMT_IS);
2331 ahci_pwrite(ap, AHCI_PREG_SERR,
2332 (AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_X));
cec07d75
MD
2333 ahci_pwrite(ap, AHCI_PREG_IS,
2334 is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS));
2335 is &= ~(AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS);
22181ab7 2336 ahci_port_stop(ap, 0);
258223a3
MD
2337 switch (ahci_pread(ap, AHCI_PREG_SSTS) & AHCI_PREG_SSTS_DET) {
2338 case AHCI_PREG_SSTS_DET_DEV:
12feb904 2339 if (ap->ap_probe == ATA_PROBE_FAILED) {
22181ab7
MD
2340 need = NEED_HOTPLUG_INSERT;
2341 goto fatal;
258223a3 2342 }
22181ab7 2343 need = NEED_RESTART;
258223a3
MD
2344 break;
2345 default:
12feb904 2346 if (ap->ap_type != ATA_PROBE_FAILED) {
22181ab7
MD
2347 need = NEED_HOTPLUG_REMOVE;
2348 goto fatal;
258223a3 2349 }
22181ab7 2350 need = NEED_RESTART;
258223a3
MD
2351 break;
2352 }
2353 }
2354
22181ab7 2355 /*
f4553de1 2356 * Check for remaining errors - they are fatal. (blockable)
22181ab7 2357 */
258223a3
MD
2358 if (is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | AHCI_PREG_IS_IFS |
2359 AHCI_PREG_IS_OFS | AHCI_PREG_IS_UFS)) {
cec07d75
MD
2360 u_int32_t serr;
2361
2362 ahci_pwrite(ap, AHCI_PREG_IS,
2363 is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2364 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2365 AHCI_PREG_IS_UFS));
cec07d75 2366 serr = ahci_pread(ap, AHCI_PREG_SERR);
831bc9e3 2367 kprintf("%s: Unrecoverable errors (IS: %b, SERR: %b), "
4444122d
MD
2368 "disabling port.\n",
2369 PORTNAME(ap),
2370 is, AHCI_PFMT_IS,
1980eff3 2371 serr, AHCI_PFMT_SERR
4444122d 2372 );
831bc9e3
MD
2373 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2374 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2375 AHCI_PREG_IS_UFS);
258223a3
MD
2376 /* XXX try recovery first */
2377 goto fatal;
2378 }
2379
22181ab7
MD
2380 /*
2381 * Fail all outstanding commands if we know the port won't recover.
1980eff3
MD
2382 *
2383 * We may have a ccb_at if the failed command is known and was
2384 * being sent to a device over a port multiplier (PM). In this
2385 * case if the port itself has not completely failed we fail just
2386 * the commands related to that target.
12feb904
MD
2387 *
2388 * ci_saved contains the mask of active commands as of when the
2389 * error occured, prior to any port stops.
22181ab7 2390 */
258223a3
MD
2391 if (ap->ap_state == AP_S_FATAL_ERROR) {
2392fatal:
2393 ap->ap_state = AP_S_FATAL_ERROR;
cf5f3a81 2394 ahci_port_stop(ap, 0);
12feb904
MD
2395failall:
2396 kprintf("%s: Failing all commands\n", PORTNAME(ap));
258223a3 2397
1980eff3 2398 /*
12feb904
MD
2399 * Error all the active slots not already errored. If
2400 * running across a PM try to error out just the slots
2401 * related to the target.
1980eff3 2402 */
12feb904 2403 ci_masked = ci_saved & *active & ~ap->ap_expired;
258223a3
MD
2404 while (ci_masked) {
2405 slot = ffs(ci_masked) - 1;
2406 ccb = &ap->ap_ccbs[slot];
1980eff3
MD
2407 if (ccb_at == ccb->ccb_xa.at ||
2408 ap->ap_state == AP_S_FATAL_ERROR) {
12feb904
MD
2409 ccb->ccb_xa.state = ATA_S_TIMEOUT;
2410 ap->ap_expired |= 1 << slot;
2411 ci_saved &= ~(1 << slot);
1980eff3 2412 }
12feb904 2413 ci_masked &= ~(1 << slot);
258223a3
MD
2414 }
2415
12feb904
MD
2416 /*
2417 * Clear bits in ci_saved (cause completions to be run)
2418 * for all slots which are not active.
2419 */
258223a3
MD
2420 ci_saved &= ~*active;
2421
2422 /*
2423 * Don't restart the port if our problems were deemed fatal.
2424 *
2425 * Also acknowlege all fatal interrupt sources to prevent
2426 * a livelock.
2427 */
2428 if (ap->ap_state == AP_S_FATAL_ERROR) {
22181ab7
MD
2429 if (need == NEED_RESTART)
2430 need = NEED_NOTHING;
258223a3
MD
2431 ahci_pwrite(ap, AHCI_PREG_IS,
2432 AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2433 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2434 AHCI_PREG_IS_UFS);
2435 }
2436 }
2437
2438 /*
f4553de1
MD
2439 * CCB completion (non blocking).
2440 *
258223a3
MD
2441 * CCB completion is detected by noticing its slot's bit in CI has
2442 * changed to zero some time after we activated it.
2443 * If we are polling, we may only be interested in particular slot(s).
cf5f3a81
MD
2444 *
2445 * Any active bits not saved are completed within the restrictions
2446 * imposed by the caller.
258223a3 2447 */
3209f581 2448 ci_masked = ~ci_saved & *active;
258223a3
MD
2449 while (ci_masked) {
2450 slot = ffs(ci_masked) - 1;
2451 ccb = &ap->ap_ccbs[slot];
2452 ci_masked &= ~(1 << slot);
2453
2454 DPRINTF(AHCI_D_INTR, "%s: slot %d is complete%s\n",
2455 PORTNAME(ap), slot, ccb->ccb_xa.state == ATA_S_ERROR ?
2456 " (error)" : "");
2457
2458 bus_dmamap_sync(sc->sc_tag_cmdh,
2459 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list),
2460 BUS_DMASYNC_POSTWRITE);
2461
2462 bus_dmamap_sync(sc->sc_tag_cmdt,
2463 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table),
2464 BUS_DMASYNC_POSTWRITE);
2465
2466 bus_dmamap_sync(sc->sc_tag_rfis,
2467 AHCI_DMA_MAP(ap->ap_dmamem_rfis),
2468 BUS_DMASYNC_POSTREAD);
2469
2470 *active &= ~(1 << ccb->ccb_slot);
1980eff3
MD
2471 if (active == &ap->ap_active) {
2472 KKASSERT(ap->ap_active_cnt > 0);
2473 --ap->ap_active_cnt;
2474 }
4c339a5f
MD
2475
2476 /*
2477 * Complete the ccb. If the ccb was marked expired it
2478 * was probably already removed from the command processor,
2479 * so don't take the clear ci_saved bit as meaning the
2480 * command actually succeeded, it didn't.
2481 */
2482 if (ap->ap_expired & (1 << ccb->ccb_slot)) {
76497a9c 2483 ap->ap_expired &= ~(1 << ccb->ccb_slot);
4c339a5f
MD
2484 ccb->ccb_xa.state = ATA_S_TIMEOUT;
2485 ccb->ccb_done(ccb);
2486 ccb->ccb_xa.complete(&ccb->ccb_xa);
2487 } else {
12feb904 2488 if (ccb->ccb_xa.state == ATA_S_ONCHIP) {
4c339a5f 2489 ccb->ccb_xa.state = ATA_S_COMPLETE;
12feb904
MD
2490 if (ccb->ccb_xa.flags & ATA_F_AUTOSENSE) {
2491 memcpy(&ccb->ccb_xa.rfis,
2492 ap->ap_rfis->rfis,
2493 sizeof(struct ata_fis_d2h));
2494 if (ccb->ccb_xa.state == ATA_S_TIMEOUT)
2495 ccb->ccb_xa.state = ATA_S_ERROR;
2496 }
2497 }
4c339a5f
MD
2498 ccb->ccb_done(ccb);
2499 }
258223a3 2500 }
12feb904 2501 ahci_issue_pending_commands(ap, NULL);
258223a3 2502
f4553de1
MD
2503 /*
2504 * Cleanup. Will not be set if non-blocking.
2505 */
22181ab7
MD
2506 switch(need) {
2507 case NEED_RESTART:
2508 /*
2509 * A recoverable error occured and we can restart outstanding
2510 * commands on the port.
2511 */
12feb904 2512 ci_saved &= ~ap->ap_expired;
258223a3 2513 if (ci_saved) {
12feb904 2514 kprintf("%s: Restart %08x\n", PORTNAME(ap), ci_saved);
4c339a5f 2515 ahci_issue_saved_commands(ap, ci_saved);
258223a3 2516 }
22181ab7
MD
2517 break;
2518 case NEED_HOTPLUG_INSERT:
2519 /*
cf5f3a81
MD
2520 * A hot-plug insertion event has occured and all
2521 * outstanding commands have already been revoked.
1980eff3
MD
2522 *
2523 * Don't recurse if this occurs while we are
2524 * resetting the port.
22181ab7 2525 */
1980eff3
MD
2526 if ((ap->ap_flags & AP_F_IN_RESET) == 0) {
2527 kprintf("%s: HOTPLUG - Device inserted\n",
2528 PORTNAME(ap));
3209f581
MD
2529 ap->ap_probe = ATA_PROBE_NEED_INIT;
2530 ahci_cam_changed(ap, NULL, -1);
1980eff3 2531 }
22181ab7
MD
2532 break;
2533 case NEED_HOTPLUG_REMOVE:
cf5f3a81
MD
2534 /*
2535 * A hot-plug removal event has occured and all
2536 * outstanding commands have already been revoked.
1980eff3
MD
2537 *
2538 * Don't recurse if this occurs while we are
2539 * resetting the port.
cf5f3a81 2540 */
1980eff3
MD
2541 if ((ap->ap_flags & AP_F_IN_RESET) == 0) {
2542 kprintf("%s: HOTPLUG - Device removed\n",
2543 PORTNAME(ap));
2544 ahci_port_hardstop(ap);
3209f581
MD
2545 /* ap_probe set to failed */
2546 ahci_cam_changed(ap, NULL, -1);
1980eff3 2547 }
22181ab7
MD
2548 break;
2549 default:
2550 break;
258223a3 2551 }
258223a3
MD
2552}
2553
2554struct ahci_ccb *
2555ahci_get_ccb(struct ahci_port *ap)
2556{
2557 struct ahci_ccb *ccb;
2558
2559 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE);
2560 ccb = TAILQ_FIRST(&ap->ap_ccb_free);
2561 if (ccb != NULL) {
2562 KKASSERT(ccb->ccb_xa.state == ATA_S_PUT);
2563 TAILQ_REMOVE(&ap->ap_ccb_free, ccb, ccb_entry);
2564 ccb->ccb_xa.state = ATA_S_SETUP;
1980eff3 2565 ccb->ccb_xa.at = NULL;
258223a3
MD
2566 }
2567 lockmgr(&ap->ap_ccb_lock, LK_RELEASE);
2568
2569 return (ccb);
2570}
2571
2572void
2573ahci_put_ccb(struct ahci_ccb *ccb)
2574{
2575 struct ahci_port *ap = ccb->ccb_port;
2576
258223a3
MD
2577 ccb->ccb_xa.state = ATA_S_PUT;
2578 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE);
2579 TAILQ_INSERT_TAIL(&ap->ap_ccb_free, ccb, ccb_entry);
2580 lockmgr(&ap->ap_ccb_lock, LK_RELEASE);
2581}
2582
2583struct ahci_ccb *
2584ahci_get_err_ccb(struct ahci_port *ap)
2585{
2586 struct ahci_ccb *err_ccb;
2587 u_int32_t sact;
2588
2589 /* No commands may be active on the chip. */
2590 sact = ahci_pread(ap, AHCI_PREG_SACT);
2591 if (sact != 0)
2592 kprintf("ahci_get_err_ccb but SACT %08x != 0?\n", sact);
2593 KKASSERT(ahci_pread(ap, AHCI_PREG_CI) == 0);
baef7501
MD
2594 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) == 0);
2595 ap->ap_flags |= AP_F_ERR_CCB_RESERVED;
258223a3 2596
258223a3
MD
2597 /* Save outstanding command state. */
2598 ap->ap_err_saved_active = ap->ap_active;
2599 ap->ap_err_saved_active_cnt = ap->ap_active_cnt;
2600 ap->ap_err_saved_sactive = ap->ap_sactive;
2601
2602 /*
2603 * Pretend we have no commands outstanding, so that completions won't
2604 * run prematurely.
2605 */
2606 ap->ap_active = ap->ap_active_cnt = ap->ap_sactive = 0;
2607
2608 /*
2609 * Grab a CCB to use for error recovery. This should never fail, as
2610 * we ask atascsi to reserve one for us at init time.
2611 */
1067474a 2612 err_ccb = ap->ap_err_ccb;
258223a3
MD
2613 KKASSERT(err_ccb != NULL);
2614 err_ccb->ccb_xa.flags = 0;
2615 err_ccb->ccb_done = ahci_empty_done;
2616
2617 return err_ccb;
2618}
2619
2620void
2621ahci_put_err_ccb(struct ahci_ccb *ccb)
2622{
2623 struct ahci_port *ap = ccb->ccb_port;
2624 u_int32_t sact;
5f8c1efd 2625 u_int32_t ci;
258223a3 2626
baef7501
MD
2627 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) != 0);
2628
5f8c1efd
MD
2629 /*
2630 * No commands may be active on the chip
2631 */
258223a3 2632 sact = ahci_pread(ap, AHCI_PREG_SACT);
5f8c1efd
MD
2633 if (sact) {
2634 panic("ahci_port_err_ccb(%d) but SACT %08x != 0\n",
2635 ccb->ccb_slot, sact);
2636 }
2637 ci = ahci_pread(ap, AHCI_PREG_CI);
2638 if (ci) {
cf5f3a81
MD
2639 panic("ahci_put_err_ccb(%d) but CI %08x != 0 "
2640 "(act=%08x sact=%08x)\n",
2641 ccb->ccb_slot, ci,
2642 ap->ap_active, ap->ap_sactive);
258223a3 2643 }
258223a3 2644
1067474a 2645 KKASSERT(ccb == ap->ap_err_ccb);
258223a3
MD
2646
2647 /* Restore outstanding command state */
2648 ap->ap_sactive = ap->ap_err_saved_sactive;
2649 ap->ap_active_cnt = ap->ap_err_saved_active_cnt;
2650 ap->ap_active = ap->ap_err_saved_active;
2651
baef7501 2652 ap->ap_flags &= ~AP_F_ERR_CCB_RESERVED;
258223a3
MD
2653}
2654
1980eff3
MD
2655/*
2656 * Read log page to get NCQ error.
2657 *
2658 * NOTE: NCQ not currently supported on port multipliers. XXX
2659 */
258223a3 2660int
12feb904 2661ahci_port_read_ncq_error(struct ahci_port *ap, int target)
258223a3 2662{
12feb904
MD
2663 struct ata_log_page_10h *log;
2664 struct ahci_ccb *ccb;
2665 struct ahci_cmd_hdr *cmd_slot;
2666 struct ata_fis_h2d *fis;
2667 int err_slot;
258223a3 2668
12feb904
MD
2669 if (bootverbose) {
2670 kprintf("%s: READ LOG PAGE target %d\n", PORTNAME(ap),
2671 target);
2672 }
258223a3 2673
12feb904
MD
2674 /*
2675 * Prep error CCB for READ LOG EXT, page 10h, 1 sector.
2676 *
2677 * Getting err_ccb clears active/sactive/active_cnt, putting
2678 * it back restores the fields.
2679 */
258223a3 2680 ccb = ahci_get_err_ccb(ap);
12feb904 2681 ccb->ccb_xa.flags = ATA_F_READ | ATA_F_POLL;
258223a3
MD
2682 ccb->ccb_xa.data = ap->ap_err_scratch;
2683 ccb->ccb_xa.datalen = 512;
12feb904
MD
2684 ccb->ccb_xa.complete = ahci_dummy_done;
2685 ccb->ccb_xa.at = &ap->ap_ata[target];
258223a3
MD
2686
2687 fis = (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis;
12feb904 2688 bzero(fis, sizeof(*fis));
258223a3 2689 fis->type = ATA_FIS_TYPE_H2D;
12feb904 2690 fis->flags = ATA_H2D_FLAGS_CMD | target;
258223a3
MD
2691 fis->command = ATA_C_READ_LOG_EXT;
2692 fis->lba_low = 0x10; /* queued error log page (10h) */
2693 fis->sector_count = 1; /* number of sectors (1) */
2694 fis->sector_count_exp = 0;
2695 fis->lba_mid = 0; /* starting offset */
2696 fis->lba_mid_exp = 0;
2697 fis->device = 0;
2698
12feb904 2699 cmd_slot = ccb->ccb_cmd_hdr;
258223a3
MD
2700 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
2701
2702 if (ahci_load_prdt(ccb) != 0) {
12feb904 2703 err_slot = -1;
258223a3
MD
2704 goto err;
2705 }
2706
2707 ccb->ccb_xa.state = ATA_S_PENDING;
12feb904
MD
2708 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) {
2709 err_slot = -1;
2710 ahci_unload_prdt(ccb);
258223a3 2711 goto err;
258223a3 2712 }
258223a3 2713 ahci_unload_prdt(ccb);
258223a3 2714
12feb904
MD
2715 /*
2716 * Success, extract failed register set and tags from the scratch
2717 * space.
2718 */
2719 log = (struct ata_log_page_10h *)ap->ap_err_scratch;
2720 if (log->err_regs.type & ATA_LOG_10H_TYPE_NOTQUEUED) {
2721 /* Not queued bit was set - wasn't an NCQ error? */
2722 kprintf("%s: read NCQ error page, but not an NCQ error?\n",
2723 PORTNAME(ap));
2724 err_slot = -1;
2725 } else {
2726 /* Copy back the log record as a D2H register FIS. */
2727 err_slot = log->err_regs.type & ATA_LOG_10H_TYPE_TAG_MASK;
258223a3 2728
12feb904
MD
2729 ccb = &ap->ap_ccbs[err_slot];
2730 if (ccb->ccb_xa.state == ATA_S_ONCHIP) {
2731 kprintf("%s: read NCQ error page slot=%d\n",
2732 ATANAME(ap, ccb->ccb_xa.at),
2733 err_slot);
258223a3 2734 memcpy(&ccb->ccb_xa.rfis, &log->err_regs,
12feb904 2735 sizeof(struct ata_fis_d2h));
258223a3
MD
2736 ccb->ccb_xa.rfis.type = ATA_FIS_TYPE_D2H;
2737 ccb->ccb_xa.rfis.flags = 0;
12feb904
MD
2738 } else {
2739 kprintf("%s: read NCQ error page slot=%d, "
2740 "slot does not match any cmds\n",
2741 ATANAME(ccb->ccb_port, ccb->ccb_xa.at),
2742 err_slot);
2743 err_slot = -1;
258223a3
MD
2744 }
2745 }
12feb904
MD
2746err:
2747 ahci_put_err_ccb(ccb);
2748 kprintf("%s: DONE log page target %d err_slot=%d\n",
2749 PORTNAME(ap), target, err_slot);
2750 return (err_slot);
258223a3
MD
2751}
2752
2753/*
2754 * Allocate memory for various structures DMAd by hardware. The maximum
2755 * number of segments for these tags is 1 so the DMA memory will have a
2756 * single physical base address.
2757 */
2758struct ahci_dmamem *
2759ahci_dmamem_alloc(struct ahci_softc *sc, bus_dma_tag_t tag)
2760{
2761 struct ahci_dmamem *adm;
2762 int error;
2763
2764 adm = kmalloc(sizeof(*adm), M_DEVBUF, M_INTWAIT | M_ZERO);
2765
2766 error = bus_dmamem_alloc(tag, (void **)&adm->adm_kva,
2767 BUS_DMA_ZERO, &adm->adm_map);
2768 if (error == 0) {
2769 adm->adm_tag = tag;
2770 error = bus_dmamap_load(tag, adm->adm_map,
2771 adm->adm_kva,
2772 bus_dma_tag_getmaxsize(tag),
2773 ahci_dmamem_saveseg, &adm->adm_busaddr,
2774 0);
2775 }
2776 if (error) {
2777 if (adm->adm_map) {
2778 bus_dmamap_destroy(tag, adm->adm_map);
2779 adm->adm_map = NULL;
2780 adm->adm_tag = NULL;
2781 adm->adm_kva = NULL;
2782 }
2783 kfree(adm, M_DEVBUF);
2784 adm = NULL;
2785 }
2786 return (adm);
2787}
2788
2789static
2790void
2791ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error)
2792{
2793 KKASSERT(error == 0);
2794 KKASSERT(nsegs == 1);
2795 *(bus_addr_t *)info = segs->ds_addr;
2796}
2797
2798
2799void
2800ahci_dmamem_free(struct ahci_softc *sc, struct ahci_dmamem *adm)
2801{
2802 if (adm->adm_map) {
2803 bus_dmamap_unload(adm->adm_tag, adm->adm_map);
2804 bus_dmamap_destroy(adm->adm_tag, adm->adm_map);
2805 adm->adm_map = NULL;
2806 adm->adm_tag = NULL;
2807 adm->adm_kva = NULL;
2808 }
2809 kfree(adm, M_DEVBUF);
2810}
2811
2812u_int32_t
2813ahci_read(struct ahci_softc *sc, bus_size_t r)
2814{
2815 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4,
2816 BUS_SPACE_BARRIER_READ);
2817 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r));
2818}
2819
2820void
2821ahci_write(struct ahci_softc *sc, bus_size_t r, u_int32_t v)
2822{
2823 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v);
2824 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4,
2825 BUS_SPACE_BARRIER_WRITE);
2826}
2827
258223a3
MD
2828u_int32_t
2829ahci_pread(struct ahci_port *ap, bus_size_t r)
2830{
2831 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4,
2832 BUS_SPACE_BARRIER_READ);
2833 return (bus_space_read_4(ap->ap_sc->sc_iot, ap->ap_ioh, r));
2834}
2835
2836void
2837ahci_pwrite(struct ahci_port *ap, bus_size_t r, u_int32_t v)
2838{
2839 bus_space_write_4(ap->ap_sc->sc_iot, ap->ap_ioh, r, v);
2840 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4,
2841 BUS_SPACE_BARRIER_WRITE);
2842}
2843
831bc9e3
MD
2844/*
2845 * Wait up to (timeout) milliseconds for the masked port register to
2846 * match the target.
2847 *
2848 * Timeout is in milliseconds.
2849 */
258223a3 2850int
cec85a37
MD
2851ahci_pwait_eq(struct ahci_port *ap, int timeout,
2852 bus_size_t r, u_int32_t mask, u_int32_t target)
258223a3 2853{
831bc9e3 2854 int t;
258223a3 2855
831bc9e3
MD
2856 /*
2857 * Loop hard up to 100uS
2858 */
2859 for (t = 0; t < 100; ++t) {
258223a3
MD
2860 if ((ahci_pread(ap, r) & mask) == target)
2861 return (0);
831bc9e3 2862 ahci_os_hardsleep(1); /* us */
258223a3
MD
2863 }
2864
831bc9e3
MD
2865 do {
2866 timeout -= ahci_os_softsleep();
2867 if ((ahci_pread(ap, r) & mask) == target)
2868 return (0);
2869 } while (timeout > 0);
258223a3
MD
2870 return (1);
2871}
2872
831bc9e3
MD
2873int
2874ahci_wait_ne(struct ahci_softc *sc, bus_size_t r, u_int32_t mask,
2875 u_int32_t target)
2876{
2877 int t;
2878
2879 /*
2880 * Loop hard up to 100uS
2881 */
2882 for (t = 0; t < 100; ++t) {
2883 if ((ahci_read(sc, r) & mask) != target)
2884 return (0);
2885 ahci_os_hardsleep(1); /* us */
2886 }
2887
2888 /*
2889 * And one millisecond the slow way
2890 */
2891 t = 1000;
2892 do {
2893 t -= ahci_os_softsleep();
2894 if ((ahci_read(sc, r) & mask) != target)
2895 return (0);
2896 } while (t > 0);
2897
2898 return (1);
2899}
2900
2901
1980eff3
MD
2902/*
2903 * Acquire an ata transfer.
2904 *
2905 * Pass a NULL at for direct-attached transfers, and a non-NULL at for
2906 * targets that go through the port multiplier.
2907 */
258223a3 2908struct ata_xfer *
1980eff3 2909ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at)
258223a3 2910{
258223a3
MD
2911 struct ahci_ccb *ccb;
2912
2913 ccb = ahci_get_ccb(ap);
2914 if (ccb == NULL) {
2915 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer: NULL ccb\n",
2916 PORTNAME(ap));
2917 return (NULL);
2918 }
2919
2920 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer got slot %d\n",
2921 PORTNAME(ap), ccb->ccb_slot);
2922
2cc2e845 2923 bzero(ccb->ccb_xa.fis, sizeof(*ccb->ccb_xa.fis));
1980eff3 2924 ccb->ccb_xa.at = at;
258223a3
MD
2925 ccb->ccb_xa.fis->type = ATA_FIS_TYPE_H2D;
2926
2927 return (&ccb->ccb_xa);
2928}
2929
2930void
2931ahci_ata_put_xfer(struct ata_xfer *xa)
2932{
2933 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
2934
2935 DPRINTF(AHCI_D_XFER, "ahci_ata_put_xfer slot %d\n", ccb->ccb_slot);
2936
2937 ahci_put_ccb(ccb);
2938}
2939
2940int
2941ahci_ata_cmd(struct ata_xfer *xa)
2942{
2943 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
2944 struct ahci_cmd_hdr *cmd_slot;
2945
2946 KKASSERT(xa->state == ATA_S_SETUP);
2947
2948 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR)
2949 goto failcmd;
258223a3
MD
2950 ccb->ccb_done = ahci_ata_cmd_done;
2951
2952 cmd_slot = ccb->ccb_cmd_hdr;
2953 cmd_slot->flags = htole16(5); /* FIS length (in DWORDs) */
1980eff3
MD
2954 if (ccb->ccb_xa.at) {
2955 cmd_slot->flags |= htole16(ccb->ccb_xa.at->at_target <<
2956 AHCI_CMD_LIST_FLAG_PMP_SHIFT);
2957 }
258223a3
MD
2958
2959 if (xa->flags & ATA_F_WRITE)
2960 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_W);
2961
2962 if (xa->flags & ATA_F_PACKET)
2963 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_A);
2964
2965 if (ahci_load_prdt(ccb) != 0)
2966 goto failcmd;
2967
2968 xa->state = ATA_S_PENDING;
2969
831bc9e3
MD
2970 if (xa->flags & ATA_F_POLL)
2971 return (ahci_poll(ccb, xa->timeout, ahci_ata_cmd_timeout));
258223a3
MD
2972
2973 crit_enter();
f4553de1 2974 KKASSERT((xa->flags & ATA_F_TIMEOUT_EXPIRED) == 0);
3209f581 2975 xa->flags |= ATA_F_TIMEOUT_DESIRED;
258223a3
MD
2976 ahci_start(ccb);
2977 crit_exit();
831bc9e3 2978 return (xa->state);
258223a3
MD
2979
2980failcmd:
2981 crit_enter();
2982 xa->state = ATA_S_ERROR;
2983 xa->complete(xa);
2984 crit_exit();
831bc9e3 2985 return (ATA_S_ERROR);
258223a3
MD
2986}
2987
2988void
2989ahci_ata_cmd_done(struct ahci_ccb *ccb)
2990{
2991 struct ata_xfer *xa = &ccb->ccb_xa;
2992
831bc9e3
MD
2993 /*
2994 * NOTE: callout does not lock port and may race us modifying
2995 * the flags, so make sure its stopped.
2996 */
258223a3 2997 if (xa->flags & ATA_F_TIMEOUT_RUNNING) {
258223a3 2998 callout_stop(&ccb->ccb_timeout);
831bc9e3 2999 xa->flags &= ~ATA_F_TIMEOUT_RUNNING;
258223a3 3000 }
f4553de1 3001 xa->flags &= ~(ATA_F_TIMEOUT_DESIRED | ATA_F_TIMEOUT_EXPIRED);
258223a3 3002
4c339a5f 3003 KKASSERT(xa->state != ATA_S_ONCHIP);
258223a3
MD
3004 ahci_unload_prdt(ccb);
3005
258223a3
MD
3006 if (xa->state != ATA_S_TIMEOUT)
3007 xa->complete(xa);
3008}
3009
f4553de1
MD
3010/*
3011 * Timeout from callout, MPSAFE - nothing can mess with the CCB's flags
3012 * while the callout is runing.
3013 *
3014 * We can't safely get the port lock here or delay, we could block
3015 * the callout thread.
3016 */
258223a3
MD
3017static void
3018ahci_ata_cmd_timeout_unserialized(void *arg)
3019{
3020 struct ahci_ccb *ccb = arg;
3021 struct ahci_port *ap = ccb->ccb_port;
3022
f4553de1
MD
3023 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING;
3024 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_EXPIRED;
3025 ahci_os_signal_port_thread(ap, AP_SIGF_TIMEOUT);
258223a3
MD
3026}
3027
4c339a5f
MD
3028/*
3029 * Timeout code, typically called when the port command processor is running.
3030 *
3031 * We have to be very very careful here. We cannot stop the port unless
3032 * CR is already clear or the only active commands remaining are timed-out
3033 * ones. Otherwise stopping the port will race the command processor and
3034 * we can lose events. While we can theoretically just restart everything
3035 * that could result in a double-issue which will not work for ATAPI commands.
3036 */
1980eff3 3037void
831bc9e3 3038ahci_ata_cmd_timeout(struct ahci_ccb *ccb)
258223a3 3039{
258223a3
MD
3040 struct ata_xfer *xa = &ccb->ccb_xa;
3041 struct ahci_port *ap = ccb->ccb_port;
4c339a5f
MD
3042 struct ata_port *at;
3043 int ci_saved;
3044 int slot;
258223a3 3045
4c339a5f
MD
3046 at = ccb->ccb_xa.at;
3047
3048 kprintf("%s: CMD TIMEOUT state=%d slot=%d\n"
3049 "\tcmd-reg 0x%b\n"
3050 "\tsactive=%08x active=%08x expired=%08x\n"
08fb24a7
MD
3051 "\t sact=%08x ci=%08x\n"
3052 "\t STS=%b\n",
4c339a5f
MD
3053 ATANAME(ap, at),
3054 ccb->ccb_xa.state, ccb->ccb_slot,
258223a3 3055 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD,
4c339a5f 3056 ap->ap_sactive, ap->ap_active, ap->ap_expired,
258223a3 3057 ahci_pread(ap, AHCI_PREG_SACT),
08fb24a7
MD
3058 ahci_pread(ap, AHCI_PREG_CI),
3059 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS
3060 );
3061
258223a3 3062
9e145b23
MD
3063 /*
3064 * NOTE: Timeout will not be running if the command was polled.
3209f581 3065 * If we got here at least one of these flags should be set.
9e145b23 3066 */
3209f581
MD
3067 KKASSERT(xa->flags & (ATA_F_POLL | ATA_F_TIMEOUT_DESIRED |
3068 ATA_F_TIMEOUT_RUNNING));
f4553de1 3069 xa->flags &= ~(ATA_F_TIMEOUT_RUNNING | ATA_F_TIMEOUT_EXPIRED);
258223a3
MD
3070
3071 if (ccb->ccb_xa.state == ATA_S_PENDING) {
258223a3 3072 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
4c339a5f 3073 ccb->ccb_xa.state = ATA_S_TIMEOUT;
258223a3 3074 ccb->ccb_done(ccb);
4c339a5f
MD
3075 xa->complete(xa);
3076 ahci_issue_pending_commands(ap, NULL);
3077 return;
3078 }
3079 if (ccb->ccb_xa.state != ATA_S_ONCHIP) {
3080 kprintf("%s: Unexpected state during timeout: %d\n",
3081 ATANAME(ap, at), ccb->ccb_xa.state);
3082 return;
258223a3
MD
3083 }
3084
4c339a5f
MD
3085 /*
3086 * Ok, we can only get this command off the chip if CR is inactive
3087 * or if the only commands running on the chip are all expired.
3088 * Otherwise we have to wait until the port is in a safe state.
3089 *
3090 * Do not set state here, it will cause polls to return when the
3091 * ccb is not yet off the chip.
3092 */
3093 ap->ap_expired |= 1 << ccb->ccb_slot;
3094
3095 if ((ahci_pread(ap, AHCI_PREG_CMD) & AHCI_PREG_CMD_CR) &&
3096 (ap->ap_active | ap->ap_sactive) != ap->ap_expired) {
3097 /*
3098 * If using FBSS or NCQ we can't safely stop the port
3099 * right now.
3100 */
3101 kprintf("%s: Deferred timeout until its safe, slot %d\n",
3102 ATANAME(ap, at), ccb->ccb_slot);
3103 return;
1980eff3 3104 }
4c339a5f
MD
3105
3106 /*
3107 * We can safely stop the port and process all expired ccb's,
3108 * which will include our current ccb.
3109 */
3110 ci_saved = (ap->ap_sactive) ? ahci_pread(ap, AHCI_PREG_SACT) :
3111 ahci_pread(ap, AHCI_PREG_CI);
3112 ahci_port_stop(ap, 0);
3113
3114 while (ap->ap_expired) {
3115 slot = ffs(ap->ap_expired) - 1;
3116 ap->ap_expired &= ~(1 << slot);
3117 ci_saved &= ~(1 << slot);
3118 ccb = &ap->ap_ccbs[slot];
3119 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3120 if (ccb->ccb_xa.flags & ATA_F_NCQ) {
3121 KKASSERT(ap->ap_sactive & (1 << slot));
3122 ap->ap_sactive &= ~(1 << slot);
cf5f3a81 3123 } else {
4c339a5f
MD
3124 KKASSERT(ap->ap_active & (1 << slot));
3125 ap->ap_active &= ~(1 << slot);
3126 --ap->ap_active_cnt;
258223a3 3127 }
4c339a5f
MD
3128 ccb->ccb_done(ccb);
3129 ccb->ccb_xa.complete(&ccb->ccb_xa);
258223a3 3130 }
4c339a5f 3131 /* ccb invalid now */
258223a3 3132
4c339a5f
MD
3133 /*
3134 * We can safely CLO the port to clear any BSY/DRQ, a case which
3135 * can occur with port multipliers. This will unbrick the port
3136 * and allow commands to other targets behind the PM continue.
3137 * (FBSS).
3138 *
3139 * Finally, once the port has been restarted we can issue any
3140 * previously saved pending commands, and run the port interrupt
3141 * code to handle any completions which may have occured when
3142 * we saved CI.
3143 */
3144 if (ahci_pread(ap, AHCI_PREG_TFD) &
3145 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
3146 kprintf("%s: Warning, issuing CLO after timeout\n",
3147 ATANAME(ap, at));
3148 ahci_port_clo(ap);
3149 }
3150 ahci_port_start(ap);
3151 ahci_issue_saved_commands(ap, ci_saved & ~ap->ap_expired);
3152 ahci_issue_pending_commands(ap, NULL);
3153 ahci_port_intr(ap, 0);
3154}
258223a3 3155
4c339a5f
MD
3156/*
3157 * Issue a previously saved set of commands
3158 */
3159void
3160ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t ci_saved)
3161{
3162 if (ci_saved) {
3163 KKASSERT(!((ap->ap_active & ci_saved) &&
3164 (ap->ap_sactive & ci_saved)));
3165 KKASSERT((ci_saved & ap->ap_expired) == 0);
3166 if (ap->ap_sactive & ci_saved)
3167 ahci_pwrite(ap, AHCI_PREG_SACT, ci_saved);
3168 ahci_pwrite(ap, AHCI_PREG_CI, ci_saved);
3169 }
258223a3
MD
3170}
3171
831bc9e3
MD
3172/*
3173 * Used by the softreset, pmprobe, and read_ncq_error only, in very
3174 * specialized, controlled circumstances.
3175 *
3176 * Only one command may be pending.
3177 */
3178void
3179ahci_quick_timeout(struct ahci_ccb *ccb)
3180{
3181 struct ahci_port *ap = ccb->ccb_port;
3182
3183 switch (ccb->ccb_xa.state) {
3184 case ATA_S_PENDING:
3185 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
3186 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3187 break;
3188 case ATA_S_ONCHIP:
3189 KKASSERT(ap->ap_active == (1 << ccb->ccb_slot) &&
3190 ap->ap_sactive == 0);
3191 ahci_port_stop(ap, 0);
3192 ahci_port_start(ap);
3193
3194 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3195 ap->ap_active &= ~(1 << ccb->ccb_slot);
3196 KKASSERT(ap->ap_active_cnt > 0);
3197 --ap->ap_active_cnt;
3198 break;
3199 default:
3200 panic("%s: ahci_quick_timeout: ccb in bad state %d",
3201 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_xa.state);
3202 }
3203}
3204
12feb904
MD
3205static void
3206ahci_dummy_done(struct ata_xfer *xa)
3207{
3208}
3209
3210static void
258223a3
MD
3211ahci_empty_done(struct ahci_ccb *ccb)
3212{
258223a3 3213}