[dragonfly.git] / sys / bus / u4b / controller / xhci_pci.c

/*-
 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/stdint.h>
#include <sys/param.h>
#include <sys/queue.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/sysctl.h>
#include <sys/unistd.h>
#include <sys/callout.h>
#include <sys/malloc.h>
#include <sys/priv.h>

#include <bus/u4b/usb.h>
#include <bus/u4b/usbdi.h>

#include <bus/u4b/usb_core.h>
#include <bus/u4b/usb_busdma.h>
#include <bus/u4b/usb_process.h>
#include <bus/u4b/usb_util.h>

#include <bus/u4b/usb_controller.h>
#include <bus/u4b/usb_bus.h>
#include <bus/u4b/usb_pci.h>
#include <bus/u4b/controller/xhci.h>
#include <bus/u4b/controller/xhcireg.h>
#include "usb_if.h"

static device_probe_t xhci_pci_probe;
static device_attach_t xhci_pci_attach;
static device_detach_t xhci_pci_detach;
static usb_take_controller_t xhci_pci_take_controller;

static device_method_t xhci_device_methods[] = {
	/* device interface */
	DEVMETHOD(device_probe, xhci_pci_probe),
	DEVMETHOD(device_attach, xhci_pci_attach),
	DEVMETHOD(device_detach, xhci_pci_detach),
	DEVMETHOD(device_suspend, bus_generic_suspend),
	DEVMETHOD(device_resume, bus_generic_resume),
	DEVMETHOD(device_shutdown, bus_generic_shutdown),
	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),

	{ 0, 0 }
};

static driver_t xhci_driver = {
	.name = "xhci",
	.methods = xhci_device_methods,
	.size = sizeof(struct xhci_softc),
};

static devclass_t xhci_devclass;

DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
MODULE_DEPEND(xhci, usb, 1, 1, 1);


static const char *
xhci_pci_match(device_t self)
{
	if ((pci_get_class(self) == PCIC_SERIALBUS)
	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
		return ("XHCI (generic) USB 3.0 controller");
	}
	return (NULL);			/* dunno */
}

static int
xhci_pci_probe(device_t self)
{
	const char *desc = xhci_pci_match(self);

	if (desc) {
		device_set_desc(self, desc);
		return (0);
	} else {
		return (ENXIO);
	}
}

static int
xhci_pci_attach(device_t self)
{
	struct xhci_softc *sc = device_get_softc(self);
	int err;
	int rid;

	/* XXX check for 64-bit capability */

	if (xhci_init(sc, self)) {
		device_printf(self, "Could not initialize softc\n");
		goto error;
	}

	pci_enable_busmaster(self);

	rid = PCI_XHCI_CBMEM;
	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
	    RF_ACTIVE);
	if (!sc->sc_io_res) {
		device_printf(self, "Could not map memory\n");
		goto error;
	}
	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
	sc->sc_io_size = rman_get_size(sc->sc_io_res);

	rid = 0;
	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
	    RF_SHAREABLE | RF_ACTIVE);
	if (sc->sc_irq_res == NULL) {
		device_printf(self, "Could not allocate IRQ\n");
		goto error;
	}
	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
	if (sc->sc_bus.bdev == NULL) {
		device_printf(self, "Could not add USB device\n");
		goto error;
	}
	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);

	ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));

	err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE,
	    (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL);
	if (err) {
		device_printf(self, "Could not setup IRQ, err=%d\n", err);
		sc->sc_intr_hdl = NULL;
		goto error;
	}
	xhci_pci_take_controller(self);

	err = xhci_halt_controller(sc);

	if (err == 0)
		err = xhci_start_controller(sc);

	if (err == 0)
		err = device_probe_and_attach(sc->sc_bus.bdev);

	if (err) {
		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
		goto error;
	}
	return (0);

error:
	xhci_pci_detach(self);
	return (ENXIO);
}

static int
xhci_pci_detach(device_t self)
{
	struct xhci_softc *sc = device_get_softc(self);
	device_t bdev;

	if (sc->sc_bus.bdev != NULL) {
		bdev = sc->sc_bus.bdev;
		device_detach(bdev);
		device_delete_child(self, bdev);
	}
#if 0 /* XXX */
	/* during module unload there are lots of children leftover */
	device_delete_children(self);
#endif

	pci_disable_busmaster(self);

	if (sc->sc_irq_res && sc->sc_intr_hdl) {

		xhci_halt_controller(sc);

		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
		sc->sc_intr_hdl = NULL;
	}
	if (sc->sc_irq_res) {
		bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
		sc->sc_irq_res = NULL;
	}
	if (sc->sc_io_res) {
		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
		    sc->sc_io_res);
		sc->sc_io_res = NULL;
	}

	xhci_uninit(sc);

	return (0);
}

static int
xhci_pci_take_controller(device_t self)
{
	struct xhci_softc *sc = device_get_softc(self);
	uint32_t cparams;
	uint32_t eecp;
	uint32_t eec;
	uint16_t to;
	uint8_t bios_sem;

	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);

	eec = -1;

	/* Synchronise with the BIOS if it owns the controller. */
	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
	    eecp += XHCI_XECP_NEXT(eec) << 2) {
		eec = XREAD4(sc, capa, eecp);

		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
			continue;
		bios_sem = XREAD1(sc, capa, eecp +
		    XHCI_XECP_BIOS_SEM);
		if (bios_sem == 0)
			continue;
		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
		    "to give up control\n");
		XWRITE1(sc, capa, eecp +
		    XHCI_XECP_OS_SEM, 1);
		to = 500;
		while (1) {
			bios_sem = XREAD1(sc, capa, eecp +
			    XHCI_XECP_BIOS_SEM);
			if (bios_sem == 0)
				break;

			if (--to == 0) {
				device_printf(sc->sc_bus.bdev,
				    "timed out waiting for BIOS\n");
				break;
			}
			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
		}
	}
	return (0);
}
Commit	Line	Data
12bd3c8b SW	1	/*-
	2	* Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
	3	*
	4	* Redistribution and use in source and binary forms, with or without
	5	* modification, are permitted provided that the following conditions
	6	* are met:
	7	* 1. Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* 2. Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	*
	13	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
	14	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
	17	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	18	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	19	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	20	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	21	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	22	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	23	* SUCH DAMAGE.
	24	*/
	25
12bd3c8b	26	#include <sys/stdint.h>
12bd3c8b SW	27	#include <sys/param.h>
	28	#include <sys/queue.h>
	29	#include <sys/types.h>
	30	#include <sys/systm.h>
	31	#include <sys/kernel.h>
	32	#include <sys/bus.h>
	33	#include <sys/module.h>
	34	#include <sys/lock.h>
	35	#include <sys/mutex.h>
	36	#include <sys/condvar.h>
	37	#include <sys/sysctl.h>
12bd3c8b SW	38	#include <sys/unistd.h>
	39	#include <sys/callout.h>
	40	#include <sys/malloc.h>
	41	#include <sys/priv.h>
	42
722d05c3 SW	43	#include <bus/u4b/usb.h>
722d05c3 SW	44	#include <bus/u4b/usbdi.h>
12bd3c8b	45
722d05c3 SW	46	#include <bus/u4b/usb_core.h>
	47	#include <bus/u4b/usb_busdma.h>
	48	#include <bus/u4b/usb_process.h>
	49	#include <bus/u4b/usb_util.h>
12bd3c8b	50
722d05c3 SW	51	#include <bus/u4b/usb_controller.h>
	52	#include <bus/u4b/usb_bus.h>
	53	#include <bus/u4b/usb_pci.h>
	54	#include <bus/u4b/controller/xhci.h>
	55	#include <bus/u4b/controller/xhcireg.h>
12bd3c8b SW	56	#include "usb_if.h"
	57
	58	static device_probe_t xhci_pci_probe;
	59	static device_attach_t xhci_pci_attach;
	60	static device_detach_t xhci_pci_detach;
	61	static usb_take_controller_t xhci_pci_take_controller;
	62
	63	static device_method_t xhci_device_methods[] = {
	64	/* device interface */
	65	DEVMETHOD(device_probe, xhci_pci_probe),
	66	DEVMETHOD(device_attach, xhci_pci_attach),
	67	DEVMETHOD(device_detach, xhci_pci_detach),
	68	DEVMETHOD(device_suspend, bus_generic_suspend),
	69	DEVMETHOD(device_resume, bus_generic_resume),
	70	DEVMETHOD(device_shutdown, bus_generic_shutdown),
	71	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
	72
63da4a34	73	{ 0, 0 }
12bd3c8b SW	74	};
	75
	76	static driver_t xhci_driver = {
	77	.name = "xhci",
	78	.methods = xhci_device_methods,
	79	.size = sizeof(struct xhci_softc),
	80	};
	81
	82	static devclass_t xhci_devclass;
	83
15f415f6	84	DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
12bd3c8b SW	85	MODULE_DEPEND(xhci, usb, 1, 1, 1);
	86
	87
	88	static const char *
	89	xhci_pci_match(device_t self)
	90	{
	91	if ((pci_get_class(self) == PCIC_SERIALBUS)
	92	&& (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
	93	&& (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
	94	return ("XHCI (generic) USB 3.0 controller");
	95	}
	96	return (NULL); /* dunno */
	97	}
	98
	99	static int
	100	xhci_pci_probe(device_t self)
	101	{
	102	const char *desc = xhci_pci_match(self);
	103
	104	if (desc) {
	105	device_set_desc(self, desc);
	106	return (0);
	107	} else {
	108	return (ENXIO);
	109	}
	110	}
	111
	112	static int
	113	xhci_pci_attach(device_t self)
	114	{
	115	struct xhci_softc *sc = device_get_softc(self);
	116	int err;
	117	int rid;
	118
	119	/* XXX check for 64-bit capability */
	120
	121	if (xhci_init(sc, self)) {
	122	device_printf(self, "Could not initialize softc\n");
	123	goto error;
	124	}
	125
	126	pci_enable_busmaster(self);
	127
	128	rid = PCI_XHCI_CBMEM;
	129	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
	130	RF_ACTIVE);
	131	if (!sc->sc_io_res) {
	132	device_printf(self, "Could not map memory\n");
	133	goto error;
	134	}
	135	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
	136	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
	137	sc->sc_io_size = rman_get_size(sc->sc_io_res);
	138
	139	rid = 0;
	140	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
	141	RF_SHAREABLE \| RF_ACTIVE);
	142	if (sc->sc_irq_res == NULL) {
	143	device_printf(self, "Could not allocate IRQ\n");
	144	goto error;
	145	}
	146	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
	147	if (sc->sc_bus.bdev == NULL) {
	148	device_printf(self, "Could not add USB device\n");
149	goto error;
150	}
151	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
152
722d05c3	153	ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
12bd3c8b	154
722d05c3 SW	155	err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE,
722d05c3 SW	156	(driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL);
12bd3c8b SW	157	if (err) {
	158	device_printf(self, "Could not setup IRQ, err=%d\n", err);
	159	sc->sc_intr_hdl = NULL;
	160	goto error;
	161	}
	162	xhci_pci_take_controller(self);
	163
	164	err = xhci_halt_controller(sc);
	165
	166	if (err == 0)
	167	err = xhci_start_controller(sc);
	168
	169	if (err == 0)
	170	err = device_probe_and_attach(sc->sc_bus.bdev);
	171
	172	if (err) {
	173	device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
	174	goto error;
	175	}
	176	return (0);
	177
	178	error:
	179	xhci_pci_detach(self);
	180	return (ENXIO);
	181	}
	182
	183	static int
	184	xhci_pci_detach(device_t self)
	185	{
	186	struct xhci_softc *sc = device_get_softc(self);
	187	device_t bdev;
	188
	189	if (sc->sc_bus.bdev != NULL) {
	190	bdev = sc->sc_bus.bdev;
	191	device_detach(bdev);
	192	device_delete_child(self, bdev);
	193	}
63da4a34	194	#if 0 /* XXX */
12bd3c8b SW	195	/* during module unload there are lots of children leftover */
12bd3c8b SW	196	device_delete_children(self);
63da4a34 SW	197	#endif
63da4a34 SW	198
12bd3c8b SW	199	pci_disable_busmaster(self);
	200
	201	if (sc->sc_irq_res && sc->sc_intr_hdl) {
	202
	203	xhci_halt_controller(sc);
	204
	205	bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
	206	sc->sc_intr_hdl = NULL;
	207	}
	208	if (sc->sc_irq_res) {
	209	bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
	210	sc->sc_irq_res = NULL;
	211	}
	212	if (sc->sc_io_res) {
	213	bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
	214	sc->sc_io_res);
	215	sc->sc_io_res = NULL;
	216	}
	217
	218	xhci_uninit(sc);
	219
	220	return (0);
	221	}
	222
	223	static int
	224	xhci_pci_take_controller(device_t self)
	225	{
	226	struct xhci_softc *sc = device_get_softc(self);
	227	uint32_t cparams;
	228	uint32_t eecp;
	229	uint32_t eec;
	230	uint16_t to;
	231	uint8_t bios_sem;
	232
	233	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
	234
	235	eec = -1;
	236
	237	/* Synchronise with the BIOS if it owns the controller. */
	238	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
	239	eecp += XHCI_XECP_NEXT(eec) << 2) {
	240	eec = XREAD4(sc, capa, eecp);
	241
	242	if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
	243	continue;
	244	bios_sem = XREAD1(sc, capa, eecp +
	245	XHCI_XECP_BIOS_SEM);
	246	if (bios_sem == 0)
	247	continue;
	248	device_printf(sc->sc_bus.bdev, "waiting for BIOS "
	249	"to give up control\n");
	250	XWRITE1(sc, capa, eecp +
	251	XHCI_XECP_OS_SEM, 1);
	252	to = 500;
	253	while (1) {
	254	bios_sem = XREAD1(sc, capa, eecp +
	255	XHCI_XECP_BIOS_SEM);
	256	if (bios_sem == 0)
	257	break;
	258
	259	if (--to == 0) {
	260	device_printf(sc->sc_bus.bdev,
	261	"timed out waiting for BIOS\n");
	262	break;
263	}
264	usb_pause_mtx(NULL, hz / 100); /* wait 10ms */
265	}
266	}
267	return (0);
268	}