AMD64 - Fix bogus signal interruption
[dragonfly.git] / sys / platform / pc64 / amd64 / exception.S
CommitLineData
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1/*-
2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
5 * Copyright (c) 2008 The DragonFly Project.
6 * Copyright (c) 2008 Jordan Gordeev.
7 * All rights reserved.
8 *
9 * Portions of this software were developed by A. Joseph Koshy under
10 * sponsorship from the FreeBSD Foundation and Google, Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $FreeBSD$
37 * $DragonFly: src/sys/platform/pc64/amd64/exception.S,v 1.1 2008/08/29 17:07:10 dillon Exp $
38 */
39
40#if JG
41#include "opt_atpic.h"
42#endif
43#include "opt_compat.h"
44
45#include <machine/asmacros.h>
46#include <machine/psl.h>
47#include <machine/trap.h>
48
49#include "assym.s"
50
51 .text
52
53/*****************************************************************************/
54/* Trap handling */
55/*****************************************************************************/
56/*
57 * Trap and fault vector routines.
58 *
59 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
60 * state on the stack but also disables interrupts. This is important for
61 * us for the use of the swapgs instruction. We cannot be interrupted
62 * until the GS.base value is correct. For most traps, we automatically
63 * then enable interrupts if the interrupted context had them enabled.
64 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
65 *
66 * The cpu will push a certain amount of state onto the kernel stack for
67 * the current process. See amd64/include/frame.h.
68 * This includes the current RFLAGS (status register, which includes
69 * the interrupt disable state prior to the trap), the code segment register,
70 * and the return instruction pointer are pushed by the cpu. The cpu
71 * will also push an 'error' code for certain traps. We push a dummy
72 * error code for those traps where the cpu doesn't in order to maintain
73 * a consistent frame. We also push a contrived 'trap number'.
74 *
75 * The cpu does not push the general registers, we must do that, and we
76 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
77 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
78 * must load them with appropriate values for supervisor mode operation.
79 */
80
81MCOUNT_LABEL(user)
82MCOUNT_LABEL(btrap)
83
84/* Traps that we leave interrupts disabled for.. */
85#define TRAP_NOEN(a) \
86 subq $TF_RIP,%rsp; \
5b9f6cc4 87 movq $0,TF_XFLAGS(%rsp) ; \
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88 movq $(a),TF_TRAPNO(%rsp) ; \
89 movq $0,TF_ADDR(%rsp) ; \
90 movq $0,TF_ERR(%rsp) ; \
91 jmp alltraps_noen
92IDTVEC(dbg)
93 TRAP_NOEN(T_TRCTRAP)
94IDTVEC(bpt)
95 TRAP_NOEN(T_BPTFLT)
96
97/* Regular traps; The cpu does not supply tf_err for these. */
98#define TRAP(a) \
99 subq $TF_RIP,%rsp; \
5b9f6cc4 100 movq $0,TF_XFLAGS(%rsp) ; \
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101 movq $(a),TF_TRAPNO(%rsp) ; \
102 movq $0,TF_ADDR(%rsp) ; \
103 movq $0,TF_ERR(%rsp) ; \
104 jmp alltraps
105IDTVEC(div)
106 TRAP(T_DIVIDE)
107IDTVEC(ofl)
108 TRAP(T_OFLOW)
109IDTVEC(bnd)
110 TRAP(T_BOUND)
111IDTVEC(ill)
112 TRAP(T_PRIVINFLT)
113IDTVEC(dna)
114 TRAP(T_DNA)
115IDTVEC(fpusegm)
116 TRAP(T_FPOPFLT)
117IDTVEC(mchk)
118 TRAP(T_MCHK)
119IDTVEC(rsvd)
120 TRAP(T_RESERVED)
121IDTVEC(fpu)
122 TRAP(T_ARITHTRAP)
123IDTVEC(xmm)
124 TRAP(T_XMMFLT)
125
126/* This group of traps have tf_err already pushed by the cpu */
127#define TRAP_ERR(a) \
128 subq $TF_ERR,%rsp; \
129 movq $(a),TF_TRAPNO(%rsp) ; \
130 movq $0,TF_ADDR(%rsp) ; \
16094a36 131 movq $0,TF_XFLAGS(%rsp) ; \
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132 jmp alltraps
133IDTVEC(tss)
134 TRAP_ERR(T_TSSFLT)
135IDTVEC(missing)
136 TRAP_ERR(T_SEGNPFLT)
137IDTVEC(stk)
138 TRAP_ERR(T_STKFLT)
139IDTVEC(align)
140 TRAP_ERR(T_ALIGNFLT)
141
142 /*
143 * alltraps entry point. Use swapgs if this is the first time in the
144 * kernel from userland. Reenable interrupts if they were enabled
145 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
146 */
147
148 SUPERALIGN_TEXT
149 .globl alltraps
150 .type alltraps,@function
151alltraps:
152 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
153 jz alltraps_testi /* already running with kernel GS.base */
154 swapgs
155alltraps_testi:
156 testq $PSL_I,TF_RFLAGS(%rsp)
157 jz alltraps_pushregs
158 sti
159alltraps_pushregs:
160 movq %rdi,TF_RDI(%rsp)
161alltraps_pushregs_no_rdi:
162 movq %rsi,TF_RSI(%rsp)
163 movq %rdx,TF_RDX(%rsp)
164 movq %rcx,TF_RCX(%rsp)
165 movq %r8,TF_R8(%rsp)
166 movq %r9,TF_R9(%rsp)
167 movq %rax,TF_RAX(%rsp)
168 movq %rbx,TF_RBX(%rsp)
169 movq %rbp,TF_RBP(%rsp)
170 movq %r10,TF_R10(%rsp)
171 movq %r11,TF_R11(%rsp)
172 movq %r12,TF_R12(%rsp)
173 movq %r13,TF_R13(%rsp)
174 movq %r14,TF_R14(%rsp)
175 movq %r15,TF_R15(%rsp)
176 FAKE_MCOUNT(TF_RIP(%rsp))
177 .globl calltrap
178 .type calltrap,@function
179calltrap:
180 movq %rsp, %rdi
181 call trap
182 MEXITCOUNT
183 jmp doreti /* Handle any pending ASTs */
184
185 /*
186 * alltraps_noen entry point. Unlike alltraps above, we want to
187 * leave the interrupts disabled. This corresponds to
188 * SDT_SYS386IGT on the i386 port.
189 */
190 SUPERALIGN_TEXT
191 .globl alltraps_noen
192 .type alltraps_noen,@function
193alltraps_noen:
194 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
195 jz alltraps_pushregs /* already running with kernel GS.base */
196 swapgs
197 jmp alltraps_pushregs
198
199IDTVEC(dblfault)
200 subq $TF_ERR,%rsp
201 movq $T_DOUBLEFLT,TF_TRAPNO(%rsp)
202 movq $0,TF_ADDR(%rsp)
203 movq $0,TF_ERR(%rsp)
16094a36 204 movq $0,TF_XFLAGS(%rsp)
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205 movq %rdi,TF_RDI(%rsp)
206 movq %rsi,TF_RSI(%rsp)
207 movq %rdx,TF_RDX(%rsp)
208 movq %rcx,TF_RCX(%rsp)
209 movq %r8,TF_R8(%rsp)
210 movq %r9,TF_R9(%rsp)
211 movq %rax,TF_RAX(%rsp)
212 movq %rbx,TF_RBX(%rsp)
213 movq %rbp,TF_RBP(%rsp)
214 movq %r10,TF_R10(%rsp)
215 movq %r11,TF_R11(%rsp)
216 movq %r12,TF_R12(%rsp)
217 movq %r13,TF_R13(%rsp)
218 movq %r14,TF_R14(%rsp)
219 movq %r15,TF_R15(%rsp)
220 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
221 jz 1f /* already running with kernel GS.base */
222 swapgs
2231: movq %rsp, %rdi
224 call dblfault_handler
2252: hlt
226 jmp 2b
227
228IDTVEC(page)
229 subq $TF_ERR,%rsp
230 movq $T_PAGEFLT,TF_TRAPNO(%rsp)
231 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
232 jz 1f /* already running with kernel GS.base */
233 swapgs
2341:
235 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
236 movq %cr2,%rdi /* preserve %cr2 before .. */
237 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
16094a36 238 movq $0,TF_XFLAGS(%rsp)
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239 testq $PSL_I,TF_RFLAGS(%rsp)
240 jz alltraps_pushregs_no_rdi
241 sti
242 jmp alltraps_pushregs_no_rdi
243
244 /*
245 * We have to special-case this one. If we get a trap in doreti() at
246 * the iretq stage, we'll reenter with the wrong gs state. We'll have
247 * to do a special the swapgs in this case even coming from the kernel.
248 * XXX linux has a trap handler for their equivalent of load_gs().
249 */
250IDTVEC(prot)
251 subq $TF_ERR,%rsp
252 movq $T_PROTFLT,TF_TRAPNO(%rsp)
253 movq $0,TF_ADDR(%rsp)
16094a36 254 movq $0,TF_XFLAGS(%rsp)
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255 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
256 leaq doreti_iret(%rip),%rdi
257 cmpq %rdi,TF_RIP(%rsp)
258 je 2f /* kernel but with user gsbase!! */
259 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
260 jz 1f /* already running with kernel GS.base */
2612:
262 swapgs
2631:
264 testq $PSL_I,TF_RFLAGS(%rsp)
265 jz alltraps_pushregs_no_rdi
266 sti
267 jmp alltraps_pushregs_no_rdi
268
269/*
270 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
271 * and the new privilige level. We are still running on the old user stack
272 * pointer. We have to juggle a few things around to find our stack etc.
273 * swapgs gives us access to our PCPU space only.
274 */
275IDTVEC(fast_syscall)
276 swapgs
277 movq %rsp,PCPU(scratch_rsp)
278 movq PCPU(rsp0),%rsp
279 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
280 subq $TF_SIZE,%rsp
281 /* defer TF_RSP till we have a spare register */
282 movq %r11,TF_RFLAGS(%rsp)
283 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
284 movq PCPU(scratch_rsp),%r11 /* %r11 already saved */
285 movq %r11,TF_RSP(%rsp) /* user stack pointer */
286 sti
287 movq $KUDSEL,TF_SS(%rsp)
288 movq $KUCSEL,TF_CS(%rsp)
289 movq $2,TF_ERR(%rsp)
16094a36 290 movq $0,TF_XFLAGS(%rsp) /* note: used in signal frame */
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291 movq %rdi,TF_RDI(%rsp) /* arg 1 */
292 movq %rsi,TF_RSI(%rsp) /* arg 2 */
293 movq %rdx,TF_RDX(%rsp) /* arg 3 */
294 movq %r10,TF_RCX(%rsp) /* arg 4 */
295 movq %r8,TF_R8(%rsp) /* arg 5 */
296 movq %r9,TF_R9(%rsp) /* arg 6 */
297 movq %rax,TF_RAX(%rsp) /* syscall number */
298 movq %rbx,TF_RBX(%rsp) /* C preserved */
299 movq %rbp,TF_RBP(%rsp) /* C preserved */
300 movq %r12,TF_R12(%rsp) /* C preserved */
301 movq %r13,TF_R13(%rsp) /* C preserved */
302 movq %r14,TF_R14(%rsp) /* C preserved */
303 movq %r15,TF_R15(%rsp) /* C preserved */
304 FAKE_MCOUNT(TF_RIP(%rsp))
305 movq %rsp, %rdi
306 call syscall2
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307 MEXITCOUNT
308 jmp doreti
309
310/*
311 * Here for CYA insurance, in case a "syscall" instruction gets
312 * issued from 32 bit compatability mode. MSR_CSTAR has to point
313 * to *something* if EFER_SCE is enabled.
314 */
315IDTVEC(fast_syscall32)
316 sysret
317
318/*
319 * NMI handling is special.
320 *
321 * First, NMIs do not respect the state of the processor's RFLAGS.IF
322 * bit and the NMI handler may be invoked at any time, including when
323 * the processor is in a critical section with RFLAGS.IF == 0. In
324 * particular, this means that the processor's GS.base values could be
325 * inconsistent on entry to the handler, and so we need to read
326 * MSR_GSBASE to determine if a 'swapgs' is needed. We use '%ebx', a
327 * C-preserved register, to remember whether to swap GS back on the
328 * exit path.
329 *
330 * Second, the processor treats NMIs specially, blocking further NMIs
331 * until an 'iretq' instruction is executed. We therefore need to
332 * execute the NMI handler with interrupts disabled to prevent a
333 * nested interrupt from executing an 'iretq' instruction and
334 * inadvertently taking the processor out of NMI mode.
335 *
336 * Third, the NMI handler runs on its own stack (tss_ist1), shared
337 * with the double fault handler.
338 */
339
340IDTVEC(nmi)
341 subq $TF_RIP,%rsp
342 movq $(T_NMI),TF_TRAPNO(%rsp)
343 movq $0,TF_ADDR(%rsp)
344 movq $0,TF_ERR(%rsp)
16094a36 345 movq $0,TF_XFLAGS(%rsp)
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346 movq %rdi,TF_RDI(%rsp)
347 movq %rsi,TF_RSI(%rsp)
348 movq %rdx,TF_RDX(%rsp)
349 movq %rcx,TF_RCX(%rsp)
350 movq %r8,TF_R8(%rsp)
351 movq %r9,TF_R9(%rsp)
352 movq %rax,TF_RAX(%rsp)
353 movq %rbx,TF_RBX(%rsp)
354 movq %rbp,TF_RBP(%rsp)
355 movq %r10,TF_R10(%rsp)
356 movq %r11,TF_R11(%rsp)
357 movq %r12,TF_R12(%rsp)
358 movq %r13,TF_R13(%rsp)
359 movq %r14,TF_R14(%rsp)
360 movq %r15,TF_R15(%rsp)
361 xorl %ebx,%ebx
362 testb $SEL_RPL_MASK,TF_CS(%rsp)
363 jnz nmi_needswapgs /* we came from userland */
364 movl $MSR_GSBASE,%ecx
365 rdmsr
48ffc236 366 cmpl $VM_MAX_USER_ADDRESS >> 32,%edx
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367 jae nmi_calltrap /* GS.base holds a kernel VA */
368nmi_needswapgs:
369 incl %ebx
370 swapgs
371/* Note: this label is also used by ddb and gdb: */
372nmi_calltrap:
373 FAKE_MCOUNT(TF_RIP(%rsp))
374 movq %rsp, %rdi
375 call trap
376 MEXITCOUNT
377 testl %ebx,%ebx
378 jz nmi_restoreregs
379 swapgs
380nmi_restoreregs:
381 movq TF_RDI(%rsp),%rdi
382 movq TF_RSI(%rsp),%rsi
383 movq TF_RDX(%rsp),%rdx
384 movq TF_RCX(%rsp),%rcx
385 movq TF_R8(%rsp),%r8
386 movq TF_R9(%rsp),%r9
387 movq TF_RAX(%rsp),%rax
388 movq TF_RBX(%rsp),%rbx
389 movq TF_RBP(%rsp),%rbp
390 movq TF_R10(%rsp),%r10
391 movq TF_R11(%rsp),%r11
392 movq TF_R12(%rsp),%r12
393 movq TF_R13(%rsp),%r13
394 movq TF_R14(%rsp),%r14
395 movq TF_R15(%rsp),%r15
396 addq $TF_RIP,%rsp
397 iretq
398
399/*
400 * This function is what cpu_heavy_restore jumps to after a new process
401 * is created. The LWKT subsystem switches while holding a critical
402 * section and we maintain that abstraction here (e.g. because
403 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of
404 * it before calling the initial function (typically fork_return()) and/or
405 * returning to user mode.
406 *
407 * The MP lock is held on entry, but for processes fork_return(esi)
408 * releases it. 'doreti' always runs without the MP lock.
409 */
410ENTRY(fork_trampoline)
411 movq PCPU(curthread),%rax
412 subl $TDPRI_CRIT,TD_PRI(%rax)
413
414 /*
415 * cpu_set_fork_handler intercepts this function call to
416 * have this call a non-return function to stay in kernel mode.
417 *
418 * initproc has its own fork handler, start_init(), which DOES
419 * return.
420 *
421 * %rbx - chaining function (typically fork_return)
422 * %r12 -> %rdi (argument)
423 * frame-> %rsi (trap frame)
424 *
425 * void (func:rbx)(arg:rdi, trapframe:rsi)
426 */
427 movq %rsp, %rsi /* pass trapframe by reference */
428 movq %r12, %rdi /* arg1 */
429 call *%rbx /* function */
430
431 /* cut from syscall */
432
433 sti
434 call splz
435
436#if defined(INVARIANTS) && defined(SMP)
437 movq PCPU(curthread),%rax
438 cmpl $0,TD_MPCOUNT(%rax)
439 je 1f
440 movq $pmsg4, %rdi
46d4e165 441 movl TD_MPCOUNT(%rax), %esi
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442 movq %rbx, %rdx
443 xorl %eax, %eax
444 call panic
445pmsg4: .asciz "fork_trampoline mpcount %d after calling %p"
446 /* JG what's the purpose of this alignment and is it enough on amd64? */
447 .p2align 2
4481:
449#endif
450 /*
451 * Return via doreti to handle ASTs.
452 *
453 * trapframe is at the top of the stack.
454 */
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455 MEXITCOUNT
456 jmp doreti
457
458/*
459 * To efficiently implement classification of trap and interrupt handlers
460 * for profiling, there must be only trap handlers between the labels btrap
461 * and bintr, and only interrupt handlers between the labels bintr and
462 * eintr. This is implemented (partly) by including files that contain
463 * some of the handlers. Before including the files, set up a normal asm
464 * environment so that the included files doen't need to know that they are
465 * included.
466 */
467
468#ifdef COMPAT_IA32
469 .data
470 .p2align 4
471 .text
472 SUPERALIGN_TEXT
473
474#include <amd64/ia32/ia32_exception.S>
475#endif
476
477 .data
478 .p2align 4
479 .text
480 SUPERALIGN_TEXT
481MCOUNT_LABEL(bintr)
482
483#if JG
484#include <amd64/amd64/apic_vector.S>
485#endif
486
487#ifdef DEV_ATPIC
488 .data
489 .p2align 4
490 .text
491 SUPERALIGN_TEXT
492
493#include <amd64/isa/atpic_vector.S>
494#endif
495
496 .text
497MCOUNT_LABEL(eintr)
498