emx: Add comment and add assertion about serializer initialization
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
e6cde6e6 68#include "opt_emx.h"
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69
70#include <sys/param.h>
71#include <sys/bus.h>
72#include <sys/endian.h>
73#include <sys/interrupt.h>
74#include <sys/kernel.h>
75#include <sys/ktr.h>
76#include <sys/malloc.h>
77#include <sys/mbuf.h>
78#include <sys/proc.h>
79#include <sys/rman.h>
80#include <sys/serialize.h>
bc197380 81#include <sys/serialize2.h>
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82#include <sys/socket.h>
83#include <sys/sockio.h>
84#include <sys/sysctl.h>
85#include <sys/systm.h>
86
87#include <net/bpf.h>
88#include <net/ethernet.h>
89#include <net/if.h>
90#include <net/if_arp.h>
91#include <net/if_dl.h>
92#include <net/if_media.h>
93#include <net/ifq_var.h>
89d8e73d 94#include <net/toeplitz.h>
9cc86e17 95#include <net/toeplitz2.h>
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96#include <net/vlan/if_vlan_var.h>
97#include <net/vlan/if_vlan_ether.h>
b3a7093f 98#include <net/if_poll.h>
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99
100#include <netinet/in_systm.h>
101#include <netinet/in.h>
102#include <netinet/ip.h>
103#include <netinet/tcp.h>
104#include <netinet/udp.h>
105
106#include <bus/pci/pcivar.h>
107#include <bus/pci/pcireg.h>
108
109#include <dev/netif/ig_hal/e1000_api.h>
110#include <dev/netif/ig_hal/e1000_82571.h>
111#include <dev/netif/emx/if_emx.h>
112
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113#ifdef EMX_RSS_DEBUG
114#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
115do { \
89d8e73d 116 if (sc->rss_debug >= lvl) \
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117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
118} while (0)
119#else /* !EMX_RSS_DEBUG */
120#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121#endif /* EMX_RSS_DEBUG */
122
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123#define EMX_TX_SERIALIZE 1
124#define EMX_RX_SERIALIZE 2
125
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126#define EMX_NAME "Intel(R) PRO/1000 "
127
128#define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130#define EMX_DEVICE_NULL { 0, 0, NULL }
131
132static const struct emx_device {
133 uint16_t vid;
134 uint16_t did;
135 const char *desc;
136} emx_devices[] = {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
147
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
151 EMX_DEVICE(82572EI),
152
153 EMX_DEVICE(82573E),
154 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(82573L),
156
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
161
162 EMX_DEVICE(82574L),
2d0e5700 163 EMX_DEVICE(82574LA),
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164
165 /* required last entry */
166 EMX_DEVICE_NULL
167};
168
169static int emx_probe(device_t);
170static int emx_attach(device_t);
171static int emx_detach(device_t);
172static int emx_shutdown(device_t);
173static int emx_suspend(device_t);
174static int emx_resume(device_t);
175
176static void emx_init(void *);
177static void emx_stop(struct emx_softc *);
178static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179static void emx_start(struct ifnet *);
b3a7093f 180#ifdef IFPOLL_ENABLE
f994de37 181static void emx_npoll(struct ifnet *, struct ifpoll_info *);
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182static void emx_npoll_status(struct ifnet *);
183static void emx_npoll_tx(struct ifnet *, void *, int);
184static void emx_npoll_rx(struct ifnet *, void *, int);
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185#endif
186static void emx_watchdog(struct ifnet *);
187static void emx_media_status(struct ifnet *, struct ifmediareq *);
188static int emx_media_change(struct ifnet *);
189static void emx_timer(void *);
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190static void emx_serialize(struct ifnet *, enum ifnet_serialize);
191static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
192static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
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193#ifdef INVARIANTS
194static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
195 boolean_t);
196#endif
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197
198static void emx_intr(void *);
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199static void emx_intr_mask(void *);
200static void emx_intr_body(struct emx_softc *, boolean_t);
c39e3a1f 201static void emx_rxeof(struct emx_softc *, int, int);
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202static void emx_txeof(struct emx_softc *);
203static void emx_tx_collect(struct emx_softc *);
204static void emx_tx_purge(struct emx_softc *);
205static void emx_enable_intr(struct emx_softc *);
206static void emx_disable_intr(struct emx_softc *);
207
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208static int emx_dma_alloc(struct emx_softc *);
209static void emx_dma_free(struct emx_softc *);
5330213c 210static void emx_init_tx_ring(struct emx_softc *);
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211static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
212static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 213static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 214static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 215static void emx_destroy_tx_ring(struct emx_softc *, int);
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216static void emx_destroy_rx_ring(struct emx_softc *,
217 struct emx_rxdata *, int);
218static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 219static int emx_encap(struct emx_softc *, struct mbuf **);
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220static int emx_txcsum(struct emx_softc *, struct mbuf *,
221 uint32_t *, uint32_t *);
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222static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
223static int emx_tso_setup(struct emx_softc *, struct mbuf *,
224 uint32_t *, uint32_t *);
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225
226static int emx_is_valid_eaddr(const uint8_t *);
2d0e5700 227static int emx_reset(struct emx_softc *);
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228static void emx_setup_ifp(struct emx_softc *);
229static void emx_init_tx_unit(struct emx_softc *);
230static void emx_init_rx_unit(struct emx_softc *);
231static void emx_update_stats(struct emx_softc *);
232static void emx_set_promisc(struct emx_softc *);
233static void emx_disable_promisc(struct emx_softc *);
234static void emx_set_multi(struct emx_softc *);
235static void emx_update_link_status(struct emx_softc *);
236static void emx_smartspeed(struct emx_softc *);
2d0e5700 237static void emx_set_itr(struct emx_softc *, uint32_t);
6d5e2922 238static void emx_disable_aspm(struct emx_softc *);
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239
240static void emx_print_debug_info(struct emx_softc *);
241static void emx_print_nvm_info(struct emx_softc *);
242static void emx_print_hw_stats(struct emx_softc *);
243
244static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
245static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
246static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
247static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
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248#ifdef IFPOLL_ENABLE
249static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
250static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
251#endif
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252static void emx_add_sysctl(struct emx_softc *);
253
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254static void emx_serialize_skipmain(struct emx_softc *);
255static void emx_deserialize_skipmain(struct emx_softc *);
256
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257/* Management and WOL Support */
258static void emx_get_mgmt(struct emx_softc *);
259static void emx_rel_mgmt(struct emx_softc *);
260static void emx_get_hw_control(struct emx_softc *);
261static void emx_rel_hw_control(struct emx_softc *);
262static void emx_enable_wol(device_t);
263
264static device_method_t emx_methods[] = {
265 /* Device interface */
266 DEVMETHOD(device_probe, emx_probe),
267 DEVMETHOD(device_attach, emx_attach),
268 DEVMETHOD(device_detach, emx_detach),
269 DEVMETHOD(device_shutdown, emx_shutdown),
270 DEVMETHOD(device_suspend, emx_suspend),
271 DEVMETHOD(device_resume, emx_resume),
272 { 0, 0 }
273};
274
275static driver_t emx_driver = {
276 "emx",
277 emx_methods,
278 sizeof(struct emx_softc),
279};
280
281static devclass_t emx_devclass;
282
283DECLARE_DUMMY_MODULE(if_emx);
284MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
aa2b9d05 285DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
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286
287/*
288 * Tunables
289 */
290static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
291static int emx_rxd = EMX_DEFAULT_RXD;
292static int emx_txd = EMX_DEFAULT_TXD;
704b6287 293static int emx_smart_pwr_down = 0;
724cbff8 294static int emx_rxr = 0;
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295
296/* Controls whether promiscuous also shows bad packets */
b4d8c36b 297static int emx_debug_sbp = 0;
5330213c 298
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299static int emx_82573_workaround = 1;
300static int emx_msi_enable = 1;
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301
302TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
303TUNABLE_INT("hw.emx.rxd", &emx_rxd);
724cbff8 304TUNABLE_INT("hw.emx.rxr", &emx_rxr);
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305TUNABLE_INT("hw.emx.txd", &emx_txd);
306TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
307TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
308TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
704b6287 309TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
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310
311/* Global used in WOL setup with multiport cards */
312static int emx_global_quad_port_a = 0;
313
314/* Set this to one to display debug statistics */
315static int emx_display_debug_stats = 0;
316
317#if !defined(KTR_IF_EMX)
318#define KTR_IF_EMX KTR_ALL
319#endif
320KTR_INFO_MASTER(if_emx);
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321KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
322KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
323KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
324KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
325KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
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326#define logif(name) KTR_LOG(if_emx_ ## name)
327
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328static __inline void
329emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
330{
331 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 332 /* DD bit must be cleared */
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333 rxd->rxd_staterr = 0;
334}
335
336static __inline void
337emx_rxcsum(uint32_t staterr, struct mbuf *mp)
338{
339 /* Ignore Checksum bit is set */
340 if (staterr & E1000_RXD_STAT_IXSM)
341 return;
342
343 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
344 E1000_RXD_STAT_IPCS)
345 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
346
347 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
348 E1000_RXD_STAT_TCPCS) {
349 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
350 CSUM_PSEUDO_HDR |
351 CSUM_FRAG_NOT_CHECKED;
352 mp->m_pkthdr.csum_data = htons(0xffff);
353 }
354}
355
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356static __inline struct pktinfo *
357emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
358 uint32_t mrq, uint32_t hash, uint32_t staterr)
359{
360 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
361 case EMX_RXDMRQ_IPV4_TCP:
362 pi->pi_netisr = NETISR_IP;
363 pi->pi_flags = 0;
364 pi->pi_l3proto = IPPROTO_TCP;
365 break;
366
367 case EMX_RXDMRQ_IPV6_TCP:
368 pi->pi_netisr = NETISR_IPV6;
369 pi->pi_flags = 0;
370 pi->pi_l3proto = IPPROTO_TCP;
371 break;
372
373 case EMX_RXDMRQ_IPV4:
374 if (staterr & E1000_RXD_STAT_IXSM)
375 return NULL;
376
377 if ((staterr &
378 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
379 E1000_RXD_STAT_TCPCS) {
380 pi->pi_netisr = NETISR_IP;
381 pi->pi_flags = 0;
382 pi->pi_l3proto = IPPROTO_UDP;
383 break;
384 }
385 /* FALL THROUGH */
386 default:
387 return NULL;
388 }
389
390 m->m_flags |= M_HASH;
391 m->m_pkthdr.hash = toeplitz_hash(hash);
392 return pi;
393}
394
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395static int
396emx_probe(device_t dev)
397{
398 const struct emx_device *d;
399 uint16_t vid, did;
400
401 vid = pci_get_vendor(dev);
402 did = pci_get_device(dev);
403
404 for (d = emx_devices; d->desc != NULL; ++d) {
405 if (vid == d->vid && did == d->did) {
406 device_set_desc(dev, d->desc);
407 device_set_async_attach(dev, TRUE);
408 return 0;
409 }
410 }
411 return ENXIO;
412}
413
414static int
415emx_attach(device_t dev)
416{
417 struct emx_softc *sc = device_get_softc(dev);
418 struct ifnet *ifp = &sc->arpcom.ac_if;
d01335e8 419 int error = 0, i, throttle, msi_enable;
704b6287 420 u_int intr_flags;
2d0e5700 421 uint16_t eeprom_data, device_id, apme_mask;
4cb541ae 422 driver_intr_t *intr_func;
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423#ifdef IFPOLL_ENABLE
424 int offset, offset_def;
425#endif
5330213c 426
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427 /*
428 * Initialize serializers
429 */
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430 lwkt_serialize_init(&sc->main_serialize);
431 lwkt_serialize_init(&sc->tx_serialize);
432 for (i = 0; i < EMX_NRX_RING; ++i)
433 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
434
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435 /*
436 * Initialize serializer array
437 */
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438 i = 0;
439 sc->serializes[i++] = &sc->main_serialize;
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440
441 KKASSERT(i == EMX_TX_SERIALIZE);
6d435846 442 sc->serializes[i++] = &sc->tx_serialize;
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443
444 KKASSERT(i == EMX_RX_SERIALIZE);
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445 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
446 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
447 KKASSERT(i == EMX_NSERIALIZE);
448
c2022416 449 callout_init_mp(&sc->timer);
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450
451 sc->dev = sc->osdep.dev = dev;
452
453 /*
454 * Determine hardware and mac type
455 */
456 sc->hw.vendor_id = pci_get_vendor(dev);
457 sc->hw.device_id = pci_get_device(dev);
458 sc->hw.revision_id = pci_get_revid(dev);
459 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
460 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
461
462 if (e1000_set_mac_type(&sc->hw))
463 return ENXIO;
464
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465 /*
466 * Pullup extra 4bytes into the first data segment, see:
467 * 82571/82572 specification update errata #7
468 *
469 * NOTE:
470 * 4bytes instead of 2bytes, which are mentioned in the errata,
471 * are pulled; mainly to keep rest of the data properly aligned.
472 */
473 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
474 sc->flags |= EMX_FLAG_TSO_PULLEX;
475
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476 /* Enable bus mastering */
477 pci_enable_busmaster(dev);
478
479 /*
480 * Allocate IO memory
481 */
482 sc->memory_rid = EMX_BAR_MEM;
483 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
484 &sc->memory_rid, RF_ACTIVE);
485 if (sc->memory == NULL) {
486 device_printf(dev, "Unable to allocate bus resource: memory\n");
487 error = ENXIO;
488 goto fail;
489 }
490 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
491 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
492
493 /* XXX This is quite goofy, it is not actually used */
494 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
495
d01335e8 496 /*
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497 * Don't enable MSI-X on 82574, see:
498 * 82574 specification update errata #15
499 *
d01335e8 500 * Don't enable MSI on 82571/82572, see:
a835687d 501 * 82571/82572 specification update errata #63
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502 */
503 msi_enable = emx_msi_enable;
504 if (msi_enable &&
505 (sc->hw.mac.type == e1000_82571 ||
506 sc->hw.mac.type == e1000_82572))
507 msi_enable = 0;
508
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509 /*
510 * Allocate interrupt
511 */
d01335e8 512 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
7fb43956 513 &sc->intr_rid, &intr_flags);
704b6287 514
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515 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
516 int unshared;
517
518 unshared = device_getenv_int(dev, "irq.unshared", 0);
519 if (!unshared) {
520 sc->flags |= EMX_FLAG_SHARED_INTR;
521 if (bootverbose)
522 device_printf(dev, "IRQ shared\n");
523 } else {
524 intr_flags &= ~RF_SHAREABLE;
525 if (bootverbose)
526 device_printf(dev, "IRQ unshared\n");
527 }
528 }
529
5330213c 530 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
704b6287 531 intr_flags);
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532 if (sc->intr_res == NULL) {
533 device_printf(dev, "Unable to allocate bus resource: "
534 "interrupt\n");
535 error = ENXIO;
536 goto fail;
537 }
538
539 /* Save PCI command register for Shared Code */
540 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
541 sc->hw.back = &sc->osdep;
542
543 /* Do Shared Code initialization */
544 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
545 device_printf(dev, "Setup of Shared code failed\n");
546 error = ENXIO;
547 goto fail;
548 }
549 e1000_get_bus_info(&sc->hw);
550
5330213c
SZ
551 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
552 sc->hw.phy.autoneg_wait_to_complete = FALSE;
553 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
5330213c
SZ
554
555 /*
556 * Interrupt throttle rate
557 */
b4d8c36b
SZ
558 throttle = device_getenv_int(dev, "int_throttle_ceil",
559 emx_int_throttle_ceil);
560 if (throttle == 0) {
5330213c
SZ
561 sc->int_throttle_ceil = 0;
562 } else {
5330213c
SZ
563 if (throttle < 0)
564 throttle = EMX_DEFAULT_ITR;
565
566 /* Recalculate the tunable value to get the exact frequency. */
567 throttle = 1000000000 / 256 / throttle;
568
569 /* Upper 16bits of ITR is reserved and should be zero */
570 if (throttle & 0xffff0000)
571 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
572
573 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
574 }
575
576 e1000_init_script_state_82541(&sc->hw, TRUE);
577 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
578
579 /* Copper options */
580 if (sc->hw.phy.media_type == e1000_media_type_copper) {
581 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
582 sc->hw.phy.disable_polarity_correction = FALSE;
583 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
584 }
585
586 /* Set the frame limits assuming standard ethernet sized frames. */
587 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
588 sc->min_frame_size = ETHER_MIN_LEN;
589
590 /* This controls when hardware reports transmit completion status. */
591 sc->hw.mac.report_tx_early = 1;
592
65c7a6af 593 /* Calculate # of RX rings */
724cbff8 594 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
a317449e 595 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
65c7a6af 596
071699f8
SZ
597 /* Allocate RX/TX rings' busdma(9) stuffs */
598 error = emx_dma_alloc(sc);
599 if (error)
e5b3bcc4 600 goto fail;
e5b3bcc4 601
2d0e5700
SZ
602 /* Allocate multicast array memory. */
603 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
604 M_DEVBUF, M_WAITOK);
605
606 /* Indicate SOL/IDER usage */
607 if (e1000_check_reset_block(&sc->hw)) {
608 device_printf(dev,
609 "PHY reset is blocked due to SOL/IDER session.\n");
610 }
611
612 /*
613 * Start from a known state, this is important in reading the
614 * nvm and mac from that.
615 */
616 e1000_reset_hw(&sc->hw);
617
5330213c
SZ
618 /* Make sure we have a good EEPROM before we read from it */
619 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
620 /*
621 * Some PCI-E parts fail the first check due to
622 * the link being in sleep state, call it again,
623 * if it fails a second time its a real issue.
624 */
625 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
626 device_printf(dev,
627 "The EEPROM Checksum Is Not Valid\n");
628 error = EIO;
629 goto fail;
630 }
631 }
632
5330213c
SZ
633 /* Copy the permanent MAC address out of the EEPROM */
634 if (e1000_read_mac_addr(&sc->hw) < 0) {
635 device_printf(dev, "EEPROM read error while reading MAC"
636 " address\n");
637 error = EIO;
638 goto fail;
639 }
640 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
641 device_printf(dev, "Invalid MAC address\n");
642 error = EIO;
643 goto fail;
644 }
645
5330213c 646 /* Determine if we have to control management hardware */
de0836d4
SZ
647 if (e1000_enable_mng_pass_thru(&sc->hw))
648 sc->flags |= EMX_FLAG_HAS_MGMT;
5330213c
SZ
649
650 /*
651 * Setup Wake-on-Lan
652 */
2d0e5700
SZ
653 apme_mask = EMX_EEPROM_APME;
654 eeprom_data = 0;
5330213c 655 switch (sc->hw.mac.type) {
2d0e5700 656 case e1000_82573:
de0836d4 657 sc->flags |= EMX_FLAG_HAS_AMT;
2d0e5700
SZ
658 /* FALL THROUGH */
659
5330213c 660 case e1000_82571:
2d0e5700 661 case e1000_82572:
5330213c
SZ
662 case e1000_80003es2lan:
663 if (sc->hw.bus.func == 1) {
664 e1000_read_nvm(&sc->hw,
665 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
666 } else {
667 e1000_read_nvm(&sc->hw,
668 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
669 }
5330213c
SZ
670 break;
671
672 default:
2d0e5700
SZ
673 e1000_read_nvm(&sc->hw,
674 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
5330213c
SZ
675 break;
676 }
2d0e5700
SZ
677 if (eeprom_data & apme_mask)
678 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
679
5330213c
SZ
680 /*
681 * We have the eeprom settings, now apply the special cases
682 * where the eeprom may be wrong or the board won't support
683 * wake on lan on a particular port
684 */
685 device_id = pci_get_device(dev);
686 switch (device_id) {
687 case E1000_DEV_ID_82571EB_FIBER:
688 /*
689 * Wake events only supported on port A for dual fiber
690 * regardless of eeprom setting
691 */
692 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
693 E1000_STATUS_FUNC_1)
694 sc->wol = 0;
695 break;
696
697 case E1000_DEV_ID_82571EB_QUAD_COPPER:
698 case E1000_DEV_ID_82571EB_QUAD_FIBER:
699 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
700 /* if quad port sc, disable WoL on all but port A */
701 if (emx_global_quad_port_a != 0)
702 sc->wol = 0;
703 /* Reset for multiple quad port adapters */
704 if (++emx_global_quad_port_a == 4)
705 emx_global_quad_port_a = 0;
706 break;
707 }
708
709 /* XXX disable wol */
710 sc->wol = 0;
711
09f49d52
SZ
712#ifdef IFPOLL_ENABLE
713 /*
714 * NPOLLING RX CPU offset
715 */
716 if (sc->rx_ring_cnt == ncpus2) {
717 offset = 0;
718 } else {
719 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
720 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
721 if (offset >= ncpus2 ||
722 offset % sc->rx_ring_cnt != 0) {
723 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
724 offset, offset_def);
725 offset = offset_def;
726 }
727 }
728 sc->rx_npoll_off = offset;
729
730 /*
731 * NPOLLING TX CPU offset
732 */
733 offset_def = sc->rx_npoll_off;
734 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
735 if (offset >= ncpus2) {
736 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
737 offset, offset_def);
738 offset = offset_def;
739 }
740 sc->tx_npoll_off = offset;
741#endif
742
2d0e5700
SZ
743 /* Setup OS specific network interface */
744 emx_setup_ifp(sc);
745
746 /* Add sysctl tree, must after em_setup_ifp() */
747 emx_add_sysctl(sc);
748
749 /* Reset the hardware */
750 error = emx_reset(sc);
751 if (error) {
752 device_printf(dev, "Unable to reset the hardware\n");
753 goto fail;
754 }
755
756 /* Initialize statistics */
757 emx_update_stats(sc);
758
759 sc->hw.mac.get_link_status = 1;
760 emx_update_link_status(sc);
761
5330213c
SZ
762 sc->spare_tx_desc = EMX_TX_SPARE;
763
764 /*
765 * Keep following relationship between spare_tx_desc, oact_tx_desc
766 * and tx_int_nsegs:
767 * (spare_tx_desc + EMX_TX_RESERVED) <=
768 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
769 */
770 sc->oact_tx_desc = sc->num_tx_desc / 8;
771 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
772 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
773 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
774 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
775
776 sc->tx_int_nsegs = sc->num_tx_desc / 16;
777 if (sc->tx_int_nsegs < sc->oact_tx_desc)
778 sc->tx_int_nsegs = sc->oact_tx_desc;
779
2d0e5700 780 /* Non-AMT based hardware can now take control from firmware */
de0836d4
SZ
781 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
782 EMX_FLAG_HAS_MGMT)
2d0e5700
SZ
783 emx_get_hw_control(sc);
784
4cb541ae
SZ
785 /*
786 * Missing Interrupt Following ICR read:
787 *
a835687d
SZ
788 * 82571/82572 specification update errata #76
789 * 82573 specification update errata #31
790 * 82574 specification update errata #12
4cb541ae
SZ
791 */
792 intr_func = emx_intr;
793 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
794 (sc->hw.mac.type == e1000_82571 ||
795 sc->hw.mac.type == e1000_82572 ||
796 sc->hw.mac.type == e1000_82573 ||
797 sc->hw.mac.type == e1000_82574))
798 intr_func = emx_intr_mask;
799
800 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
6d435846 801 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ
802 if (error) {
803 device_printf(dev, "Failed to register interrupt handler");
804 ether_ifdetach(&sc->arpcom.ac_if);
805 goto fail;
806 }
807
704b6287 808 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
5330213c
SZ
809 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
810 return (0);
811fail:
812 emx_detach(dev);
813 return (error);
814}
815
816static int
817emx_detach(device_t dev)
818{
819 struct emx_softc *sc = device_get_softc(dev);
820
821 if (device_is_attached(dev)) {
822 struct ifnet *ifp = &sc->arpcom.ac_if;
823
6d435846 824 ifnet_serialize_all(ifp);
5330213c
SZ
825
826 emx_stop(sc);
827
828 e1000_phy_hw_reset(&sc->hw);
829
830 emx_rel_mgmt(sc);
2d0e5700 831 emx_rel_hw_control(sc);
5330213c
SZ
832
833 if (sc->wol) {
834 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
835 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
836 emx_enable_wol(dev);
837 }
838
839 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
840
6d435846 841 ifnet_deserialize_all(ifp);
5330213c
SZ
842
843 ether_ifdetach(ifp);
a19a8754 844 } else if (sc->memory != NULL) {
2d0e5700 845 emx_rel_hw_control(sc);
5330213c
SZ
846 }
847 bus_generic_detach(dev);
848
849 if (sc->intr_res != NULL) {
850 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
851 sc->intr_res);
852 }
853
7fb43956 854 if (sc->intr_type == PCI_INTR_TYPE_MSI)
704b6287
SZ
855 pci_release_msi(dev);
856
5330213c
SZ
857 if (sc->memory != NULL) {
858 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
859 sc->memory);
860 }
861
071699f8 862 emx_dma_free(sc);
5330213c
SZ
863
864 /* Free sysctl tree */
865 if (sc->sysctl_tree != NULL)
866 sysctl_ctx_free(&sc->sysctl_ctx);
867
a19a8754
SZ
868 if (sc->mta != NULL)
869 kfree(sc->mta, M_DEVBUF);
870
5330213c
SZ
871 return (0);
872}
873
874static int
875emx_shutdown(device_t dev)
876{
877 return emx_suspend(dev);
878}
879
880static int
881emx_suspend(device_t dev)
882{
883 struct emx_softc *sc = device_get_softc(dev);
884 struct ifnet *ifp = &sc->arpcom.ac_if;
885
6d435846 886 ifnet_serialize_all(ifp);
5330213c
SZ
887
888 emx_stop(sc);
889
890 emx_rel_mgmt(sc);
2d0e5700 891 emx_rel_hw_control(sc);
5330213c 892
2d0e5700 893 if (sc->wol) {
5330213c
SZ
894 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
895 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
896 emx_enable_wol(dev);
2d0e5700 897 }
5330213c 898
6d435846 899 ifnet_deserialize_all(ifp);
5330213c
SZ
900
901 return bus_generic_suspend(dev);
902}
903
904static int
905emx_resume(device_t dev)
906{
907 struct emx_softc *sc = device_get_softc(dev);
908 struct ifnet *ifp = &sc->arpcom.ac_if;
909
6d435846 910 ifnet_serialize_all(ifp);
5330213c
SZ
911
912 emx_init(sc);
913 emx_get_mgmt(sc);
914 if_devstart(ifp);
915
6d435846 916 ifnet_deserialize_all(ifp);
5330213c
SZ
917
918 return bus_generic_resume(dev);
919}
920
921static void
922emx_start(struct ifnet *ifp)
923{
924 struct emx_softc *sc = ifp->if_softc;
925 struct mbuf *m_head;
926
6d435846 927 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ
928
929 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
930 return;
931
932 if (!sc->link_active) {
933 ifq_purge(&ifp->if_snd);
934 return;
935 }
936
937 while (!ifq_is_empty(&ifp->if_snd)) {
938 /* Now do we at least have a minimal? */
939 if (EMX_IS_OACTIVE(sc)) {
940 emx_tx_collect(sc);
941 if (EMX_IS_OACTIVE(sc)) {
942 ifp->if_flags |= IFF_OACTIVE;
5330213c
SZ
943 break;
944 }
945 }
946
947 logif(pkt_txqueue);
948 m_head = ifq_dequeue(&ifp->if_snd, NULL);
949 if (m_head == NULL)
950 break;
951
952 if (emx_encap(sc, &m_head)) {
953 ifp->if_oerrors++;
954 emx_tx_collect(sc);
955 continue;
956 }
957
958 /* Send a copy of the frame to the BPF listener */
959 ETHER_BPF_MTAP(ifp, m_head);
960
961 /* Set timeout in case hardware has problems transmitting. */
962 ifp->if_timer = EMX_TX_TIMEOUT;
963 }
964}
965
966static int
967emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
968{
969 struct emx_softc *sc = ifp->if_softc;
970 struct ifreq *ifr = (struct ifreq *)data;
971 uint16_t eeprom_data = 0;
972 int max_frame_size, mask, reinit;
973 int error = 0;
974
2c9effcf 975 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
976
977 switch (command) {
978 case SIOCSIFMTU:
979 switch (sc->hw.mac.type) {
980 case e1000_82573:
981 /*
982 * 82573 only supports jumbo frames
983 * if ASPM is disabled.
984 */
985 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
986 &eeprom_data);
987 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
988 max_frame_size = ETHER_MAX_LEN;
989 break;
990 }
991 /* FALL THROUGH */
992
993 /* Limit Jumbo Frame size */
994 case e1000_82571:
995 case e1000_82572:
996 case e1000_82574:
997 case e1000_80003es2lan:
998 max_frame_size = 9234;
999 break;
1000
1001 default:
1002 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1003 break;
1004 }
1005 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1006 ETHER_CRC_LEN) {
1007 error = EINVAL;
1008 break;
1009 }
1010
1011 ifp->if_mtu = ifr->ifr_mtu;
1012 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1013 ETHER_CRC_LEN;
1014
1015 if (ifp->if_flags & IFF_RUNNING)
1016 emx_init(sc);
1017 break;
1018
1019 case SIOCSIFFLAGS:
1020 if (ifp->if_flags & IFF_UP) {
1021 if ((ifp->if_flags & IFF_RUNNING)) {
1022 if ((ifp->if_flags ^ sc->if_flags) &
1023 (IFF_PROMISC | IFF_ALLMULTI)) {
1024 emx_disable_promisc(sc);
1025 emx_set_promisc(sc);
1026 }
1027 } else {
1028 emx_init(sc);
1029 }
1030 } else if (ifp->if_flags & IFF_RUNNING) {
1031 emx_stop(sc);
1032 }
1033 sc->if_flags = ifp->if_flags;
1034 break;
1035
1036 case SIOCADDMULTI:
1037 case SIOCDELMULTI:
1038 if (ifp->if_flags & IFF_RUNNING) {
1039 emx_disable_intr(sc);
1040 emx_set_multi(sc);
b3a7093f
SZ
1041#ifdef IFPOLL_ENABLE
1042 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ
1043#endif
1044 emx_enable_intr(sc);
1045 }
1046 break;
1047
1048 case SIOCSIFMEDIA:
1049 /* Check SOL/IDER usage */
1050 if (e1000_check_reset_block(&sc->hw)) {
1051 device_printf(sc->dev, "Media change is"
1052 " blocked due to SOL/IDER session.\n");
1053 break;
1054 }
1055 /* FALL THROUGH */
1056
1057 case SIOCGIFMEDIA:
1058 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1059 break;
1060
1061 case SIOCSIFCAP:
1062 reinit = 0;
1063 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3eb0ea09
SZ
1064 if (mask & IFCAP_RXCSUM) {
1065 ifp->if_capenable ^= IFCAP_RXCSUM;
5330213c
SZ
1066 reinit = 1;
1067 }
1068 if (mask & IFCAP_VLAN_HWTAGGING) {
1069 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1070 reinit = 1;
1071 }
3eb0ea09
SZ
1072 if (mask & IFCAP_TXCSUM) {
1073 ifp->if_capenable ^= IFCAP_TXCSUM;
1074 if (ifp->if_capenable & IFCAP_TXCSUM)
1075 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1076 else
1077 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1078 }
1079 if (mask & IFCAP_TSO) {
1080 ifp->if_capenable ^= IFCAP_TSO;
1081 if (ifp->if_capenable & IFCAP_TSO)
1082 ifp->if_hwassist |= CSUM_TSO;
1083 else
1084 ifp->if_hwassist &= ~CSUM_TSO;
1085 }
13890b61 1086 if (mask & IFCAP_RSS)
8434a83b 1087 ifp->if_capenable ^= IFCAP_RSS;
5330213c
SZ
1088 if (reinit && (ifp->if_flags & IFF_RUNNING))
1089 emx_init(sc);
1090 break;
1091
1092 default:
1093 error = ether_ioctl(ifp, command, data);
1094 break;
1095 }
1096 return (error);
1097}
1098
1099static void
1100emx_watchdog(struct ifnet *ifp)
1101{
1102 struct emx_softc *sc = ifp->if_softc;
1103
2c9effcf 1104 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1105
1106 /*
1107 * The timer is set to 5 every time start queues a packet.
1108 * Then txeof keeps resetting it as long as it cleans at
1109 * least one descriptor.
1110 * Finally, anytime all descriptors are clean the timer is
1111 * set to 0.
1112 */
1113
1114 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1115 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1116 /*
1117 * If we reach here, all TX jobs are completed and
1118 * the TX engine should have been idled for some time.
1119 * We don't need to call if_devstart() here.
1120 */
1121 ifp->if_flags &= ~IFF_OACTIVE;
1122 ifp->if_timer = 0;
1123 return;
1124 }
1125
1126 /*
1127 * If we are in this routine because of pause frames, then
1128 * don't reset the hardware.
1129 */
1130 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1131 ifp->if_timer = EMX_TX_TIMEOUT;
1132 return;
1133 }
1134
1135 if (e1000_check_for_link(&sc->hw) == 0)
1136 if_printf(ifp, "watchdog timeout -- resetting\n");
1137
1138 ifp->if_oerrors++;
5330213c
SZ
1139
1140 emx_init(sc);
1141
1142 if (!ifq_is_empty(&ifp->if_snd))
1143 if_devstart(ifp);
1144}
1145
1146static void
1147emx_init(void *xsc)
1148{
1149 struct emx_softc *sc = xsc;
1150 struct ifnet *ifp = &sc->arpcom.ac_if;
1151 device_t dev = sc->dev;
1152 uint32_t pba;
3f939c23 1153 int i;
5330213c 1154
2c9effcf 1155 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1156
1157 emx_stop(sc);
1158
1159 /*
1160 * Packet Buffer Allocation (PBA)
1161 * Writing PBA sets the receive portion of the buffer
1162 * the remainder is used for the transmit buffer.
1163 */
1164 switch (sc->hw.mac.type) {
1165 /* Total Packet Buffer on these is 48K */
1166 case e1000_82571:
1167 case e1000_82572:
1168 case e1000_80003es2lan:
1169 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1170 break;
1171
1172 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1173 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1174 break;
1175
1176 case e1000_82574:
1177 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1178 break;
1179
1180 default:
1181 /* Devices before 82547 had a Packet Buffer of 64K. */
1182 if (sc->max_frame_size > 8192)
1183 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1184 else
1185 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1186 }
1187 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1188
1189 /* Get the latest mac address, User can use a LAA */
1190 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1191
1192 /* Put the address into the Receive Address Array */
1193 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1194
1195 /*
1196 * With the 82571 sc, RAR[0] may be overwritten
1197 * when the other port is reset, we make a duplicate
1198 * in RAR[14] for that eventuality, this assures
1199 * the interface continues to function.
1200 */
1201 if (sc->hw.mac.type == e1000_82571) {
1202 e1000_set_laa_state_82571(&sc->hw, TRUE);
1203 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1204 E1000_RAR_ENTRIES - 1);
1205 }
1206
1207 /* Initialize the hardware */
2d0e5700
SZ
1208 if (emx_reset(sc)) {
1209 device_printf(dev, "Unable to reset the hardware\n");
5330213c
SZ
1210 /* XXX emx_stop()? */
1211 return;
1212 }
1213 emx_update_link_status(sc);
1214
1215 /* Setup VLAN support, basic and offload if available */
1216 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1217
1218 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1219 uint32_t ctrl;
1220
1221 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1222 ctrl |= E1000_CTRL_VME;
1223 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1224 }
1225
5330213c
SZ
1226 /* Configure for OS presence */
1227 emx_get_mgmt(sc);
1228
1229 /* Prepare transmit descriptors and buffers */
1230 emx_init_tx_ring(sc);
1231 emx_init_tx_unit(sc);
1232
1233 /* Setup Multicast table */
1234 emx_set_multi(sc);
1235
1236 /* Prepare receive descriptors and buffers */
13890b61 1237 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
1238 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1239 device_printf(dev,
1240 "Could not setup receive structures\n");
1241 emx_stop(sc);
1242 return;
1243 }
5330213c
SZ
1244 }
1245 emx_init_rx_unit(sc);
1246
1247 /* Don't lose promiscuous settings */
1248 emx_set_promisc(sc);
1249
1250 ifp->if_flags |= IFF_RUNNING;
1251 ifp->if_flags &= ~IFF_OACTIVE;
1252
1253 callout_reset(&sc->timer, hz, emx_timer, sc);
1254 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1255
1256 /* MSI/X configuration for 82574 */
1257 if (sc->hw.mac.type == e1000_82574) {
1258 int tmp;
1259
1260 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1261 tmp |= E1000_CTRL_EXT_PBA_CLR;
1262 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1263 /*
2d0e5700 1264 * XXX MSIX
5330213c
SZ
1265 * Set the IVAR - interrupt vector routing.
1266 * Each nibble represents a vector, high bit
1267 * is enable, other 3 bits are the MSIX table
1268 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1269 * Link (other) to 2, hence the magic number.
1270 */
1271 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1272 }
1273
b3a7093f 1274#ifdef IFPOLL_ENABLE
5330213c
SZ
1275 /*
1276 * Only enable interrupts if we are not polling, make sure
1277 * they are off otherwise.
1278 */
b3a7093f 1279 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ
1280 emx_disable_intr(sc);
1281 else
b3a7093f 1282#endif /* IFPOLL_ENABLE */
5330213c
SZ
1283 emx_enable_intr(sc);
1284
2d0e5700 1285 /* AMT based hardware can now take control from firmware */
de0836d4
SZ
1286 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1287 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
2d0e5700
SZ
1288 emx_get_hw_control(sc);
1289
5330213c
SZ
1290 /* Don't reset the phy next time init gets called */
1291 sc->hw.phy.reset_disable = TRUE;
1292}
1293
5330213c
SZ
1294static void
1295emx_intr(void *xsc)
1296{
4cb541ae
SZ
1297 emx_intr_body(xsc, TRUE);
1298}
1299
1300static void
1301emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1302{
5330213c
SZ
1303 struct ifnet *ifp = &sc->arpcom.ac_if;
1304 uint32_t reg_icr;
1305
1306 logif(intr_beg);
6d435846 1307 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ
1308
1309 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1310
4cb541ae 1311 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
5330213c
SZ
1312 logif(intr_end);
1313 return;
1314 }
1315
1316 /*
1317 * XXX: some laptops trigger several spurious interrupts
df50f778 1318 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ
1319 * reports all-ones value in this case. Processing such
1320 * interrupts would lead to a freeze. I don't know why.
1321 */
1322 if (reg_icr == 0xffffffff) {
1323 logif(intr_end);
1324 return;
1325 }
1326
1327 if (ifp->if_flags & IFF_RUNNING) {
1328 if (reg_icr &
3f939c23
SZ
1329 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1330 int i;
1331
13890b61 1332 for (i = 0; i < sc->rx_ring_cnt; ++i) {
6d435846
SZ
1333 lwkt_serialize_enter(
1334 &sc->rx_data[i].rx_serialize);
3f939c23 1335 emx_rxeof(sc, i, -1);
6d435846
SZ
1336 lwkt_serialize_exit(
1337 &sc->rx_data[i].rx_serialize);
1338 }
3f939c23 1339 }
6446af7b 1340 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1341 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ
1342 emx_txeof(sc);
1343 if (!ifq_is_empty(&ifp->if_snd))
1344 if_devstart(ifp);
6d435846 1345 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ
1346 }
1347 }
1348
1349 /* Link status change */
1350 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1351 emx_serialize_skipmain(sc);
6d435846 1352
5330213c
SZ
1353 callout_stop(&sc->timer);
1354 sc->hw.mac.get_link_status = 1;
1355 emx_update_link_status(sc);
1356
1357 /* Deal with TX cruft when link lost */
1358 emx_tx_purge(sc);
1359
1360 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1361
bca7c435 1362 emx_deserialize_skipmain(sc);
5330213c
SZ
1363 }
1364
1365 if (reg_icr & E1000_ICR_RXO)
1366 sc->rx_overruns++;
1367
1368 logif(intr_end);
1369}
1370
4cb541ae
SZ
1371static void
1372emx_intr_mask(void *xsc)
1373{
1374 struct emx_softc *sc = xsc;
1375
1376 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1377 /*
1378 * NOTE:
1379 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1380 * so don't check it.
1381 */
1382 emx_intr_body(sc, FALSE);
1383 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1384}
1385
5330213c
SZ
1386static void
1387emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1388{
1389 struct emx_softc *sc = ifp->if_softc;
1390
2c9effcf 1391 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1392
1393 emx_update_link_status(sc);
1394
1395 ifmr->ifm_status = IFM_AVALID;
1396 ifmr->ifm_active = IFM_ETHER;
1397
1398 if (!sc->link_active)
1399 return;
1400
1401 ifmr->ifm_status |= IFM_ACTIVE;
1402
1403 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1404 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1405 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1406 } else {
1407 switch (sc->link_speed) {
1408 case 10:
1409 ifmr->ifm_active |= IFM_10_T;
1410 break;
1411 case 100:
1412 ifmr->ifm_active |= IFM_100_TX;
1413 break;
1414
1415 case 1000:
1416 ifmr->ifm_active |= IFM_1000_T;
1417 break;
1418 }
1419 if (sc->link_duplex == FULL_DUPLEX)
1420 ifmr->ifm_active |= IFM_FDX;
1421 else
1422 ifmr->ifm_active |= IFM_HDX;
1423 }
1424}
1425
1426static int
1427emx_media_change(struct ifnet *ifp)
1428{
1429 struct emx_softc *sc = ifp->if_softc;
1430 struct ifmedia *ifm = &sc->media;
1431
2c9effcf 1432 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1433
1434 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1435 return (EINVAL);
1436
1437 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1438 case IFM_AUTO:
1439 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1440 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1441 break;
1442
1443 case IFM_1000_LX:
1444 case IFM_1000_SX:
1445 case IFM_1000_T:
1446 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1447 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1448 break;
1449
1450 case IFM_100_TX:
1451 sc->hw.mac.autoneg = FALSE;
1452 sc->hw.phy.autoneg_advertised = 0;
1453 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1454 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1455 else
1456 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1457 break;
1458
1459 case IFM_10_T:
1460 sc->hw.mac.autoneg = FALSE;
1461 sc->hw.phy.autoneg_advertised = 0;
1462 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1463 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1464 else
1465 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1466 break;
1467
1468 default:
1469 if_printf(ifp, "Unsupported media type\n");
1470 break;
1471 }
1472
1473 /*
1474 * As the speed/duplex settings my have changed we need to
1475 * reset the PHY.
1476 */
1477 sc->hw.phy.reset_disable = FALSE;
1478
1479 emx_init(sc);
1480
1481 return (0);
1482}
1483
1484static int
1485emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1486{
1487 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1488 bus_dmamap_t map;
323e5ecd 1489 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ
1490 struct e1000_tx_desc *ctxd = NULL;
1491 struct mbuf *m_head = *m_headp;
1492 uint32_t txd_upper, txd_lower, cmd = 0;
1493 int maxsegs, nsegs, i, j, first, last = 0, error;
1494
3eb0ea09
SZ
1495 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1496 error = emx_tso_pullup(sc, m_headp);
1497 if (error)
1498 return error;
1499 m_head = *m_headp;
1500 }
1501
5330213c
SZ
1502 txd_upper = txd_lower = 0;
1503
1504 /*
1505 * Capture the first descriptor index, this descriptor
1506 * will have the index of the EOP which is the only one
1507 * that now gets a DONE bit writeback.
1508 */
1509 first = sc->next_avail_tx_desc;
323e5ecd 1510 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
1511 tx_buffer_mapped = tx_buffer;
1512 map = tx_buffer->map;
1513
1514 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
ed20d0e3 1515 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
5330213c
SZ
1516 if (maxsegs > EMX_MAX_SCATTER)
1517 maxsegs = EMX_MAX_SCATTER;
1518
1519 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1520 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1521 if (error) {
5330213c
SZ
1522 m_freem(*m_headp);
1523 *m_headp = NULL;
1524 return error;
1525 }
1526 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1527
1528 m_head = *m_headp;
1529 sc->tx_nsegs += nsegs;
1530
3eb0ea09
SZ
1531 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1532 /* TSO will consume one TX desc */
1533 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1534 &txd_upper, &txd_lower);
1535 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
5330213c
SZ
1536 /* TX csum offloading will consume one TX desc */
1537 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1538 }
1539 i = sc->next_avail_tx_desc;
1540
1541 /* Set up our transmit descriptors */
1542 for (j = 0; j < nsegs; j++) {
323e5ecd 1543 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1544 ctxd = &sc->tx_desc_base[i];
1545
1546 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1547 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1548 txd_lower | segs[j].ds_len);
1549 ctxd->upper.data = htole32(txd_upper);
1550
1551 last = i;
1552 if (++i == sc->num_tx_desc)
1553 i = 0;
5330213c
SZ
1554 }
1555
1556 sc->next_avail_tx_desc = i;
1557
1558 KKASSERT(sc->num_tx_desc_avail > nsegs);
1559 sc->num_tx_desc_avail -= nsegs;
1560
1561 /* Handle VLAN tag */
1562 if (m_head->m_flags & M_VLANTAG) {
1563 /* Set the vlan id. */
1564 ctxd->upper.fields.special =
1565 htole16(m_head->m_pkthdr.ether_vlantag);
1566
1567 /* Tell hardware to add tag */
1568 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1569 }
1570
1571 tx_buffer->m_head = m_head;
1572 tx_buffer_mapped->map = tx_buffer->map;
1573 tx_buffer->map = map;
1574
1575 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1576 sc->tx_nsegs = 0;
4e4e8481
SZ
1577
1578 /*
1579 * Report Status (RS) is turned on
1580 * every tx_int_nsegs descriptors.
1581 */
5330213c
SZ
1582 cmd = E1000_TXD_CMD_RS;
1583
b4b0a2b4
SZ
1584 /*
1585 * Keep track of the descriptor, which will
1586 * be written back by hardware.
1587 */
5330213c
SZ
1588 sc->tx_dd[sc->tx_dd_tail] = last;
1589 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1590 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1591 }
1592
1593 /*
1594 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ
1595 */
1596 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1597
5330213c
SZ
1598 /*
1599 * Advance the Transmit Descriptor Tail (TDT), this tells
1600 * the E1000 that this frame is available to transmit.
1601 */
1602 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1603
1604 return (0);
1605}
1606
1607static void
1608emx_set_promisc(struct emx_softc *sc)
1609{
1610 struct ifnet *ifp = &sc->arpcom.ac_if;
1611 uint32_t reg_rctl;
1612
1613 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1614
1615 if (ifp->if_flags & IFF_PROMISC) {
1616 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1617 /* Turn this on if you want to see bad packets */
1618 if (emx_debug_sbp)
1619 reg_rctl |= E1000_RCTL_SBP;
1620 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1621 } else if (ifp->if_flags & IFF_ALLMULTI) {
1622 reg_rctl |= E1000_RCTL_MPE;
1623 reg_rctl &= ~E1000_RCTL_UPE;
1624 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1625 }
1626}
1627
1628static void
1629emx_disable_promisc(struct emx_softc *sc)
1630{
1631 uint32_t reg_rctl;
1632
1633 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1634
1635 reg_rctl &= ~E1000_RCTL_UPE;
1636 reg_rctl &= ~E1000_RCTL_MPE;
1637 reg_rctl &= ~E1000_RCTL_SBP;
1638 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1639}
1640
1641static void
1642emx_set_multi(struct emx_softc *sc)
1643{
1644 struct ifnet *ifp = &sc->arpcom.ac_if;
1645 struct ifmultiaddr *ifma;
1646 uint32_t reg_rctl = 0;
2d0e5700 1647 uint8_t *mta;
5330213c
SZ
1648 int mcnt = 0;
1649
2d0e5700
SZ
1650 mta = sc->mta;
1651 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1652
441d34b2 1653 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ
1654 if (ifma->ifma_addr->sa_family != AF_LINK)
1655 continue;
1656
1657 if (mcnt == EMX_MCAST_ADDR_MAX)
1658 break;
1659
1660 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1661 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1662 mcnt++;
1663 }
1664
1665 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1666 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1667 reg_rctl |= E1000_RCTL_MPE;
1668 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1669 } else {
6a5a645e 1670 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
5330213c
SZ
1671 }
1672}
1673
1674/*
1675 * This routine checks for link status and updates statistics.
1676 */
1677static void
1678emx_timer(void *xsc)
1679{
1680 struct emx_softc *sc = xsc;
1681 struct ifnet *ifp = &sc->arpcom.ac_if;
1682
37e854ff 1683 lwkt_serialize_enter(&sc->main_serialize);
5330213c
SZ
1684
1685 emx_update_link_status(sc);
1686 emx_update_stats(sc);
1687
1688 /* Reset LAA into RAR[0] on 82571 */
1689 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1690 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1691
1692 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1693 emx_print_hw_stats(sc);
1694
1695 emx_smartspeed(sc);
1696
1697 callout_reset(&sc->timer, hz, emx_timer, sc);
1698
37e854ff 1699 lwkt_serialize_exit(&sc->main_serialize);
5330213c
SZ
1700}
1701
1702static void
1703emx_update_link_status(struct emx_softc *sc)
1704{
1705 struct e1000_hw *hw = &sc->hw;
1706 struct ifnet *ifp = &sc->arpcom.ac_if;
1707 device_t dev = sc->dev;
1708 uint32_t link_check = 0;
1709
1710 /* Get the cached link value or read phy for real */
1711 switch (hw->phy.media_type) {
1712 case e1000_media_type_copper:
1713 if (hw->mac.get_link_status) {
1714 /* Do the work to read phy */
1715 e1000_check_for_link(hw);
1716 link_check = !hw->mac.get_link_status;
1717 if (link_check) /* ESB2 fix */
1718 e1000_cfg_on_link_up(hw);
1719 } else {
1720 link_check = TRUE;
1721 }
1722 break;
1723
1724 case e1000_media_type_fiber:
1725 e1000_check_for_link(hw);
1726 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1727 break;
1728
1729 case e1000_media_type_internal_serdes:
1730 e1000_check_for_link(hw);
1731 link_check = sc->hw.mac.serdes_has_link;
1732 break;
1733
1734 case e1000_media_type_unknown:
1735 default:
1736 break;
1737 }
1738
1739 /* Now check for a transition */
1740 if (link_check && sc->link_active == 0) {
1741 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1742 &sc->link_duplex);
1743
1744 /*
1745 * Check if we should enable/disable SPEED_MODE bit on
1746 * 82571EB/82572EI
1747 */
2d0e5700
SZ
1748 if (sc->link_speed != SPEED_1000 &&
1749 (hw->mac.type == e1000_82571 ||
1750 hw->mac.type == e1000_82572)) {
5330213c
SZ
1751 int tarc0;
1752
1753 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 1754 tarc0 &= ~EMX_TARC_SPEED_MODE;
5330213c
SZ
1755 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1756 }
1757 if (bootverbose) {
1758 device_printf(dev, "Link is up %d Mbps %s\n",
1759 sc->link_speed,
1760 ((sc->link_duplex == FULL_DUPLEX) ?
1761 "Full Duplex" : "Half Duplex"));
1762 }
1763 sc->link_active = 1;
1764 sc->smartspeed = 0;
1765 ifp->if_baudrate = sc->link_speed * 1000000;
1766 ifp->if_link_state = LINK_STATE_UP;
1767 if_link_state_change(ifp);
1768 } else if (!link_check && sc->link_active == 1) {
1769 ifp->if_baudrate = sc->link_speed = 0;
1770 sc->link_duplex = 0;
1771 if (bootverbose)
1772 device_printf(dev, "Link is Down\n");
1773 sc->link_active = 0;
1774#if 0
1775 /* Link down, disable watchdog */
1776 if->if_timer = 0;
1777#endif
1778 ifp->if_link_state = LINK_STATE_DOWN;
1779 if_link_state_change(ifp);
1780 }
1781}
1782
1783static void
1784emx_stop(struct emx_softc *sc)
1785{
1786 struct ifnet *ifp = &sc->arpcom.ac_if;
1787 int i;
1788
2c9effcf 1789 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1790
1791 emx_disable_intr(sc);
1792
1793 callout_stop(&sc->timer);
1794
1795 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1796 ifp->if_timer = 0;
1797
3f939c23
SZ
1798 /*
1799 * Disable multiple receive queues.
1800 *
1801 * NOTE:
1802 * We should disable multiple receive queues before
1803 * resetting the hardware.
1804 */
1805 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1806
5330213c
SZ
1807 e1000_reset_hw(&sc->hw);
1808 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1809
1810 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1811 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1812
1813 if (tx_buffer->m_head != NULL) {
1814 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1815 m_freem(tx_buffer->m_head);
1816 tx_buffer->m_head = NULL;
1817 }
1818 }
1819
13890b61 1820 for (i = 0; i < sc->rx_ring_cnt; ++i)
3f939c23 1821 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ
1822
1823 sc->csum_flags = 0;
3eb0ea09 1824 sc->csum_lhlen = 0;
5330213c 1825 sc->csum_iphlen = 0;
3eb0ea09
SZ
1826 sc->csum_thlen = 0;
1827 sc->csum_mss = 0;
1828 sc->csum_pktlen = 0;
5330213c
SZ
1829
1830 sc->tx_dd_head = 0;
1831 sc->tx_dd_tail = 0;
1832 sc->tx_nsegs = 0;
1833}
1834
1835static int
2d0e5700 1836emx_reset(struct emx_softc *sc)
5330213c
SZ
1837{
1838 device_t dev = sc->dev;
1839 uint16_t rx_buffer_size;
1840
5330213c
SZ
1841 /* Set up smart power down as default off on newer adapters. */
1842 if (!emx_smart_pwr_down &&
1843 (sc->hw.mac.type == e1000_82571 ||
1844 sc->hw.mac.type == e1000_82572)) {
1845 uint16_t phy_tmp = 0;
1846
1847 /* Speed up time to link by disabling smart power down. */
1848 e1000_read_phy_reg(&sc->hw,
1849 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1850 phy_tmp &= ~IGP02E1000_PM_SPD;
1851 e1000_write_phy_reg(&sc->hw,
1852 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1853 }
1854
1855 /*
1856 * These parameters control the automatic generation (Tx) and
1857 * response (Rx) to Ethernet PAUSE frames.
1858 * - High water mark should allow for at least two frames to be
1859 * received after sending an XOFF.
1860 * - Low water mark works best when it is very near the high water mark.
1861 * This allows the receiver to restart by sending XON when it has
1862 * drained a bit. Here we use an arbitary value of 1500 which will
1863 * restart after one full frame is pulled from the buffer. There
1864 * could be several smaller frames in the buffer and if so they will
1865 * not trigger the XON until their total number reduces the buffer
1866 * by 1500.
1867 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1868 */
1869 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1870
1871 sc->hw.fc.high_water = rx_buffer_size -
1872 roundup2(sc->max_frame_size, 1024);
1873 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1874
1875 if (sc->hw.mac.type == e1000_80003es2lan)
1876 sc->hw.fc.pause_time = 0xFFFF;
1877 else
1878 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1879 sc->hw.fc.send_xon = TRUE;
1880 sc->hw.fc.requested_mode = e1000_fc_full;
1881
2d0e5700
SZ
1882 /* Issue a global reset */
1883 e1000_reset_hw(&sc->hw);
1884 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
6d5e2922 1885 emx_disable_aspm(sc);
2d0e5700 1886
5330213c
SZ
1887 if (e1000_init_hw(&sc->hw) < 0) {
1888 device_printf(dev, "Hardware Initialization Failed\n");
1889 return (EIO);
1890 }
1891
2d0e5700
SZ
1892 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1893 e1000_get_phy_info(&sc->hw);
5330213c
SZ
1894 e1000_check_for_link(&sc->hw);
1895
1896 return (0);
1897}
1898
1899static void
1900emx_setup_ifp(struct emx_softc *sc)
1901{
1902 struct ifnet *ifp = &sc->arpcom.ac_if;
1903
1904 if_initname(ifp, device_get_name(sc->dev),
1905 device_get_unit(sc->dev));
1906 ifp->if_softc = sc;
1907 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1908 ifp->if_init = emx_init;
1909 ifp->if_ioctl = emx_ioctl;
1910 ifp->if_start = emx_start;
b3a7093f 1911#ifdef IFPOLL_ENABLE
f994de37 1912 ifp->if_npoll = emx_npoll;
5330213c
SZ
1913#endif
1914 ifp->if_watchdog = emx_watchdog;
6d435846
SZ
1915 ifp->if_serialize = emx_serialize;
1916 ifp->if_deserialize = emx_deserialize;
1917 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ
1918#ifdef INVARIANTS
1919 ifp->if_serialize_assert = emx_serialize_assert;
1920#endif
5330213c
SZ
1921 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1922 ifq_set_ready(&ifp->if_snd);
1923
ae474cfa 1924 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ
1925
1926 ifp->if_capabilities = IFCAP_HWCSUM |
1927 IFCAP_VLAN_HWTAGGING |
3eb0ea09
SZ
1928 IFCAP_VLAN_MTU |
1929 IFCAP_TSO;
8434a83b
SZ
1930 if (sc->rx_ring_cnt > 1)
1931 ifp->if_capabilities |= IFCAP_RSS;
5330213c 1932 ifp->if_capenable = ifp->if_capabilities;
3eb0ea09 1933 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
5330213c
SZ
1934
1935 /*
1936 * Tell the upper layer(s) we support long frames.
1937 */
1938 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1939
1940 /*
1941 * Specify the media types supported by this sc and register
1942 * callbacks to update media and link information
1943 */
1944 ifmedia_init(&sc->media, IFM_IMASK,
1945 emx_media_change, emx_media_status);
1946 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1947 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1948 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1949 0, NULL);
1950 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1951 } else {
1952 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1953 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1954 0, NULL);
1955 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1956 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1957 0, NULL);
1958 if (sc->hw.phy.type != e1000_phy_ife) {
1959 ifmedia_add(&sc->media,
1960 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1961 ifmedia_add(&sc->media,
1962 IFM_ETHER | IFM_1000_T, 0, NULL);
1963 }
1964 }
1965 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1966 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1967}
1968
1969/*
1970 * Workaround for SmartSpeed on 82541 and 82547 controllers
1971 */
1972static void
1973emx_smartspeed(struct emx_softc *sc)
1974{
1975 uint16_t phy_tmp;
1976
1977 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1978 sc->hw.mac.autoneg == 0 ||
1979 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1980 return;
1981
1982 if (sc->smartspeed == 0) {
1983 /*
1984 * If Master/Slave config fault is asserted twice,
1985 * we assume back-to-back
1986 */
1987 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1988 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1989 return;
1990 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1991 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1992 e1000_read_phy_reg(&sc->hw,
1993 PHY_1000T_CTRL, &phy_tmp);
1994 if (phy_tmp & CR_1000T_MS_ENABLE) {
1995 phy_tmp &= ~CR_1000T_MS_ENABLE;
1996 e1000_write_phy_reg(&sc->hw,
1997 PHY_1000T_CTRL, phy_tmp);
1998 sc->smartspeed++;
1999 if (sc->hw.mac.autoneg &&
2000 !e1000_phy_setup_autoneg(&sc->hw) &&
2001 !e1000_read_phy_reg(&sc->hw,
2002 PHY_CONTROL, &phy_tmp)) {
2003 phy_tmp |= MII_CR_AUTO_NEG_EN |
2004 MII_CR_RESTART_AUTO_NEG;
2005 e1000_write_phy_reg(&sc->hw,
2006 PHY_CONTROL, phy_tmp);
2007 }
2008 }
2009 }
2010 return;
2011 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2012 /* If still no link, perhaps using 2/3 pair cable */
2013 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2014 phy_tmp |= CR_1000T_MS_ENABLE;
2015 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2016 if (sc->hw.mac.autoneg &&
2017 !e1000_phy_setup_autoneg(&sc->hw) &&
2018 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2019 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2020 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2021 }
2022 }
2023
2024 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2025 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2026 sc->smartspeed = 0;
2027}
2028
5330213c
SZ
2029static int
2030emx_create_tx_ring(struct emx_softc *sc)
2031{
2032 device_t dev = sc->dev;
323e5ecd 2033 struct emx_txbuf *tx_buffer;
b4d8c36b 2034 int error, i, tsize, ntxd;
bdca134f
SZ
2035
2036 /*
2037 * Validate number of transmit descriptors. It must not exceed
2038 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2039 */
b4d8c36b
SZ
2040 ntxd = device_getenv_int(dev, "txd", emx_txd);
2041 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2042 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
bdca134f 2043 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
b4d8c36b 2044 EMX_DEFAULT_TXD, ntxd);
bdca134f
SZ
2045 sc->num_tx_desc = EMX_DEFAULT_TXD;
2046 } else {
b4d8c36b 2047 sc->num_tx_desc = ntxd;
bdca134f
SZ
2048 }
2049
2050 /*
2051 * Allocate Transmit Descriptor ring
2052 */
2053 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2054 EMX_DBA_ALIGN);
a596084c
SZ
2055 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2056 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2057 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2058 &sc->tx_desc_paddr);
2059 if (sc->tx_desc_base == NULL) {
bdca134f 2060 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 2061 return ENOMEM;
bdca134f 2062 }
5330213c 2063
323e5ecd
SZ
2064 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2065 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2066
2067 /*
2068 * Create DMA tags for tx buffers
2069 */
2070 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2071 1, 0, /* alignment, bounds */
2072 BUS_SPACE_MAXADDR, /* lowaddr */
2073 BUS_SPACE_MAXADDR, /* highaddr */
2074 NULL, NULL, /* filter, filterarg */
2075 EMX_TSO_SIZE, /* maxsize */
2076 EMX_MAX_SCATTER, /* nsegments */
2077 EMX_MAX_SEGSIZE, /* maxsegsize */
2078 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2079 BUS_DMA_ONEBPAGE, /* flags */
2080 &sc->txtag);
2081 if (error) {
2082 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ
2083 kfree(sc->tx_buf, M_DEVBUF);
2084 sc->tx_buf = NULL;
5330213c
SZ
2085 return error;
2086 }
2087
2088 /*
2089 * Create DMA maps for tx buffers
2090 */
2091 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 2092 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2093
2094 error = bus_dmamap_create(sc->txtag,
2095 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2096 &tx_buffer->map);
2097 if (error) {
2098 device_printf(dev, "Unable to create TX DMA map\n");
2099 emx_destroy_tx_ring(sc, i);
2100 return error;
2101 }
2102 }
2103 return (0);
2104}
2105
2106static void
2107emx_init_tx_ring(struct emx_softc *sc)
2108{
2109 /* Clear the old ring contents */
2110 bzero(sc->tx_desc_base,
2111 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2112
2113 /* Reset state */
2114 sc->next_avail_tx_desc = 0;
2115 sc->next_tx_to_clean = 0;
2116 sc->num_tx_desc_avail = sc->num_tx_desc;
2117}
2118
2119static void
2120emx_init_tx_unit(struct emx_softc *sc)
2121{
2122 uint32_t tctl, tarc, tipg = 0;
2123 uint64_t bus_addr;
2124
2125 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 2126 bus_addr = sc->tx_desc_paddr;
5330213c
SZ
2127 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2128 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2129 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2130 (uint32_t)(bus_addr >> 32));
2131 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2132 (uint32_t)bus_addr);
2133 /* Setup the HW Tx Head and Tail descriptor pointers */
2134 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2135 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2136
2137 /* Set the default values for the Tx Inter Packet Gap timer */
2138 switch (sc->hw.mac.type) {
2139 case e1000_80003es2lan:
2140 tipg = DEFAULT_82543_TIPG_IPGR1;
2141 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2142 E1000_TIPG_IPGR2_SHIFT;
2143 break;
2144
2145 default:
2146 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2147 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2148 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2149 else
2150 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2151 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2152 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2153 break;
2154 }
2155
2156 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2157
2158 /* NOTE: 0 is not allowed for TIDV */
2159 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2160 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2161
2162 if (sc->hw.mac.type == e1000_82571 ||
2163 sc->hw.mac.type == e1000_82572) {
2164 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2165 tarc |= EMX_TARC_SPEED_MODE;
2166 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2167 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2168 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2169 tarc |= 1;
2170 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2171 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2172 tarc |= 1;
2173 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2174 }
2175
2176 /* Program the Transmit Control Register */
2177 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2178 tctl &= ~E1000_TCTL_CT;
2179 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2180 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2181 tctl |= E1000_TCTL_MULR;
2182
2183 /* This write will effectively turn on the transmit unit. */
2184 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2185}
2186
2187static void
2188emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2189{
323e5ecd 2190 struct emx_txbuf *tx_buffer;
5330213c
SZ
2191 int i;
2192
bdca134f 2193 /* Free Transmit Descriptor ring */
a596084c
SZ
2194 if (sc->tx_desc_base) {
2195 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2196 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2197 sc->tx_desc_dmap);
2198 bus_dma_tag_destroy(sc->tx_desc_dtag);
2199
2200 sc->tx_desc_base = NULL;
2201 }
bdca134f 2202
323e5ecd 2203 if (sc->tx_buf == NULL)
5330213c
SZ
2204 return;
2205
2206 for (i = 0; i < ndesc; i++) {
323e5ecd 2207 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2208
2209 KKASSERT(tx_buffer->m_head == NULL);
2210 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2211 }
2212 bus_dma_tag_destroy(sc->txtag);
2213
323e5ecd
SZ
2214 kfree(sc->tx_buf, M_DEVBUF);
2215 sc->tx_buf = NULL;
5330213c
SZ
2216}
2217
2218/*
2219 * The offload context needs to be set when we transfer the first
2220 * packet of a particular protocol (TCP/UDP). This routine has been
2221 * enhanced to deal with inserted VLAN headers.
2222 *
2223 * If the new packet's ether header length, ip header length and
2224 * csum offloading type are same as the previous packet, we should
2225 * avoid allocating a new csum context descriptor; mainly to take
2226 * advantage of the pipeline effect of the TX data read request.
2227 *
2228 * This function returns number of TX descrptors allocated for
2229 * csum context.
2230 */
2231static int
2232emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2233 uint32_t *txd_upper, uint32_t *txd_lower)
2234{
2235 struct e1000_context_desc *TXD;
5330213c
SZ
2236 int curr_txd, ehdrlen, csum_flags;
2237 uint32_t cmd, hdr_len, ip_hlen;
5330213c
SZ
2238
2239 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
68447568
SZ
2240 ip_hlen = mp->m_pkthdr.csum_iphlen;
2241 ehdrlen = mp->m_pkthdr.csum_lhlen;
5330213c 2242
3eb0ea09 2243 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
5330213c
SZ
2244 sc->csum_flags == csum_flags) {
2245 /*
2246 * Same csum offload context as the previous packets;
2247 * just return.
2248 */
2249 *txd_upper = sc->csum_txd_upper;
2250 *txd_lower = sc->csum_txd_lower;
2251 return 0;
2252 }
2253
2254 /*
2255 * Setup a new csum offload context.
2256 */
2257
2258 curr_txd = sc->next_avail_tx_desc;
5330213c
SZ
2259 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2260
2261 cmd = 0;
2262
2263 /* Setup of IP header checksum. */
2264 if (csum_flags & CSUM_IP) {
2265 /*
2266 * Start offset for header checksum calculation.
2267 * End offset for header checksum calculation.
2268 * Offset of place to put the checksum.
2269 */
2270 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2271 TXD->lower_setup.ip_fields.ipcse =
2272 htole16(ehdrlen + ip_hlen - 1);
2273 TXD->lower_setup.ip_fields.ipcso =
2274 ehdrlen + offsetof(struct ip, ip_sum);
2275 cmd |= E1000_TXD_CMD_IP;
2276 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2277 }
2278 hdr_len = ehdrlen + ip_hlen;
2279
2280 if (csum_flags & CSUM_TCP) {
2281 /*
2282 * Start offset for payload checksum calculation.
2283 * End offset for payload checksum calculation.
2284 * Offset of place to put the checksum.
2285 */
2286 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2287 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2288 TXD->upper_setup.tcp_fields.tucso =
2289 hdr_len + offsetof(struct tcphdr, th_sum);
2290 cmd |= E1000_TXD_CMD_TCP;
2291 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2292 } else if (csum_flags & CSUM_UDP) {
2293 /*
2294 * Start offset for header checksum calculation.
2295 * End offset for header checksum calculation.
2296 * Offset of place to put the checksum.
2297 */
2298 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2299 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2300 TXD->upper_setup.tcp_fields.tucso =
2301 hdr_len + offsetof(struct udphdr, uh_sum);
2302 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2303 }
2304
2305 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2306 E1000_TXD_DTYP_D; /* Data descr */
2307
2308 /* Save the information for this csum offloading context */
3eb0ea09 2309 sc->csum_lhlen = ehdrlen;
5330213c
SZ
2310 sc->csum_iphlen = ip_hlen;
2311 sc->csum_flags = csum_flags;
2312 sc->csum_txd_upper = *txd_upper;
2313 sc->csum_txd_lower = *txd_lower;
2314
2315 TXD->tcp_seg_setup.data = htole32(0);
2316 TXD->cmd_and_length =
2317 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ
2318
2319 if (++curr_txd == sc->num_tx_desc)
2320 curr_txd = 0;
2321
2322 KKASSERT(sc->num_tx_desc_avail > 0);
2323 sc->num_tx_desc_avail--;
2324
2325 sc->next_avail_tx_desc = curr_txd;
2326 return 1;
2327}
2328
5330213c
SZ
2329static void
2330emx_txeof(struct emx_softc *sc)
2331{
2332 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2333 struct emx_txbuf *tx_buffer;
5330213c
SZ
2334 int first, num_avail;
2335
2336 if (sc->tx_dd_head == sc->tx_dd_tail)
2337 return;
2338
2339 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2340 return;
2341
2342 num_avail = sc->num_tx_desc_avail;
2343 first = sc->next_tx_to_clean;
2344
2345 while (sc->tx_dd_head != sc->tx_dd_tail) {
2346 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2347 struct e1000_tx_desc *tx_desc;
5330213c
SZ
2348
2349 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ
2350 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2351 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2352
2353 if (++dd_idx == sc->num_tx_desc)
2354 dd_idx = 0;
2355
2356 while (first != dd_idx) {
2357 logif(pkt_txclean);
2358
5330213c
SZ
2359 num_avail++;
2360
323e5ecd 2361 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2362 if (tx_buffer->m_head) {
2363 ifp->if_opackets++;
2364 bus_dmamap_unload(sc->txtag,
2365 tx_buffer->map);
2366 m_freem(tx_buffer->m_head);
2367 tx_buffer->m_head = NULL;
2368 }
2369
2370 if (++first == sc->num_tx_desc)
2371 first = 0;
2372 }
2373 } else {
2374 break;
2375 }
2376 }
2377 sc->next_tx_to_clean = first;
2378 sc->num_tx_desc_avail = num_avail;
2379
2380 if (sc->tx_dd_head == sc->tx_dd_tail) {
2381 sc->tx_dd_head = 0;
2382 sc->tx_dd_tail = 0;
2383 }
2384
2385 if (!EMX_IS_OACTIVE(sc)) {
2386 ifp->if_flags &= ~IFF_OACTIVE;
2387
2388 /* All clean, turn off the timer */
2389 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2390 ifp->if_timer = 0;
2391 }
2392}
2393
2394static void
2395emx_tx_collect(struct emx_softc *sc)
2396{
2397 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2398 struct emx_txbuf *tx_buffer;
5330213c
SZ
2399 int tdh, first, num_avail, dd_idx = -1;
2400
2401 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2402 return;
2403
2404 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2405 if (tdh == sc->next_tx_to_clean)
2406 return;
2407
2408 if (sc->tx_dd_head != sc->tx_dd_tail)
2409 dd_idx = sc->tx_dd[sc->tx_dd_head];
2410
2411 num_avail = sc->num_tx_desc_avail;
2412 first = sc->next_tx_to_clean;
2413
2414 while (first != tdh) {
2415 logif(pkt_txclean);
2416
5330213c
SZ
2417 num_avail++;
2418
323e5ecd 2419 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2420 if (tx_buffer->m_head) {
2421 ifp->if_opackets++;
2422 bus_dmamap_unload(sc->txtag,
2423 tx_buffer->map);
2424 m_freem(tx_buffer->m_head);
2425 tx_buffer->m_head = NULL;
2426 }
2427
2428 if (first == dd_idx) {
2429 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2430 if (sc->tx_dd_head == sc->tx_dd_tail) {
2431 sc->tx_dd_head = 0;
2432 sc->tx_dd_tail = 0;
2433 dd_idx = -1;
2434 } else {
2435 dd_idx = sc->tx_dd[sc->tx_dd_head];
2436 }
2437 }
2438
2439 if (++first == sc->num_tx_desc)
2440 first = 0;
2441 }
2442 sc->next_tx_to_clean = first;
2443 sc->num_tx_desc_avail = num_avail;
2444
2445 if (!EMX_IS_OACTIVE(sc)) {
2446 ifp->if_flags &= ~IFF_OACTIVE;
2447
2448 /* All clean, turn off the timer */
2449 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2450 ifp->if_timer = 0;
2451 }
2452}
2453
2454/*
2455 * When Link is lost sometimes there is work still in the TX ring
2456 * which will result in a watchdog, rather than allow that do an
2457 * attempted cleanup and then reinit here. Note that this has been
2458 * seens mostly with fiber adapters.
2459 */
2460static void
2461emx_tx_purge(struct emx_softc *sc)
2462{
2463 struct ifnet *ifp = &sc->arpcom.ac_if;
2464
2465 if (!sc->link_active && ifp->if_timer) {
2466 emx_tx_collect(sc);
2467 if (ifp->if_timer) {
2468 if_printf(ifp, "Link lost, TX pending, reinit\n");
2469 ifp->if_timer = 0;
2470 emx_init(sc);
2471 }
2472 }
2473}
2474
2475static int
c39e3a1f 2476emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ
2477{
2478 struct mbuf *m;
2479 bus_dma_segment_t seg;
2480 bus_dmamap_t map;
323e5ecd 2481 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2482 int error, nseg;
2483
2484 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2485 if (m == NULL) {
5330213c
SZ
2486 if (init) {
2487 if_printf(&sc->arpcom.ac_if,
2488 "Unable to allocate RX mbuf\n");
2489 }
2490 return (ENOBUFS);
2491 }
2492 m->m_len = m->m_pkthdr.len = MCLBYTES;
2493
2494 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2495 m_adj(m, ETHER_ALIGN);
2496
c39e3a1f
SZ
2497 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2498 rdata->rx_sparemap, m,
5330213c
SZ
2499 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2500 if (error) {
2501 m_freem(m);
2502 if (init) {
2503 if_printf(&sc->arpcom.ac_if,
2504 "Unable to load RX mbuf\n");
2505 }
2506 return (error);
2507 }
2508
323e5ecd 2509 rx_buffer = &rdata->rx_buf[i];
5330213c 2510 if (rx_buffer->m_head != NULL)
c39e3a1f 2511 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ
2512
2513 map = rx_buffer->map;
c39e3a1f
SZ
2514 rx_buffer->map = rdata->rx_sparemap;
2515 rdata->rx_sparemap = map;
5330213c
SZ
2516
2517 rx_buffer->m_head = m;
235b9d30 2518 rx_buffer->paddr = seg.ds_addr;
5330213c 2519
235b9d30 2520 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ
2521 return (0);
2522}
2523
2524static int
c39e3a1f 2525emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2526{
2527 device_t dev = sc->dev;
323e5ecd 2528 struct emx_rxbuf *rx_buffer;
b4d8c36b 2529 int i, error, rsize, nrxd;
bdca134f
SZ
2530
2531 /*
2532 * Validate number of receive descriptors. It must not exceed
2533 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2534 */
b4d8c36b
SZ
2535 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2536 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2537 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
bdca134f 2538 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
b4d8c36b 2539 EMX_DEFAULT_RXD, nrxd);
c39e3a1f 2540 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2541 } else {
b4d8c36b 2542 rdata->num_rx_desc = nrxd;
bdca134f
SZ
2543 }
2544
2545 /*
2546 * Allocate Receive Descriptor ring
2547 */
235b9d30 2548 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2549 EMX_DBA_ALIGN);
235b9d30 2550 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2551 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ
2552 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2553 &rdata->rx_desc_paddr);
235b9d30 2554 if (rdata->rx_desc == NULL) {
bdca134f 2555 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2556 return ENOMEM;
bdca134f 2557 }
5330213c 2558
323e5ecd
SZ
2559 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2560 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2561
2562 /*
2563 * Create DMA tag for rx buffers
2564 */
2565 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2566 1, 0, /* alignment, bounds */
2567 BUS_SPACE_MAXADDR, /* lowaddr */
2568 BUS_SPACE_MAXADDR, /* highaddr */
2569 NULL, NULL, /* filter, filterarg */
2570 MCLBYTES, /* maxsize */
2571 1, /* nsegments */
2572 MCLBYTES, /* maxsegsize */
2573 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2574 &rdata->rxtag);
5330213c
SZ
2575 if (error) {
2576 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ
2577 kfree(rdata->rx_buf, M_DEVBUF);
2578 rdata->rx_buf = NULL;
5330213c
SZ
2579 return error;
2580 }
2581
2582 /*
2583 * Create spare DMA map for rx buffers
2584 */
c39e3a1f
SZ
2585 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2586 &rdata->rx_sparemap);
5330213c
SZ
2587 if (error) {
2588 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2589 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ
2590 kfree(rdata->rx_buf, M_DEVBUF);
2591 rdata->rx_buf = NULL;
5330213c
SZ
2592 return error;
2593 }
2594
2595 /*
2596 * Create DMA maps for rx buffers
2597 */
c39e3a1f 2598 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2599 rx_buffer = &rdata->rx_buf[i];
5330213c 2600
c39e3a1f 2601 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ
2602 &rx_buffer->map);
2603 if (error) {
2604 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2605 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ
2606 return error;
2607 }
2608 }
2609 return (0);
2610}
2611
c39e3a1f
SZ
2612static void
2613emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2614{
2615 int i;
2616
2617 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2618 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ
2619
2620 if (rx_buffer->m_head != NULL) {
2621 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2622 m_freem(rx_buffer->m_head);
2623 rx_buffer->m_head = NULL;
2624 }
2625 }
2626
2627 if (rdata->fmp != NULL)
2628 m_freem(rdata->fmp);
2629 rdata->fmp = NULL;
2630 rdata->lmp = NULL;
2631}
2632
5330213c 2633static int
c39e3a1f 2634emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2635{
2636 int i, error;
2637
2638 /* Reset descriptor ring */
235b9d30 2639 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ
2640
2641 /* Allocate new ones. */
c39e3a1f
SZ
2642 for (i = 0; i < rdata->num_rx_desc; i++) {
2643 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ
2644 if (error)
2645 return (error);
2646 }
2647
2648 /* Setup our descriptor pointers */
c39e3a1f 2649 rdata->next_rx_desc_to_check = 0;
5330213c
SZ
2650
2651 return (0);
2652}
2653
2654static void
2655emx_init_rx_unit(struct emx_softc *sc)
2656{
2657 struct ifnet *ifp = &sc->arpcom.ac_if;
2658 uint64_t bus_addr;
2d0e5700 2659 uint32_t rctl, itr, rfctl;
3f939c23 2660 int i;
5330213c
SZ
2661
2662 /*
2663 * Make sure receives are disabled while setting
2664 * up the descriptor ring
2665 */
2666 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2667 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2668
2669 /*
2670 * Set the interrupt throttling rate. Value is calculated
2671 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2672 */
2d0e5700
SZ
2673 if (sc->int_throttle_ceil)
2674 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2675 else
2676 itr = 0;
2677 emx_set_itr(sc, itr);
5330213c 2678
235b9d30
SZ
2679 /* Use extended RX descriptor */
2680 rfctl = E1000_RFCTL_EXTEN;
2681
5330213c 2682 /* Disable accelerated ackknowledge */
235b9d30
SZ
2683 if (sc->hw.mac.type == e1000_82574)
2684 rfctl |= E1000_RFCTL_ACK_DIS;
2685
2686 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c 2687
65c7a6af
SZ
2688 /*
2689 * Receive Checksum Offload for TCP and UDP
2690 *
2691 * Checksum offloading is also enabled if multiple receive
2692 * queue is to be supported, since we need it to figure out
2693 * packet type.
2694 */
13890b61
SZ
2695 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2696 sc->rx_ring_cnt > 1) {
2d0e5700
SZ
2697 uint32_t rxcsum;
2698
5330213c 2699 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ
2700
2701 /*
2702 * NOTE:
2703 * PCSD must be enabled to enable multiple
2704 * receive queues.
2705 */
2706 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2707 E1000_RXCSUM_PCSD;
5330213c
SZ
2708 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2709 }
2710
3f939c23 2711 /*
65c7a6af 2712 * Configure multiple receive queue (RSS)
3f939c23 2713 */
13890b61 2714 if (sc->rx_ring_cnt > 1) {
89d8e73d
SZ
2715 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2716 uint32_t reta;
2717
13890b61
SZ
2718 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2719 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
89d8e73d 2720
65c7a6af
SZ
2721 /*
2722 * NOTE:
2723 * When we reach here, RSS has already been disabled
2724 * in emx_stop(), so we could safely configure RSS key
2725 * and redirect table.
2726 */
3f939c23 2727
65c7a6af
SZ
2728 /*
2729 * Configure RSS key
2730 */
89d8e73d
SZ
2731 toeplitz_get_key(key, sizeof(key));
2732 for (i = 0; i < EMX_NRSSRK; ++i) {
2733 uint32_t rssrk;
2734
2735 rssrk = EMX_RSSRK_VAL(key, i);
2736 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2737
2738 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2739 }
3f939c23 2740
65c7a6af 2741 /*
89d8e73d
SZ
2742 * Configure RSS redirect table in following fashion:
2743 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2744 */
89d8e73d
SZ
2745 reta = 0;
2746 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2747 uint32_t q;
2748
13890b61 2749 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
89d8e73d
SZ
2750 reta |= q << (8 * i);
2751 }
2752 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2753
65c7a6af
SZ
2754 for (i = 0; i < EMX_NRETA; ++i)
2755 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2756
65c7a6af
SZ
2757 /*
2758 * Enable multiple receive queues.
2759 * Enable IPv4 RSS standard hash functions.
2760 * Disable RSS interrupt.
2761 */
2762 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2763 E1000_MRQC_ENABLE_RSS_2Q |
2764 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2765 E1000_MRQC_RSS_FIELD_IPV4);
2766 }
3f939c23 2767
5330213c
SZ
2768 /*
2769 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2770 * long latencies are observed, like Lenovo X60. This
2771 * change eliminates the problem, but since having positive
2772 * values in RDTR is a known source of problems on other
2773 * platforms another solution is being sought.
2774 */
2775 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2776 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2777 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2778 }
2779
13890b61 2780 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2d0e5700
SZ
2781 struct emx_rxdata *rdata = &sc->rx_data[i];
2782
2783 /*
2784 * Setup the Base and Length of the Rx Descriptor Ring
2785 */
2786 bus_addr = rdata->rx_desc_paddr;
2787 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2788 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2789 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2790 (uint32_t)(bus_addr >> 32));
2791 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2792 (uint32_t)bus_addr);
2793
2794 /*
2795 * Setup the HW Rx Head and Tail Descriptor Pointers
2796 */
3f939c23
SZ
2797 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2798 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2799 sc->rx_data[i].num_rx_desc - 1);
2800 }
2801
2d0e5700
SZ
2802 /* Setup the Receive Control Register */
2803 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2804 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2805 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2806 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2807
2808 /* Make sure VLAN Filters are off */
2809 rctl &= ~E1000_RCTL_VFE;
2810
2811 /* Don't store bad paket */
2812 rctl &= ~E1000_RCTL_SBP;
2813
2814 /* MCLBYTES */
2815 rctl |= E1000_RCTL_SZ_2048;
2816
2817 if (ifp->if_mtu > ETHERMTU)
2818 rctl |= E1000_RCTL_LPE;
2819 else
2820 rctl &= ~E1000_RCTL_LPE;
2821
3f939c23
SZ
2822 /* Enable Receives */
2823 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ
2824}
2825
2826static void
c39e3a1f 2827emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2828{
323e5ecd 2829 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2830 int i;
2831
bdca134f 2832 /* Free Receive Descriptor ring */
235b9d30 2833 if (rdata->rx_desc) {
c39e3a1f 2834 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2835 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ
2836 rdata->rx_desc_dmap);
2837 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2838
235b9d30 2839 rdata->rx_desc = NULL;
a596084c 2840 }
bdca134f 2841
323e5ecd 2842 if (rdata->rx_buf == NULL)
5330213c
SZ
2843 return;
2844
2845 for (i = 0; i < ndesc; i++) {
323e5ecd 2846 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ
2847
2848 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2849 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2850 }
c39e3a1f
SZ
2851 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2852 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2853
323e5ecd
SZ
2854 kfree(rdata->rx_buf, M_DEVBUF);
2855 rdata->rx_buf = NULL;
5330213c
SZ
2856}
2857
2858static void
c39e3a1f 2859emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2860{
c39e3a1f 2861 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2862 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2863 uint32_t staterr;
235b9d30 2864 emx_rxdesc_t *current_desc;
5330213c
SZ
2865 struct mbuf *mp;
2866 int i;
5330213c 2867
c39e3a1f 2868 i = rdata->next_rx_desc_to_check;
235b9d30
SZ
2869 current_desc = &rdata->rx_desc[i];
2870 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2871
235b9d30 2872 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ
2873 return;
2874
235b9d30 2875 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2876 struct pktinfo *pi = NULL, pi0;
235b9d30 2877 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2878 struct mbuf *m = NULL;
0acc29d6 2879 int eop, len;
5330213c
SZ
2880
2881 logif(pkt_receive);
2882
235b9d30 2883 mp = rx_buf->m_head;
5330213c
SZ
2884
2885 /*
2886 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2887 * needs to access the last received byte in the mbuf.
2888 */
235b9d30 2889 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ
2890 BUS_DMASYNC_POSTREAD);
2891
0acc29d6 2892 len = le16toh(current_desc->rxd_length);
235b9d30 2893 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ
2894 count--;
2895 eop = 1;
5330213c
SZ
2896 } else {
2897 eop = 0;
5330213c
SZ
2898 }
2899
235b9d30
SZ
2900 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2901 uint16_t vlan = 0;
3f939c23 2902 uint32_t mrq, rss_hash;
235b9d30
SZ
2903
2904 /*
2905 * Save several necessary information,
2906 * before emx_newbuf() destroy it.
2907 */
2908 if ((staterr & E1000_RXD_STAT_VP) && eop)
2909 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2910
3f939c23
SZ
2911 mrq = le32toh(current_desc->rxd_mrq);
2912 rss_hash = le32toh(current_desc->rxd_rss);
2913
2914 EMX_RSS_DPRINTF(sc, 10,
2915 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2916 ring_idx, mrq, rss_hash);
2917
c39e3a1f 2918 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ
2919 ifp->if_iqdrops++;
2920 goto discard;
2921 }
2922
2923 /* Assign correct length to the current fragment */
2924 mp->m_len = len;
2925
c39e3a1f 2926 if (rdata->fmp == NULL) {
5330213c 2927 mp->m_pkthdr.len = len;
c39e3a1f
SZ
2928 rdata->fmp = mp; /* Store the first mbuf */
2929 rdata->lmp = mp;
5330213c
SZ
2930 } else {
2931 /*
2932 * Chain mbuf's together
2933 */
c39e3a1f
SZ
2934 rdata->lmp->m_next = mp;
2935 rdata->lmp = rdata->lmp->m_next;
2936 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ
2937 }
2938
2939 if (eop) {
c39e3a1f 2940 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ
2941 ifp->if_ipackets++;
2942
235b9d30
SZ
2943 if (ifp->if_capenable & IFCAP_RXCSUM)
2944 emx_rxcsum(staterr, rdata->fmp);
5330213c 2945
235b9d30 2946 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2947 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2948 vlan;
c39e3a1f 2949 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2950 }
c39e3a1f
SZ
2951 m = rdata->fmp;
2952 rdata->fmp = NULL;
2953 rdata->lmp = NULL;
3f939c23 2954
9cc86e17
SZ
2955 if (ifp->if_capenable & IFCAP_RSS) {
2956 pi = emx_rssinfo(m, &pi0, mrq,
2957 rss_hash, staterr);
2958 }
3f939c23
SZ
2959#ifdef EMX_RSS_DEBUG
2960 rdata->rx_pkts++;
2961#endif
5330213c
SZ
2962 }
2963 } else {
2964 ifp->if_ierrors++;
2965discard:
235b9d30 2966 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ
2967 if (rdata->fmp != NULL) {
2968 m_freem(rdata->fmp);
2969 rdata->fmp = NULL;
2970 rdata->lmp = NULL;
5330213c
SZ
2971 }
2972 m = NULL;
2973 }
2974
5330213c 2975 if (m != NULL)
eda7db08 2976 ether_input_pkt(ifp, m, pi);
5330213c
SZ
2977
2978 /* Advance our pointers to the next descriptor. */
c39e3a1f 2979 if (++i == rdata->num_rx_desc)
5330213c 2980 i = 0;
235b9d30
SZ
2981
2982 current_desc = &rdata->rx_desc[i];
2983 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2984 }
c39e3a1f 2985 rdata->next_rx_desc_to_check = i;
5330213c 2986
3f939c23 2987 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2988 if (--i < 0)
c39e3a1f 2989 i = rdata->num_rx_desc - 1;
3f939c23 2990 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ
2991}
2992
5330213c
SZ
2993static void
2994emx_enable_intr(struct emx_softc *sc)
2995{
2d0e5700
SZ
2996 uint32_t ims_mask = IMS_ENABLE_MASK;
2997
6d435846 2998 lwkt_serialize_handler_enable(&sc->main_serialize);
2d0e5700
SZ
2999
3000#if 0
3001 if (sc->hw.mac.type == e1000_82574) {
3002 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3003 ims_mask |= EM_MSIX_MASK;
3004 }
3005#endif
3006 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
5330213c
SZ
3007}
3008
3009static void
3010emx_disable_intr(struct emx_softc *sc)
3011{
2d0e5700
SZ
3012 if (sc->hw.mac.type == e1000_82574)
3013 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
5330213c 3014 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2d0e5700 3015
6d435846 3016 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ
3017}
3018
3019/*
3020 * Bit of a misnomer, what this really means is
3021 * to enable OS management of the system... aka
3022 * to disable special hardware management features
3023 */
3024static void
3025emx_get_mgmt(struct emx_softc *sc)
3026{
3027 /* A shared code workaround */
de0836d4 3028 if (sc->flags & EMX_FLAG_HAS_MGMT) {
5330213c
SZ
3029 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3030 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3031
3032 /* disable hardware interception of ARP */
3033 manc &= ~(E1000_MANC_ARP_EN);
3034
3035 /* enable receiving management packets to the host */
3036 manc |= E1000_MANC_EN_MNG2HOST;
3037#define E1000_MNG2HOST_PORT_623 (1 << 5)
3038#define E1000_MNG2HOST_PORT_664 (1 << 6)
3039 manc2h |= E1000_MNG2HOST_PORT_623;
3040 manc2h |= E1000_MNG2HOST_PORT_664;
3041 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3042
3043 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3044 }
3045}
3046
3047/*
3048 * Give control back to hardware management
3049 * controller if there is one.
3050 */
3051static void
3052emx_rel_mgmt(struct emx_softc *sc)
3053{
de0836d4 3054 if (sc->flags & EMX_FLAG_HAS_MGMT) {
5330213c
SZ
3055 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3056
3057 /* re-enable hardware interception of ARP */
3058 manc |= E1000_MANC_ARP_EN;
3059 manc &= ~E1000_MANC_EN_MNG2HOST;
3060
3061 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3062 }
3063}
3064
3065/*
3066 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3067 * For ASF and Pass Through versions of f/w this means that
3068 * the driver is loaded. For AMT version (only with 82573)
3069 * of the f/w this means that the network i/f is open.
3070 */
3071static void
3072emx_get_hw_control(struct emx_softc *sc)
3073{
5330213c 3074 /* Let firmware know the driver has taken over */
2d0e5700
SZ
3075 if (sc->hw.mac.type == e1000_82573) {
3076 uint32_t swsm;
3077
5330213c
SZ
3078 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3079 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3080 swsm | E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3081 } else {
3082 uint32_t ctrl_ext;
5330213c 3083
5330213c
SZ
3084 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3085 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3086 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
5330213c 3087 }
de0836d4 3088 sc->flags |= EMX_FLAG_HW_CTRL;
5330213c
SZ
3089}
3090
3091/*
3092 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3093 * For ASF and Pass Through versions of f/w this means that the
3094 * driver is no longer loaded. For AMT version (only with 82573)
3095 * of the f/w this means that the network i/f is closed.
3096 */
3097static void
3098emx_rel_hw_control(struct emx_softc *sc)
3099{
de0836d4 3100 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
2d0e5700 3101 return;
de0836d4 3102 sc->flags &= ~EMX_FLAG_HW_CTRL;
5330213c
SZ
3103
3104 /* Let firmware taken over control of h/w */
2d0e5700
SZ
3105 if (sc->hw.mac.type == e1000_82573) {
3106 uint32_t swsm;
3107
5330213c
SZ
3108 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3109 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3110 swsm & ~E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3111 } else {
3112 uint32_t ctrl_ext;
5330213c 3113
5330213c
SZ
3114 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3115 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3116 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
5330213c
SZ
3117 }
3118}
3119
3120static int
3121emx_is_valid_eaddr(const uint8_t *addr)
3122{
3123 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3124
3125 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3126 return (FALSE);
3127
3128 return (TRUE);
3129}
3130
3131/*
3132 * Enable PCI Wake On Lan capability
3133 */
3134void
3135emx_enable_wol(device_t dev)
3136{
3137 uint16_t cap, status;
3138 uint8_t id;
3139
3140 /* First find the capabilities pointer*/
3141 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3142
3143 /* Read the PM Capabilities */
3144 id = pci_read_config(dev, cap, 1);
3145 if (id != PCIY_PMG) /* Something wrong */
3146 return;
3147
3148 /*
3149 * OK, we have the power capabilities,
3150 * so now get the status register
3151 */
3152 cap += PCIR_POWER_STATUS;
3153 status = pci_read_config(dev, cap, 2);
3154 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3155 pci_write_config(dev, cap, status, 2);
3156}
3157
3158static void
3159emx_update_stats(struct emx_softc *sc)
3160{
3161 struct ifnet *ifp = &sc->arpcom.ac_if;
3162
3163 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3164 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3165 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3166 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3167 }
3168 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3169 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3170 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3171 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3172
3173 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3174 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3175 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3176 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3177 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3178 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3179 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3180 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3181 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3182 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3183 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3184 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3185 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3186 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3187 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3188 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3189 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3190 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3191 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3192 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3193
3194 /* For the 64-bit byte counters the low dword must be read first. */
3195 /* Both registers clear on the read of the high dword */
3196
3197 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3198 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3199
3200 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3201 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3202 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3203 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3204 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3205
3206 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3207 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3208
3209 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3210 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3211 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3212 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3213 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3214 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3215 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3216 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3217 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3218 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3219
3220 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3221 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3222 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3223 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3224 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3225 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3226
3227 ifp->if_collisions = sc->stats.colc;
3228
3229 /* Rx Errors */
ec1092aa 3230 ifp->if_ierrors = sc->stats.rxerrc +
5330213c
SZ
3231 sc->stats.crcerrs + sc->stats.algnerrc +
3232 sc->stats.ruc + sc->stats.roc +
3233 sc->stats.mpc + sc->stats.cexterr;
3234
3235 /* Tx Errors */
ec1092aa 3236 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol;
5330213c
SZ
3237}
3238
3239static void
3240emx_print_debug_info(struct emx_softc *sc)
3241{
3242 device_t dev = sc->dev;
3243 uint8_t *hw_addr = sc->hw.hw_addr;
3244
3245 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3246 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3247 E1000_READ_REG(&sc->hw, E1000_CTRL),
3248 E1000_READ_REG(&sc->hw, E1000_RCTL));
3249 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3250 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3251 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3252 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3253 sc->hw.fc.high_water, sc->hw.fc.low_water);
3254 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3255 E1000_READ_REG(&sc->hw, E1000_TIDV),
3256 E1000_READ_REG(&sc->hw, E1000_TADV));
3257 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3258 E1000_READ_REG(&sc->hw, E1000_RDTR),
3259 E1000_READ_REG(&sc->hw, E1000_RADV));
3260 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3261 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3262 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3263 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3264 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3265 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3266 device_printf(dev, "Num Tx descriptors avail = %d\n",
3267 sc->num_tx_desc_avail);
0c0e1638
SZ
3268
3269 device_printf(dev, "TSO segments %lu\n", sc->tso_segments);
3270 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused);
5330213c
SZ
3271}
3272
3273static void
3274emx_print_hw_stats(struct emx_softc *sc)
3275{
3276 device_t dev = sc->dev;
3277
3278 device_printf(dev, "Excessive collisions = %lld\n",
3279 (long long)sc->stats.ecol);
3280#if (DEBUG_HW > 0) /* Dont output these errors normally */
3281 device_printf(dev, "Symbol errors = %lld\n",
3282 (long long)sc->stats.symerrs);
3283#endif
3284 device_printf(dev, "Sequence errors = %lld\n",
3285 (long long)sc->stats.sec);
3286 device_printf(dev, "Defer count = %lld\n",
3287 (long long)sc->stats.dc);
3288 device_printf(dev, "Missed Packets = %lld\n",
3289 (long long)sc->stats.mpc);
3290 device_printf(dev, "Receive No Buffers = %lld\n",
3291 (long long)sc->stats.rnbc);
3292 /* RLEC is inaccurate on some hardware, calculate our own. */
3293 device_printf(dev, "Receive Length Errors = %lld\n",
3294 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3295 device_printf(dev, "Receive errors = %lld\n",
3296 (long long)sc->stats.rxerrc);
3297 device_printf(dev, "Crc errors = %lld\n",
3298 (long long)sc->stats.crcerrs);
3299 device_printf(dev, "Alignment errors = %lld\n",
3300 (long long)sc->stats.algnerrc);
3301 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3302 (long long)sc->stats.cexterr);
3303 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
5330213c
SZ
3304 device_printf(dev, "XON Rcvd = %lld\n",
3305 (long long)sc->stats.xonrxc);
3306 device_printf(dev, "XON Xmtd = %lld\n",
3307 (long long)sc->stats.xontxc);
3308 device_printf(dev, "XOFF Rcvd = %lld\n",
3309 (long long)sc->stats.xoffrxc);
3310 device_printf(dev, "XOFF Xmtd = %lld\n",
3311 (long long)sc->stats.xofftxc);
3312 device_printf(dev, "Good Packets Rcvd = %lld\n",
3313 (long long)sc->stats.gprc);
3314 device_printf(dev, "Good Packets Xmtd = %lld\n",
3315 (long long)sc->stats.gptc);
3316}
3317
3318static void
3319emx_print_nvm_info(struct emx_softc *sc)
3320{
3321 uint16_t eeprom_data;
3322 int i, j, row = 0;
3323
3324 /* Its a bit crude, but it gets the job done */
3325 kprintf("\nInterface EEPROM Dump:\n");
3326 kprintf("Offset\n0x0000 ");
3327 for (i = 0, j = 0; i < 32; i++, j++) {
3328 if (j == 8) { /* Make the offset block */
3329 j = 0; ++row;
3330 kprintf("\n0x00%x0 ",row);
3331 }
3332 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3333 kprintf("%04x ", eeprom_data);
3334 }
3335 kprintf("\n");
3336}
3337
3338static int
3339emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3340{
3341 struct emx_softc *sc;
3342 struct ifnet *ifp;
3343 int error, result;
3344
3345 result = -1;
3346 error = sysctl_handle_int(oidp, &result, 0, req);
3347 if (error || !req->newptr)
3348 return (error);
3349
3350 sc = (struct emx_softc *)arg1;
3351 ifp = &sc->arpcom.ac_if;
3352
6d435846 3353 ifnet_serialize_all(ifp);
5330213c
SZ
3354
3355 if (result == 1)
3356 emx_print_debug_info(sc);
3357
3358 /*
3359 * This value will cause a hex dump of the
3360 * first 32 16-bit words of the EEPROM to
3361 * the screen.
3362 */
3363 if (result == 2)
3364 emx_print_nvm_info(sc);
3365
6d435846 3366 ifnet_deserialize_all(ifp);
5330213c
SZ
3367
3368 return (error);
3369}
3370
3371static int
3372emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3373{
3374 int error, result;
3375
3376 result = -1;
3377 error = sysctl_handle_int(oidp, &result, 0, req);
3378 if (error || !req->newptr)
3379 return (error);
3380
3381 if (result == 1) {
3382 struct emx_softc *sc = (struct emx_softc *)arg1;
3383 struct ifnet *ifp = &sc->arpcom.ac_if;
3384
6d435846 3385 ifnet_serialize_all(ifp);
5330213c 3386 emx_print_hw_stats(sc);
6d435846 3387 ifnet_deserialize_all(ifp);
5330213c
SZ
3388 }
3389 return (error);
3390}
3391
3392static void
3393emx_add_sysctl(struct emx_softc *sc)
3394{
3f939c23
SZ
3395#ifdef EMX_RSS_DEBUG
3396 char rx_pkt[32];
3397 int i;
3398#endif
5330213c
SZ
3399
3400 sysctl_ctx_init(&sc->sysctl_ctx);
3401 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3402 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3403 device_get_nameunit(sc->dev),
3404 CTLFLAG_RD, 0, "");
3405 if (sc->sysctl_tree == NULL) {
3406 device_printf(sc->dev, "can't add sysctl node\n");
3407 return;
3408 }
3409
3410 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3411 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3412 emx_sysctl_debug_info, "I", "Debug Information");
3413
3414 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3415 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3416 emx_sysctl_stats, "I", "Statistics");
3417
3418 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ
3419 OID_AUTO, "rxd", CTLFLAG_RD,
3420 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3421 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3422 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3423
5330213c
SZ
3424 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3425 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3426 sc, 0, emx_sysctl_int_throttle, "I",
3427 "interrupt throttling rate");
3428 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3429 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3430 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3431 "# segments per TX interrupt");
3f939c23 3432
8434a83b 3433 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
13890b61
SZ
3434 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3435 &sc->rx_ring_cnt, 0, "RX ring count");
8434a83b 3436
09f49d52
SZ
3437#ifdef IFPOLL_ENABLE
3438 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3439 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3440 sc, 0, emx_sysctl_npoll_rxoff, "I",
3441 "NPOLLING RX cpu offset");
3442 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3443 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3444 sc, 0, emx_sysctl_npoll_txoff, "I",
3445 "NPOLLING TX cpu offset");
3446#endif
3447
3f939c23
SZ
3448#ifdef EMX_RSS_DEBUG
3449 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3450 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3451 0, "RSS debug level");
65c7a6af 3452 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3453 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3454 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3455 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3456 rx_pkt, CTLFLAG_RW,
3f939c23
SZ
3457 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3458 }
3459#endif
5330213c
SZ
3460}
3461
3462static int
3463emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3464{
3465 struct emx_softc *sc = (void *)arg1;
3466 struct ifnet *ifp = &sc->arpcom.ac_if;
3467 int error, throttle;
3468
3469 throttle = sc->int_throttle_ceil;
3470 error = sysctl_handle_int(oidp, &throttle, 0, req);
3471 if (error || req->newptr == NULL)
3472 return error;
3473 if (throttle < 0 || throttle > 1000000000 / 256)
3474 return EINVAL;
3475
3476 if (throttle) {
3477 /*
3478 * Set the interrupt throttling rate in 256ns increments,
3479 * recalculate sysctl value assignment to get exact frequency.
3480 */
3481 throttle = 1000000000 / 256 / throttle;
3482
3483 /* Upper 16bits of ITR is reserved and should be zero */
3484 if (throttle & 0xffff0000)
3485 return EINVAL;
3486 }
3487
6d435846 3488 ifnet_serialize_all(ifp);
5330213c
SZ
3489
3490 if (throttle)
3491 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3492 else
3493 sc->int_throttle_ceil = 0;
3494
3495 if (ifp->if_flags & IFF_RUNNING)
2d0e5700 3496 emx_set_itr(sc, throttle);
5330213c 3497
6d435846 3498 ifnet_deserialize_all(ifp);
5330213c
SZ
3499
3500 if (bootverbose) {
3501 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3502 sc->int_throttle_ceil);
3503 }
3504 return 0;
3505}
3506
3507static int
3508emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3509{
3510 struct emx_softc *sc = (void *)arg1;
3511 struct ifnet *ifp = &sc->arpcom.ac_if;
3512 int error, segs;
3513
3514 segs = sc->tx_int_nsegs;
3515 error = sysctl_handle_int(oidp, &segs, 0, req);
3516 if (error || req->newptr == NULL)
3517 return error;
3518 if (segs <= 0)
3519 return EINVAL;
3520
6d435846 3521 ifnet_serialize_all(ifp);
5330213c
SZ
3522
3523 /*
3524 * Don't allow int_tx_nsegs to become:
3525 * o Less the oact_tx_desc
3526 * o Too large that no TX desc will cause TX interrupt to
3527 * be generated (OACTIVE will never recover)
3528 * o Too small that will cause tx_dd[] overflow
3529 */
3530 if (segs < sc->oact_tx_desc ||
3531 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3532 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3533 error = EINVAL;
3534 } else {
3535 error = 0;
3536 sc->tx_int_nsegs = segs;
3537 }
3538
6d435846 3539 ifnet_deserialize_all(ifp);
5330213c
SZ
3540
3541 return error;
3542}
071699f8 3543
09f49d52
SZ
3544#ifdef IFPOLL_ENABLE
3545
3546static int
3547emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3548{
3549 struct emx_softc *sc = (void *)arg1;
3550 struct ifnet *ifp = &sc->arpcom.ac_if;
3551 int error, off;
3552
3553 off = sc->rx_npoll_off;
3554 error = sysctl_handle_int(oidp, &off, 0, req);
3555 if (error || req->newptr == NULL)
3556 return error;
3557 if (off < 0)
3558 return EINVAL;
3559
3560 ifnet_serialize_all(ifp);
3561 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3562 error = EINVAL;
3563 } else {
3564 error = 0;
3565 sc->rx_npoll_off = off;
3566 }
3567 ifnet_deserialize_all(ifp);
3568
3569 return error;
3570}
3571
3572static int
3573emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3574{
3575 struct emx_softc *sc = (void *)arg1;
3576 struct ifnet *ifp = &sc->arpcom.ac_if;
3577 int error, off;
3578
3579 off = sc->tx_npoll_off;
3580 error = sysctl_handle_int(oidp, &off, 0, req);
3581 if (error || req->newptr == NULL)
3582 return error;
3583 if (off < 0)
3584 return EINVAL;
3585
3586 ifnet_serialize_all(ifp);
3587 if (off >= ncpus2) {
3588 error = EINVAL;
3589 } else {
3590 error = 0;
3591 sc->tx_npoll_off = off;
3592 }
3593 ifnet_deserialize_all(ifp);
3594
3595 return error;
3596}
3597
3598#endif /* IFPOLL_ENABLE */
3599
071699f8
SZ
3600static int
3601emx_dma_alloc(struct emx_softc *sc)
3602{
3f939c23 3603 int error, i;
071699f8
SZ
3604
3605 /*
3606 * Create top level busdma tag
3607 */
3608 error = bus_dma_tag_create(NULL, 1, 0,
3609 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3610 NULL, NULL,
3611 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3612 0, &sc->parent_dtag);
3613 if (error) {
3614 device_printf(sc->dev, "could not create top level DMA tag\n");
3615 return error;
3616 }
3617
3618 /*
3619 * Allocate transmit descriptors ring and buffers
3620 */
3621 error = emx_create_tx_ring(sc);
3622 if (error) {
3623 device_printf(sc->dev, "Could not setup transmit structures\n");
3624 return error;
3625 }
3626
3627 /*
3628 * Allocate receive descriptors ring and buffers
3629 */
65c7a6af 3630 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3631 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3632 if (error) {
3633 device_printf(sc->dev,
3634 "Could not setup receive structures\n");
3635 return error;
3636 }
071699f8
SZ
3637 }
3638 return 0;
3639}
3640
3641static void
3642emx_dma_free(struct emx_softc *sc)
3643{
3f939c23
SZ
3644 int i;
3645
071699f8 3646 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3647
65c7a6af 3648 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3649 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3650 sc->rx_data[i].num_rx_desc);
3651 }
071699f8
SZ
3652
3653 /* Free top level busdma tag */
3654 if (sc->parent_dtag != NULL)
3655 bus_dma_tag_destroy(sc->parent_dtag);
3656}
6d435846
SZ
3657
3658static void
3659emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3660{
3661 struct emx_softc *sc = ifp->if_softc;
6d435846 3662
8f594b38
SZ
3663 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3664 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3665}
3666
3667static void
3668emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3669{
3670 struct emx_softc *sc = ifp->if_softc;
6d435846 3671
8f594b38
SZ
3672 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3673 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3674}
3675
3676static int
3677emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3678{
3679 struct emx_softc *sc = ifp->if_softc;
6d435846 3680
8f594b38
SZ
3681 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3682 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846 3683}
bca7c435
SZ
3684
3685static void
3686emx_serialize_skipmain(struct emx_softc *sc)
3687{
3688 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3689}
3690
3691static void
3692emx_deserialize_skipmain(struct emx_softc *sc)
3693{
3694 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3695}
2c9effcf
SZ
3696
3697#ifdef INVARIANTS
3698
3699static void