Optimize lwkt_rwlock.c a bit
[dragonfly.git] / sys / dev / serial / sio / sio.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/isa/sio.c,v 1.291.2.35 2003/05/18 08:51:15 murray Exp $
1de703da 34 * $DragonFly: src/sys/dev/serial/sio/sio.c,v 1.2 2003/06/17 04:28:40 dillon Exp $
984263bc
MD
35 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
36 * from: i386/isa sio.c,v 1.234
37 */
38
39#include "opt_comconsole.h"
40#include "opt_compat.h"
41#include "opt_ddb.h"
42#include "opt_sio.h"
43#include "card.h"
44#include "pci.h"
45#ifdef __i386__
46#include "puc.h"
47#endif
48#include "sio.h"
49
50/*
51 * Serial driver, based on 386BSD-0.1 com driver.
52 * Mostly rewritten to use pseudo-DMA.
53 * Works for National Semiconductor NS8250-NS16550AF UARTs.
54 * COM driver, based on HP dca driver.
55 *
56 * Changes for PC-Card integration:
57 * - Added PC-Card driver table and handlers
58 */
59#include <sys/param.h>
60#include <sys/systm.h>
61#include <sys/reboot.h>
62#include <sys/malloc.h>
63#include <sys/tty.h>
64#include <sys/proc.h>
65#include <sys/module.h>
66#include <sys/conf.h>
67#include <sys/dkstat.h>
68#include <sys/fcntl.h>
69#include <sys/interrupt.h>
70#include <sys/kernel.h>
71#include <sys/syslog.h>
72#include <sys/sysctl.h>
73#include <sys/bus.h>
74#include <machine/bus_pio.h>
75#include <machine/bus.h>
76#include <sys/rman.h>
77#include <sys/timepps.h>
78
79#include <machine/limits.h>
80
81#include <isa/isareg.h>
82#include <isa/isavar.h>
83#if NPCI > 0
84#include <pci/pcireg.h>
85#include <pci/pcivar.h>
86#endif
87#if NPUC > 0
88#include <dev/puc/pucvar.h>
89#endif
90#include <machine/lock.h>
91
92#include <machine/clock.h>
93#include <machine/ipl.h>
94#ifndef SMP
95#include <machine/lock.h>
96#endif
97#include <machine/resource.h>
98
99#include <isa/sioreg.h>
100
101#ifdef COM_ESP
102#include <dev/ic/esp.h>
103#endif
104#include <dev/ic/ns16550.h>
105
106#ifndef __i386__
107#define disable_intr()
108#define enable_intr()
109#endif
110
111#ifdef SMP
112#define disable_intr() COM_DISABLE_INTR()
113#define enable_intr() COM_ENABLE_INTR()
114#endif /* SMP */
115
116#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
117
118#define CALLOUT_MASK 0x80
119#define CONTROL_MASK 0x60
120#define CONTROL_INIT_STATE 0x20
121#define CONTROL_LOCK_STATE 0x40
122#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
123#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \
124 | ((mynor) & 0x1f))
125#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \
126 | ((unit) & 0x1f))
127
128#ifdef COM_MULTIPORT
129/* checks in flags for multiport and which is multiport "master chip"
130 * for a given card
131 */
132#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
133#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
134#define COM_NOTAST4(flags) ((flags) & 0x04)
135#endif /* COM_MULTIPORT */
136
137#define COM_CONSOLE(flags) ((flags) & 0x10)
138#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
139#define COM_LLCONSOLE(flags) ((flags) & 0x40)
140#define COM_DEBUGGER(flags) ((flags) & 0x80)
141#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
142#define COM_NOFIFO(flags) ((flags) & 0x02)
143#define COM_ST16650A(flags) ((flags) & 0x20000)
144#define COM_C_NOPROBE (0x40000)
145#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
146#define COM_C_IIR_TXRDYBUG (0x80000)
147#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
148#define COM_TI16754(flags) ((flags) & 0x200000)
149#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
150
151#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
152
153#define sio_getreg(com, off) \
154 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
155#define sio_setreg(com, off, value) \
156 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
157
158/*
159 * com state bits.
160 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
161 * than the other bits so that they can be tested as a group without masking
162 * off the low bits.
163 *
164 * The following com and tty flags correspond closely:
165 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
166 * comstop())
167 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
168 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
169 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
170 * TS_FLUSH is not used.
171 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
172 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
173 */
174#define CS_BUSY 0x80 /* output in progress */
175#define CS_TTGO 0x40 /* output not stopped by XOFF */
176#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
177#define CS_CHECKMSR 1 /* check of MSR scheduled */
178#define CS_CTS_OFLOW 2 /* use CTS output flow control */
179#define CS_DTR_OFF 0x10 /* DTR held off */
180#define CS_ODONE 4 /* output completed */
181#define CS_RTS_IFLOW 8 /* use RTS input flow control */
182#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
183
184static char const * const error_desc[] = {
185#define CE_OVERRUN 0
186 "silo overflow",
187#define CE_INTERRUPT_BUF_OVERFLOW 1
188 "interrupt-level buffer overflow",
189#define CE_TTY_BUF_OVERFLOW 2
190 "tty-level buffer overflow",
191};
192
193#define CE_NTYPES 3
194#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
195
196/* types. XXX - should be elsewhere */
197typedef u_int Port_t; /* hardware port */
198typedef u_char bool_t; /* boolean */
199
200/* queue of linear buffers */
201struct lbq {
202 u_char *l_head; /* next char to process */
203 u_char *l_tail; /* one past the last char to process */
204 struct lbq *l_next; /* next in queue */
205 bool_t l_queued; /* nonzero if queued */
206};
207
208/* com device structure */
209struct com_s {
210 u_int flags; /* Copy isa device flags */
211 u_char state; /* miscellaneous flag bits */
212 bool_t active_out; /* nonzero if the callout device is open */
213 u_char cfcr_image; /* copy of value written to CFCR */
214#ifdef COM_ESP
215 bool_t esp; /* is this unit a hayes esp board? */
216#endif
217 u_char extra_state; /* more flag bits, separate for order trick */
218 u_char fifo_image; /* copy of value written to FIFO */
219 bool_t hasfifo; /* nonzero for 16550 UARTs */
220 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
221 bool_t loses_outints; /* nonzero if device loses output interrupts */
222 u_char mcr_image; /* copy of value written to MCR */
223#ifdef COM_MULTIPORT
224 bool_t multiport; /* is this unit part of a multiport device? */
225#endif /* COM_MULTIPORT */
226 bool_t no_irq; /* nonzero if irq is not attached */
227 bool_t gone; /* hardware disappeared */
228 bool_t poll; /* nonzero if polling is required */
229 bool_t poll_output; /* nonzero if polling for output is required */
230 int unit; /* unit number */
231 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
232 u_int tx_fifo_size;
233 u_int wopeners; /* # processes waiting for DCD in open() */
234
235 /*
236 * The high level of the driver never reads status registers directly
237 * because there would be too many side effects to handle conveniently.
238 * Instead, it reads copies of the registers stored here by the
239 * interrupt handler.
240 */
241 u_char last_modem_status; /* last MSR read by intr handler */
242 u_char prev_modem_status; /* last MSR handled by high level */
243
244 u_char hotchar; /* ldisc-specific char to be handled ASAP */
245 u_char *ibuf; /* start of input buffer */
246 u_char *ibufend; /* end of input buffer */
247 u_char *ibufold; /* old input buffer, to be freed */
248 u_char *ihighwater; /* threshold in input buffer */
249 u_char *iptr; /* next free spot in input buffer */
250 int ibufsize; /* size of ibuf (not include error bytes) */
251 int ierroff; /* offset of error bytes in ibuf */
252
253 struct lbq obufq; /* head of queue of output buffers */
254 struct lbq obufs[2]; /* output buffers */
255
256 bus_space_tag_t bst;
257 bus_space_handle_t bsh;
258
259 Port_t data_port; /* i/o ports */
260#ifdef COM_ESP
261 Port_t esp_port;
262#endif
263 Port_t int_id_port;
264 Port_t modem_ctl_port;
265 Port_t line_status_port;
266 Port_t modem_status_port;
267 Port_t intr_ctl_port; /* Ports of IIR register */
268
269 struct tty *tp; /* cross reference */
270
271 /* Initial state. */
272 struct termios it_in; /* should be in struct tty */
273 struct termios it_out;
274
275 /* Lock state. */
276 struct termios lt_in; /* should be in struct tty */
277 struct termios lt_out;
278
279 bool_t do_timestamp;
280 bool_t do_dcd_timestamp;
281 struct timeval timestamp;
282 struct timeval dcd_timestamp;
283 struct pps_state pps;
284
285 u_long bytes_in; /* statistics */
286 u_long bytes_out;
287 u_int delta_error_counts[CE_NTYPES];
288 u_long error_counts[CE_NTYPES];
289
290 u_long rclk;
291
292 struct resource *irqres;
293 struct resource *ioportres;
294 void *cookie;
295
296 /*
297 * Data area for output buffers. Someday we should build the output
298 * buffer queue without copying data.
299 */
300 u_char obuf1[256];
301 u_char obuf2[256];
302};
303
304#ifdef COM_ESP
305static int espattach __P((struct com_s *com, Port_t esp_port));
306#endif
307static int sioattach __P((device_t dev, int rid, u_long rclk));
308static int sio_isa_attach __P((device_t dev));
309
310static timeout_t siobusycheck;
311static u_int siodivisor __P((u_long rclk, speed_t speed));
312static timeout_t siodtrwakeup;
313static void comhardclose __P((struct com_s *com));
314static void sioinput __P((struct com_s *com));
315static void siointr1 __P((struct com_s *com));
316static void siointr __P((void *arg));
317static int commctl __P((struct com_s *com, int bits, int how));
318static int comparam __P((struct tty *tp, struct termios *t));
319static swihand_t siopoll;
320static int sioprobe __P((device_t dev, int xrid, u_long rclk));
321static int sio_isa_probe __P((device_t dev));
322static void siosettimeout __P((void));
323static int siosetwater __P((struct com_s *com, speed_t speed));
324static void comstart __P((struct tty *tp));
325static void comstop __P((struct tty *tp, int rw));
326static timeout_t comwakeup;
327static void disc_optim __P((struct tty *tp, struct termios *t,
328 struct com_s *com));
329
330#if NCARD > 0
331static int sio_pccard_attach __P((device_t dev));
332static int sio_pccard_detach __P((device_t dev));
333static int sio_pccard_probe __P((device_t dev));
334#endif /* NCARD > 0 */
335
336#if NPCI > 0
337static int sio_pci_attach __P((device_t dev));
338static void sio_pci_kludge_unit __P((device_t dev));
339static int sio_pci_probe __P((device_t dev));
340#endif /* NPCI > 0 */
341
342#if NPUC > 0
343static int sio_puc_attach __P((device_t dev));
344static int sio_puc_probe __P((device_t dev));
345#endif /* NPUC > 0 */
346
347static char driver_name[] = "sio";
348
349/* table and macro for fast conversion from a unit number to its com struct */
350static devclass_t sio_devclass;
351#define com_addr(unit) ((struct com_s *) \
352 devclass_get_softc(sio_devclass, unit))
353
354static device_method_t sio_isa_methods[] = {
355 /* Device interface */
356 DEVMETHOD(device_probe, sio_isa_probe),
357 DEVMETHOD(device_attach, sio_isa_attach),
358
359 { 0, 0 }
360};
361
362static driver_t sio_isa_driver = {
363 driver_name,
364 sio_isa_methods,
365 sizeof(struct com_s),
366};
367
368#if NCARD > 0
369static device_method_t sio_pccard_methods[] = {
370 /* Device interface */
371 DEVMETHOD(device_probe, sio_pccard_probe),
372 DEVMETHOD(device_attach, sio_pccard_attach),
373 DEVMETHOD(device_detach, sio_pccard_detach),
374
375 { 0, 0 }
376};
377
378static driver_t sio_pccard_driver = {
379 driver_name,
380 sio_pccard_methods,
381 sizeof(struct com_s),
382};
383#endif /* NCARD > 0 */
384
385#if NPCI > 0
386static device_method_t sio_pci_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, sio_pci_probe),
389 DEVMETHOD(device_attach, sio_pci_attach),
390
391 { 0, 0 }
392};
393
394static driver_t sio_pci_driver = {
395 driver_name,
396 sio_pci_methods,
397 sizeof(struct com_s),
398};
399#endif /* NPCI > 0 */
400
401#if NPUC > 0
402static device_method_t sio_puc_methods[] = {
403 /* Device interface */
404 DEVMETHOD(device_probe, sio_puc_probe),
405 DEVMETHOD(device_attach, sio_puc_attach),
406
407 { 0, 0 }
408};
409
410static driver_t sio_puc_driver = {
411 driver_name,
412 sio_puc_methods,
413 sizeof(struct com_s),
414};
415#endif /* NPUC > 0 */
416
417static d_open_t sioopen;
418static d_close_t sioclose;
419static d_read_t sioread;
420static d_write_t siowrite;
421static d_ioctl_t sioioctl;
422
423#define CDEV_MAJOR 28
424static struct cdevsw sio_cdevsw = {
425 /* open */ sioopen,
426 /* close */ sioclose,
427 /* read */ sioread,
428 /* write */ siowrite,
429 /* ioctl */ sioioctl,
430 /* poll */ ttypoll,
431 /* mmap */ nommap,
432 /* strategy */ nostrategy,
433 /* name */ driver_name,
434 /* maj */ CDEV_MAJOR,
435 /* dump */ nodump,
436 /* psize */ nopsize,
437 /* flags */ D_TTY | D_KQFILTER,
438 /* bmaj */ -1,
439 /* kqfilter */ ttykqfilter,
440};
441
442int comconsole = -1;
443static volatile speed_t comdefaultrate = CONSPEED;
444static u_long comdefaultrclk = DEFAULT_RCLK;
445SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
446#ifdef __alpha__
447static volatile speed_t gdbdefaultrate = CONSPEED;
448#endif
449static u_int com_events; /* input chars + weighted output completions */
450static Port_t siocniobase;
451static int siocnunit;
452static Port_t siogdbiobase;
453static int siogdbunit = -1;
454static bool_t sio_registered;
455static int sio_timeout;
456static int sio_timeouts_until_log;
457static struct callout_handle sio_timeout_handle
458 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
459static int sio_numunits;
460
461#ifdef COM_ESP
462/* XXX configure this properly. */
463static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
464static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
465#endif
466
467/*
468 * handle sysctl read/write requests for console speed
469 *
470 * In addition to setting comdefaultrate for I/O through /dev/console,
471 * also set the initial and lock values for the /dev/ttyXX device
472 * if there is one associated with the console. Finally, if the /dev/tty
473 * device has already been open, change the speed on the open running port
474 * itself.
475 */
476
477static int
478sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
479{
480 int error, s;
481 speed_t newspeed;
482 struct com_s *com;
483 struct tty *tp;
484
485 newspeed = comdefaultrate;
486
487 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
488 if (error || !req->newptr)
489 return (error);
490
491 comdefaultrate = newspeed;
492
493 if (comconsole < 0) /* serial console not selected? */
494 return (0);
495
496 com = com_addr(comconsole);
497 if (com == NULL)
498 return (ENXIO);
499
500 /*
501 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
502 * (note, the lock rates really are boolean -- if non-zero, disallow
503 * speed changes)
504 */
505 com->it_in.c_ispeed = com->it_in.c_ospeed =
506 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
507 com->it_out.c_ispeed = com->it_out.c_ospeed =
508 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
509
510 /*
511 * if we're open, change the running rate too
512 */
513 tp = com->tp;
514 if (tp && (tp->t_state & TS_ISOPEN)) {
515 tp->t_termios.c_ispeed =
516 tp->t_termios.c_ospeed = comdefaultrate;
517 s = spltty();
518 error = comparam(tp, &tp->t_termios);
519 splx(s);
520 }
521 return error;
522}
523
524SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
525 0, 0, sysctl_machdep_comdefaultrate, "I", "");
526
527#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
528#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
529
530#if NCARD > 0
531static int
532sio_pccard_probe(dev)
533 device_t dev;
534{
535 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */
536 /* until bus_setup_intr */
537 SET_FLAG(dev, COM_C_NOPROBE);
538
539 return (sioprobe(dev, 0, 0UL));
540}
541
542static int
543sio_pccard_attach(dev)
544 device_t dev;
545{
546 return (sioattach(dev, 0, 0UL));
547}
548
549/*
550 * sio_detach - unload the driver and clear the table.
551 * XXX TODO:
552 * This is usually called when the card is ejected, but
553 * can be caused by a modunload of a controller driver.
554 * The idea is to reset the driver's view of the device
555 * and ensure that any driver entry points such as
556 * read and write do not hang.
557 */
558static int
559sio_pccard_detach(dev)
560 device_t dev;
561{
562 struct com_s *com;
563
564 com = (struct com_s *) device_get_softc(dev);
565 if (com == NULL) {
566 device_printf(dev, "NULL com in siounload\n");
567 return (0);
568 }
569 com->gone = 1;
570 if (com->irqres) {
571 bus_teardown_intr(dev, com->irqres, com->cookie);
572 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
573 }
574 if (com->ioportres)
575 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
576 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
577 device_printf(dev, "still open, forcing close\n");
578 com->tp->t_gen++;
579 ttyclose(com->tp);
580 ttwakeup(com->tp);
581 ttwwakeup(com->tp);
582 } else {
583 if (com->ibuf != NULL)
584 free(com->ibuf, M_DEVBUF);
585 }
586 device_printf(dev, "unloaded\n");
587 return (0);
588}
589#endif /* NCARD > 0 */
590
591#if NPCI > 0
592struct pci_ids {
593 u_int32_t type;
594 const char *desc;
595 int rid;
596};
597
598static struct pci_ids pci_ids[] = {
599 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
600 { 0x2000131f, "CyberSerial (1-port) 16550", 0x10 },
601 { 0x01101407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
602 { 0x01111407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
603 { 0x048011c1, "Lucent kermit based PCI Modem", 0x14 },
604 { 0x95211415, "Oxford Semiconductor PCI Dual Port Serial", 0x10 },
605 { 0x7101135e, "SeaLevel Ultra 530.PCI Single Port Serial", 0x18 },
606 { 0x0000151f, "SmartLink 5634PCV SurfRider", 0x10 },
607 { 0x98459710, "Netmos Nm9845 PCI Bridge with Dual UART", 0x10 },
608 { 0x00000000, NULL, 0 }
609};
610
611static int
612sio_pci_attach(dev)
613 device_t dev;
614{
615 u_int32_t type;
616 struct pci_ids *id;
617
618 type = pci_get_devid(dev);
619 id = pci_ids;
620 while (id->type && id->type != type)
621 id++;
622 if (id->desc == NULL)
623 return (ENXIO);
624 sio_pci_kludge_unit(dev);
625 return (sioattach(dev, id->rid, 0UL));
626}
627
628/*
629 * Don't cut and paste this to other drivers. It is a horrible kludge
630 * which will fail to work and also be unnecessary in future versions.
631 */
632static void
633sio_pci_kludge_unit(dev)
634 device_t dev;
635{
636 devclass_t dc;
637 int err;
638 int start;
639 int unit;
640
641 unit = 0;
642 start = 0;
643 while (resource_int_value("sio", unit, "port", &start) == 0 &&
644 start > 0)
645 unit++;
646 if (device_get_unit(dev) < unit) {
647 dc = device_get_devclass(dev);
648 while (devclass_get_device(dc, unit))
649 unit++;
650 device_printf(dev, "moving to sio%d\n", unit);
651 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
652 if (err)
653 device_printf(dev, "error moving device %d\n", err);
654 }
655}
656
657static int
658sio_pci_probe(dev)
659 device_t dev;
660{
661 u_int32_t type;
662 struct pci_ids *id;
663
664 type = pci_get_devid(dev);
665 id = pci_ids;
666 while (id->type && id->type != type)
667 id++;
668 if (id->desc == NULL)
669 return (ENXIO);
670 device_set_desc(dev, id->desc);
671 return (sioprobe(dev, id->rid, 0UL));
672}
673#endif /* NPCI > 0 */
674
675#if NPUC > 0
676static int
677sio_puc_attach(dev)
678 device_t dev;
679{
680 u_int rclk;
681
682 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
683 &rclk) != 0)
684 rclk = DEFAULT_RCLK;
685 return (sioattach(dev, 0, rclk));
686}
687
688static int
689sio_puc_probe(dev)
690 device_t dev;
691{
692 u_int rclk;
693
694 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
695 &rclk) != 0)
696 rclk = DEFAULT_RCLK;
697 return (sioprobe(dev, 0, rclk));
698}
699#endif /* NPUC */
700
701static struct isa_pnp_id sio_ids[] = {
702 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
703 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
704 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
705 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
706 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
707 /* Devices that do not have a compatid */
708 {0x12206804, NULL}, /* ACH2012 - 5634BTS 56K Video Ready Modem */
709 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
710 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
711 {0x21107905, NULL}, /* AKY1021 - 56K Plug&Play Modem */
712 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
713 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
714 {0x56159008, NULL}, /* BDP1556 - B.D. Smart One 56SPS,Voice Modem*/
715 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
716 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
717 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
718 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
719 {0x0094490a, NULL}, /* BRI9400 - Boca K56Flex PnP */
720 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
721 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
722 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
723 {0x01308c0e, NULL}, /* CTL3001 - Creative Labs Phoneblaster */
724 {0x36033610, NULL}, /* DAV0336 - DAVICOM 336PNP MODEM */
725 {0x01009416, NULL}, /* ETT0001 - E-Tech Bullet 33k6 PnP */
726 {0x0000aa1a, NULL}, /* FUJ0000 - FUJITSU Modem 33600 PNP/I2 */
727 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
728 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
729 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
730 {0x0116c31e, NULL}, /* GVC1601 - Rockwell V.34 Plug & Play Modem */
731 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
732 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
733 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
734 {0x8100e425, NULL}, /* IOD0081 - I-O DATA DEVICE,INC. IFML-560 */
735 {0x21002534, NULL}, /* MAE0021 - Jetstream Int V.90 56k Voice Series 2*/
736 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
737 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
738 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
739 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
740 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
741 {0x08804f3f, NULL}, /* OZO8008 - Zoom (33.6k Modem) */
742 {0x0f804f3f, NULL}, /* OZO800f - Zoom 2812 (56k Modem) */
743 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
744 {0x00914f3f, NULL}, /* OZO9100 - Zoom 2919 (K56 Faxmodem) */
745 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
746 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
747 {0x1200b23d, NULL}, /* RSS0012 - OMRON ME5614ISA */
748 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
749 {0x6202734a, NULL}, /* RSS0262 - 5614Jx3[G] V90+K56Flex Modem */
750 {0x1010104d, NULL}, /* SHP1010 - Rockwell 33600bps Modem */
751 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
752 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
753 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
754 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
755 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
756 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
757 {0x7016b04e, NULL}, /* SUP1670 - Supra 336i V+ Intl */
758 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
759 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
760 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
761 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
762 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
763 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
764 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
765 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
766 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
767 {0x11007256, NULL}, /* USR0011 - USR ? */
768 {0x01017256, NULL}, /* USR0101 - USR ? */
769 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
770 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
771 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
772 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
773 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
774 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
775 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
776 {0x90307256, NULL}, /* USR3090 - USR ? */
777 {0x70917256, NULL}, /* USR9170 - U.S. Robotics 56K FAX INT */
778 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
779 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
780 {0x01a0896a, NULL}, /* ZTIA001 - Zoom Internal V90 Faxmodem */
781 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
782 {0}
783};
784
785
786
787static int
788sio_isa_probe(dev)
789 device_t dev;
790{
791 /* Check isapnp ids */
792 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
793 return (ENXIO);
794 return (sioprobe(dev, 0, 0UL));
795}
796
797static int
798sioprobe(dev, xrid, rclk)
799 device_t dev;
800 int xrid;
801 u_long rclk;
802{
803#if 0
804 static bool_t already_init;
805 device_t xdev;
806#endif
807 struct com_s *com;
808 u_int divisor;
809 bool_t failures[10];
810 int fn;
811 device_t idev;
812 Port_t iobase;
813 intrmask_t irqmap[4];
814 intrmask_t irqs;
815 u_char mcr_image;
816 int result;
817 u_long xirq;
818 u_int flags = device_get_flags(dev);
819 int rid;
820 struct resource *port;
821
822 rid = xrid;
823 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
824 0, ~0, IO_COMSIZE, RF_ACTIVE);
825 if (!port)
826 return (ENXIO);
827
828 com = device_get_softc(dev);
829 com->bst = rman_get_bustag(port);
830 com->bsh = rman_get_bushandle(port);
831 if (rclk == 0)
832 rclk = DEFAULT_RCLK;
833 com->rclk = rclk;
834
835#if 0
836 /*
837 * XXX this is broken - when we are first called, there are no
838 * previously configured IO ports. We could hard code
839 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
840 * This code has been doing nothing since the conversion since
841 * "count" is zero the first time around.
842 */
843 if (!already_init) {
844 /*
845 * Turn off MCR_IENABLE for all likely serial ports. An unused
846 * port with its MCR_IENABLE gate open will inhibit interrupts
847 * from any used port that shares the interrupt vector.
848 * XXX the gate enable is elsewhere for some multiports.
849 */
850 device_t *devs;
851 int count, i, xioport;
852
853 devclass_get_devices(sio_devclass, &devs, &count);
854 for (i = 0; i < count; i++) {
855 xdev = devs[i];
856 if (device_is_enabled(xdev) &&
857 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
858 NULL) == 0)
859 outb(xioport + com_mcr, 0);
860 }
861 free(devs, M_TEMP);
862 already_init = TRUE;
863 }
864#endif
865
866 if (COM_LLCONSOLE(flags)) {
867 printf("sio%d: reserved for low-level i/o\n",
868 device_get_unit(dev));
869 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
870 return (ENXIO);
871 }
872
873 /*
874 * If the device is on a multiport card and has an AST/4
875 * compatible interrupt control register, initialize this
876 * register and prepare to leave MCR_IENABLE clear in the mcr.
877 * Otherwise, prepare to set MCR_IENABLE in the mcr.
878 * Point idev to the device struct giving the correct id_irq.
879 * This is the struct for the master device if there is one.
880 */
881 idev = dev;
882 mcr_image = MCR_IENABLE;
883#ifdef COM_MULTIPORT
884 if (COM_ISMULTIPORT(flags)) {
885 Port_t xiobase;
886 u_long io;
887
888 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
889 if (idev == NULL) {
890 printf("sio%d: master device %d not configured\n",
891 device_get_unit(dev), COM_MPMASTER(flags));
892 idev = dev;
893 }
894 if (!COM_NOTAST4(flags)) {
895 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
896 NULL) == 0) {
897 xiobase = io;
898 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
899 NULL, NULL) == 0)
900 outb(xiobase + com_scr, 0x80);
901 else
902 outb(xiobase + com_scr, 0);
903 }
904 mcr_image = 0;
905 }
906 }
907#endif /* COM_MULTIPORT */
908 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
909 mcr_image = 0;
910
911 bzero(failures, sizeof failures);
912 iobase = rman_get_start(port);
913
914 /*
915 * We don't want to get actual interrupts, just masked ones.
916 * Interrupts from this line should already be masked in the ICU,
917 * but mask them in the processor as well in case there are some
918 * (misconfigured) shared interrupts.
919 */
920 disable_intr();
921/* EXTRA DELAY? */
922
923 /*
924 * For the TI16754 chips, set prescaler to 1 (4 is often the
925 * default after-reset value) as otherwise it's impossible to
926 * get highest baudrates.
927 */
928 if (COM_TI16754(flags)) {
929 u_char cfcr, efr;
930
931 cfcr = sio_getreg(com, com_cfcr);
932 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
933 efr = sio_getreg(com, com_efr);
934 /* Unlock extended features to turn off prescaler. */
935 sio_setreg(com, com_efr, efr | EFR_EFE);
936 /* Disable EFR. */
937 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
938 /* Turn off prescaler. */
939 sio_setreg(com, com_mcr,
940 sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
941 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
942 sio_setreg(com, com_efr, efr);
943 sio_setreg(com, com_cfcr, cfcr);
944 }
945
946 /*
947 * Initialize the speed and the word size and wait long enough to
948 * drain the maximum of 16 bytes of junk in device output queues.
949 * The speed is undefined after a master reset and must be set
950 * before relying on anything related to output. There may be
951 * junk after a (very fast) soft reboot and (apparently) after
952 * master reset.
953 * XXX what about the UART bug avoided by waiting in comparam()?
954 * We don't want to to wait long enough to drain at 2 bps.
955 */
956 if (iobase == siocniobase)
957 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
958 else {
959 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
960 divisor = siodivisor(rclk, SIO_TEST_SPEED);
961 sio_setreg(com, com_dlbl, divisor & 0xff);
962 sio_setreg(com, com_dlbh, divisor >> 8);
963 sio_setreg(com, com_cfcr, CFCR_8BITS);
964 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
965 }
966
967 /*
968 * Enable the interrupt gate and disable device interupts. This
969 * should leave the device driving the interrupt line low and
970 * guarantee an edge trigger if an interrupt can be generated.
971 */
972/* EXTRA DELAY? */
973 sio_setreg(com, com_mcr, mcr_image);
974 sio_setreg(com, com_ier, 0);
975 DELAY(1000); /* XXX */
976 irqmap[0] = isa_irq_pending();
977
978 /*
979 * Attempt to set loopback mode so that we can send a null byte
980 * without annoying any external device.
981 */
982/* EXTRA DELAY? */
983 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
984
985 /*
986 * Attempt to generate an output interrupt. On 8250's, setting
987 * IER_ETXRDY generates an interrupt independent of the current
988 * setting and independent of whether the THR is empty. On 16450's,
989 * setting IER_ETXRDY generates an interrupt independent of the
990 * current setting. On 16550A's, setting IER_ETXRDY only
991 * generates an interrupt when IER_ETXRDY is not already set.
992 */
993 sio_setreg(com, com_ier, IER_ETXRDY);
994
995 /*
996 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
997 * an interrupt. They'd better generate one for actually doing
998 * output. Loopback may be broken on the same incompatibles but
999 * it's unlikely to do more than allow the null byte out.
1000 */
1001 sio_setreg(com, com_data, 0);
1002 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1003
1004 /*
1005 * Turn off loopback mode so that the interrupt gate works again
1006 * (MCR_IENABLE was hidden). This should leave the device driving
1007 * an interrupt line high. It doesn't matter if the interrupt
1008 * line oscillates while we are not looking at it, since interrupts
1009 * are disabled.
1010 */
1011/* EXTRA DELAY? */
1012 sio_setreg(com, com_mcr, mcr_image);
1013
1014 /*
1015 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1016 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1017 */
1018 if (COM_NOPROBE(flags)) {
1019 /* Reading IIR register twice */
1020 for (fn = 0; fn < 2; fn ++) {
1021 DELAY(10000);
1022 failures[6] = sio_getreg(com, com_iir);
1023 }
1024 /* Check IIR_TXRDY clear ? */
1025 result = 0;
1026 if (failures[6] & IIR_TXRDY) {
1027 /* Nop, Double check with clearing IER */
1028 sio_setreg(com, com_ier, 0);
1029 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1030 /* Ok. we're familia this gang */
1031 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1032 } else {
1033 /* Unknown, Just omit this chip.. XXX */
1034 result = ENXIO;
1035 sio_setreg(com, com_mcr, 0);
1036 }
1037 } else {
1038 /* OK. this is well-known guys */
1039 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1040 }
1041 sio_setreg(com, com_ier, 0);
1042 sio_setreg(com, com_cfcr, CFCR_8BITS);
1043 enable_intr();
1044 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1045 return (iobase == siocniobase ? 0 : result);
1046 }
1047
1048 /*
1049 * Check that
1050 * o the CFCR, IER and MCR in UART hold the values written to them
1051 * (the values happen to be all distinct - this is good for
1052 * avoiding false positive tests from bus echoes).
1053 * o an output interrupt is generated and its vector is correct.
1054 * o the interrupt goes away when the IIR in the UART is read.
1055 */
1056/* EXTRA DELAY? */
1057 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1058 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1059 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1060 DELAY(10000); /* Some internal modems need this time */
1061 irqmap[1] = isa_irq_pending();
1062 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1063 DELAY(1000); /* XXX */
1064 irqmap[2] = isa_irq_pending();
1065 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1066
1067 /*
1068 * Turn off all device interrupts and check that they go off properly.
1069 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1070 * the OUT2 output of the UART to
1071 * the ICU input. Closing the gate would give a floating ICU input
1072 * (unless there is another device driving it) and spurious interrupts.
1073 * (On the system that this was first tested on, the input floats high
1074 * and gives a (masked) interrupt as soon as the gate is closed.)
1075 */
1076 sio_setreg(com, com_ier, 0);
1077 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1078 failures[7] = sio_getreg(com, com_ier);
1079 DELAY(1000); /* XXX */
1080 irqmap[3] = isa_irq_pending();
1081 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1082
1083 enable_intr();
1084
1085 irqs = irqmap[1] & ~irqmap[0];
1086 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1087 ((1 << xirq) & irqs) == 0)
1088 printf(
1089 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1090 device_get_unit(dev), xirq, irqs);
1091 if (bootverbose)
1092 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1093 device_get_unit(dev),
1094 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1095
1096 result = 0;
1097 for (fn = 0; fn < sizeof failures; ++fn)
1098 if (failures[fn]) {
1099 sio_setreg(com, com_mcr, 0);
1100 result = ENXIO;
1101 if (bootverbose) {
1102 printf("sio%d: probe failed test(s):",
1103 device_get_unit(dev));
1104 for (fn = 0; fn < sizeof failures; ++fn)
1105 if (failures[fn])
1106 printf(" %d", fn);
1107 printf("\n");
1108 }
1109 break;
1110 }
1111 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1112 return (iobase == siocniobase ? 0 : result);
1113}
1114
1115#ifdef COM_ESP
1116static int
1117espattach(com, esp_port)
1118 struct com_s *com;
1119 Port_t esp_port;
1120{
1121 u_char dips;
1122 u_char val;
1123
1124 /*
1125 * Check the ESP-specific I/O port to see if we're an ESP
1126 * card. If not, return failure immediately.
1127 */
1128 if ((inb(esp_port) & 0xf3) == 0) {
1129 printf(" port 0x%x is not an ESP board?\n", esp_port);
1130 return (0);
1131 }
1132
1133 /*
1134 * We've got something that claims to be a Hayes ESP card.
1135 * Let's hope so.
1136 */
1137
1138 /* Get the dip-switch configuration */
1139 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1140 dips = inb(esp_port + ESP_STATUS1);
1141
1142 /*
1143 * Bits 0,1 of dips say which COM port we are.
1144 */
1145 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1146 printf(" : ESP");
1147 else {
1148 printf(" esp_port has com %d\n", dips & 0x03);
1149 return (0);
1150 }
1151
1152 /*
1153 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1154 */
1155 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1156 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1157 val = inb(esp_port + ESP_STATUS2);
1158 if ((val & 0x70) < 0x20) {
1159 printf("-old (%o)", val & 0x70);
1160 return (0);
1161 }
1162
1163 /*
1164 * Check for ability to emulate 16550: bit 7 == 1
1165 */
1166 if ((dips & 0x80) == 0) {
1167 printf(" slave");
1168 return (0);
1169 }
1170
1171 /*
1172 * Okay, we seem to be a Hayes ESP card. Whee.
1173 */
1174 com->esp = TRUE;
1175 com->esp_port = esp_port;
1176 return (1);
1177}
1178#endif /* COM_ESP */
1179
1180static int
1181sio_isa_attach(dev)
1182 device_t dev;
1183{
1184 return (sioattach(dev, 0, 0UL));
1185}
1186
1187static int
1188sioattach(dev, xrid, rclk)
1189 device_t dev;
1190 int xrid;
1191 u_long rclk;
1192{
1193 struct com_s *com;
1194#ifdef COM_ESP
1195 Port_t *espp;
1196#endif
1197 Port_t iobase;
1198 int minorbase;
1199 int unit;
1200 u_int flags;
1201 int rid;
1202 struct resource *port;
1203 int ret;
1204
1205 rid = xrid;
1206 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1207 0, ~0, IO_COMSIZE, RF_ACTIVE);
1208 if (!port)
1209 return (ENXIO);
1210
1211 iobase = rman_get_start(port);
1212 unit = device_get_unit(dev);
1213 com = device_get_softc(dev);
1214 flags = device_get_flags(dev);
1215
1216 if (unit >= sio_numunits)
1217 sio_numunits = unit + 1;
1218 /*
1219 * sioprobe() has initialized the device registers as follows:
1220 * o cfcr = CFCR_8BITS.
1221 * It is most important that CFCR_DLAB is off, so that the
1222 * data port is not hidden when we enable interrupts.
1223 * o ier = 0.
1224 * Interrupts are only enabled when the line is open.
1225 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1226 * interrupt control register or the config specifies no irq.
1227 * Keeping MCR_DTR and MCR_RTS off might stop the external
1228 * device from sending before we are ready.
1229 */
1230 bzero(com, sizeof *com);
1231 com->unit = unit;
1232 com->ioportres = port;
1233 com->bst = rman_get_bustag(port);
1234 com->bsh = rman_get_bushandle(port);
1235 com->cfcr_image = CFCR_8BITS;
1236 com->dtr_wait = 3 * hz;
1237 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1238 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1239 com->tx_fifo_size = 1;
1240 com->obufs[0].l_head = com->obuf1;
1241 com->obufs[1].l_head = com->obuf2;
1242
1243 com->data_port = iobase + com_data;
1244 com->int_id_port = iobase + com_iir;
1245 com->modem_ctl_port = iobase + com_mcr;
1246 com->mcr_image = inb(com->modem_ctl_port);
1247 com->line_status_port = iobase + com_lsr;
1248 com->modem_status_port = iobase + com_msr;
1249 com->intr_ctl_port = iobase + com_ier;
1250
1251 if (rclk == 0)
1252 rclk = DEFAULT_RCLK;
1253 com->rclk = rclk;
1254
1255 /*
1256 * We don't use all the flags from <sys/ttydefaults.h> since they
1257 * are only relevant for logins. It's important to have echo off
1258 * initially so that the line doesn't start blathering before the
1259 * echo flag can be turned off.
1260 */
1261 com->it_in.c_iflag = 0;
1262 com->it_in.c_oflag = 0;
1263 com->it_in.c_cflag = TTYDEF_CFLAG;
1264 com->it_in.c_lflag = 0;
1265 if (unit == comconsole) {
1266 com->it_in.c_iflag = TTYDEF_IFLAG;
1267 com->it_in.c_oflag = TTYDEF_OFLAG;
1268 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1269 com->it_in.c_lflag = TTYDEF_LFLAG;
1270 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1271 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1272 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1273 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1274 } else
1275 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1276 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1277 enable_intr();
1278 /*
1279 * Leave i/o resources allocated if this is a `cn'-level
1280 * console, so that other devices can't snarf them.
1281 */
1282 if (iobase != siocniobase)
1283 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1284 return (ENOMEM);
1285 }
1286 enable_intr();
1287 termioschars(&com->it_in);
1288 com->it_out = com->it_in;
1289
1290 /* attempt to determine UART type */
1291 printf("sio%d: type", unit);
1292
1293
1294#ifdef COM_MULTIPORT
1295 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1296#else
1297 if (!COM_IIR_TXRDYBUG(flags))
1298#endif
1299 {
1300 u_char scr;
1301 u_char scr1;
1302 u_char scr2;
1303
1304 scr = sio_getreg(com, com_scr);
1305 sio_setreg(com, com_scr, 0xa5);
1306 scr1 = sio_getreg(com, com_scr);
1307 sio_setreg(com, com_scr, 0x5a);
1308 scr2 = sio_getreg(com, com_scr);
1309 sio_setreg(com, com_scr, scr);
1310 if (scr1 != 0xa5 || scr2 != 0x5a) {
1311 printf(" 8250");
1312 goto determined_type;
1313 }
1314 }
1315 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1316 DELAY(100);
1317 com->st16650a = 0;
1318 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1319 case FIFO_RX_LOW:
1320 printf(" 16450");
1321 break;
1322 case FIFO_RX_MEDL:
1323 printf(" 16450?");
1324 break;
1325 case FIFO_RX_MEDH:
1326 printf(" 16550?");
1327 break;
1328 case FIFO_RX_HIGH:
1329 if (COM_NOFIFO(flags)) {
1330 printf(" 16550A fifo disabled");
1331 } else {
1332 com->hasfifo = TRUE;
1333 if (COM_ST16650A(flags)) {
1334 com->st16650a = 1;
1335 com->tx_fifo_size = 32;
1336 printf(" ST16650A");
1337 } else if (COM_TI16754(flags)) {
1338 com->tx_fifo_size = 64;
1339 printf(" TI16754");
1340 } else {
1341 com->tx_fifo_size = COM_FIFOSIZE(flags);
1342 printf(" 16550A");
1343 }
1344 }
1345#ifdef COM_ESP
1346 for (espp = likely_esp_ports; *espp != 0; espp++)
1347 if (espattach(com, *espp)) {
1348 com->tx_fifo_size = 1024;
1349 break;
1350 }
1351#endif
1352 if (!com->st16650a && !COM_TI16754(flags)) {
1353 if (!com->tx_fifo_size)
1354 com->tx_fifo_size = 16;
1355 else
1356 printf(" lookalike with %d bytes FIFO",
1357 com->tx_fifo_size);
1358 }
1359
1360 break;
1361 }
1362
1363#ifdef COM_ESP
1364 if (com->esp) {
1365 /*
1366 * Set 16550 compatibility mode.
1367 * We don't use the ESP_MODE_SCALE bit to increase the
1368 * fifo trigger levels because we can't handle large
1369 * bursts of input.
1370 * XXX flow control should be set in comparam(), not here.
1371 */
1372 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1373 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1374
1375 /* Set RTS/CTS flow control. */
1376 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1377 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1378 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1379
1380 /* Set flow-control levels. */
1381 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1382 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1383 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1384 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1385 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1386 }
1387#endif /* COM_ESP */
1388 sio_setreg(com, com_fifo, 0);
1389determined_type: ;
1390
1391#ifdef COM_MULTIPORT
1392 if (COM_ISMULTIPORT(flags)) {
1393 device_t masterdev;
1394
1395 com->multiport = TRUE;
1396 printf(" (multiport");
1397 if (unit == COM_MPMASTER(flags))
1398 printf(" master");
1399 printf(")");
1400 masterdev = devclass_get_device(sio_devclass,
1401 COM_MPMASTER(flags));
1402 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1403 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1404 }
1405#endif /* COM_MULTIPORT */
1406 if (unit == comconsole)
1407 printf(", console");
1408 if (COM_IIR_TXRDYBUG(flags))
1409 printf(" with a bogus IIR_TXRDY register");
1410 printf("\n");
1411
1412 if (!sio_registered) {
1413 register_swi(SWI_TTY, siopoll);
1414 sio_registered = TRUE;
1415 }
1416 minorbase = UNIT_TO_MINOR(unit);
1417 make_dev(&sio_cdevsw, minorbase,
1418 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1419 make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE,
1420 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1421 make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE,
1422 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1423 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK,
1424 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1425 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_INIT_STATE,
1426 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1427 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE,
1428 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1429 com->flags = flags;
1430 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1431 pps_init(&com->pps);
1432
1433 rid = 0;
1434 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1435 RF_ACTIVE);
1436 if (com->irqres) {
1437 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1438 INTR_TYPE_TTY | INTR_TYPE_FAST,
1439 siointr, com, &com->cookie);
1440 if (ret) {
1441 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1442 com->irqres, INTR_TYPE_TTY,
1443 siointr, com, &com->cookie);
1444 if (ret == 0)
1445 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1446 }
1447 if (ret)
1448 device_printf(dev, "could not activate interrupt\n");
1449#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1450 defined(ALT_BREAK_TO_DEBUGGER))
1451 /*
1452 * Enable interrupts for early break-to-debugger support
1453 * on the console.
1454 */
1455 if (ret == 0 && unit == comconsole)
1456 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1457 IER_EMSC);
1458#endif
1459 }
1460
1461 return (0);
1462}
1463
1464static int
1465sioopen(dev, flag, mode, p)
1466 dev_t dev;
1467 int flag;
1468 int mode;
1469 struct proc *p;
1470{
1471 struct com_s *com;
1472 int error;
1473 int mynor;
1474 int s;
1475 struct tty *tp;
1476 int unit;
1477
1478 mynor = minor(dev);
1479 unit = MINOR_TO_UNIT(mynor);
1480 com = com_addr(unit);
1481 if (com == NULL)
1482 return (ENXIO);
1483 if (com->gone)
1484 return (ENXIO);
1485 if (mynor & CONTROL_MASK)
1486 return (0);
1487 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1488 s = spltty();
1489 /*
1490 * We jump to this label after all non-interrupted sleeps to pick
1491 * up any changes of the device state.
1492 */
1493open_top:
1494 while (com->state & CS_DTR_OFF) {
1495 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1496 if (com_addr(unit) == NULL)
1497 return (ENXIO);
1498 if (error != 0 || com->gone)
1499 goto out;
1500 }
1501 if (tp->t_state & TS_ISOPEN) {
1502 /*
1503 * The device is open, so everything has been initialized.
1504 * Handle conflicts.
1505 */
1506 if (mynor & CALLOUT_MASK) {
1507 if (!com->active_out) {
1508 error = EBUSY;
1509 goto out;
1510 }
1511 } else {
1512 if (com->active_out) {
1513 if (flag & O_NONBLOCK) {
1514 error = EBUSY;
1515 goto out;
1516 }
1517 error = tsleep(&com->active_out,
1518 TTIPRI | PCATCH, "siobi", 0);
1519 if (com_addr(unit) == NULL)
1520 return (ENXIO);
1521 if (error != 0 || com->gone)
1522 goto out;
1523 goto open_top;
1524 }
1525 }
1526 if (tp->t_state & TS_XCLUDE &&
1527 suser(p)) {
1528 error = EBUSY;
1529 goto out;
1530 }
1531 } else {
1532 /*
1533 * The device isn't open, so there are no conflicts.
1534 * Initialize it. Initialization is done twice in many
1535 * cases: to preempt sleeping callin opens if we are
1536 * callout, and to complete a callin open after DCD rises.
1537 */
1538 tp->t_oproc = comstart;
1539 tp->t_param = comparam;
1540 tp->t_stop = comstop;
1541 tp->t_dev = dev;
1542 tp->t_termios = mynor & CALLOUT_MASK
1543 ? com->it_out : com->it_in;
1544 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1545 com->poll = com->no_irq;
1546 com->poll_output = com->loses_outints;
1547 ++com->wopeners;
1548 error = comparam(tp, &tp->t_termios);
1549 --com->wopeners;
1550 if (error != 0)
1551 goto out;
1552 /*
1553 * XXX we should goto open_top if comparam() slept.
1554 */
1555 if (com->hasfifo) {
1556 /*
1557 * (Re)enable and drain fifos.
1558 *
1559 * Certain SMC chips cause problems if the fifos
1560 * are enabled while input is ready. Turn off the
1561 * fifo if necessary to clear the input. We test
1562 * the input ready bit after enabling the fifos
1563 * since we've already enabled them in comparam()
1564 * and to handle races between enabling and fresh
1565 * input.
1566 */
1567 while (TRUE) {
1568 sio_setreg(com, com_fifo,
1569 FIFO_RCV_RST | FIFO_XMT_RST
1570 | com->fifo_image);
1571 /*
1572 * XXX the delays are for superstitious
1573 * historical reasons. It must be less than
1574 * the character time at the maximum
1575 * supported speed (87 usec at 115200 bps
1576 * 8N1). Otherwise we might loop endlessly
1577 * if data is streaming in. We used to use
1578 * delays of 100. That usually worked
1579 * because DELAY(100) used to usually delay
1580 * for about 85 usec instead of 100.
1581 */
1582 DELAY(50);
1583 if (!(inb(com->line_status_port) & LSR_RXRDY))
1584 break;
1585 sio_setreg(com, com_fifo, 0);
1586 DELAY(50);
1587 (void) inb(com->data_port);
1588 }
1589 }
1590
1591 disable_intr();
1592 (void) inb(com->line_status_port);
1593 (void) inb(com->data_port);
1594 com->prev_modem_status = com->last_modem_status
1595 = inb(com->modem_status_port);
1596 if (COM_IIR_TXRDYBUG(com->flags)) {
1597 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1598 | IER_EMSC);
1599 } else {
1600 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1601 | IER_ERLS | IER_EMSC);
1602 }
1603 enable_intr();
1604 /*
1605 * Handle initial DCD. Callout devices get a fake initial
1606 * DCD (trapdoor DCD). If we are callout, then any sleeping
1607 * callin opens get woken up and resume sleeping on "siobi"
1608 * instead of "siodcd".
1609 */
1610 /*
1611 * XXX `mynor & CALLOUT_MASK' should be
1612 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1613 * TRAPDOOR_CARRIER is the default initial state for callout
1614 * devices and SOFT_CARRIER is like CLOCAL except it hides
1615 * the true carrier.
1616 */
1617 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1618 (*linesw[tp->t_line].l_modem)(tp, 1);
1619 }
1620 /*
1621 * Wait for DCD if necessary.
1622 */
1623 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1624 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1625 ++com->wopeners;
1626 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
1627 if (com_addr(unit) == NULL)
1628 return (ENXIO);
1629 --com->wopeners;
1630 if (error != 0 || com->gone)
1631 goto out;
1632 goto open_top;
1633 }
1634 error = (*linesw[tp->t_line].l_open)(dev, tp);
1635 disc_optim(tp, &tp->t_termios, com);
1636 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1637 com->active_out = TRUE;
1638 siosettimeout();
1639out:
1640 splx(s);
1641 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1642 comhardclose(com);
1643 return (error);
1644}
1645
1646static int
1647sioclose(dev, flag, mode, p)
1648 dev_t dev;
1649 int flag;
1650 int mode;
1651 struct proc *p;
1652{
1653 struct com_s *com;
1654 int mynor;
1655 int s;
1656 struct tty *tp;
1657
1658 mynor = minor(dev);
1659 if (mynor & CONTROL_MASK)
1660 return (0);
1661 com = com_addr(MINOR_TO_UNIT(mynor));
1662 if (com == NULL)
1663 return (ENODEV);
1664 tp = com->tp;
1665 s = spltty();
1666 (*linesw[tp->t_line].l_close)(tp, flag);
1667 disc_optim(tp, &tp->t_termios, com);
1668 comstop(tp, FREAD | FWRITE);
1669 comhardclose(com);
1670 ttyclose(tp);
1671 siosettimeout();
1672 splx(s);
1673 if (com->gone) {
1674 printf("sio%d: gone\n", com->unit);
1675 s = spltty();
1676 if (com->ibuf != NULL)
1677 free(com->ibuf, M_DEVBUF);
1678 bzero(tp, sizeof *tp);
1679 splx(s);
1680 }
1681 return (0);
1682}
1683
1684static void
1685comhardclose(com)
1686 struct com_s *com;
1687{
1688 int s;
1689 struct tty *tp;
1690 int unit;
1691
1692 unit = com->unit;
1693 s = spltty();
1694 com->poll = FALSE;
1695 com->poll_output = FALSE;
1696 com->do_timestamp = FALSE;
1697 com->do_dcd_timestamp = FALSE;
1698 com->pps.ppsparam.mode = 0;
1699 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1700 tp = com->tp;
1701
1702#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1703 defined(ALT_BREAK_TO_DEBUGGER))
1704 /*
1705 * Leave interrupts enabled and don't clear DTR if this is the
1706 * console. This allows us to detect break-to-debugger events
1707 * while the console device is closed.
1708 */
1709 if (com->unit != comconsole)
1710#endif
1711 {
1712 sio_setreg(com, com_ier, 0);
1713 if (tp->t_cflag & HUPCL
1714 /*
1715 * XXX we will miss any carrier drop between here and the
1716 * next open. Perhaps we should watch DCD even when the
1717 * port is closed; it is not sufficient to check it at
1718 * the next open because it might go up and down while
1719 * we're not watching.
1720 */
1721 || (!com->active_out
1722 && !(com->prev_modem_status & MSR_DCD)
1723 && !(com->it_in.c_cflag & CLOCAL))
1724 || !(tp->t_state & TS_ISOPEN)) {
1725 (void)commctl(com, TIOCM_DTR, DMBIC);
1726 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1727 timeout(siodtrwakeup, com, com->dtr_wait);
1728 com->state |= CS_DTR_OFF;
1729 }
1730 }
1731 }
1732 if (com->hasfifo) {
1733 /*
1734 * Disable fifos so that they are off after controlled
1735 * reboots. Some BIOSes fail to detect 16550s when the
1736 * fifos are enabled.
1737 */
1738 sio_setreg(com, com_fifo, 0);
1739 }
1740 com->active_out = FALSE;
1741 wakeup(&com->active_out);
1742 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1743 splx(s);
1744}
1745
1746static int
1747sioread(dev, uio, flag)
1748 dev_t dev;
1749 struct uio *uio;
1750 int flag;
1751{
1752 int mynor;
1753 struct com_s *com;
1754
1755 mynor = minor(dev);
1756 if (mynor & CONTROL_MASK)
1757 return (ENODEV);
1758 com = com_addr(MINOR_TO_UNIT(mynor));
1759 if (com == NULL || com->gone)
1760 return (ENODEV);
1761 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1762}
1763
1764static int
1765siowrite(dev, uio, flag)
1766 dev_t dev;
1767 struct uio *uio;
1768 int flag;
1769{
1770 int mynor;
1771 struct com_s *com;
1772 int unit;
1773
1774 mynor = minor(dev);
1775 if (mynor & CONTROL_MASK)
1776 return (ENODEV);
1777
1778 unit = MINOR_TO_UNIT(mynor);
1779 com = com_addr(unit);
1780 if (com == NULL || com->gone)
1781 return (ENODEV);
1782 /*
1783 * (XXX) We disallow virtual consoles if the physical console is
1784 * a serial port. This is in case there is a display attached that
1785 * is not the console. In that situation we don't need/want the X
1786 * server taking over the console.
1787 */
1788 if (constty != NULL && unit == comconsole)
1789 constty = NULL;
1790 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1791}
1792
1793static void
1794siobusycheck(chan)
1795 void *chan;
1796{
1797 struct com_s *com;
1798 int s;
1799
1800 com = (struct com_s *)chan;
1801
1802 /*
1803 * Clear TS_BUSY if low-level output is complete.
1804 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1805 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1806 * called again. Reading the line status port outside of siointr1()
1807 * is safe because CS_BUSY is clear so there are no output interrupts
1808 * to lose.
1809 */
1810 s = spltty();
1811 if (com->state & CS_BUSY)
1812 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1813 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1814 == (LSR_TSRE | LSR_TXRDY)) {
1815 com->tp->t_state &= ~TS_BUSY;
1816 ttwwakeup(com->tp);
1817 com->extra_state &= ~CSE_BUSYCHECK;
1818 } else
1819 timeout(siobusycheck, com, hz / 100);
1820 splx(s);
1821}
1822
1823static u_int
1824siodivisor(rclk, speed)
1825 u_long rclk;
1826 speed_t speed;
1827{
1828 long actual_speed;
1829 u_int divisor;
1830 int error;
1831
1832 if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1833 return (0);
1834 divisor = (rclk / (8UL * speed) + 1) / 2;
1835 if (divisor == 0 || divisor >= 65536)
1836 return (0);
1837 actual_speed = rclk / (16UL * divisor);
1838
1839 /* 10 times error in percent: */
1840 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1841
1842 /* 3.0% maximum error tolerance: */
1843 if (error < -30 || error > 30)
1844 return (0);
1845
1846 return (divisor);
1847}
1848
1849static void
1850siodtrwakeup(chan)
1851 void *chan;
1852{
1853 struct com_s *com;
1854
1855 com = (struct com_s *)chan;
1856 com->state &= ~CS_DTR_OFF;
1857 wakeup(&com->dtr_wait);
1858}
1859
1860static void
1861sioinput(com)
1862 struct com_s *com;
1863{
1864 u_char *buf;
1865 int incc;
1866 u_char line_status;
1867 int recv_data;
1868 struct tty *tp;
1869
1870 buf = com->ibuf;
1871 tp = com->tp;
1872 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1873 com_events -= (com->iptr - com->ibuf);
1874 com->iptr = com->ibuf;
1875 return;
1876 }
1877 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1878 /*
1879 * Avoid the grotesquely inefficient lineswitch routine
1880 * (ttyinput) in "raw" mode. It usually takes about 450
1881 * instructions (that's without canonical processing or echo!).
1882 * slinput is reasonably fast (usually 40 instructions plus
1883 * call overhead).
1884 */
1885 do {
1886 enable_intr();
1887 incc = com->iptr - buf;
1888 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1889 && (com->state & CS_RTS_IFLOW
1890 || tp->t_iflag & IXOFF)
1891 && !(tp->t_state & TS_TBLOCK))
1892 ttyblock(tp);
1893 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1894 += b_to_q((char *)buf, incc, &tp->t_rawq);
1895 buf += incc;
1896 tk_nin += incc;
1897 tk_rawcc += incc;
1898 tp->t_rawcc += incc;
1899 ttwakeup(tp);
1900 if (tp->t_state & TS_TTSTOP
1901 && (tp->t_iflag & IXANY
1902 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1903 tp->t_state &= ~TS_TTSTOP;
1904 tp->t_lflag &= ~FLUSHO;
1905 comstart(tp);
1906 }
1907 disable_intr();
1908 } while (buf < com->iptr);
1909 } else {
1910 do {
1911 enable_intr();
1912 line_status = buf[com->ierroff];
1913 recv_data = *buf++;
1914 if (line_status
1915 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1916 if (line_status & LSR_BI)
1917 recv_data |= TTY_BI;
1918 if (line_status & LSR_FE)
1919 recv_data |= TTY_FE;
1920 if (line_status & LSR_OE)
1921 recv_data |= TTY_OE;
1922 if (line_status & LSR_PE)
1923 recv_data |= TTY_PE;
1924 }
1925 (*linesw[tp->t_line].l_rint)(recv_data, tp);
1926 disable_intr();
1927 } while (buf < com->iptr);
1928 }
1929 com_events -= (com->iptr - com->ibuf);
1930 com->iptr = com->ibuf;
1931
1932 /*
1933 * There is now room for another low-level buffer full of input,
1934 * so enable RTS if it is now disabled and there is room in the
1935 * high-level buffer.
1936 */
1937 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1938 !(tp->t_state & TS_TBLOCK))
1939 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1940}
1941
1942void
1943siointr(arg)
1944 void *arg;
1945{
1946#ifndef COM_MULTIPORT
1947 COM_LOCK();
1948 siointr1((struct com_s *) arg);
1949 COM_UNLOCK();
1950#else /* COM_MULTIPORT */
1951 bool_t possibly_more_intrs;
1952 int unit;
1953 struct com_s *com;
1954
1955 /*
1956 * Loop until there is no activity on any port. This is necessary
1957 * to get an interrupt edge more than to avoid another interrupt.
1958 * If the IRQ signal is just an OR of the IRQ signals from several
1959 * devices, then the edge from one may be lost because another is
1960 * on.
1961 */
1962 COM_LOCK();
1963 do {
1964 possibly_more_intrs = FALSE;
1965 for (unit = 0; unit < sio_numunits; ++unit) {
1966 com = com_addr(unit);
1967 /*
1968 * XXX COM_LOCK();
1969 * would it work here, or be counter-productive?
1970 */
1971 if (com != NULL
1972 && !com->gone
1973 && (inb(com->int_id_port) & IIR_IMASK)
1974 != IIR_NOPEND) {
1975 siointr1(com);
1976 possibly_more_intrs = TRUE;
1977 }
1978 /* XXX COM_UNLOCK(); */
1979 }
1980 } while (possibly_more_intrs);
1981 COM_UNLOCK();
1982#endif /* COM_MULTIPORT */
1983}
1984
1985static void
1986siointr1(com)
1987 struct com_s *com;
1988{
1989 u_char line_status;
1990 u_char modem_status;
1991 u_char *ioptr;
1992 u_char recv_data;
1993 u_char int_ctl;
1994 u_char int_ctl_new;
1995 struct timecounter *tc;
1996 u_int count;
1997
1998 int_ctl = inb(com->intr_ctl_port);
1999 int_ctl_new = int_ctl;
2000
2001 while (!com->gone) {
2002 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2003 modem_status = inb(com->modem_status_port);
2004 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2005 tc = timecounter;
2006 count = tc->tc_get_timecount(tc);
2007 pps_event(&com->pps, tc, count,
2008 (modem_status & MSR_DCD) ?
2009 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2010 }
2011 }
2012 line_status = inb(com->line_status_port);
2013
2014 /* input event? (check first to help avoid overruns) */
2015 while (line_status & LSR_RCV_MASK) {
2016 /* break/unnattached error bits or real input? */
2017 if (!(line_status & LSR_RXRDY))
2018 recv_data = 0;
2019 else
2020 recv_data = inb(com->data_port);
2021#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
2022 /*
2023 * Solaris implements a new BREAK which is initiated
2024 * by a character sequence CR ~ ^b which is similar
2025 * to a familiar pattern used on Sun servers by the
2026 * Remote Console.
2027 */
2028#define KEY_CRTLB 2 /* ^B */
2029#define KEY_CR 13 /* CR '\r' */
2030#define KEY_TILDE 126 /* ~ */
2031
2032 if (com->unit == comconsole) {
2033 static int brk_state1 = 0, brk_state2 = 0;
2034 if (recv_data == KEY_CR) {
2035 brk_state1 = recv_data;
2036 brk_state2 = 0;
2037 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) {
2038 if (recv_data == KEY_TILDE)
2039 brk_state2 = recv_data;
2040 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) {
2041 breakpoint();
2042 brk_state1 = brk_state2 = 0;
2043 goto cont;
2044 } else
2045 brk_state2 = 0;
2046 } else
2047 brk_state1 = 0;
2048 }
2049#endif
2050 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2051 /*
2052 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2053 * Otherwise, push the work to a higher level
2054 * (to handle PARMRK) if we're bypassing.
2055 * Otherwise, convert BI/FE and PE+INPCK to 0.
2056 *
2057 * This makes bypassing work right in the
2058 * usual "raw" case (IGNBRK set, and IGNPAR
2059 * and INPCK clear).
2060 *
2061 * Note: BI together with FE/PE means just BI.
2062 */
2063 if (line_status & LSR_BI) {
2064#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2065 if (com->unit == comconsole) {
2066 breakpoint();
2067 goto cont;
2068 }
2069#endif
2070 if (com->tp == NULL
2071 || com->tp->t_iflag & IGNBRK)
2072 goto cont;
2073 } else {
2074 if (com->tp == NULL
2075 || com->tp->t_iflag & IGNPAR)
2076 goto cont;
2077 }
2078 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2079 && (line_status & (LSR_BI | LSR_FE)
2080 || com->tp->t_iflag & INPCK))
2081 recv_data = 0;
2082 }
2083 ++com->bytes_in;
2084 if (com->hotchar != 0 && recv_data == com->hotchar)
2085 setsofttty();
2086 ioptr = com->iptr;
2087 if (ioptr >= com->ibufend)
2088 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2089 else {
2090 if (com->do_timestamp)
2091 microtime(&com->timestamp);
2092 ++com_events;
2093 schedsofttty();
2094#if 0 /* for testing input latency vs efficiency */
2095if (com->iptr - com->ibuf == 8)
2096 setsofttty();
2097#endif
2098 ioptr[0] = recv_data;
2099 ioptr[com->ierroff] = line_status;
2100 com->iptr = ++ioptr;
2101 if (ioptr == com->ihighwater
2102 && com->state & CS_RTS_IFLOW)
2103 outb(com->modem_ctl_port,
2104 com->mcr_image &= ~MCR_RTS);
2105 if (line_status & LSR_OE)
2106 CE_RECORD(com, CE_OVERRUN);
2107 }
2108cont:
2109 /*
2110 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2111 * jump from the top of the loop to here
2112 */
2113 line_status = inb(com->line_status_port) & 0x7F;
2114 }
2115
2116 /* modem status change? (always check before doing output) */
2117 modem_status = inb(com->modem_status_port);
2118 if (modem_status != com->last_modem_status) {
2119 if (com->do_dcd_timestamp
2120 && !(com->last_modem_status & MSR_DCD)
2121 && modem_status & MSR_DCD)
2122 microtime(&com->dcd_timestamp);
2123
2124 /*
2125 * Schedule high level to handle DCD changes. Note
2126 * that we don't use the delta bits anywhere. Some
2127 * UARTs mess them up, and it's easy to remember the
2128 * previous bits and calculate the delta.
2129 */
2130 com->last_modem_status = modem_status;
2131 if (!(com->state & CS_CHECKMSR)) {
2132 com_events += LOTS_OF_EVENTS;
2133 com->state |= CS_CHECKMSR;
2134 setsofttty();
2135 }
2136
2137 /* handle CTS change immediately for crisp flow ctl */
2138 if (com->state & CS_CTS_OFLOW) {
2139 if (modem_status & MSR_CTS)
2140 com->state |= CS_ODEVREADY;
2141 else
2142 com->state &= ~CS_ODEVREADY;
2143 }
2144 }
2145
2146 /* output queued and everything ready? */
2147 if (line_status & LSR_TXRDY
2148 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2149 ioptr = com->obufq.l_head;
2150 if (com->tx_fifo_size > 1) {
2151 u_int ocount;
2152
2153 ocount = com->obufq.l_tail - ioptr;
2154 if (ocount > com->tx_fifo_size)
2155 ocount = com->tx_fifo_size;
2156 com->bytes_out += ocount;
2157 do
2158 outb(com->data_port, *ioptr++);
2159 while (--ocount != 0);
2160 } else {
2161 outb(com->data_port, *ioptr++);
2162 ++com->bytes_out;
2163 }
2164 com->obufq.l_head = ioptr;
2165 if (COM_IIR_TXRDYBUG(com->flags)) {
2166 int_ctl_new = int_ctl | IER_ETXRDY;
2167 }
2168 if (ioptr >= com->obufq.l_tail) {
2169 struct lbq *qp;
2170
2171 qp = com->obufq.l_next;
2172 qp->l_queued = FALSE;
2173 qp = qp->l_next;
2174 if (qp != NULL) {
2175 com->obufq.l_head = qp->l_head;
2176 com->obufq.l_tail = qp->l_tail;
2177 com->obufq.l_next = qp;
2178 } else {
2179 /* output just completed */
2180 if (COM_IIR_TXRDYBUG(com->flags)) {
2181 int_ctl_new = int_ctl & ~IER_ETXRDY;
2182 }
2183 com->state &= ~CS_BUSY;
2184 }
2185 if (!(com->state & CS_ODONE)) {
2186 com_events += LOTS_OF_EVENTS;
2187 com->state |= CS_ODONE;
2188 setsofttty(); /* handle at high level ASAP */
2189 }
2190 }
2191 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2192 outb(com->intr_ctl_port, int_ctl_new);
2193 }
2194 }
2195
2196 /* finished? */
2197#ifndef COM_MULTIPORT
2198 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2199#endif /* COM_MULTIPORT */
2200 return;
2201 }
2202}
2203
2204static int
2205sioioctl(dev, cmd, data, flag, p)
2206 dev_t dev;
2207 u_long cmd;
2208 caddr_t data;
2209 int flag;
2210 struct proc *p;
2211{
2212 struct com_s *com;
2213 int error;
2214 int mynor;
2215 int s;
2216 struct tty *tp;
2217#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2218 u_long oldcmd;
2219 struct termios term;
2220#endif
2221
2222 mynor = minor(dev);
2223 com = com_addr(MINOR_TO_UNIT(mynor));
2224 if (com == NULL || com->gone)
2225 return (ENODEV);
2226 if (mynor & CONTROL_MASK) {
2227 struct termios *ct;
2228
2229 switch (mynor & CONTROL_MASK) {
2230 case CONTROL_INIT_STATE:
2231 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2232 break;
2233 case CONTROL_LOCK_STATE:
2234 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2235 break;
2236 default:
2237 return (ENODEV); /* /dev/nodev */
2238 }
2239 switch (cmd) {
2240 case TIOCSETA:
2241 error = suser(p);
2242 if (error != 0)
2243 return (error);
2244 *ct = *(struct termios *)data;
2245 return (0);
2246 case TIOCGETA:
2247 *(struct termios *)data = *ct;
2248 return (0);
2249 case TIOCGETD:
2250 *(int *)data = TTYDISC;
2251 return (0);
2252 case TIOCGWINSZ:
2253 bzero(data, sizeof(struct winsize));
2254 return (0);
2255 default:
2256 return (ENOTTY);
2257 }
2258 }
2259 tp = com->tp;
2260#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2261 term = tp->t_termios;
2262 oldcmd = cmd;
2263 error = ttsetcompat(tp, &cmd, data, &term);
2264 if (error != 0)
2265 return (error);
2266 if (cmd != oldcmd)
2267 data = (caddr_t)&term;
2268#endif
2269 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2270 int cc;
2271 struct termios *dt = (struct termios *)data;
2272 struct termios *lt = mynor & CALLOUT_MASK
2273 ? &com->lt_out : &com->lt_in;
2274
2275 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2276 | (dt->c_iflag & ~lt->c_iflag);
2277 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2278 | (dt->c_oflag & ~lt->c_oflag);
2279 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2280 | (dt->c_cflag & ~lt->c_cflag);
2281 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2282 | (dt->c_lflag & ~lt->c_lflag);
2283 for (cc = 0; cc < NCCS; ++cc)
2284 if (lt->c_cc[cc] != 0)
2285 dt->c_cc[cc] = tp->t_cc[cc];
2286 if (lt->c_ispeed != 0)
2287 dt->c_ispeed = tp->t_ispeed;
2288 if (lt->c_ospeed != 0)
2289 dt->c_ospeed = tp->t_ospeed;
2290 }
2291 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2292 if (error != ENOIOCTL)
2293 return (error);
2294 s = spltty();
2295 error = ttioctl(tp, cmd, data, flag);
2296 disc_optim(tp, &tp->t_termios, com);
2297 if (error != ENOIOCTL) {
2298 splx(s);
2299 return (error);
2300 }
2301 switch (cmd) {
2302 case TIOCSBRK:
2303 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2304 break;
2305 case TIOCCBRK:
2306 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2307 break;
2308 case TIOCSDTR:
2309 (void)commctl(com, TIOCM_DTR, DMBIS);
2310 break;
2311 case TIOCCDTR:
2312 (void)commctl(com, TIOCM_DTR, DMBIC);
2313 break;
2314 /*
2315 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2316 * changes get undone on the next call to comparam().
2317 */
2318 case TIOCMSET:
2319 (void)commctl(com, *(int *)data, DMSET);
2320 break;
2321 case TIOCMBIS:
2322 (void)commctl(com, *(int *)data, DMBIS);
2323 break;
2324 case TIOCMBIC:
2325 (void)commctl(com, *(int *)data, DMBIC);
2326 break;
2327 case TIOCMGET:
2328 *(int *)data = commctl(com, 0, DMGET);
2329 break;
2330 case TIOCMSDTRWAIT:
2331 /* must be root since the wait applies to following logins */
2332 error = suser(p);
2333 if (error != 0) {
2334 splx(s);
2335 return (error);
2336 }
2337 com->dtr_wait = *(int *)data * hz / 100;
2338 break;
2339 case TIOCMGDTRWAIT:
2340 *(int *)data = com->dtr_wait * 100 / hz;
2341 break;
2342 case TIOCTIMESTAMP:
2343 com->do_timestamp = TRUE;
2344 *(struct timeval *)data = com->timestamp;
2345 break;
2346 case TIOCDCDTIMESTAMP:
2347 com->do_dcd_timestamp = TRUE;
2348 *(struct timeval *)data = com->dcd_timestamp;
2349 break;
2350 default:
2351 splx(s);
2352 error = pps_ioctl(cmd, data, &com->pps);
2353 if (error == ENODEV)
2354 error = ENOTTY;
2355 return (error);
2356 }
2357 splx(s);
2358 return (0);
2359}
2360
2361static void
2362siopoll()
2363{
2364 int unit;
2365
2366 if (com_events == 0)
2367 return;
2368repeat:
2369 for (unit = 0; unit < sio_numunits; ++unit) {
2370 struct com_s *com;
2371 int incc;
2372 struct tty *tp;
2373
2374 com = com_addr(unit);
2375 if (com == NULL)
2376 continue;
2377 tp = com->tp;
2378 if (tp == NULL || com->gone) {
2379 /*
2380 * Discard any events related to never-opened or
2381 * going-away devices.
2382 */
2383 disable_intr();
2384 incc = com->iptr - com->ibuf;
2385 com->iptr = com->ibuf;
2386 if (com->state & CS_CHECKMSR) {
2387 incc += LOTS_OF_EVENTS;
2388 com->state &= ~CS_CHECKMSR;
2389 }
2390 com_events -= incc;
2391 enable_intr();
2392 continue;
2393 }
2394 if (com->iptr != com->ibuf) {
2395 disable_intr();
2396 sioinput(com);
2397 enable_intr();
2398 }
2399 if (com->state & CS_CHECKMSR) {
2400 u_char delta_modem_status;
2401
2402 disable_intr();
2403 delta_modem_status = com->last_modem_status
2404 ^ com->prev_modem_status;
2405 com->prev_modem_status = com->last_modem_status;
2406 com_events -= LOTS_OF_EVENTS;
2407 com->state &= ~CS_CHECKMSR;
2408 enable_intr();
2409 if (delta_modem_status & MSR_DCD)
2410 (*linesw[tp->t_line].l_modem)
2411 (tp, com->prev_modem_status & MSR_DCD);
2412 }
2413 if (com->state & CS_ODONE) {
2414 disable_intr();
2415 com_events -= LOTS_OF_EVENTS;
2416 com->state &= ~CS_ODONE;
2417 enable_intr();
2418 if (!(com->state & CS_BUSY)
2419 && !(com->extra_state & CSE_BUSYCHECK)) {
2420 timeout(siobusycheck, com, hz / 100);
2421 com->extra_state |= CSE_BUSYCHECK;
2422 }
2423 (*linesw[tp->t_line].l_start)(tp);
2424 }
2425 if (com_events == 0)
2426 break;
2427 }
2428 if (com_events >= LOTS_OF_EVENTS)
2429 goto repeat;
2430}
2431
2432static int
2433comparam(tp, t)
2434 struct tty *tp;
2435 struct termios *t;
2436{
2437 u_int cfcr;
2438 int cflag;
2439 struct com_s *com;
2440 u_int divisor;
2441 u_char dlbh;
2442 u_char dlbl;
2443 int s;
2444 int unit;
2445
2446 unit = DEV_TO_UNIT(tp->t_dev);
2447 com = com_addr(unit);
2448 if (com == NULL)
2449 return (ENODEV);
2450
2451 /* do historical conversions */
2452 if (t->c_ispeed == 0)
2453 t->c_ispeed = t->c_ospeed;
2454
2455 /* check requested parameters */
2456 if (t->c_ospeed == 0)
2457 divisor = 0;
2458 else {
2459 if (t->c_ispeed != t->c_ospeed)
2460 return (EINVAL);
2461 divisor = siodivisor(com->rclk, t->c_ispeed);
2462 if (divisor == 0)
2463 return (EINVAL);
2464 }
2465
2466 /* parameters are OK, convert them to the com struct and the device */
2467 s = spltty();
2468 if (divisor == 0)
2469 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2470 else
2471 (void)commctl(com, TIOCM_DTR, DMBIS);
2472 cflag = t->c_cflag;
2473 switch (cflag & CSIZE) {
2474 case CS5:
2475 cfcr = CFCR_5BITS;
2476 break;
2477 case CS6:
2478 cfcr = CFCR_6BITS;
2479 break;
2480 case CS7:
2481 cfcr = CFCR_7BITS;
2482 break;
2483 default:
2484 cfcr = CFCR_8BITS;
2485 break;
2486 }
2487 if (cflag & PARENB) {
2488 cfcr |= CFCR_PENAB;
2489 if (!(cflag & PARODD))
2490 cfcr |= CFCR_PEVEN;
2491 }
2492 if (cflag & CSTOPB)
2493 cfcr |= CFCR_STOPB;
2494
2495 if (com->hasfifo && divisor != 0) {
2496 /*
2497 * Use a fifo trigger level low enough so that the input
2498 * latency from the fifo is less than about 16 msec and
2499 * the total latency is less than about 30 msec. These
2500 * latencies are reasonable for humans. Serial comms
2501 * protocols shouldn't expect anything better since modem
2502 * latencies are larger.
2503 *
2504 * Interrupts can be held up for long periods of time
2505 * due to inefficiencies in other parts of the kernel,
2506 * certain video cards, etc. Setting the FIFO trigger
2507 * point to MEDH instead of HIGH gives us 694uS of slop
2508 * (8 character times) instead of 173uS (2 character times)
2509 * @ 115200 bps.
2510 */
2511 com->fifo_image = t->c_ospeed <= 4800
2512 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2513#ifdef COM_ESP
2514 /*
2515 * The Hayes ESP card needs the fifo DMA mode bit set
2516 * in compatibility mode. If not, it will interrupt
2517 * for each character received.
2518 */
2519 if (com->esp)
2520 com->fifo_image |= FIFO_DMA_MODE;
2521#endif
2522 sio_setreg(com, com_fifo, com->fifo_image);
2523 }
2524
2525 /*
2526 * This returns with interrupts disabled so that we can complete
2527 * the speed change atomically. Keeping interrupts disabled is
2528 * especially important while com_data is hidden.
2529 */
2530 (void) siosetwater(com, t->c_ispeed);
2531
2532 if (divisor != 0) {
2533 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2534 /*
2535 * Only set the divisor registers if they would change,
2536 * since on some 16550 incompatibles (UMC8669F), setting
2537 * them while input is arriving them loses sync until
2538 * data stops arriving.
2539 */
2540 dlbl = divisor & 0xFF;
2541 if (sio_getreg(com, com_dlbl) != dlbl)
2542 sio_setreg(com, com_dlbl, dlbl);
2543 dlbh = divisor >> 8;
2544 if (sio_getreg(com, com_dlbh) != dlbh)
2545 sio_setreg(com, com_dlbh, dlbh);
2546 }
2547
2548 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2549
2550 if (!(tp->t_state & TS_TTSTOP))
2551 com->state |= CS_TTGO;
2552
2553 if (cflag & CRTS_IFLOW) {
2554 if (com->st16650a) {
2555 sio_setreg(com, com_cfcr, 0xbf);
2556 sio_setreg(com, com_fifo,
2557 sio_getreg(com, com_fifo) | 0x40);
2558 }
2559 com->state |= CS_RTS_IFLOW;
2560 /*
2561 * If CS_RTS_IFLOW just changed from off to on, the change
2562 * needs to be propagated to MCR_RTS. This isn't urgent,
2563 * so do it later by calling comstart() instead of repeating
2564 * a lot of code from comstart() here.
2565 */
2566 } else if (com->state & CS_RTS_IFLOW) {
2567 com->state &= ~CS_RTS_IFLOW;
2568 /*
2569 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2570 * on here, since comstart() won't do it later.
2571 */
2572 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2573 if (com->st16650a) {
2574 sio_setreg(com, com_cfcr, 0xbf);
2575 sio_setreg(com, com_fifo,
2576 sio_getreg(com, com_fifo) & ~0x40);
2577 }
2578 }
2579
2580
2581 /*
2582 * Set up state to handle output flow control.
2583 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2584 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2585 */
2586 com->state |= CS_ODEVREADY;
2587 com->state &= ~CS_CTS_OFLOW;
2588 if (cflag & CCTS_OFLOW) {
2589 com->state |= CS_CTS_OFLOW;
2590 if (!(com->last_modem_status & MSR_CTS))
2591 com->state &= ~CS_ODEVREADY;
2592 if (com->st16650a) {
2593 sio_setreg(com, com_cfcr, 0xbf);
2594 sio_setreg(com, com_fifo,
2595 sio_getreg(com, com_fifo) | 0x80);
2596 }
2597 } else {
2598 if (com->st16650a) {
2599 sio_setreg(com, com_cfcr, 0xbf);
2600 sio_setreg(com, com_fifo,
2601 sio_getreg(com, com_fifo) & ~0x80);
2602 }
2603 }
2604
2605 sio_setreg(com, com_cfcr, com->cfcr_image);
2606
2607 /* XXX shouldn't call functions while intrs are disabled. */
2608 disc_optim(tp, t, com);
2609 /*
2610 * Recover from fiddling with CS_TTGO. We used to call siointr1()
2611 * unconditionally, but that defeated the careful discarding of
2612 * stale input in sioopen().
2613 */
2614 if (com->state >= (CS_BUSY | CS_TTGO))
2615 siointr1(com);
2616
2617 enable_intr();
2618 splx(s);
2619 comstart(tp);
2620 if (com->ibufold != NULL) {
2621 free(com->ibufold, M_DEVBUF);
2622 com->ibufold = NULL;
2623 }
2624 return (0);
2625}
2626
2627static int
2628siosetwater(com, speed)
2629 struct com_s *com;
2630 speed_t speed;
2631{
2632 int cp4ticks;
2633 u_char *ibuf;
2634 int ibufsize;
2635 struct tty *tp;
2636
2637 /*
2638 * Make the buffer size large enough to handle a softtty interrupt
2639 * latency of about 2 ticks without loss of throughput or data
2640 * (about 3 ticks if input flow control is not used or not honoured,
2641 * but a bit less for CS5-CS7 modes).
2642 */
2643 cp4ticks = speed / 10 / hz * 4;
2644 for (ibufsize = 128; ibufsize < cp4ticks;)
2645 ibufsize <<= 1;
2646 if (ibufsize == com->ibufsize) {
2647 disable_intr();
2648 return (0);
2649 }
2650
2651 /*
2652 * Allocate input buffer. The extra factor of 2 in the size is
2653 * to allow for an error byte for each input byte.
2654 */
2655 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2656 if (ibuf == NULL) {
2657 disable_intr();
2658 return (ENOMEM);
2659 }
2660
2661 /* Initialize non-critical variables. */
2662 com->ibufold = com->ibuf;
2663 com->ibufsize = ibufsize;
2664 tp = com->tp;
2665 if (tp != NULL) {
2666 tp->t_ififosize = 2 * ibufsize;
2667 tp->t_ispeedwat = (speed_t)-1;
2668 tp->t_ospeedwat = (speed_t)-1;
2669 }
2670
2671 /*
2672 * Read current input buffer, if any. Continue with interrupts
2673 * disabled.
2674 */
2675 disable_intr();
2676 if (com->iptr != com->ibuf)
2677 sioinput(com);
2678
2679 /*-
2680 * Initialize critical variables, including input buffer watermarks.
2681 * The external device is asked to stop sending when the buffer
2682 * exactly reaches high water, or when the high level requests it.
2683 * The high level is notified immediately (rather than at a later
2684 * clock tick) when this watermark is reached.
2685 * The buffer size is chosen so the watermark should almost never
2686 * be reached.
2687 * The low watermark is invisibly 0 since the buffer is always
2688 * emptied all at once.
2689 */
2690 com->iptr = com->ibuf = ibuf;
2691 com->ibufend = ibuf + ibufsize;
2692 com->ierroff = ibufsize;
2693 com->ihighwater = ibuf + 3 * ibufsize / 4;
2694 return (0);
2695}
2696
2697static void
2698comstart(tp)
2699 struct tty *tp;
2700{
2701 struct com_s *com;
2702 int s;
2703 int unit;
2704
2705 unit = DEV_TO_UNIT(tp->t_dev);
2706 com = com_addr(unit);
2707 if (com == NULL)
2708 return;
2709 s = spltty();
2710 disable_intr();
2711 if (tp->t_state & TS_TTSTOP)
2712 com->state &= ~CS_TTGO;
2713 else
2714 com->state |= CS_TTGO;
2715 if (tp->t_state & TS_TBLOCK) {
2716 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2717 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2718 } else {
2719 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2720 && com->state & CS_RTS_IFLOW)
2721 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2722 }
2723 enable_intr();
2724 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2725 ttwwakeup(tp);
2726 splx(s);
2727 return;
2728 }
2729 if (tp->t_outq.c_cc != 0) {
2730 struct lbq *qp;
2731 struct lbq *next;
2732
2733 if (!com->obufs[0].l_queued) {
2734 com->obufs[0].l_tail
2735 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2736 sizeof com->obuf1);
2737 com->obufs[0].l_next = NULL;
2738 com->obufs[0].l_queued = TRUE;
2739 disable_intr();
2740 if (com->state & CS_BUSY) {
2741 qp = com->obufq.l_next;
2742 while ((next = qp->l_next) != NULL)
2743 qp = next;
2744 qp->l_next = &com->obufs[0];
2745 } else {
2746 com->obufq.l_head = com->obufs[0].l_head;
2747 com->obufq.l_tail = com->obufs[0].l_tail;
2748 com->obufq.l_next = &com->obufs[0];
2749 com->state |= CS_BUSY;
2750 }
2751 enable_intr();
2752 }
2753 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2754 com->obufs[1].l_tail
2755 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2756 sizeof com->obuf2);
2757 com->obufs[1].l_next = NULL;
2758 com->obufs[1].l_queued = TRUE;
2759 disable_intr();
2760 if (com->state & CS_BUSY) {
2761 qp = com->obufq.l_next;
2762 while ((next = qp->l_next) != NULL)
2763 qp = next;
2764 qp->l_next = &com->obufs[1];
2765 } else {
2766 com->obufq.l_head = com->obufs[1].l_head;
2767 com->obufq.l_tail = com->obufs[1].l_tail;
2768 com->obufq.l_next = &com->obufs[1];
2769 com->state |= CS_BUSY;
2770 }
2771 enable_intr();
2772 }
2773 tp->t_state |= TS_BUSY;
2774 }
2775 disable_intr();
2776 if (com->state >= (CS_BUSY | CS_TTGO))
2777 siointr1(com); /* fake interrupt to start output */
2778 enable_intr();
2779 ttwwakeup(tp);
2780 splx(s);
2781}
2782
2783static void
2784comstop(tp, rw)
2785 struct tty *tp;
2786 int rw;
2787{
2788 struct com_s *com;
2789
2790 com = com_addr(DEV_TO_UNIT(tp->t_dev));
2791 if (com == NULL || com->gone)
2792 return;
2793 disable_intr();
2794 if (rw & FWRITE) {
2795 if (com->hasfifo)
2796#ifdef COM_ESP
2797 /* XXX avoid h/w bug. */
2798 if (!com->esp)
2799#endif
2800 sio_setreg(com, com_fifo,
2801 FIFO_XMT_RST | com->fifo_image);
2802 com->obufs[0].l_queued = FALSE;
2803 com->obufs[1].l_queued = FALSE;
2804 if (com->state & CS_ODONE)
2805 com_events -= LOTS_OF_EVENTS;
2806 com->state &= ~(CS_ODONE | CS_BUSY);
2807 com->tp->t_state &= ~TS_BUSY;
2808 }
2809 if (rw & FREAD) {
2810 if (com->hasfifo)
2811#ifdef COM_ESP
2812 /* XXX avoid h/w bug. */
2813 if (!com->esp)
2814#endif
2815 sio_setreg(com, com_fifo,
2816 FIFO_RCV_RST | com->fifo_image);
2817 com_events -= (com->iptr - com->ibuf);
2818 com->iptr = com->ibuf;
2819 }
2820 enable_intr();
2821 comstart(tp);
2822}
2823
2824static int
2825commctl(com, bits, how)
2826 struct com_s *com;
2827 int bits;
2828 int how;
2829{
2830 int mcr;
2831 int msr;
2832
2833 if (how == DMGET) {
2834 bits = TIOCM_LE; /* XXX - always enabled while open */
2835 mcr = com->mcr_image;
2836 if (mcr & MCR_DTR)
2837 bits |= TIOCM_DTR;
2838 if (mcr & MCR_RTS)
2839 bits |= TIOCM_RTS;
2840 msr = com->prev_modem_status;
2841 if (msr & MSR_CTS)
2842 bits |= TIOCM_CTS;
2843 if (msr & MSR_DCD)
2844 bits |= TIOCM_CD;
2845 if (msr & MSR_DSR)
2846 bits |= TIOCM_DSR;
2847 /*
2848 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2849 * more volatile by reading the modem status a lot. Perhaps
2850 * we should latch both bits until the status is read here.
2851 */
2852 if (msr & (MSR_RI | MSR_TERI))
2853 bits |= TIOCM_RI;
2854 return (bits);
2855 }
2856 mcr = 0;
2857 if (bits & TIOCM_DTR)
2858 mcr |= MCR_DTR;
2859 if (bits & TIOCM_RTS)
2860 mcr |= MCR_RTS;
2861 if (com->gone)
2862 return(0);
2863 disable_intr();
2864 switch (how) {
2865 case DMSET:
2866 outb(com->modem_ctl_port,
2867 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2868 break;
2869 case DMBIS:
2870 outb(com->modem_ctl_port, com->mcr_image |= mcr);
2871 break;
2872 case DMBIC:
2873 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2874 break;
2875 }
2876 enable_intr();
2877 return (0);
2878}
2879
2880static void
2881siosettimeout()
2882{
2883 struct com_s *com;
2884 bool_t someopen;
2885 int unit;
2886
2887 /*
2888 * Set our timeout period to 1 second if no polled devices are open.
2889 * Otherwise set it to max(1/200, 1/hz).
2890 * Enable timeouts iff some device is open.
2891 */
2892 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2893 sio_timeout = hz;
2894 someopen = FALSE;
2895 for (unit = 0; unit < sio_numunits; ++unit) {
2896 com = com_addr(unit);
2897 if (com != NULL && com->tp != NULL
2898 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2899 someopen = TRUE;
2900 if (com->poll || com->poll_output) {
2901 sio_timeout = hz > 200 ? hz / 200 : 1;
2902 break;
2903 }
2904 }
2905 }
2906 if (someopen) {
2907 sio_timeouts_until_log = hz / sio_timeout;
2908 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2909 sio_timeout);
2910 } else {
2911 /* Flush error messages, if any. */
2912 sio_timeouts_until_log = 1;
2913 comwakeup((void *)NULL);
2914 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2915 }
2916}
2917
2918static void
2919comwakeup(chan)
2920 void *chan;
2921{
2922 struct com_s *com;
2923 int unit;
2924
2925 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2926
2927 /*
2928 * Recover from lost output interrupts.
2929 * Poll any lines that don't use interrupts.
2930 */
2931 for (unit = 0; unit < sio_numunits; ++unit) {
2932 com = com_addr(unit);
2933 if (com != NULL && !com->gone
2934 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2935 disable_intr();
2936 siointr1(com);
2937 enable_intr();
2938 }
2939 }
2940
2941 /*
2942 * Check for and log errors, but not too often.
2943 */
2944 if (--sio_timeouts_until_log > 0)
2945 return;
2946 sio_timeouts_until_log = hz / sio_timeout;
2947 for (unit = 0; unit < sio_numunits; ++unit) {
2948 int errnum;
2949
2950 com = com_addr(unit);
2951 if (com == NULL)
2952 continue;
2953 if (com->gone)
2954 continue;
2955 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2956 u_int delta;
2957 u_long total;
2958
2959 disable_intr();
2960 delta = com->delta_error_counts[errnum];
2961 com->delta_error_counts[errnum] = 0;
2962 enable_intr();
2963 if (delta == 0)
2964 continue;
2965 total = com->error_counts[errnum] += delta;
2966 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2967 unit, delta, error_desc[errnum],
2968 delta == 1 ? "" : "s", total);
2969 }
2970 }
2971}
2972
2973static void
2974disc_optim(tp, t, com)
2975 struct tty *tp;
2976 struct termios *t;
2977 struct com_s *com;
2978{
2979 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2980 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2981 && (!(t->c_iflag & PARMRK)
2982 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2983 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2984 && linesw[tp->t_line].l_rint == ttyinput)
2985 tp->t_state |= TS_CAN_BYPASS_L_RINT;
2986 else
2987 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2988 com->hotchar = linesw[tp->t_line].l_hotchar;
2989}
2990
2991/*
2992 * Following are all routines needed for SIO to act as console
2993 */
2994#include <sys/cons.h>
2995
2996struct siocnstate {
2997 u_char dlbl;
2998 u_char dlbh;
2999 u_char ier;
3000 u_char cfcr;
3001 u_char mcr;
3002};
3003
3004static speed_t siocngetspeed __P((Port_t, u_long rclk));
3005static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
3006static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
3007static void siocntxwait __P((Port_t iobase));
3008
3009static cn_probe_t siocnprobe;
3010static cn_init_t siocninit;
3011static cn_checkc_t siocncheckc;
3012static cn_getc_t siocngetc;
3013static cn_putc_t siocnputc;
3014
3015#ifdef __i386__
3016CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc,
3017 siocnputc, NULL);
3018#endif
3019
3020/* To get the GDB related variables */
3021#if DDB > 0
3022#include <ddb/ddb.h>
3023#endif
3024
3025static void
3026siocntxwait(iobase)
3027 Port_t iobase;
3028{
3029 int timo;
3030
3031 /*
3032 * Wait for any pending transmission to finish. Required to avoid
3033 * the UART lockup bug when the speed is changed, and for normal
3034 * transmits.
3035 */
3036 timo = 100000;
3037 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3038 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3039 ;
3040}
3041
3042/*
3043 * Read the serial port specified and try to figure out what speed
3044 * it's currently running at. We're assuming the serial port has
3045 * been initialized and is basicly idle. This routine is only intended
3046 * to be run at system startup.
3047 *
3048 * If the value read from the serial port doesn't make sense, return 0.
3049 */
3050
3051static speed_t
3052siocngetspeed(iobase, rclk)
3053 Port_t iobase;
3054 u_long rclk;
3055{
3056 u_int divisor;
3057 u_char dlbh;
3058 u_char dlbl;
3059 u_char cfcr;
3060
3061 cfcr = inb(iobase + com_cfcr);
3062 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3063
3064 dlbl = inb(iobase + com_dlbl);
3065 dlbh = inb(iobase + com_dlbh);
3066
3067 outb(iobase + com_cfcr, cfcr);
3068
3069 divisor = dlbh << 8 | dlbl;
3070
3071 /* XXX there should be more sanity checking. */
3072 if (divisor == 0)
3073 return (CONSPEED);
3074 return (rclk / (16UL * divisor));
3075}
3076
3077static void
3078siocnopen(sp, iobase, speed)
3079 struct siocnstate *sp;
3080 Port_t iobase;
3081 int speed;
3082{
3083 u_int divisor;
3084 u_char dlbh;
3085 u_char dlbl;
3086
3087 /*
3088 * Save all the device control registers except the fifo register
3089 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3090 * We can't save the fifo register since it is read-only.
3091 */
3092 sp->ier = inb(iobase + com_ier);
3093 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3094 siocntxwait(iobase);
3095 sp->cfcr = inb(iobase + com_cfcr);
3096 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3097 sp->dlbl = inb(iobase + com_dlbl);
3098 sp->dlbh = inb(iobase + com_dlbh);
3099 /*
3100 * Only set the divisor registers if they would change, since on
3101 * some 16550 incompatibles (Startech), setting them clears the
3102 * data input register. This also reduces the effects of the
3103 * UMC8669F bug.
3104 */
3105 divisor = siodivisor(comdefaultrclk, speed);
3106 dlbl = divisor & 0xFF;
3107 if (sp->dlbl != dlbl)
3108 outb(iobase + com_dlbl, dlbl);
3109 dlbh = divisor >> 8;
3110 if (sp->dlbh != dlbh)
3111 outb(iobase + com_dlbh, dlbh);
3112 outb(iobase + com_cfcr, CFCR_8BITS);
3113 sp->mcr = inb(iobase + com_mcr);
3114 /*
3115 * We don't want interrupts, but must be careful not to "disable"
3116 * them by clearing the MCR_IENABLE bit, since that might cause
3117 * an interrupt by floating the IRQ line.
3118 */
3119 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3120}
3121
3122static void
3123siocnclose(sp, iobase)
3124 struct siocnstate *sp;
3125 Port_t iobase;
3126{
3127 /*
3128 * Restore the device control registers.
3129 */
3130 siocntxwait(iobase);
3131 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3132 if (sp->dlbl != inb(iobase + com_dlbl))
3133 outb(iobase + com_dlbl, sp->dlbl);
3134 if (sp->dlbh != inb(iobase + com_dlbh))
3135 outb(iobase + com_dlbh, sp->dlbh);
3136 outb(iobase + com_cfcr, sp->cfcr);
3137 /*
3138 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3139 */
3140 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3141 outb(iobase + com_ier, sp->ier);
3142}
3143
3144static void
3145siocnprobe(cp)
3146 struct consdev *cp;
3147{
3148 speed_t boot_speed;
3149 u_char cfcr;
3150 u_int divisor;
3151 int s, unit;
3152 struct siocnstate sp;
3153
3154 /*
3155 * Find our first enabled console, if any. If it is a high-level
3156 * console device, then initialize it and return successfully.
3157 * If it is a low-level console device, then initialize it and
3158 * return unsuccessfully. It must be initialized in both cases
3159 * for early use by console drivers and debuggers. Initializing
3160 * the hardware is not necessary in all cases, since the i/o
3161 * routines initialize it on the fly, but it is necessary if
3162 * input might arrive while the hardware is switched back to an
3163 * uninitialized state. We can't handle multiple console devices
3164 * yet because our low-level routines don't take a device arg.
3165 * We trust the user to set the console flags properly so that we
3166 * don't need to probe.
3167 */
3168 cp->cn_pri = CN_DEAD;
3169
3170 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
3171 int flags;
3172 int disabled;
3173 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
3174 if (disabled)
3175 continue;
3176 }
3177 if (resource_int_value("sio", unit, "flags", &flags))
3178 continue;
3179 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
3180 int port;
3181 Port_t iobase;
3182
3183 if (resource_int_value("sio", unit, "port", &port))
3184 continue;
3185 iobase = port;
3186 s = spltty();
3187 if (boothowto & RB_SERIAL) {
3188 boot_speed =
3189 siocngetspeed(iobase, comdefaultrclk);
3190 if (boot_speed)
3191 comdefaultrate = boot_speed;
3192 }
3193
3194 /*
3195 * Initialize the divisor latch. We can't rely on
3196 * siocnopen() to do this the first time, since it
3197 * avoids writing to the latch if the latch appears
3198 * to have the correct value. Also, if we didn't
3199 * just read the speed from the hardware, then we
3200 * need to set the speed in hardware so that
3201 * switching it later is null.
3202 */
3203 cfcr = inb(iobase + com_cfcr);
3204 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3205 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3206 outb(iobase + com_dlbl, divisor & 0xff);
3207 outb(iobase + com_dlbh, divisor >> 8);
3208 outb(iobase + com_cfcr, cfcr);
3209
3210 siocnopen(&sp, iobase, comdefaultrate);
3211
3212 splx(s);
3213 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
3214 cp->cn_dev = makedev(CDEV_MAJOR, unit);
3215 cp->cn_pri = COM_FORCECONSOLE(flags)
3216 || boothowto & RB_SERIAL
3217 ? CN_REMOTE : CN_NORMAL;
3218 siocniobase = iobase;
3219 siocnunit = unit;
3220 }
3221 if (COM_DEBUGGER(flags)) {
3222 printf("sio%d: gdb debugging port\n", unit);
3223 siogdbiobase = iobase;
3224 siogdbunit = unit;
3225#if DDB > 0
3226 gdbdev = makedev(CDEV_MAJOR, unit);
3227 gdb_getc = siocngetc;
3228 gdb_putc = siocnputc;
3229#endif
3230 }
3231 }
3232 }
3233#ifdef __i386__
3234#if DDB > 0
3235 /*
3236 * XXX Ugly Compatability.
3237 * If no gdb port has been specified, set it to be the console
3238 * as some configuration files don't specify the gdb port.
3239 */
3240 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
3241 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
3242 siocnunit);
3243 printf("Set flag 0x80 on desired GDB port in your\n");
3244 printf("configuration file (currently sio only).\n");
3245 siogdbiobase = siocniobase;
3246 siogdbunit = siocnunit;
3247 gdbdev = makedev(CDEV_MAJOR, siocnunit);
3248 gdb_getc = siocngetc;
3249 gdb_putc = siocnputc;
3250 }
3251#endif
3252#endif
3253}
3254
3255#ifdef __alpha__
3256
3257CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
3258
3259int
3260siocnattach(port, speed)
3261 int port;
3262 int speed;
3263{
3264 int s;
3265 u_char cfcr;
3266 u_int divisor;
3267 struct siocnstate sp;
3268
3269 siocniobase = port;
3270 comdefaultrate = speed;
3271 sio_consdev.cn_pri = CN_NORMAL;
3272 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
3273
3274 s = spltty();
3275
3276 /*
3277 * Initialize the divisor latch. We can't rely on
3278 * siocnopen() to do this the first time, since it
3279 * avoids writing to the latch if the latch appears
3280 * to have the correct value. Also, if we didn't
3281 * just read the speed from the hardware, then we
3282 * need to set the speed in hardware so that
3283 * switching it later is null.
3284 */
3285 cfcr = inb(siocniobase + com_cfcr);
3286 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
3287 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3288 outb(siocniobase + com_dlbl, divisor & 0xff);
3289 outb(siocniobase + com_dlbh, divisor >> 8);
3290 outb(siocniobase + com_cfcr, cfcr);
3291
3292 siocnopen(&sp, siocniobase, comdefaultrate);
3293 splx(s);
3294
3295 cn_tab = &sio_consdev;
3296 return (0);
3297}
3298
3299int
3300siogdbattach(port, speed)
3301 int port;
3302 int speed;
3303{
3304 int s;
3305 u_char cfcr;
3306 u_int divisor;
3307 struct siocnstate sp;
3308
3309 siogdbiobase = port;
3310 gdbdefaultrate = speed;
3311
3312 s = spltty();
3313
3314 /*
3315 * Initialize the divisor latch. We can't rely on
3316 * siocnopen() to do this the first time, since it
3317 * avoids writing to the latch if the latch appears
3318 * to have the correct value. Also, if we didn't
3319 * just read the speed from the hardware, then we
3320 * need to set the speed in hardware so that
3321 * switching it later is null.
3322 */
3323 cfcr = inb(siogdbiobase + com_cfcr);
3324 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3325 divisor = siodivisor(comdefaultrclk, gdbdefaultrate);
3326 outb(siogdbiobase + com_dlbl, divisor & 0xff);
3327 outb(siogdbiobase + com_dlbh, divisor >> 8);
3328 outb(siogdbiobase + com_cfcr, cfcr);
3329
3330 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3331 splx(s);
3332
3333 return (0);
3334}
3335
3336#endif
3337
3338static void
3339siocninit(cp)
3340 struct consdev *cp;
3341{
3342 comconsole = DEV_TO_UNIT(cp->cn_dev);
3343}
3344
3345static int
3346siocncheckc(dev)
3347 dev_t dev;
3348{
3349 int c;
3350 Port_t iobase;
3351 int s;
3352 struct siocnstate sp;
3353
3354 if (minor(dev) == siogdbunit)
3355 iobase = siogdbiobase;
3356 else
3357 iobase = siocniobase;
3358 s = spltty();
3359 siocnopen(&sp, iobase, comdefaultrate);
3360 if (inb(iobase + com_lsr) & LSR_RXRDY)
3361 c = inb(iobase + com_data);
3362 else
3363 c = -1;
3364 siocnclose(&sp, iobase);
3365 splx(s);
3366 return (c);
3367}
3368
3369
3370int
3371siocngetc(dev)
3372 dev_t dev;
3373{
3374 int c;
3375 Port_t iobase;
3376 int s;
3377 struct siocnstate sp;
3378
3379 if (minor(dev) == siogdbunit)
3380 iobase = siogdbiobase;
3381 else
3382 iobase = siocniobase;
3383 s = spltty();
3384 siocnopen(&sp, iobase, comdefaultrate);
3385 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3386 ;
3387 c = inb(iobase + com_data);
3388 siocnclose(&sp, iobase);
3389 splx(s);
3390 return (c);
3391}
3392
3393void
3394siocnputc(dev, c)
3395 dev_t dev;
3396 int c;
3397{
3398 int s;
3399 struct siocnstate sp;
3400 Port_t iobase;
3401
3402 if (minor(dev) == siogdbunit)
3403 iobase = siogdbiobase;
3404 else
3405 iobase = siocniobase;
3406 s = spltty();
3407 siocnopen(&sp, iobase, comdefaultrate);
3408 siocntxwait(iobase);
3409 outb(iobase + com_data, c);
3410 siocnclose(&sp, iobase);
3411 splx(s);
3412}
3413
3414#ifdef __alpha__
3415int
3416siogdbgetc()
3417{
3418 int c;
3419 Port_t iobase;
3420 int s;
3421 struct siocnstate sp;
3422
3423 iobase = siogdbiobase;
3424 s = spltty();
3425 siocnopen(&sp, iobase, gdbdefaultrate);
3426 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3427 ;
3428 c = inb(iobase + com_data);
3429 siocnclose(&sp, iobase);
3430 splx(s);
3431 return (c);
3432}
3433
3434void
3435siogdbputc(c)
3436 int c;
3437{
3438 int s;
3439 struct siocnstate sp;
3440
3441 s = spltty();
3442 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3443 siocntxwait(siogdbiobase);
3444 outb(siogdbiobase + com_data, c);
3445 siocnclose(&sp, siogdbiobase);
3446 splx(s);
3447}
3448#endif
3449
3450DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
3451#if NCARD > 0
3452DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0);
3453#endif
3454#if NPCI > 0
3455DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
3456#endif
3457#if NPUC > 0
3458DRIVER_MODULE(sio, puc, sio_puc_driver, sio_devclass, 0, 0);
3459#endif