kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / cpu / i386 / include / atomic.h
CommitLineData
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1/*-
2 * Copyright (c) 1998 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/i386/include/atomic.h,v 1.9.2.1 2000/07/07 00:38:47 obrien Exp $
27 */
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28#ifndef _CPU_ATOMIC_H_
29#define _CPU_ATOMIC_H_
984263bc 30
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31#ifndef _SYS_TYPES_H_
32#include <sys/types.h>
33#endif
34
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35/*
36 * Various simple arithmetic on memory which is atomic in the presence
37 * of interrupts and multiple processors.
38 *
39 * atomic_set_char(P, V) (*(u_char*)(P) |= (V))
40 * atomic_clear_char(P, V) (*(u_char*)(P) &= ~(V))
41 * atomic_add_char(P, V) (*(u_char*)(P) += (V))
42 * atomic_subtract_char(P, V) (*(u_char*)(P) -= (V))
43 *
44 * atomic_set_short(P, V) (*(u_short*)(P) |= (V))
45 * atomic_clear_short(P, V) (*(u_short*)(P) &= ~(V))
46 * atomic_add_short(P, V) (*(u_short*)(P) += (V))
47 * atomic_subtract_short(P, V) (*(u_short*)(P) -= (V))
48 *
49 * atomic_set_int(P, V) (*(u_int*)(P) |= (V))
50 * atomic_clear_int(P, V) (*(u_int*)(P) &= ~(V))
51 * atomic_add_int(P, V) (*(u_int*)(P) += (V))
52 * atomic_subtract_int(P, V) (*(u_int*)(P) -= (V))
53 *
54 * atomic_set_long(P, V) (*(u_long*)(P) |= (V))
55 * atomic_clear_long(P, V) (*(u_long*)(P) &= ~(V))
56 * atomic_add_long(P, V) (*(u_long*)(P) += (V))
57 * atomic_subtract_long(P, V) (*(u_long*)(P) -= (V))
58 */
59
60/*
61 * The above functions are expanded inline in the statically-linked
62 * kernel. Lock prefixes are generated if an SMP kernel is being
46ebb8bc 63 * built, or if user code is using these functions.
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64 *
65 * Kernel modules call real functions which are built into the kernel.
66 * This allows kernel modules to be portable between UP and SMP systems.
67 */
68#if defined(KLD_MODULE)
69#define ATOMIC_ASM(NAME, TYPE, OP, V) \
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70 extern void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \
71 extern void atomic_##NAME##_##TYPE##_nonlocked(volatile u_##TYPE *p, u_##TYPE v);
984263bc 72#else /* !KLD_MODULE */
984263bc 73#define MPLOCKED "lock ; "
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74
75/*
76 * The assembly is volatilized to demark potential before-and-after side
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77 * effects if an interrupt or SMP collision were to occur. The primary
78 * atomic instructions are MP safe, the nonlocked instructions are
79 * local-interrupt-safe (so we don't depend on C 'X |= Y' generating an
80 * atomic instruction).
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81 *
82 * +m - memory is read and written (=m - memory is only written)
83 * iq - integer constant or %ax/%bx/%cx/%dx (ir = int constant or any reg)
84 * (Note: byte instructions only work on %ax,%bx,%cx, or %dx). iq
85 * is good enough for our needs so don't get fancy.
984263bc 86 */
a2a5ad0d 87
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88/* egcs 1.1.2+ version */
89#define ATOMIC_ASM(NAME, TYPE, OP, V) \
90static __inline void \
91atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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92{ \
93 __asm __volatile(MPLOCKED OP \
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94 : "+m" (*p) \
95 : "iq" (V)); \
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96} \
97static __inline void \
98atomic_##NAME##_##TYPE##_nonlocked(volatile u_##TYPE *p, u_##TYPE v)\
984263bc 99{ \
ea475962 100 __asm __volatile(OP \
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101 : "+m" (*p) \
102 : "iq" (V)); \
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103}
104
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105#endif /* KLD_MODULE */
106
984263bc 107/* egcs 1.1.2+ version */
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108ATOMIC_ASM(set, char, "orb %b1,%0", v)
109ATOMIC_ASM(clear, char, "andb %b1,%0", ~v)
110ATOMIC_ASM(add, char, "addb %b1,%0", v)
111ATOMIC_ASM(subtract, char, "subb %b1,%0", v)
984263bc 112
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113ATOMIC_ASM(set, short, "orw %w1,%0", v)
114ATOMIC_ASM(clear, short, "andw %w1,%0", ~v)
115ATOMIC_ASM(add, short, "addw %w1,%0", v)
116ATOMIC_ASM(subtract, short, "subw %w1,%0", v)
984263bc 117
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118ATOMIC_ASM(set, int, "orl %1,%0", v)
119ATOMIC_ASM(clear, int, "andl %1,%0", ~v)
120ATOMIC_ASM(add, int, "addl %1,%0", v)
121ATOMIC_ASM(subtract, int, "subl %1,%0", v)
984263bc 122
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123ATOMIC_ASM(set, long, "orl %1,%0", v)
124ATOMIC_ASM(clear, long, "andl %1,%0", ~v)
125ATOMIC_ASM(add, long, "addl %1,%0", v)
126ATOMIC_ASM(subtract, long, "subl %1,%0", v)
984263bc 127
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128#if defined(KLD_MODULE)
129
130u_int atomic_readandclear_int(volatile u_int *addr);
131
132#else /* !KLD_MODULE */
133
134static __inline u_int
135atomic_readandclear_int(volatile u_int *addr)
136{
33158619 137 u_int res;
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138
139 res = 0;
140 __asm __volatile(
141 " xchgl %1,%0 ; "
142 "# atomic_readandclear_int"
143 : "+r" (res), /* 0 */
144 "=m" (*addr) /* 1 */
145 : "m" (*addr));
146
147 return (res);
148}
149
150#endif /* KLD_MODULE */
151
152
6fc51f62 153/*
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154 * atomic_poll_acquire_int(P) Returns non-zero on success, 0 if the lock
155 * has already been acquired.
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156 * atomic_poll_release_int(P)
157 *
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158 * These support the NDIS driver and are also used for IPIQ interlocks
159 * between cpus. Both the acquisition and release must be
160 * cache-synchronizing instructions.
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161 */
162
163#if defined(KLD_MODULE)
164
b1af91cb 165extern int atomic_swap_int(volatile int *addr, int value);
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166extern int atomic_poll_acquire_int(volatile u_int *p);
167extern void atomic_poll_release_int(volatile u_int *p);
168
169#else
170
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171static __inline int
172atomic_swap_int(volatile int *addr, int value)
173{
174 __asm __volatile("xchgl %0, %1" :
175 "=r" (value), "=m" (*addr) : "0" (value) : "memory");
176 return (value);
177}
178
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179static __inline
180int
181atomic_poll_acquire_int(volatile u_int *p)
182{
183 u_int data;
184
185 __asm __volatile(MPLOCKED "btsl $0,%0; setnc %%al; andl $255,%%eax" : "+m" (*p), "=a" (data));
186 return(data);
187}
188
189static __inline
190void
191atomic_poll_release_int(volatile u_int *p)
192{
4c9f5a7f 193 __asm __volatile(MPLOCKED "btrl $0,%0" : "+m" (*p));
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194}
195
196#endif
197
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198/*
199 * These functions operate on a 32 bit interrupt interlock which is defined
200 * as follows:
201 *
202 * bit 0-30 interrupt handler disabled bits (counter)
203 * bit 31 interrupt handler currently running bit (1 = run)
204 *
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205 * atomic_intr_cond_test(P) Determine if the interlock is in an
206 * acquired state. Returns 0 if it not
207 * acquired, non-zero if it is.
e9cb6d99 208 *
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209 * atomic_intr_cond_try(P)
210 * Increment the request counter and attempt to
211 * set bit 31 to acquire the interlock. If
212 * we are unable to set bit 31 the request
213 * counter is decremented and we return -1,
214 * otherwise we return 0.
215 *
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216 * atomic_intr_cond_enter(P, func, arg)
217 * Increment the request counter and attempt to
218 * set bit 31 to acquire the interlock. If
219 * we are unable to set bit 31 func(arg) is
220 * called in a loop until we are able to set
221 * bit 31.
222 *
223 * atomic_intr_cond_exit(P, func, arg)
224 * Decrement the request counter and clear bit
225 * 31. If the request counter is still non-zero
226 * call func(arg) once.
227 *
228 * atomic_intr_handler_disable(P)
229 * Set bit 30, indicating that the interrupt
230 * handler has been disabled. Must be called
231 * after the hardware is disabled.
232 *
233 * Returns bit 31 indicating whether a serialized
234 * accessor is active (typically the interrupt
235 * handler is running). 0 == not active,
236 * non-zero == active.
237 *
238 * atomic_intr_handler_enable(P)
239 * Clear bit 30, indicating that the interrupt
240 * handler has been enabled. Must be called
241 * before the hardware is actually enabled.
242 *
243 * atomic_intr_handler_is_enabled(P)
244 * Returns bit 30, 0 indicates that the handler
245 * is enabled, non-zero indicates that it is
246 * disabled. The request counter portion of
247 * the field is ignored.
248 */
249
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250#if defined(KLD_MODULE)
251
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252void atomic_intr_init(__atomic_intr_t *p);
253int atomic_intr_handler_disable(__atomic_intr_t *p);
254void atomic_intr_handler_enable(__atomic_intr_t *p);
255int atomic_intr_handler_is_enabled(__atomic_intr_t *p);
256int atomic_intr_cond_test(__atomic_intr_t *p);
257int atomic_intr_cond_try(__atomic_intr_t *p);
258void atomic_intr_cond_enter(__atomic_intr_t *p, void (*func)(void *), void *arg);
259void atomic_intr_cond_exit(__atomic_intr_t *p, void (*func)(void *), void *arg);
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260
261#else
262
263static __inline
264void
aa368711 265atomic_intr_init(__atomic_intr_t *p)
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266{
267 *p = 0;
268}
269
270static __inline
271int
aa368711 272atomic_intr_handler_disable(__atomic_intr_t *p)
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273{
274 int data;
275
276 __asm __volatile(MPLOCKED "orl $0x40000000,%1; movl %1,%%eax; " \
277 "andl $0x80000000,%%eax" \
f0ca723e 278 : "=a"(data) , "+m"(*p));
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279 return(data);
280}
281
282static __inline
283void
aa368711 284atomic_intr_handler_enable(__atomic_intr_t *p)
e9cb6d99 285{
9c095379 286 __asm __volatile(MPLOCKED "andl $0xBFFFFFFF,%0" : "+m" (*p));
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287}
288
289static __inline
290int
aa368711 291atomic_intr_handler_is_enabled(__atomic_intr_t *p)
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292{
293 int data;
294
295 __asm __volatile("movl %1,%%eax; andl $0x40000000,%%eax" \
296 : "=a"(data) : "m"(*p));
297 return(data);
298}
299
300static __inline
301void
aa368711 302atomic_intr_cond_enter(__atomic_intr_t *p, void (*func)(void *), void *arg)
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303{
304 __asm __volatile(MPLOCKED "incl %0; " \
305 "1: ;" \
306 MPLOCKED "btsl $31,%0; jnc 2f; " \
307 "pushl %2; call *%1; addl $4,%%esp; " \
308 "jmp 1b; " \
309 "2: ;" \
310 : "+m" (*p) \
311 : "r"(func), "m"(arg) \
312 : "ax", "cx", "dx");
313}
314
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315/*
316 * Attempt to enter the interrupt condition variable. Returns zero on
317 * success, 1 on failure.
318 */
319static __inline
320int
aa368711 321atomic_intr_cond_try(__atomic_intr_t *p)
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322{
323 int ret;
324
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325 __asm __volatile(MPLOCKED "incl %0; " \
326 "1: ;" \
327 "subl %%eax,%%eax; " \
328 MPLOCKED "btsl $31,%0; jnc 2f; " \
329 MPLOCKED "decl %0; " \
330 "movl $1,%%eax;" \
331 "2: ;"
caae4d60 332 : "+m" (*p), "=&a"(ret)
c4fb66bd 333 : : "cx", "dx");
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334 return (ret);
335}
336
337
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338static __inline
339int
aa368711 340atomic_intr_cond_test(__atomic_intr_t *p)
d02b46cd 341{
f0ca723e 342 return((int)(*p & 0x80000000));
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343}
344
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345static __inline
346void
aa368711 347atomic_intr_cond_exit(__atomic_intr_t *p, void (*func)(void *), void *arg)
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348{
349 __asm __volatile(MPLOCKED "decl %0; " \
350 MPLOCKED "btrl $31,%0; " \
351 "testl $0x3FFFFFFF,%0; jz 1f; " \
352 "pushl %2; call *%1; addl $4,%%esp; " \
353 "1: ;" \
354 : "+m" (*p) \
355 : "r"(func), "m"(arg) \
356 : "ax", "cx", "dx");
357}
358
359#endif
360
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361/*
362 * Atomic compare and set
363 *
74dd601f 364 * if (*_dst == _old) *_dst = _new (all 32 bit words)
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365 *
366 * Returns 0 on failure, non-zero on success
367 */
368#if defined(KLD_MODULE)
5b296f84 369
74dd601f 370extern int atomic_cmpset_int(volatile u_int *_dst, u_int _old, u_int _new);
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371extern long atomic_cmpset_long(volatile u_long *_dst, u_long _exp, u_long _src);
372extern u_int atomic_fetchadd_int(volatile u_int *_p, u_int _v);
b12defdc 373extern u_long atomic_fetchadd_long(volatile u_long *_p, u_long _v);
5b296f84 374
3a4e0cd7 375#else
5b296f84 376
3a4e0cd7 377static __inline int
74dd601f 378atomic_cmpset_int(volatile u_int *_dst, u_int _old, u_int _new)
3a4e0cd7 379{
750f8fdb 380 u_int res = _old;
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381
382 __asm __volatile(MPLOCKED "cmpxchgl %2,%1; " \
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383 : "+a" (res), "=m" (*_dst) \
384 : "r" (_new), "m" (*_dst) \
3a4e0cd7 385 : "memory");
ab6109fb 386 return (res == _old);
3a4e0cd7 387}
5b296f84 388
a22fe0ac 389static __inline long
46037fcb 390atomic_cmpset_long(volatile u_long *_dst, u_long _exp, u_long _src)
5b296f84 391{
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392 return (atomic_cmpset_int((volatile u_int *)_dst, (u_int)_exp,
393 (u_int)_src));
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394}
395
396/*
397 * Atomically add the value of v to the integer pointed to by p and return
398 * the previous value of *p.
399 */
400static __inline u_int
46037fcb 401atomic_fetchadd_int(volatile u_int *_p, u_int _v)
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402{
403 __asm __volatile(MPLOCKED "xaddl %0,%1; " \
404 : "+r" (_v), "=m" (*_p) \
405 : "m" (*_p) \
406 : "memory");
407 return (_v);
408}
409
410static __inline u_long
411atomic_fetchadd_long(volatile u_long *_p, u_long _v)
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412{
413 __asm __volatile(MPLOCKED "xaddl %0,%1; " \
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414 : "+r" (_v), "=m" (*_p) \
415 : "m" (*_p) \
5b296f84 416 : "memory");
46037fcb 417 return (_v);
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418}
419
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420#endif /* KLD_MODULE */
421
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422#if defined(KLD_MODULE)
423
424#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
425extern u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p); \
426extern void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v);
427
428#else /* !KLD_MODULE */
429
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430#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
431static __inline u_##TYPE \
432atomic_load_acq_##TYPE(volatile u_##TYPE *p) \
433{ \
434 u_##TYPE res; \
435 \
436 __asm __volatile(MPLOCKED LOP \
437 : "=a" (res), /* 0 */ \
438 "=m" (*p) /* 1 */ \
439 : "m" (*p) /* 2 */ \
440 : "memory"); \
441 \
442 return (res); \
443} \
444 \
445/* \
446 * The XCHG instruction asserts LOCK automagically. \
447 */ \
448static __inline void \
449atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
450{ \
451 __asm __volatile(SOP \
452 : "=m" (*p), /* 0 */ \
453 "+r" (v) /* 1 */ \
454 : "m" (*p)); /* 2 */ \
455} \
456struct __hack
457
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458#endif /* !KLD_MODULE */
459
460ATOMIC_STORE_LOAD(char, "cmpxchgb %b0,%1", "xchgb %b1,%0");
461ATOMIC_STORE_LOAD(short,"cmpxchgw %w0,%1", "xchgw %w1,%0");
462ATOMIC_STORE_LOAD(int, "cmpxchgl %0,%1", "xchgl %1,%0");
463ATOMIC_STORE_LOAD(long, "cmpxchgl %0,%1", "xchgl %1,%0");
464
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465#undef ATOMIC_ASM
466#undef ATOMIC_STORE_LOAD
467
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468/* Acquire and release variants are identical to the normal ones. */
469#define atomic_set_acq_char atomic_set_char
470#define atomic_set_rel_char atomic_set_char
471#define atomic_clear_acq_char atomic_clear_char
472#define atomic_clear_rel_char atomic_clear_char
473#define atomic_add_acq_char atomic_add_char
474#define atomic_add_rel_char atomic_add_char
475#define atomic_subtract_acq_char atomic_subtract_char
476#define atomic_subtract_rel_char atomic_subtract_char
477
478#define atomic_set_acq_short atomic_set_short
479#define atomic_set_rel_short atomic_set_short
480#define atomic_clear_acq_short atomic_clear_short
481#define atomic_clear_rel_short atomic_clear_short
482#define atomic_add_acq_short atomic_add_short
483#define atomic_add_rel_short atomic_add_short
484#define atomic_subtract_acq_short atomic_subtract_short
485#define atomic_subtract_rel_short atomic_subtract_short
486
487#define atomic_set_acq_int atomic_set_int
488#define atomic_set_rel_int atomic_set_int
489#define atomic_clear_acq_int atomic_clear_int
490#define atomic_clear_rel_int atomic_clear_int
491#define atomic_add_acq_int atomic_add_int
492#define atomic_add_rel_int atomic_add_int
493#define atomic_subtract_acq_int atomic_subtract_int
494#define atomic_subtract_rel_int atomic_subtract_int
495#define atomic_cmpset_acq_int atomic_cmpset_int
496#define atomic_cmpset_rel_int atomic_cmpset_int
497
498#define atomic_set_acq_long atomic_set_long
499#define atomic_set_rel_long atomic_set_long
500#define atomic_clear_acq_long atomic_clear_long
501#define atomic_clear_rel_long atomic_clear_long
502#define atomic_add_acq_long atomic_add_long
503#define atomic_add_rel_long atomic_add_long
504#define atomic_subtract_acq_long atomic_subtract_long
505#define atomic_subtract_rel_long atomic_subtract_long
506#define atomic_cmpset_acq_long atomic_cmpset_long
507#define atomic_cmpset_rel_long atomic_cmpset_long
508
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509/* cpumask_t is 32-bits on i386 */
510#define atomic_set_cpumask atomic_set_int
511#define atomic_clear_cpumask atomic_clear_int
512#define atomic_cmpset_cpumask atomic_cmpset_int
513
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514/* Operations on 8-bit bytes. */
515#define atomic_set_8 atomic_set_char
516#define atomic_set_acq_8 atomic_set_acq_char
517#define atomic_set_rel_8 atomic_set_rel_char
518#define atomic_clear_8 atomic_clear_char
519#define atomic_clear_acq_8 atomic_clear_acq_char
520#define atomic_clear_rel_8 atomic_clear_rel_char
521#define atomic_add_8 atomic_add_char
522#define atomic_add_acq_8 atomic_add_acq_char
523#define atomic_add_rel_8 atomic_add_rel_char
524#define atomic_subtract_8 atomic_subtract_char
525#define atomic_subtract_acq_8 atomic_subtract_acq_char
526#define atomic_subtract_rel_8 atomic_subtract_rel_char
527#define atomic_load_acq_8 atomic_load_acq_char
528#define atomic_store_rel_8 atomic_store_rel_char
529
530/* Operations on 16-bit words. */
531#define atomic_set_16 atomic_set_short
532#define atomic_set_acq_16 atomic_set_acq_short
533#define atomic_set_rel_16 atomic_set_rel_short
534#define atomic_clear_16 atomic_clear_short
535#define atomic_clear_acq_16 atomic_clear_acq_short
536#define atomic_clear_rel_16 atomic_clear_rel_short
537#define atomic_add_16 atomic_add_short
538#define atomic_add_acq_16 atomic_add_acq_short
539#define atomic_add_rel_16 atomic_add_rel_short
540#define atomic_subtract_16 atomic_subtract_short
541#define atomic_subtract_acq_16 atomic_subtract_acq_short
542#define atomic_subtract_rel_16 atomic_subtract_rel_short
543#define atomic_load_acq_16 atomic_load_acq_short
544#define atomic_store_rel_16 atomic_store_rel_short
545
546/* Operations on 32-bit double words. */
547#define atomic_set_32 atomic_set_int
548#define atomic_set_acq_32 atomic_set_acq_int
549#define atomic_set_rel_32 atomic_set_rel_int
550#define atomic_clear_32 atomic_clear_int
551#define atomic_clear_acq_32 atomic_clear_acq_int
552#define atomic_clear_rel_32 atomic_clear_rel_int
553#define atomic_add_32 atomic_add_int
554#define atomic_add_acq_32 atomic_add_acq_int
555#define atomic_add_rel_32 atomic_add_rel_int
556#define atomic_subtract_32 atomic_subtract_int
557#define atomic_subtract_acq_32 atomic_subtract_acq_int
558#define atomic_subtract_rel_32 atomic_subtract_rel_int
559#define atomic_load_acq_32 atomic_load_acq_int
560#define atomic_store_rel_32 atomic_store_rel_int
561#define atomic_cmpset_32 atomic_cmpset_int
562#define atomic_cmpset_acq_32 atomic_cmpset_acq_int
563#define atomic_cmpset_rel_32 atomic_cmpset_rel_int
564#define atomic_readandclear_32 atomic_readandclear_int
565#define atomic_fetchadd_32 atomic_fetchadd_int
566
567/* Operations on pointers. */
568#define atomic_set_ptr(p, v) \
569 atomic_set_int((volatile u_int *)(p), (u_int)(v))
570#define atomic_set_acq_ptr(p, v) \
571 atomic_set_acq_int((volatile u_int *)(p), (u_int)(v))
572#define atomic_set_rel_ptr(p, v) \
573 atomic_set_rel_int((volatile u_int *)(p), (u_int)(v))
574#define atomic_clear_ptr(p, v) \
575 atomic_clear_int((volatile u_int *)(p), (u_int)(v))
576#define atomic_clear_acq_ptr(p, v) \
577 atomic_clear_acq_int((volatile u_int *)(p), (u_int)(v))
578#define atomic_clear_rel_ptr(p, v) \
579 atomic_clear_rel_int((volatile u_int *)(p), (u_int)(v))
580#define atomic_add_ptr(p, v) \
581 atomic_add_int((volatile u_int *)(p), (u_int)(v))
582#define atomic_add_acq_ptr(p, v) \
583 atomic_add_acq_int((volatile u_int *)(p), (u_int)(v))
584#define atomic_add_rel_ptr(p, v) \
585 atomic_add_rel_int((volatile u_int *)(p), (u_int)(v))
586#define atomic_subtract_ptr(p, v) \
587 atomic_subtract_int((volatile u_int *)(p), (u_int)(v))
588#define atomic_subtract_acq_ptr(p, v) \
589 atomic_subtract_acq_int((volatile u_int *)(p), (u_int)(v))
590#define atomic_subtract_rel_ptr(p, v) \
591 atomic_subtract_rel_int((volatile u_int *)(p), (u_int)(v))
592#define atomic_load_acq_ptr(p) \
593 atomic_load_acq_int((volatile u_int *)(p))
594#define atomic_store_rel_ptr(p, v) \
595 atomic_store_rel_int((volatile u_int *)(p), (v))
596#define atomic_cmpset_ptr(dst, old, new) \
597 atomic_cmpset_int((volatile u_int *)(dst), (u_int)(old), (u_int)(new))
598#define atomic_cmpset_acq_ptr(dst, old, new) \
599 atomic_cmpset_acq_int((volatile u_int *)(dst), (u_int)(old), \
600 (u_int)(new))
601#define atomic_cmpset_rel_ptr(dst, old, new) \
602 atomic_cmpset_rel_int((volatile u_int *)(dst), (u_int)(old), \
603 (u_int)(new))
604#define atomic_readandclear_ptr(p) \
605 atomic_readandclear_int((volatile u_int *)(p))
606
a9295349 607#endif /* ! _CPU_ATOMIC_H_ */