kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
MD
41#include "use_npx.h"
42#include "use_isa.h"
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43#include "opt_compat.h"
44#include "opt_cpu.h"
45#include "opt_ddb.h"
46#include "opt_directio.h"
47#include "opt_inet.h"
48#include "opt_ipx.h"
49#include "opt_maxmem.h"
50#include "opt_msgbuf.h"
51#include "opt_perfmon.h"
52#include "opt_swap.h"
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53#include "opt_userconfig.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sysproto.h>
58#include <sys/signalvar.h>
59#include <sys/kernel.h>
60#include <sys/linker.h>
61#include <sys/malloc.h>
62#include <sys/proc.h>
895c1f85 63#include <sys/priv.h>
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64#include <sys/buf.h>
65#include <sys/reboot.h>
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66#include <sys/mbuf.h>
67#include <sys/msgbuf.h>
68#include <sys/sysent.h>
69#include <sys/sysctl.h>
70#include <sys/vmmeter.h>
71#include <sys/bus.h>
a722be49 72#include <sys/upcall.h>
cb7f4ab1 73#include <sys/usched.h>
527fddf7 74#include <sys/reg.h>
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75
76#include <vm/vm.h>
77#include <vm/vm_param.h>
78#include <sys/lock.h>
79#include <vm/vm_kern.h>
80#include <vm/vm_object.h>
81#include <vm/vm_page.h>
82#include <vm/vm_map.h>
83#include <vm/vm_pager.h>
84#include <vm/vm_extern.h>
85
4b5f931b 86#include <sys/thread2.h>
684a93c4 87#include <sys/mplock2.h>
320c681e 88#include <sys/mutex2.h>
4b5f931b 89
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90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
984263bc 96#include <machine/cpu.h>
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97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#include <machine/bootinfo.h>
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100#include <machine/md_var.h>
101#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 102#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 103#include <machine/smp.h>
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104#ifdef PERFMON
105#include <machine/perfmon.h>
106#endif
107#include <machine/cputypes.h>
87cf6827 108#include <machine/intr_machdep.h>
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109
110#ifdef OLD_BUS_ARCH
21ce0dfa 111#include <bus/isa/isa_device.h>
984263bc 112#endif
87cf6827 113#include <machine_base/isa/isa_intr.h>
1f2de5d4 114#include <bus/isa/rtc.h>
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115#include <machine/vm86.h>
116#include <sys/random.h>
117#include <sys/ptrace.h>
118#include <machine/sigframe.h>
119
30c5f287 120#include <sys/machintr.h>
9284cddf 121#include <machine_base/icu/icu_abi.h>
7265a4fe 122#include <machine_base/icu/elcr_var.h>
1d6d7089 123#include <machine_base/apic/lapic.h>
ed4d621d 124#include <machine_base/apic/ioapic.h>
a3dd9120 125#include <machine_base/apic/ioapic_abi.h>
d904d4d9 126#include <machine/mptable.h>
30c5f287 127
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128#define PHYSMAP_ENTRIES 10
129
d678dc17
MN
130extern void init386(int first);
131extern void dblfault_handler(void);
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132
133extern void printcpuinfo(void); /* XXX header file */
134extern void finishidentcpu(void);
135extern void panicifcpuunsupported(void);
136extern void initializecpu(void);
137
d678dc17 138static void cpu_startup(void *);
d883128f
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139static void pic_finish(void *);
140static void cpu_finish(void *);
642a6e88 141#ifndef CPU_DISABLE_SSE
d678dc17
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142static void set_fpregs_xmm(struct save87 *, struct savexmm *);
143static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 144#endif /* CPU_DISABLE_SSE */
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145#ifdef DIRECTIO
146extern void ffs_rawread_setup(void);
147#endif /* DIRECTIO */
8a8d5d85 148static void init_locks(void);
984263bc 149
7c006a9e 150SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
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151SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
152SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
984263bc 153
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154int _udatasel, _ucodesel;
155u_int atdevbase;
c2751817 156int64_t tsc_offsets[MAXCPU];
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157
158#if defined(SWTCH_OPTIM_STATS)
159extern int swtch_optim_stats;
160SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
161 CTLFLAG_RD, &swtch_optim_stats, 0, "");
162SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
163 CTLFLAG_RD, &tlb_flush_count, 0, "");
164#endif
165
39d69dae 166long physmem = 0;
984263bc 167
1876681a
SZ
168u_long ebda_addr = 0;
169
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170int imcr_present = 0;
171
2abaa030 172int naps = 0; /* # of Applications processors */
320c681e 173struct mtx dt_lock; /* lock for GDT and LDT */
2abaa030 174
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175u_int base_memory;
176
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177static int
178sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
179{
39d69dae
AH
180 u_long pmem = ctob(physmem);
181
182 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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183 return (error);
184}
185
39d69dae 186SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 187 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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188
189static int
190sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
191{
192 int error = sysctl_handle_int(oidp, 0,
12e4aaff 193 ctob(physmem - vmstats.v_wire_count), req);
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194 return (error);
195}
196
197SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
198 0, 0, sysctl_hw_usermem, "IU", "");
199
200static int
201sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
202{
203 int error = sysctl_handle_int(oidp, 0,
204 i386_btop(avail_end - avail_start), req);
205 return (error);
206}
207
208SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
209 0, 0, sysctl_hw_availpages, "I", "");
210
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211vm_paddr_t Maxmem;
212vm_paddr_t Realmem;
984263bc 213
ff1a75a1 214vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH
215vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
216
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217
218static vm_offset_t buffer_sva, buffer_eva;
219vm_offset_t clean_sva, clean_eva;
220static vm_offset_t pager_sva, pager_eva;
221static struct trapframe proc0_tf;
222
223static void
f123d5a1 224cpu_startup(void *dummy)
984263bc 225{
c9faf524 226 caddr_t v;
984263bc 227 vm_size_t size = 0;
e4846942 228 vm_offset_t firstaddr;
984263bc 229
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230 /*
231 * Good {morning,afternoon,evening,night}.
232 */
26be20a0 233 kprintf("%s", version);
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234 startrtclock();
235 printcpuinfo();
236 panicifcpuunsupported();
237#ifdef PERFMON
238 perfmon_init();
239#endif
15dc6550 240 kprintf("real memory = %ju (%ju MB)\n",
1bda0d3d
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241 (intmax_t)Realmem,
242 (intmax_t)Realmem / 1024 / 1024);
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243 /*
244 * Display any holes after the first chunk of extended memory.
245 */
246 if (bootverbose) {
247 int indx;
248
26be20a0 249 kprintf("Physical memory chunk(s):\n");
984263bc 250 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 251 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 252
26be20a0 253 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
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254 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
255 size1 / PAGE_SIZE);
256 }
257 }
258
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259 /*
260 * Allocate space for system data structures.
261 * The first available kernel virtual address is in "v".
262 * As pages of kernel virtual memory are allocated, "v" is incremented.
263 * As pages of memory are allocated and cleared,
264 * "firstaddr" is incremented.
265 * An index into the kernel page table corresponding to the
266 * virtual memory address maintained in "v" is kept in "mapaddr".
267 */
268
269 /*
270 * Make two passes. The first pass calculates how much memory is
271 * needed and allocates it. The second pass assigns virtual
272 * addresses to the various data structures.
273 */
274 firstaddr = 0;
275again:
276 v = (caddr_t)firstaddr;
277
278#define valloc(name, type, num) \
279 (name) = (type *)v; v = (caddr_t)((name)+(num))
280#define valloclim(name, type, num, lim) \
281 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
282
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283 /*
284 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
285 * For the first 64MB of ram nominally allocate sufficient buffers to
286 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
287 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
288 * the buffer cache we limit the eventual kva reservation to
289 * maxbcache bytes.
290 *
291 * factor represents the 1/4 x ram conversion.
292 */
293 if (nbuf == 0) {
294 int factor = 4 * BKVASIZE / 1024;
295 int kbytes = physmem * (PAGE_SIZE / 1024);
296
297 nbuf = 50;
298 if (kbytes > 4096)
299 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
300 if (kbytes > 65536)
301 nbuf += (kbytes - 65536) * 2 / (factor * 5);
302 if (maxbcache && nbuf > maxbcache / BKVASIZE)
303 nbuf = maxbcache / BKVASIZE;
304 }
305
306 /*
307 * Do not allow the buffer_map to be more then 1/2 the size of the
308 * kernel_map.
309 */
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310 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
311 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
f86b3b54 312 kprintf("Warning: nbufs capped at %ld\n", nbuf);
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313 }
314
948209ce 315 /* limit to 128 on i386 */
74d62460 316 nswbuf = lmax(lmin(nbuf / 4, 128), 16);
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317#ifdef NSWBUF_MIN
318 if (nswbuf < NSWBUF_MIN)
319 nswbuf = NSWBUF_MIN;
320#endif
321#ifdef DIRECTIO
322 ffs_rawread_setup();
323#endif
324
325 valloc(swbuf, struct buf, nswbuf);
326 valloc(buf, struct buf, nbuf);
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327
328 /*
329 * End of first pass, size has been calculated so allocate memory
330 */
331 if (firstaddr == 0) {
332 size = (vm_size_t)(v - firstaddr);
e4846942 333 firstaddr = kmem_alloc(&kernel_map, round_page(size));
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334 if (firstaddr == 0)
335 panic("startup: no room for tables");
336 goto again;
337 }
338
339 /*
340 * End of second pass, addresses have been assigned
341 */
342 if ((vm_size_t)(v - firstaddr) != size)
343 panic("startup: table size inconsistency");
344
e4846942
MD
345 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
346 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
347 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
348 (nbuf*BKVASIZE));
349 buffer_map.system_map = 1;
350 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
351 (nswbuf*MAXPHYS) + pager_map_size);
352 pager_map.system_map = 1;
984263bc 353
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354#if defined(USERCONFIG)
355 userconfig();
356 cninit(); /* the preferred console may have changed */
357#endif
358
15dc6550 359 kprintf("avail memory = %ju (%ju MB)\n",
79d182b0
MD
360 (intmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
361 (intmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
362 1024 / 1024);
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363
364 /*
365 * Set up buffers, so they can be used to read disk labels.
366 */
367 bufinit();
368 vm_pager_bufferinit();
d883128f
SZ
369}
370
371static void
372cpu_finish(void *dummy __unused)
373{
374 cpu_setregs();
375}
376
377static void
378pic_finish(void *dummy __unused)
379{
380 /* Log ELCR information */
381 elcr_dump();
be1519b3 382
d904d4d9
SZ
383 /* Log MPTABLE information */
384 mptable_pci_int_dump();
385
be1519b3
SZ
386 /* Finalize PIC */
387 MachIntrABI.finalize();
984263bc
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388}
389
984263bc
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390/*
391 * Send an interrupt to process.
392 *
393 * Stack is set up to allow sigcode stored
394 * at top to call routine, followed by kcall
395 * to sigreturn routine below. After sigreturn
396 * resets the signal mask, the stack, and the
397 * frame pointer, it returns to the user
398 * specified pc, psl.
399 */
984263bc 400void
f123d5a1 401sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 402{
065b709a
SS
403 struct lwp *lp = curthread->td_lwp;
404 struct proc *p = lp->lwp_proc;
984263bc
MD
405 struct trapframe *regs;
406 struct sigacts *psp = p->p_sigacts;
407 struct sigframe sf, *sfp;
408 int oonstack;
409
065b709a
SS
410 regs = lp->lwp_md.md_regs;
411 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
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412
413 /* save user context */
414 bzero(&sf, sizeof(struct sigframe));
415 sf.sf_uc.uc_sigmask = *mask;
065b709a 416 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 417 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 418 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 419
ce3d8c4d
MD
420 /* make the size of the saved context visible to userland */
421 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
422
984263bc 423 /* Allocate and validate space for the signal handler context. */
4643740a 424 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 425 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS
426 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
427 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
428 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 429 } else {
984263bc 430 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 431 }
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MD
432
433 /* Translate the signal is appropriate */
434 if (p->p_sysent->sv_sigtbl) {
435 if (sig <= p->p_sysent->sv_sigsize)
436 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
437 }
438
439 /* Build the argument list for the signal handler. */
440 sf.sf_signum = sig;
441 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 442 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
984263bc
MD
443 /* Signal handler installed with SA_SIGINFO. */
444 sf.sf_siginfo = (register_t)&sfp->sf_si;
445 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
446
447 /* fill siginfo structure */
448 sf.sf_si.si_signo = sig;
449 sf.sf_si.si_code = code;
450 sf.sf_si.si_addr = (void*)regs->tf_err;
451 }
452 else {
453 /* Old FreeBSD-style arguments. */
454 sf.sf_siginfo = code;
455 sf.sf_addr = regs->tf_err;
456 sf.sf_ahu.sf_handler = catcher;
457 }
458
459 /*
460 * If we're a vm86 process, we want to save the segment registers.
461 * We also change eflags to be our emulated eflags, not the actual
462 * eflags.
463 */
464 if (regs->tf_eflags & PSL_VM) {
465 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 466 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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467
468 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
469 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
470 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
471 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
472
473 if (vm86->vm86_has_vme == 0)
474 sf.sf_uc.uc_mcontext.mc_eflags =
475 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
476 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
477
478 /*
479 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
480 * syscalls made by the signal handler. This just avoids
481 * wasting time for our lazy fixup of such faults. PSL_NT
482 * does nothing in vm86 mode, but vm86 programs can set it
483 * almost legitimately in probes for old cpu types.
484 */
485 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
486 }
487
1b251f0a
MD
488 /*
489 * Save the FPU state and reinit the FP unit
490 */
491 npxpush(&sf.sf_uc.uc_mcontext);
492
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493 /*
494 * Copy the sigframe out to the user's stack.
495 */
496 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
497 /*
498 * Something is wrong with the stack pointer.
499 * ...Kill the process.
500 */
b276424c 501 sigexit(lp, SIGILL);
984263bc
MD
502 }
503
504 regs->tf_esp = (int)sfp;
505 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE
506
507 /*
508 * i386 abi specifies that the direction flag must be cleared
509 * on function entry
510 */
511 regs->tf_eflags &= ~(PSL_T|PSL_D);
512
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513 regs->tf_cs = _ucodesel;
514 regs->tf_ds = _udatasel;
515 regs->tf_es = _udatasel;
dd4ad62d
MD
516
517 /*
518 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD
519 * the userland program might be using both.
520 *
521 * However, if a T_PROTFLT occured the segment registers could be
522 * totally broken. They must be reset in order to be able to
523 * return to userland.
dd4ad62d 524 */
4e7c41c5
MD
525 if (regs->tf_trapno == T_PROTFLT) {
526 regs->tf_fs = _udatasel;
527 regs->tf_gs = _udatasel;
528 }
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MD
529 regs->tf_ss = _udatasel;
530}
531
4a22e893
MD
532/*
533 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD
534 * VM context. Remove any items that would otherwise create a privilage
535 * issue.
4a22e893 536 *
4e7c41c5
MD
537 * XXX at the moment we allow userland to set the resume flag. Is this a
538 * bad idea?
4a22e893
MD
539 */
540int
541cpu_sanitize_frame(struct trapframe *frame)
542{
543 frame->tf_cs = _ucodesel;
544 frame->tf_ds = _udatasel;
4e7c41c5
MD
545 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
546#if 0
4a22e893 547 frame->tf_fs = _udatasel;
4e7c41c5
MD
548 frame->tf_gs = _udatasel;
549#endif
4a22e893 550 frame->tf_ss = _udatasel;
4e7c41c5 551 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD
552 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
553 return(0);
554}
555
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MD
556int
557cpu_sanitize_tls(struct savetls *tls)
558{
559 struct segment_descriptor *desc;
560 int i;
561
562 for (i = 0; i < NGTLS; ++i) {
563 desc = &tls->tls[i];
564 if (desc->sd_dpl == 0 && desc->sd_type == 0)
565 continue;
566 if (desc->sd_def32 == 0)
567 return(ENXIO);
568 if (desc->sd_type != SDT_MEMRWA)
569 return(ENXIO);
570 if (desc->sd_dpl != SEL_UPL)
571 return(ENXIO);
572 if (desc->sd_xx != 0 || desc->sd_p != 1)
573 return(ENXIO);
574 }
575 return(0);
576}
577
984263bc 578/*
65957d54 579 * sigreturn(ucontext_t *sigcntxp)
41c20dac 580 *
984263bc
MD
581 * System call to cleanup state after a signal
582 * has been taken. Reset signal mask and
583 * stack state from context left by sendsig (above).
584 * Return to previous pc and psl as specified by
585 * context left by sendsig. Check carefully to
586 * make sure that the user has not modified the
587 * state to gain improper privileges.
3919ced0
MD
588 *
589 * MPSAFE
984263bc
MD
590 */
591#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
592#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
593
984263bc 594int
753fd850 595sys_sigreturn(struct sigreturn_args *uap)
984263bc 596{
065b709a 597 struct lwp *lp = curthread->td_lwp;
984263bc 598 struct trapframe *regs;
1b251f0a 599 ucontext_t uc;
984263bc 600 ucontext_t *ucp;
1b251f0a
MD
601 int cs;
602 int eflags;
603 int error;
984263bc 604
1b251f0a
MD
605 /*
606 * We have to copy the information into kernel space so userland
607 * can't modify it while we are sniffing it.
608 */
065b709a 609 regs = lp->lwp_md.md_regs;
1b251f0a
MD
610 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
611 if (error)
612 return (error);
613 ucp = &uc;
984263bc
MD
614 eflags = ucp->uc_mcontext.mc_eflags;
615
616 if (eflags & PSL_VM) {
617 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
618 struct vm86_kernel *vm86;
619
620 /*
621 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
622 * set up the vm86 area, and we can't enter vm86 mode.
623 */
065b709a 624 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 625 return (EINVAL);
065b709a 626 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD
627 if (vm86->vm86_inited == 0)
628 return (EINVAL);
629
630 /* go back to user mode if both flags are set */
631 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 632 trapsignal(lp, SIGBUS, 0);
984263bc
MD
633
634 if (vm86->vm86_has_vme) {
635 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
636 (eflags & VME_USERCHANGE) | PSL_VM;
637 } else {
638 vm86->vm86_eflags = eflags; /* save VIF, VIP */
e2742650
MD
639 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
640 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 641 }
4e7c41c5 642 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
984263bc
MD
643 tf->tf_eflags = eflags;
644 tf->tf_vm86_ds = tf->tf_ds;
645 tf->tf_vm86_es = tf->tf_es;
646 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 647 tf->tf_vm86_gs = tf->tf_gs;
984263bc
MD
648 tf->tf_ds = _udatasel;
649 tf->tf_es = _udatasel;
4e7c41c5 650#if 0
984263bc 651 tf->tf_fs = _udatasel;
4e7c41c5
MD
652 tf->tf_gs = _udatasel;
653#endif
984263bc
MD
654 } else {
655 /*
656 * Don't allow users to change privileged or reserved flags.
657 */
658 /*
659 * XXX do allow users to change the privileged flag PSL_RF.
660 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
661 * should sometimes set it there too. tf_eflags is kept in
662 * the signal context during signal handling and there is no
663 * other place to remember it, so the PSL_RF bit may be
664 * corrupted by the signal handler without us knowing.
665 * Corruption of the PSL_RF bit at worst causes one more or
666 * one less debugger trap, so allowing it is fairly harmless.
667 */
668 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 669 kprintf("sigreturn: eflags = 0x%x\n", eflags);
984263bc
MD
670 return(EINVAL);
671 }
672
673 /*
674 * Don't allow users to load a valid privileged %cs. Let the
675 * hardware check for invalid selectors, excess privilege in
676 * other selectors, invalid %eip's and invalid %esp's.
677 */
678 cs = ucp->uc_mcontext.mc_cs;
679 if (!CS_SECURE(cs)) {
26be20a0 680 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 681 trapsignal(lp, SIGBUS, T_PROTFLT);
984263bc
MD
682 return(EINVAL);
683 }
4e7c41c5 684 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
984263bc
MD
685 }
686
1b251f0a
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687 /*
688 * Restore the FPU state from the frame
689 */
3919ced0 690 crit_enter();
1b251f0a
MD
691 npxpop(&ucp->uc_mcontext);
692
984263bc 693 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 694 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 695 else
065b709a 696 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 697
065b709a
SS
698 lp->lwp_sigmask = ucp->uc_sigmask;
699 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 700 crit_exit();
984263bc
MD
701 return(EJUSTRETURN);
702}
703
a722be49
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704/*
705 * Stack frame on entry to function. %eax will contain the function vector,
706 * %ecx will contain the function data. flags, ecx, and eax will have
707 * already been pushed on the stack.
708 */
709struct upc_frame {
710 register_t eax;
711 register_t ecx;
0a455ac5 712 register_t edx;
a722be49
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713 register_t flags;
714 register_t oldip;
715};
716
717void
718sendupcall(struct vmupcall *vu, int morepending)
719{
065b709a 720 struct lwp *lp = curthread->td_lwp;
a722be49
MD
721 struct trapframe *regs;
722 struct upcall upcall;
723 struct upc_frame upc_frame;
6e58b5df 724 int crit_count = 0;
a722be49 725
69c61fbe
MD
726 /*
727 * If we are a virtual kernel running an emulated user process
728 * context, switch back to the virtual kernel context before
729 * trying to post the signal.
730 */
39005e16 731 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
69c61fbe 732 lp->lwp_md.md_regs->tf_trapno = 0;
287ebb09 733 vkernel_trap(lp, lp->lwp_md.md_regs);
69c61fbe
MD
734 }
735
a722be49
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736 /*
737 * Get the upcall data structure
738 */
065b709a 739 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
6e58b5df
MD
740 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
741 ) {
a722be49 742 vu->vu_pending = 0;
26be20a0 743 kprintf("bad upcall address\n");
a722be49
MD
744 return;
745 }
746
747 /*
748 * If the data structure is already marked pending or has a critical
749 * section count, mark the data structure as pending and return
750 * without doing an upcall. vu_pending is left set.
751 */
6e58b5df
MD
752 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
753 if (upcall.upc_pending < vu->vu_pending) {
754 upcall.upc_pending = vu->vu_pending;
065b709a 755 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 756 sizeof(upcall.upc_pending));
a722be49
MD
757 }
758 return;
759 }
760
761 /*
762 * We can run this upcall now, clear vu_pending.
763 *
764 * Bump our critical section count and set or clear the
765 * user pending flag depending on whether more upcalls are
766 * pending. The user will be responsible for calling
767 * upc_dispatch(-1) to process remaining upcalls.
768 */
769 vu->vu_pending = 0;
6e58b5df 770 upcall.upc_pending = morepending;
f9235b6d 771 ++crit_count;
065b709a 772 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df
MD
773 sizeof(upcall.upc_pending));
774 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
775 sizeof(int));
a722be49
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776
777 /*
778 * Construct a stack frame and issue the upcall
779 */
065b709a 780 regs = lp->lwp_md.md_regs;
a722be49
MD
781 upc_frame.eax = regs->tf_eax;
782 upc_frame.ecx = regs->tf_ecx;
0a455ac5 783 upc_frame.edx = regs->tf_edx;
a722be49
MD
784 upc_frame.flags = regs->tf_eflags;
785 upc_frame.oldip = regs->tf_eip;
786 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
787 sizeof(upc_frame)) != 0) {
26be20a0 788 kprintf("bad stack on upcall\n");
a722be49
MD
789 } else {
790 regs->tf_eax = (register_t)vu->vu_func;
791 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 792 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
793 regs->tf_eip = (register_t)vu->vu_ctx;
794 regs->tf_esp -= sizeof(upc_frame);
795 }
796}
797
798/*
799 * fetchupcall occurs in the context of a system call, which means that
0a455ac5
MD
800 * we have to return EJUSTRETURN in order to prevent eax and edx from
801 * being overwritten by the syscall return value.
a722be49
MD
802 *
803 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
804 * and the function pointer in %eax.
805 */
806int
d678dc17 807fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
a722be49
MD
808{
809 struct upc_frame upc_frame;
065b709a 810 struct lwp *lp = curthread->td_lwp;
a722be49
MD
811 struct trapframe *regs;
812 int error;
6e58b5df
MD
813 struct upcall upcall;
814 int crit_count;
a722be49 815
065b709a 816 regs = lp->lwp_md.md_regs;
a722be49 817
065b709a 818 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
a722be49
MD
819 if (error == 0) {
820 if (vu) {
821 /*
822 * This jumps us to the next ready context.
823 */
824 vu->vu_pending = 0;
065b709a 825 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
6e58b5df
MD
826 crit_count = 0;
827 if (error == 0)
828 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 829 ++crit_count;
a722be49 830 if (error == 0)
6e58b5df 831 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
a722be49
MD
832 regs->tf_eax = (register_t)vu->vu_func;
833 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 834 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
835 regs->tf_eip = (register_t)vu->vu_ctx;
836 regs->tf_esp = (register_t)rsp;
837 } else {
838 /*
839 * This returns us to the originally interrupted code.
840 */
841 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
842 regs->tf_eax = upc_frame.eax;
843 regs->tf_ecx = upc_frame.ecx;
0a455ac5 844 regs->tf_edx = upc_frame.edx;
6e58b5df
MD
845 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
846 (upc_frame.flags & PSL_USERCHANGE);
a722be49
MD
847 regs->tf_eip = upc_frame.oldip;
848 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
849 }
850 }
851 if (error == 0)
852 error = EJUSTRETURN;
853 return(error);
854}
855
984263bc
MD
856/*
857 * Machine dependent boot() routine
858 *
859 * I haven't seen anything to put here yet
860 * Possibly some stuff might be grafted back here from boot()
861 */
862void
863cpu_boot(int howto)
864{
865}
866
867/*
868 * Shutdown the CPU as much as possible
869 */
870void
871cpu_halt(void)
872{
873 for (;;)
1184892f 874 __asm__ __volatile("hlt");
984263bc
MD
875}
876
877/*
8ad65e08
MD
878 * cpu_idle() represents the idle LWKT. You cannot return from this function
879 * (unless you want to blow things up!). Instead we look for runnable threads
880 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 881 *
26a0694b 882 * The main loop is entered with a critical section held, we must release
a2a5ad0d
MD
883 * the critical section before doing anything else. lwkt_switch() will
884 * check for pending interrupts due to entering and exiting its own
885 * critical section.
26a0694b 886 *
7d4d6fdb 887 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
7d4d6fdb 888 *
46e562ce
MD
889 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
890 * 1 to just use hlt and for debugging purposes.
984263bc 891 */
46e562ce 892static int cpu_idle_hlt = 2;
60f945af
MD
893static int cpu_idle_hltcnt;
894static int cpu_idle_spincnt;
582fd846 895static u_int cpu_idle_repeat = 750;
984263bc
MD
896SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
897 &cpu_idle_hlt, 0, "Idle loop HLT enable");
60f945af
MD
898SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
899 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
900SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
901 &cpu_idle_spincnt, 0, "Idle loop entry spins");
be71787b
MD
902SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
903 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
984263bc 904
f9d8cd12
MD
905static void
906cpu_idle_default_hook(void)
907{
908 /*
909 * We must guarentee that hlt is exactly the instruction
910 * following the sti.
911 */
912 __asm __volatile("sti; hlt");
913}
914
915/* Other subsystems (e.g., ACPI) can hook this later. */
916void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
917
984263bc
MD
918void
919cpu_idle(void)
920{
be71787b 921 globaldata_t gd = mycpu;
10662728 922 struct thread *td __debugvar = gd->gd_curthread;
be71787b
MD
923 int reqflags;
924 int quick;
a2a5ad0d 925
26a0694b 926 crit_exit();
f9235b6d 927 KKASSERT(td->td_critcount == 0);
8ad65e08 928 for (;;) {
a2a5ad0d
MD
929 /*
930 * See if there are any LWKTs ready to go.
931 */
8ad65e08 932 lwkt_switch();
a2a5ad0d
MD
933
934 /*
be71787b
MD
935 * When halting inside a cli we must check for reqflags
936 * races, particularly [re]schedule requests. Running
937 * splz() does the job.
938 *
939 * cpu_idle_hlt:
940 * 0 Never halt, just spin
941 *
942 * 1 Always use HLT (or MONITOR/MWAIT if avail).
943 * This typically eats more power than the
944 * ACPI halt.
945 *
946 * 2 Use HLT/MONITOR/MWAIT up to a point and then
947 * use the ACPI halt (default). This is a hybrid
948 * approach. See machdep.cpu_idle_repeat.
949 *
950 * 3 Always use the ACPI halt. This typically
951 * eats the least amount of power but the cpu
952 * will be slow waking up. Slows down e.g.
953 * compiles and other pipe/event oriented stuff.
954 *
955 *
956 * NOTE: Interrupts are enabled and we are not in a critical
957 * section.
958 *
959 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
960 * don't bother capping gd_idle_repeat, it is ok if
961 * it overflows.
a2a5ad0d 962 */
be71787b
MD
963 ++gd->gd_idle_repeat;
964 reqflags = gd->gd_reqflags;
965 quick = (cpu_idle_hlt == 1) ||
966 (cpu_idle_hlt < 3 &&
967 gd->gd_idle_repeat < cpu_idle_repeat);
968
969 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
970 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
971 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
972 ++cpu_idle_hltcnt;
973 } else if (cpu_idle_hlt) {
a2a5ad0d
MD
974 __asm __volatile("cli");
975 splz();
be71787b
MD
976 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
977 if (quick)
7d4d6fdb
MD
978 cpu_idle_default_hook();
979 else
980 cpu_idle_hook();
981 }
7d4d6fdb 982 __asm __volatile("sti");
60f945af 983 ++cpu_idle_hltcnt;
8ad65e08 984 } else {
60f945af 985 splz();
c5724852 986 __asm __volatile("sti");
60f945af 987 ++cpu_idle_spincnt;
8ad65e08 988 }
984263bc
MD
989 }
990}
991
06615ccb
MD
992/*
993 * This routine is called if a spinlock has been held through the
994 * exponential backoff period and is seriously contested. On a real cpu
995 * we let it spin.
996 */
997void
998cpu_spinlock_contested(void)
999{
1000 cpu_pause();
1001}
1002
984263bc
MD
1003/*
1004 * Clear registers on exec
1005 */
1006void
08f2f1bb 1007exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 1008{
08f2f1bb
SS
1009 struct thread *td = curthread;
1010 struct lwp *lp = td->td_lwp;
1011 struct pcb *pcb = td->td_pcb;
bb3cd951 1012 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 1013
984263bc
MD
1014 /* was i386_user_cleanup() in NetBSD */
1015 user_ldt_free(pcb);
984263bc
MD
1016
1017 bzero((char *)regs, sizeof(struct trapframe));
1018 regs->tf_eip = entry;
1019 regs->tf_esp = stack;
1020 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1021 regs->tf_ss = _udatasel;
1022 regs->tf_ds = _udatasel;
1023 regs->tf_es = _udatasel;
1024 regs->tf_fs = _udatasel;
4e7c41c5 1025 regs->tf_gs = _udatasel;
984263bc
MD
1026 regs->tf_cs = _ucodesel;
1027
1028 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1029 regs->tf_ebx = ps_strings;
1030
1031 /*
1032 * Reset the hardware debug registers if they were in use.
1033 * They won't have any meaning for the newly exec'd process.
1034 */
1035 if (pcb->pcb_flags & PCB_DBREGS) {
1036 pcb->pcb_dr0 = 0;
1037 pcb->pcb_dr1 = 0;
1038 pcb->pcb_dr2 = 0;
1039 pcb->pcb_dr3 = 0;
1040 pcb->pcb_dr6 = 0;
1041 pcb->pcb_dr7 = 0;
08f2f1bb 1042 if (pcb == td->td_pcb) {
984263bc
MD
1043 /*
1044 * Clear the debug registers on the running
1045 * CPU, otherwise they will end up affecting
1046 * the next process we switch to.
1047 */
1048 reset_dbregs();
1049 }
1050 pcb->pcb_flags &= ~PCB_DBREGS;
1051 }
1052
1053 /*
1054 * Initialize the math emulator (if any) for the current process.
1055 * Actually, just clear the bit that says that the emulator has
1056 * been initialized. Initialization is delayed until the process
1057 * traps to the emulator (if it is done at all) mainly because
1058 * emulators don't provide an entry point for initialization.
1059 */
08f2f1bb 1060 pcb->pcb_flags &= ~FP_SOFTFP;
984263bc
MD
1061
1062 /*
a02705a9
MD
1063 * note: do not set CR0_TS here. npxinit() must do it after clearing
1064 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
1065 * in npxdna().
984263bc 1066 */
a02705a9
MD
1067 crit_enter();
1068 load_cr0(rcr0() | CR0_MP);
984263bc
MD
1069
1070#if NNPX > 0
1071 /* Initialize the npx (if any) for the current process. */
1072 npxinit(__INITIAL_NPXCW__);
1073#endif
a02705a9 1074 crit_exit();
984263bc 1075
90b9818c
MD
1076 /*
1077 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
MD
1078 * handled in execve simply by setting the 64 bit syscall
1079 * return value to 0.
90b9818c 1080 */
984263bc
MD
1081}
1082
1083void
1084cpu_setregs(void)
1085{
1086 unsigned int cr0;
1087
1088 cr0 = rcr0();
1089 cr0 |= CR0_NE; /* Done by npxinit() */
1090 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 1091 cr0 |= CR0_WP | CR0_AM;
984263bc
MD
1092 load_cr0(cr0);
1093 load_gs(_udatasel);
1094}
1095
1096static int
1097sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1098{
1099 int error;
1100 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1101 req);
1102 if (!error && req->newptr)
1103 resettodr();
1104 return (error);
1105}
1106
1107SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1108 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1109
1110SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1111 CTLFLAG_RW, &disable_rtc_set, 0, "");
1112
1113SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1114 CTLFLAG_RD, &bootinfo, bootinfo, "");
1115
1116SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1117 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1118
b13267a5 1119extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 1120SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 1121 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
984263bc
MD
1122
1123/*
1124 * Initialize 386 and configure to run kernel
1125 */
1126
1127/*
1128 * Initialize segments & interrupt table
1129 */
1130
1131int _default_ldt;
1132union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1133static struct gate_descriptor idt0[NIDT];
1134struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1135union descriptor ldt[NLDT]; /* local descriptor table */
17a9f566
MD
1136
1137/* table descriptors - used to load tables by cpu */
984263bc 1138struct region_descriptor r_gdt, r_idt;
984263bc 1139
984263bc
MD
1140#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1141extern int has_f00f_bug;
1142#endif
1143
1144static struct i386tss dblfault_tss;
1145static char dblfault_stack[PAGE_SIZE];
1146
1147extern struct user *proc0paddr;
1148
1149
1150/* software prototypes -- in more palatable form */
1151struct soft_segment_descriptor gdt_segs[] = {
1152/* GNULL_SEL 0 Null Descriptor */
1153{ 0x0, /* segment base address */
1154 0x0, /* length */
1155 0, /* segment type */
1156 0, /* segment descriptor priority level */
1157 0, /* segment descriptor present */
1158 0, 0,
1159 0, /* default 32 vs 16 bit size */
1160 0 /* limit granularity (byte/page units)*/ },
1161/* GCODE_SEL 1 Code Descriptor for kernel */
1162{ 0x0, /* segment base address */
1163 0xfffff, /* length - all address space */
1164 SDT_MEMERA, /* segment type */
1165 0, /* segment descriptor priority level */
1166 1, /* segment descriptor present */
1167 0, 0,
1168 1, /* default 32 vs 16 bit size */
1169 1 /* limit granularity (byte/page units)*/ },
1170/* GDATA_SEL 2 Data Descriptor for kernel */
1171{ 0x0, /* segment base address */
1172 0xfffff, /* length - all address space */
1173 SDT_MEMRWA, /* segment type */
1174 0, /* segment descriptor priority level */
1175 1, /* segment descriptor present */
1176 0, 0,
1177 1, /* default 32 vs 16 bit size */
1178 1 /* limit granularity (byte/page units)*/ },
1179/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1180{ 0x0, /* segment base address */
1181 0xfffff, /* length - all address space */
1182 SDT_MEMRWA, /* segment type */
1183 0, /* segment descriptor priority level */
1184 1, /* segment descriptor present */
1185 0, 0,
1186 1, /* default 32 vs 16 bit size */
1187 1 /* limit granularity (byte/page units)*/ },
1188/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1189{
1190 0x0, /* segment base address */
1191 sizeof(struct i386tss)-1,/* length - all address space */
1192 SDT_SYS386TSS, /* segment type */
1193 0, /* segment descriptor priority level */
1194 1, /* segment descriptor present */
1195 0, 0,
1196 0, /* unused - default 32 vs 16 bit size */
1197 0 /* limit granularity (byte/page units)*/ },
1198/* GLDT_SEL 5 LDT Descriptor */
1199{ (int) ldt, /* segment base address */
1200 sizeof(ldt)-1, /* length - all address space */
1201 SDT_SYSLDT, /* segment type */
1202 SEL_UPL, /* segment descriptor priority level */
1203 1, /* segment descriptor present */
1204 0, 0,
1205 0, /* unused - default 32 vs 16 bit size */
1206 0 /* limit granularity (byte/page units)*/ },
1207/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1208{ (int) ldt, /* segment base address */
1209 (512 * sizeof(union descriptor)-1), /* length */
1210 SDT_SYSLDT, /* segment type */
1211 0, /* segment descriptor priority level */
1212 1, /* segment descriptor present */
1213 0, 0,
1214 0, /* unused - default 32 vs 16 bit size */
1215 0 /* limit granularity (byte/page units)*/ },
1216/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1217{ 0x0, /* segment base address */
1218 0x0, /* length - all address space */
1219 0, /* segment type */
1220 0, /* segment descriptor priority level */
1221 0, /* segment descriptor present */
1222 0, 0,
1223 0, /* default 32 vs 16 bit size */
1224 0 /* limit granularity (byte/page units)*/ },
1225/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1226{ 0x400, /* segment base address */
1227 0xfffff, /* length */
1228 SDT_MEMRWA, /* segment type */
1229 0, /* segment descriptor priority level */
1230 1, /* segment descriptor present */
1231 0, 0,
1232 1, /* default 32 vs 16 bit size */
1233 1 /* limit granularity (byte/page units)*/ },
1234/* GPANIC_SEL 9 Panic Tss Descriptor */
1235{ (int) &dblfault_tss, /* segment base address */
1236 sizeof(struct i386tss)-1,/* length - all address space */
1237 SDT_SYS386TSS, /* segment type */
1238 0, /* segment descriptor priority level */
1239 1, /* segment descriptor present */
1240 0, 0,
1241 0, /* unused - default 32 vs 16 bit size */
1242 0 /* limit granularity (byte/page units)*/ },
1243/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1244{ 0, /* segment base address (overwritten) */
1245 0xfffff, /* length */
1246 SDT_MEMERA, /* segment type */
1247 0, /* segment descriptor priority level */
1248 1, /* segment descriptor present */
1249 0, 0,
1250 0, /* default 32 vs 16 bit size */
1251 1 /* limit granularity (byte/page units)*/ },
1252/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1253{ 0, /* segment base address (overwritten) */
1254 0xfffff, /* length */
1255 SDT_MEMERA, /* segment type */
1256 0, /* segment descriptor priority level */
1257 1, /* segment descriptor present */
1258 0, 0,
1259 0, /* default 32 vs 16 bit size */
1260 1 /* limit granularity (byte/page units)*/ },
1261/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1262{ 0, /* segment base address (overwritten) */
1263 0xfffff, /* length */
1264 SDT_MEMRWA, /* segment type */
1265 0, /* segment descriptor priority level */
1266 1, /* segment descriptor present */
1267 0, 0,
1268 1, /* default 32 vs 16 bit size */
1269 1 /* limit granularity (byte/page units)*/ },
1270/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1271{ 0, /* segment base address (overwritten) */
1272 0xfffff, /* length */
1273 SDT_MEMRWA, /* segment type */
1274 0, /* segment descriptor priority level */
1275 1, /* segment descriptor present */
1276 0, 0,
1277 0, /* default 32 vs 16 bit size */
1278 1 /* limit granularity (byte/page units)*/ },
1279/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1280{ 0, /* segment base address (overwritten) */
1281 0xfffff, /* length */
1282 SDT_MEMRWA, /* segment type */
1283 0, /* segment descriptor priority level */
1284 1, /* segment descriptor present */
1285 0, 0,
1286 0, /* default 32 vs 16 bit size */
1287 1 /* limit granularity (byte/page units)*/ },
806bf111
MD
1288/* GTLS_START 15 TLS */
1289{ 0x0, /* segment base address */
1290 0x0, /* length */
1291 0, /* segment type */
1292 0, /* segment descriptor priority level */
1293 0, /* segment descriptor present */
1294 0, 0,
1295 0, /* default 32 vs 16 bit size */
1296 0 /* limit granularity (byte/page units)*/ },
1297/* GTLS_START+1 16 TLS */
1298{ 0x0, /* segment base address */
1299 0x0, /* length */
1300 0, /* segment type */
1301 0, /* segment descriptor priority level */
1302 0, /* segment descriptor present */
1303 0, 0,
1304 0, /* default 32 vs 16 bit size */
1305 0 /* limit granularity (byte/page units)*/ },
1306/* GTLS_END 17 TLS */
efba76b4
SW
1307{ 0x0, /* segment base address */
1308 0x0, /* length */
1309 0, /* segment type */
1310 0, /* segment descriptor priority level */
1311 0, /* segment descriptor present */
1312 0, 0,
1313 0, /* default 32 vs 16 bit size */
1314 0 /* limit granularity (byte/page units)*/ },
1315/* GNDIS_SEL 18 NDIS Descriptor */
806bf111
MD
1316{ 0x0, /* segment base address */
1317 0x0, /* length */
1318 0, /* segment type */
1319 0, /* segment descriptor priority level */
1320 0, /* segment descriptor present */
1321 0, 0,
1322 0, /* default 32 vs 16 bit size */
1323 0 /* limit granularity (byte/page units)*/ },
984263bc
MD
1324};
1325
1326static struct soft_segment_descriptor ldt_segs[] = {
1327 /* Null Descriptor - overwritten by call gate */
1328{ 0x0, /* segment base address */
1329 0x0, /* length - all address space */
1330 0, /* segment type */
1331 0, /* segment descriptor priority level */
1332 0, /* segment descriptor present */
1333 0, 0,
1334 0, /* default 32 vs 16 bit size */
1335 0 /* limit granularity (byte/page units)*/ },
1336 /* Null Descriptor - overwritten by call gate */
1337{ 0x0, /* segment base address */
1338 0x0, /* length - all address space */
1339 0, /* segment type */
1340 0, /* segment descriptor priority level */
1341 0, /* segment descriptor present */
1342 0, 0,
1343 0, /* default 32 vs 16 bit size */
1344 0 /* limit granularity (byte/page units)*/ },
1345 /* Null Descriptor - overwritten by call gate */
1346{ 0x0, /* segment base address */
1347 0x0, /* length - all address space */
1348 0, /* segment type */
1349 0, /* segment descriptor priority level */
1350 0, /* segment descriptor present */
1351 0, 0,
1352 0, /* default 32 vs 16 bit size */
1353 0 /* limit granularity (byte/page units)*/ },
1354 /* Code Descriptor for user */
1355{ 0x0, /* segment base address */
1356 0xfffff, /* length - all address space */
1357 SDT_MEMERA, /* segment type */
1358 SEL_UPL, /* segment descriptor priority level */
1359 1, /* segment descriptor present */
1360 0, 0,
1361 1, /* default 32 vs 16 bit size */
1362 1 /* limit granularity (byte/page units)*/ },
1363 /* Null Descriptor - overwritten by call gate */
1364{ 0x0, /* segment base address */
1365 0x0, /* length - all address space */
1366 0, /* segment type */
1367 0, /* segment descriptor priority level */
1368 0, /* segment descriptor present */
1369 0, 0,
1370 0, /* default 32 vs 16 bit size */
1371 0 /* limit granularity (byte/page units)*/ },
1372 /* Data Descriptor for user */
1373{ 0x0, /* segment base address */
1374 0xfffff, /* length - all address space */
1375 SDT_MEMRWA, /* segment type */
1376 SEL_UPL, /* segment descriptor priority level */
1377 1, /* segment descriptor present */
1378 0, 0,
1379 1, /* default 32 vs 16 bit size */
1380 1 /* limit granularity (byte/page units)*/ },
1381};
1382
1383void
f123d5a1 1384setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD
1385{
1386 struct gate_descriptor *ip;
1387
1388 ip = idt + idx;
1389 ip->gd_looffset = (int)func;
1390 ip->gd_selector = selec;
1391 ip->gd_stkcpy = 0;
1392 ip->gd_xx = 0;
1393 ip->gd_type = typ;
1394 ip->gd_dpl = dpl;
1395 ip->gd_p = 1;
1396 ip->gd_hioffset = ((int)func)>>16 ;
1397}
1398
1399#define IDTVEC(name) __CONCAT(X,name)
1400
1401extern inthand_t
1402 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1403 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1404 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1405 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1406 IDTVEC(xmm), IDTVEC(syscall),
1407 IDTVEC(rsvd0);
a64ba182 1408extern inthand_t
f9a13fc4 1409 IDTVEC(int0x80_syscall);
984263bc 1410
f7bc9806
MD
1411#ifdef DEBUG_INTERRUPTS
1412extern inthand_t *Xrsvdary[256];
1413#endif
1414
984263bc 1415void
f123d5a1 1416sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD
1417{
1418 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1419 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1420 ssd->ssd_type = sd->sd_type;
1421 ssd->ssd_dpl = sd->sd_dpl;
1422 ssd->ssd_p = sd->sd_p;
1423 ssd->ssd_def32 = sd->sd_def32;
1424 ssd->ssd_gran = sd->sd_gran;
1425}
1426
984263bc
MD
1427/*
1428 * Populate the (physmap) array with base/bound pairs describing the
1429 * available physical memory in the system, then test this memory and
1430 * build the phys_avail array describing the actually-available memory.
1431 *
1432 * If we cannot accurately determine the physical memory map, then use
1433 * value from the 0xE801 call, and failing that, the RTC.
1434 *
1435 * Total memory size may be set by the kernel environment variable
1436 * hw.physmem or the compile-time define MAXMEM.
1437 */
1438static void
1439getmemsize(int first)
1440{
b24cd69c 1441 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD
1442 int hasbrokenint12;
1443 u_int basemem, extmem;
1444 struct vm86frame vmf;
1445 struct vm86context vmc;
ff1a75a1
MD
1446 vm_offset_t pa;
1447 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1448 pt_entry_t *pte;
555da584 1449 quad_t maxmem;
984263bc
MD
1450 struct {
1451 u_int64_t base;
1452 u_int64_t length;
1453 u_int32_t type;
1454 } *smap;
28abdbbb 1455 quad_t dcons_addr, dcons_size;
984263bc 1456
984263bc
MD
1457 bzero(&vmf, sizeof(struct vm86frame));
1458 bzero(physmap, sizeof(physmap));
1459 basemem = 0;
1460
1461 /*
1462 * Some newer BIOSes has broken INT 12H implementation which cause
1463 * kernel panic immediately. In this case, we need to scan SMAP
1464 * with INT 15:E820 first, then determine base memory size.
1465 */
2ed482dc
MN
1466 hasbrokenint12 = 0;
1467 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD
1468 if (hasbrokenint12) {
1469 goto int15e820;
1470 }
1471
1472 /*
7febcc6e
MD
1473 * Perform "base memory" related probes & setup. If we get a crazy
1474 * value give the bios some scribble space just in case.
984263bc
MD
1475 */
1476 vm86_intcall(0x12, &vmf);
1477 basemem = vmf.vmf_ax;
1478 if (basemem > 640) {
26be20a0 1479 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD
1480 "truncating to < 640K\n", basemem);
1481 basemem = 636;
984263bc
MD
1482 }
1483
1484 /*
1485 * XXX if biosbasemem is now < 640, there is a `hole'
1486 * between the end of base memory and the start of
1487 * ISA memory. The hole may be empty or it may
1488 * contain BIOS code or data. Map it read/write so
1489 * that the BIOS can write to it. (Memory from 0 to
1490 * the physical end of the kernel is mapped read-only
1491 * to begin with and then parts of it are remapped.
1492 * The parts that aren't remapped form holes that
1493 * remain read-only and are unused by the kernel.
1494 * The base memory area is below the physical end of
1495 * the kernel and right now forms a read-only hole.
1496 * The part of it from PAGE_SIZE to
1497 * (trunc_page(biosbasemem * 1024) - 1) will be
1498 * remapped and used by the kernel later.)
1499 *
1500 * This code is similar to the code used in
1501 * pmap_mapdev, but since no memory needs to be
1502 * allocated we simply change the mapping.
1503 */
1504 for (pa = trunc_page(basemem * 1024);
1505 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1506 pte = vtopte(pa + KERNBASE);
984263bc
MD
1507 *pte = pa | PG_RW | PG_V;
1508 }
1509
1510 /*
1511 * if basemem != 640, map pages r/w into vm86 page table so
1512 * that the bios can scribble on it.
1513 */
b5b32410 1514 pte = vm86paddr;
984263bc
MD
1515 for (i = basemem / 4; i < 160; i++)
1516 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1517
1518int15e820:
1519 /*
1520 * map page 1 R/W into the kernel page table so we can use it
1521 * as a buffer. The kernel will unmap this page later.
1522 */
b5b32410 1523 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1524 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1525
1526 /*
1527 * get memory map with INT 15:E820
1528 */
1529#define SMAPSIZ sizeof(*smap)
1530#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1531
1532 vmc.npages = 0;
1533 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1534 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1535
1536 physmap_idx = 0;
1537 vmf.vmf_ebx = 0;
1538 do {
1539 vmf.vmf_eax = 0xE820;
1540 vmf.vmf_edx = SMAP_SIG;
1541 vmf.vmf_ecx = SMAPSIZ;
1542 i = vm86_datacall(0x15, &vmf, &vmc);
1543 if (i || vmf.vmf_eax != SMAP_SIG)
1544 break;
1545 if (boothowto & RB_VERBOSE)
26be20a0 1546 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD
1547 smap->type,
1548 *(u_int32_t *)((char *)&smap->base + 4),
1549 (u_int32_t)smap->base,
1550 *(u_int32_t *)((char *)&smap->length + 4),
1551 (u_int32_t)smap->length);
1552
1553 if (smap->type != 0x01)
1554 goto next_run;
1555
1556 if (smap->length == 0)
1557 goto next_run;
1558
1bda0d3d
MD
1559 Realmem += smap->length;
1560
1561 if (smap->base >= 0xffffffffLLU) {
9c3db322 1562 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1563 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD
1564 goto next_run;
1565 }
1566
1567 for (i = 0; i <= physmap_idx; i += 2) {
1568 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1569 if (boothowto & RB_VERBOSE) {
1570 kprintf("Overlapping or non-montonic "
1571 "memory region, ignoring "
1572 "second region\n");
1573 }
1574 Realmem -= smap->length;
984263bc
MD
1575 goto next_run;
1576 }
1577 }
1578
1579 if (smap->base == physmap[physmap_idx + 1]) {
1580 physmap[physmap_idx + 1] += smap->length;
1581 goto next_run;
1582 }
1583
1584 physmap_idx += 2;
ff1a75a1 1585 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD
1586 kprintf("Too many segments in the physical "
1587 "address map, giving up\n");
984263bc
MD
1588 break;
1589 }
1590 physmap[physmap_idx] = smap->base;
1591 physmap[physmap_idx + 1] = smap->base + smap->length;
1592next_run:
6b08710e 1593 ; /* fix GCC3.x warning */
984263bc
MD
1594 } while (vmf.vmf_ebx != 0);
1595
1596 /*
1597 * Perform "base memory" related probes & setup based on SMAP
1598 */
1599 if (basemem == 0) {
1600 for (i = 0; i <= physmap_idx; i += 2) {
1601 if (physmap[i] == 0x00000000) {
1602 basemem = physmap[i + 1] / 1024;
1603 break;
1604 }
1605 }
1606
1607 if (basemem == 0) {
1608 basemem = 640;
1609 }
1610
1611 if (basemem > 640) {
1bda0d3d
MD
1612 kprintf("Preposterous BIOS basemem of %uK, "
1613 "truncating to 640K\n", basemem);
984263bc
MD
1614 basemem = 640;
1615 }
1616
1617 for (pa = trunc_page(basemem * 1024);
1618 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1619 pte = vtopte(pa + KERNBASE);
984263bc
MD
1620 *pte = pa | PG_RW | PG_V;
1621 }
1622
b5b32410 1623 pte = vm86paddr;
984263bc
MD
1624 for (i = basemem / 4; i < 160; i++)
1625 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1626 }
1627
1628 if (physmap[1] != 0)
1629 goto physmap_done;
1630
1631 /*
1632 * If we failed above, try memory map with INT 15:E801
1633 */
1634 vmf.vmf_ax = 0xE801;
1635 if (vm86_intcall(0x15, &vmf) == 0) {
1636 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1637 } else {
1638#if 0
1639 vmf.vmf_ah = 0x88;
1640 vm86_intcall(0x15, &vmf);
1641 extmem = vmf.vmf_ax;
1642#else
1643 /*
1644 * Prefer the RTC value for extended memory.
1645 */
1646 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1647#endif
1648 }
1649
1650 /*
1651 * Special hack for chipsets that still remap the 384k hole when
1652 * there's 16MB of memory - this really confuses people that
1653 * are trying to use bus mastering ISA controllers with the
1654 * "16MB limit"; they only have 16MB, but the remapping puts
1655 * them beyond the limit.
1656 *
1657 * If extended memory is between 15-16MB (16-17MB phys address range),
1658 * chop it to 15MB.
1659 */
1660 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1661 extmem = 15 * 1024;
1662
1663 physmap[0] = 0;
1664 physmap[1] = basemem * 1024;
1665 physmap_idx = 2;
1666 physmap[physmap_idx] = 0x100000;
1667 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1668
1669physmap_done:
1670 /*
1671 * Now, physmap contains a map of physical memory.
1672 */
1673
ed721f0f 1674 base_memory = physmap[1];
17a9f566 1675 /* make hole for AP bootstrap code YYY */
ed721f0f 1676 physmap[1] = mp_bootaddress(base_memory);
984263bc 1677
1876681a
SZ
1678 /* Save EBDA address, if any */
1679 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1680 ebda_addr <<= 4;
984263bc
MD
1681
1682 /*
1683 * Maxmem isn't the "maximum memory", it's one larger than the
1684 * highest page of the physical address space. It should be
1685 * called something like "Maxphyspage". We may adjust this
1686 * based on ``hw.physmem'' and the results of the memory test.
1687 */
1688 Maxmem = atop(physmap[physmap_idx + 1]);
1689
1690#ifdef MAXMEM
1691 Maxmem = MAXMEM / 4;
1692#endif
1693
555da584
MD
1694 if (kgetenv_quad("hw.physmem", &maxmem))
1695 Maxmem = atop(maxmem);
984263bc
MD
1696
1697 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1698 (boothowto & RB_VERBOSE))
26be20a0 1699 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1700
1701 /*
1702 * If Maxmem has been increased beyond what the system has detected,
1703 * extend the last memory segment to the new limit.
1704 */
1705 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1706 physmap[physmap_idx + 1] = ptoa(Maxmem);
1707
1708 /* call pmap initialization to make new kernel address space */
1709 pmap_bootstrap(first, 0);
1710
1711 /*
1712 * Size up each available chunk of physical memory.
1713 */
1714 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1715 pa_indx = 0;
b24cd69c 1716 da_indx = 1;
984263bc
MD
1717 phys_avail[pa_indx++] = physmap[0];
1718 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH
1719 dump_avail[da_indx] = physmap[0];
1720
b5b32410 1721 pte = CMAP1;
984263bc 1722
28abdbbb
HS
1723 /*
1724 * Get dcons buffer address
1725 */
bc01a404
MD
1726 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1727 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS
1728 dcons_addr = 0;
1729
984263bc
MD
1730 /*
1731 * physmap is in bytes, so when converting to page boundaries,
1732 * round up the start address and round down the end address.
1733 */
1734 for (i = 0; i <= physmap_idx; i += 2) {
1735 vm_offset_t end;
1736
1737 end = ptoa(Maxmem);
1738 if (physmap[i + 1] < end)
1739 end = trunc_page(physmap[i + 1]);
1740 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1741 int tmp, page_bad, full;
984263bc
MD
1742#if 0
1743 int *ptr = 0;
1744#else
1745 int *ptr = (int *)CADDR1;
1746#endif
b24cd69c 1747 full = FALSE;
984263bc
MD
1748
1749 /*
1750 * block out kernel memory as not available.
1751 */
1752 if (pa >= 0x100000 && pa < first)
b24cd69c 1753 goto do_dump_avail;
984263bc 1754
28abdbbb
HS
1755 /*
1756 * block out dcons buffer
1757 */
1758 if (dcons_addr > 0
1759 && pa >= trunc_page(dcons_addr)
1760 && pa < dcons_addr + dcons_size)
b24cd69c 1761 goto do_dump_avail;
28abdbbb 1762
984263bc
MD
1763 page_bad = FALSE;
1764
1765 /*
1766 * map page into kernel: valid, read/write,non-cacheable
1767 */
1768 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1769 cpu_invltlb();
984263bc
MD
1770
1771 tmp = *(int *)ptr;
1772 /*
1773 * Test for alternating 1's and 0's
1774 */
1775 *(volatile int *)ptr = 0xaaaaaaaa;
1776 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1777 page_bad = TRUE;
1778 }
1779 /*
1780 * Test for alternating 0's and 1's
1781 */
1782 *(volatile int *)ptr = 0x55555555;
1783 if (*(volatile int *)ptr != 0x55555555) {
1784 page_bad = TRUE;
1785 }
1786 /*
1787 * Test for all 1's
1788 */
1789 *(volatile int *)ptr = 0xffffffff;
1790 if (*(volatile int *)ptr != 0xffffffff) {
1791 page_bad = TRUE;
1792 }
1793 /*
1794 * Test for all 0's
1795 */
1796 *(volatile int *)ptr = 0x0;
1797 if (*(volatile int *)ptr != 0x0) {
1798 page_bad = TRUE;
1799 }
1800 /*
1801 * Restore original value.
1802 */
1803 *(int *)ptr = tmp;
1804
1805 /*
1806 * Adjust array of valid/good pages.
1807 */
1808 if (page_bad == TRUE) {
1809 continue;
1810 }
1811 /*
1812 * If this good page is a continuation of the
1813 * previous set of good pages, then just increase
1814 * the end pointer. Otherwise start a new chunk.
1815 * Note that "end" points one higher than end,
1816 * making the range >= start and < end.
1817 * If we're also doing a speculative memory
1818 * test and we at or past the end, bump up Maxmem
1819 * so that we keep going. The first bad page
1820 * will terminate the loop.
1821 */
1822 if (phys_avail[pa_indx] == pa) {
1823 phys_avail[pa_indx] += PAGE_SIZE;
1824 } else {
1825 pa_indx++;
ff1a75a1 1826 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1827 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1828 pa_indx--;
b24cd69c
AH
1829 full = TRUE;
1830 goto do_dump_avail;
984263bc
MD
1831 }
1832 phys_avail[pa_indx++] = pa; /* start */
1833 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1834 }
1835 physmem++;
b24cd69c
AH
1836do_dump_avail:
1837 if (dump_avail[da_indx] == pa) {
1838 dump_avail[da_indx] += PAGE_SIZE;
1839 } else {
1840 da_indx++;
1841 if (da_indx >= PHYSMAP_ENTRIES*2) {
1842 da_indx--;
1843 goto do_next;
1844 }
1845 dump_avail[da_indx++] = pa; /* start */
1846 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1847 }
1848do_next:
1849 if (full)
1850 break;
1851
984263bc
MD
1852 }
1853 }
1854 *pte = 0;
0f7a3396 1855 cpu_invltlb();
984263bc
MD
1856
1857 /*
1858 * XXX
1859 * The last chunk must contain at least one page plus the message
1860 * buffer to avoid complicating other code (message buffer address
1861 * calculation, etc.).
1862 */
1863 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1864 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1865 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1866 phys_avail[pa_indx--] = 0;
1867 phys_avail[pa_indx--] = 0;
1868 }
1869
1870 Maxmem = atop(phys_avail[pa_indx]);
1871
1872 /* Trim off space for the message buffer. */
1873 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1874
1875 avail_end = phys_avail[pa_indx];
1876}
1877
30c5f287
MN
1878struct machintr_abi MachIntrABI;
1879
f7bc9806
MD
1880/*
1881 * IDT VECTORS:
1882 * 0 Divide by zero
1883 * 1 Debug
1884 * 2 NMI
1885 * 3 BreakPoint
1886 * 4 OverFlow
1887 * 5 Bound-Range
1888 * 6 Invalid OpCode
1889 * 7 Device Not Available (x87)
1890 * 8 Double-Fault
1891 * 9 Coprocessor Segment overrun (unsupported, reserved)
1892 * 10 Invalid-TSS
1893 * 11 Segment not present
1894 * 12 Stack
1895 * 13 General Protection
1896 * 14 Page Fault
1897 * 15 Reserved
1898 * 16 x87 FP Exception pending
1899 * 17 Alignment Check
1900 * 18 Machine Check
1901 * 19 SIMD floating point
1902 * 20-31 reserved
1903 * 32-255 INTn/external sources
1904 */
984263bc 1905void
17a9f566 1906init386(int first)
984263bc
MD
1907{
1908 struct gate_descriptor *gdp;
1909 int gsel_tss, metadata_missing, off, x;
85100692 1910 struct mdglobaldata *gd;
984263bc
MD
1911
1912 /*
1913 * Prevent lowering of the ipl if we call tsleep() early.
1914 */
85100692 1915 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1916 bzero(gd, sizeof(*gd));
984263bc 1917
85100692 1918 gd->mi.gd_curthread = &thread0;
4e7c41c5 1919 thread0.td_gd = &gd->mi;
984263bc
MD
1920
1921 atdevbase = ISA_HOLE_START + KERNBASE;
1922
1923 metadata_missing = 0;
1924 if (bootinfo.bi_modulep) {
1925 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1926 preload_bootstrap_relocate(KERNBASE);
1927 } else {
1928 metadata_missing = 1;
1929 }
1930 if (bootinfo.bi_envp)
1931 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1932
27af435a
SZ
1933 if (boothowto & RB_VERBOSE)
1934 bootverbose++;
1935
30c5f287 1936 /*
10db3cc6 1937 * Default MachIntrABI to ICU
30c5f287
MN
1938 */
1939 MachIntrABI = MachIntrABI_ICU;
1e7aaefa 1940
d745d2b8
SZ
1941 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1942 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1d6d7089 1943 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
30c5f287 1944
e6dee928 1945 /*
08771751 1946 * Some of the virtual machines do not work w/ I/O APIC
e6dee928
SZ
1947 * enabled. If the user does not explicitly enable or
1948 * disable the I/O APIC (ioapic_enable < 0), then we
1949 * disable I/O APIC on all virtual machines.
1950 */
1951 if (ioapic_enable < 0) {
1952 if (cpu_feature2 & CPUID2_VMM)
1953 ioapic_enable = 0;
1954 else
1955 ioapic_enable = 1;
1956 }
1957
c5cc06e3 1958 /*
b45759e1
MD
1959 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1960 * and ncpus_fit_mask remain 0.
c5cc06e3 1961 */
4e8e646b 1962 ncpus = 1;
c5cc06e3 1963 ncpus2 = 1;
b45759e1 1964 ncpus_fit = 1;
984263bc
MD
1965 /* Init basic tunables, hz etc */
1966 init_param1();
1967
1968 /*
1969 * make gdt memory segments, the code segment goes up to end of the
1970 * page with etext in it, the data segment goes to the end of
1971 * the address space
1972 */
1973 /*
1974 * XXX text protection is temporarily (?) disabled. The limit was
1975 * i386_btop(round_page(etext)) - 1.
1976 */
1977 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1978 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1979
984263bc
MD
1980 gdt_segs[GPRIV_SEL].ssd_limit =
1981 atop(sizeof(struct privatespace) - 1);
8ad65e08 1982 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1983 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1984 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1985
85100692 1986 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1987
84b592ba
MD
1988 /*
1989 * Note: on both UP and SMP curthread must be set non-NULL
1990 * early in the boot sequence because the system assumes
1991 * that 'curthread' is never NULL.
1992 */
984263bc
MD
1993
1994 for (x = 0; x < NGDT; x++) {
1995#ifdef BDE_DEBUGGER
1996 /* avoid overwriting db entries with APM ones */
1997 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1998 continue;
1999#endif
2000 ssdtosd(&gdt_segs[x], &gdt[x].sd);
2001 }
2002
2003 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2004 r_gdt.rd_base = (int) gdt;
2005 lgdt(&r_gdt);
2006
73e4f7b9
MD
2007 mi_gdinit(&gd->mi, 0);
2008 cpu_gdinit(gd, 0);
6bf59cd2 2009 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 2010 safepri = TDPRI_MAX;
73e4f7b9 2011
984263bc
MD
2012 /* make ldt memory segments */
2013 /*
88181b08 2014 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD
2015 * should be spelled ...MAX_USER...
2016 */
88181b08
MD
2017 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
2018 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
b370aff7 2019 for (x = 0; x < NELEM(ldt_segs); x++)
984263bc
MD
2020 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2021
2022 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
2023 lldt(_default_ldt);
17a9f566 2024 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
2025 /* spinlocks and the BGL */
2026 init_locks();
984263bc 2027
2f839e54
MD
2028 /*
2029 * Setup the hardware exception table. Most exceptions use
2030 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
2031 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
2032 * an 'interrupt trap gate', which disables interrupts on entry,
2033 * in order to be able to poll the appropriate CRn register to
2034 * determine the fault address.
2035 */
f7bc9806
MD
2036 for (x = 0; x < NIDT; x++) {
2037#ifdef DEBUG_INTERRUPTS
2038 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2039#else
2040 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2041#endif
2042 }
984263bc
MD
2043 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2044 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2045 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2046 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2047 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2048 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2049 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2050 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2051 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2052 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2053 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2054 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2055 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2056 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2057 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 2058 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
2059 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2060 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2061 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2062 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2063 setidt(0x80, &IDTVEC(int0x80_syscall),
2064 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2065
2066 r_idt.rd_limit = sizeof(idt0) - 1;
2067 r_idt.rd_base = (int) idt;
2068 lidt(&r_idt);
2069
2070 /*
2071 * Initialize the console before we print anything out.
2072 */
2073 cninit();
2074
2075 if (metadata_missing)
26be20a0 2076 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 2077
984263bc 2078#if NISA >0
e24dd6e0 2079 elcr_probe();
984263bc
MD
2080 isa_defaultirq();
2081#endif
2082 rand_initialize();
2083
a3dd9120
SZ
2084 /*
2085 * Initialize IRQ mapping
2086 *
2087 * NOTE:
2088 * SHOULD be after elcr_probe()
2089 */
2090 MachIntrABI_ICU.initmap();
a3dd9120 2091 MachIntrABI_IOAPIC.initmap();
a3dd9120 2092
984263bc
MD
2093#ifdef DDB
2094 kdb_init();
2095 if (boothowto & RB_KDB)
2096 Debugger("Boot flags requested debugger");
2097#endif
2098
2099 finishidentcpu(); /* Final stage of CPU initialization */
2100 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2101 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2102 initializecpu(); /* Initialize CPU registers */
2103
b7c628e4
MD
2104 /*
2105 * make an initial tss so cpu can get interrupt stack on syscall!
2106 * The 16 bytes is to save room for a VM86 context.
2107 */
17a9f566
MD
2108 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
2109 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 2110 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
2111 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
2112 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 2113 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
2114 ltr(gsel_tss);
2115
2116 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2117 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
2118 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2119 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2120 dblfault_tss.tss_cr3 = (int)IdlePTD;
2121 dblfault_tss.tss_eip = (int) dblfault_handler;
2122 dblfault_tss.tss_eflags = PSL_KERNEL;
2123 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2124 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2125 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2126 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2127 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2128
2129 vm86_initialize();
2130 getmemsize(first);
2131 init_param2(physmem);
2132
2133 /* now running on new page tables, configured,and u/iom is accessible */
2134
2135 /* Map the message buffer. */
2136 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2137 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2138
2139 msgbufinit(msgbufp, MSGBUF_SIZE);
2140
2141 /* make a call gate to reenter kernel with */
2142 gdp = &ldt[LSYS5CALLS_SEL].gd;
2143
2144 x = (int) &IDTVEC(syscall);
2145 gdp->gd_looffset = x++;
2146 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2147 gdp->gd_stkcpy = 1;
2148 gdp->gd_type = SDT_SYS386CGT;
2149 gdp->gd_dpl = SEL_UPL;
2150 gdp->gd_p = 1;
2151 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2152
2153 /* XXX does this work? */
2154 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2155 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2156
2157 /* transfer to user mode */
2158
2159 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2160 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2161
2162 /* setup proc 0's pcb */
b7c628e4
MD
2163 thread0.td_pcb->pcb_flags = 0;
2164 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
d8061892 2165 thread0.td_pcb->pcb_ext = NULL;
08f2f1bb 2166 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD
2167}
2168
8ad65e08 2169/*
17a9f566
MD
2170 * Initialize machine-dependant portions of the global data structure.
2171 * Note that the global data area and cpu0's idlestack in the private
2172 * data space were allocated in locore.
ef0fdad1
MD
2173 *
2174 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2175 *
2176 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2177 */
2178void
85100692 2179cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2180{
7d0bac62 2181 if (cpu)
a2a5ad0d 2182 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2183
f470d0c8
MD
2184 lwkt_init_thread(&gd->mi.gd_idlethread,
2185 gd->mi.gd_prvspace->idlestack,
d3d32139 2186 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2187 0, &gd->mi);
a2a5ad0d
MD
2188 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2189 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2190 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2191 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2192}
2193
0cd275af
MD
2194int
2195is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2196{
2197 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2198 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2199 return (TRUE);
2200 }
2201 return (FALSE);
2202}
2203
12e4aaff
MD
2204struct globaldata *
2205globaldata_find(int cpu)
2206{
2207 KKASSERT(cpu >= 0 && cpu < ncpus);
2208 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2209}
2210
984263bc
MD
2211#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2212static void f00f_hack(void *unused);
ba39e2e0 2213SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD
2214
2215static void
17a9f566
MD
2216f00f_hack(void *unused)
2217{
984263bc 2218 struct gate_descriptor *new_idt;
984263bc
MD
2219 vm_offset_t tmp;
2220
2221 if (!has_f00f_bug)
2222 return;
2223
26be20a0 2224 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD
2225
2226 r_idt.rd_limit = sizeof(idt0) - 1;
2227
e4846942 2228 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD
2229 if (tmp == 0)
2230 panic("kmem_alloc returned 0");
2231 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2232 panic("kmem_alloc returned non-page-aligned memory");
2233 /* Put the first seven entries in the lower page */
2234 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2235 bcopy(idt, new_idt, sizeof(idt0));
2236 r_idt.rd_base = (int)new_idt;
2237 lidt(&r_idt);
2238 idt = new_idt;
e4846942 2239 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD
2240 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2241 panic("vm_map_protect failed");
2242 return;
2243}
2244#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2245
2246int
08f2f1bb 2247ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2248{
08f2f1bb 2249 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD
2250 return (0);
2251}
2252
2253int
e9182c58 2254ptrace_single_step(struct lwp *lp)
984263bc 2255{
e9182c58 2256 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD
2257 return (0);
2258}
2259
984263bc 2260int
e9182c58 2261fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2262{
984263bc
MD
2263 struct trapframe *tp;
2264
d64d3805
MD
2265 if ((tp = lp->lwp_md.md_regs) == NULL)
2266 return EINVAL;
4e7c41c5 2267 regs->r_gs = tp->tf_gs;
984263bc
MD
2268 regs->r_fs = tp->tf_fs;
2269 regs->r_es = tp->tf_es;
2270 regs->r_ds = tp->tf_ds;
2271 regs->r_edi = tp->tf_edi;
2272 regs->r_esi = tp->tf_esi;
2273 regs->r_ebp = tp->tf_ebp;
2274 regs->r_ebx = tp->tf_ebx;
2275 regs->r_edx = tp->tf_edx;
2276 regs->r_ecx = tp->tf_ecx;
2277 regs->r_eax = tp->tf_eax;
2278 regs->r_eip = tp->tf_eip;
2279 regs->r_cs = tp->tf_cs;
2280 regs->r_eflags = tp->tf_eflags;
2281 regs->r_esp = tp->tf_esp;
2282 regs->r_ss = tp->tf_ss;
984263bc
MD
2283 return (0);
2284}
2285
2286int
e9182c58 2287set_regs(struct lwp *lp, struct reg *regs)
984263bc 2288{
984263bc
MD
2289 struct trapframe *tp;
2290
e9182c58 2291 tp = lp->lwp_md.md_regs;
984263bc
MD
2292 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2293 !CS_SECURE(regs->r_cs))
2294 return (EINVAL);
4e7c41c5 2295 tp->tf_gs = regs->r_gs;
984263bc
MD
2296 tp->tf_fs = regs->r_fs;
2297 tp->tf_es = regs->r_es;
2298 tp->tf_ds = regs->r_ds;
2299 tp->tf_edi = regs->r_edi;
2300 tp->tf_esi = regs->r_esi;
2301 tp->tf_ebp = regs->r_ebp;
2302 tp->tf_ebx = regs->r_ebx;
2303 tp->tf_edx = regs->r_edx;
2304 tp->tf_ecx = regs->r_ecx;
2305 tp->tf_eax = regs->r_eax;
2306 tp->tf_eip = regs->r_eip;
2307 tp->tf_cs = regs->r_cs;
2308 tp->tf_eflags = regs->r_eflags;
2309 tp->tf_esp = regs->r_esp;
2310 tp->tf_ss = regs->r_ss;
984263bc
MD
2311 return (0);
2312}
2313
642a6e88 2314#ifndef CPU_DISABLE_SSE
984263bc 2315static void
f123d5a1 2316fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2317{
c9faf524
RG
2318 struct env87 *penv_87 = &sv_87->sv_env;
2319 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2320 int i;
2321
2322 /* FPU control/status */
2323 penv_87->en_cw = penv_xmm->en_cw;
2324 penv_87->en_sw = penv_xmm->en_sw;
2325 penv_87->en_tw = penv_xmm->en_tw;
2326 penv_87->en_fip = penv_xmm->en_fip;
2327 penv_87->en_fcs = penv_xmm->en_fcs;
2328 penv_87->en_opcode = penv_xmm->en_opcode;
2329 penv_87->en_foo = penv_xmm->en_foo;
2330 penv_87->en_fos = penv_xmm->en_fos;
2331
2332 /* FPU registers */
2333 for (i = 0; i < 8; ++i)
2334 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
984263bc
MD
2335}
2336
2337static void
f123d5a1 2338set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2339{
c9faf524
RG
2340 struct env87 *penv_87 = &sv_87->sv_env;
2341 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2342 int i;
2343
2344 /* FPU control/status */
2345 penv_xmm->en_cw = penv_87->en_cw;
2346 penv_xmm->en_sw = penv_87->en_sw;
2347 penv_xmm->en_tw = penv_87->en_tw;
2348 penv_xmm->en_fip = penv_87->en_fip;
2349 penv_xmm->en_fcs = penv_87->en_fcs;
2350 penv_xmm->en_opcode = penv_87->en_opcode;
2351 penv_xmm->en_foo = penv_87->en_foo;
2352 penv_xmm->en_fos = penv_87->en_fos;
2353
2354 /* FPU registers */
2355 for (i = 0; i < 8; ++i)
2356 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
984263bc 2357}
642a6e88 2358#endif /* CPU_DISABLE_SSE */
984263bc
MD
2359
2360int
e9182c58 2361fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2362{
d64d3805
MD
2363 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2364 return EINVAL;
642a6e88 2365#ifndef CPU_DISABLE_SSE
984263bc 2366 if (cpu_fxsr) {
e9182c58
SZ
2367 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2368 (struct save87 *)fpregs);
984263bc
MD
2369 return (0);
2370 }
642a6e88 2371#endif /* CPU_DISABLE_SSE */
e9182c58 2372 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2373 return (0);
2374}
2375
2376int
e9182c58 2377set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2378{
642a6e88 2379#ifndef CPU_DISABLE_SSE
984263bc
MD
2380 if (cpu_fxsr) {
2381 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2382 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD
2383 return (0);
2384 }
642a6e88 2385#endif /* CPU_DISABLE_SSE */
e9182c58 2386 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2387 return (0);
2388}
2389
2390int
e9182c58 2391fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2392{
d64d3805
MD
2393 struct pcb *pcb;
2394
e9182c58 2395 if (lp == NULL) {
984263bc
MD
2396 dbregs->dr0 = rdr0();
2397 dbregs->dr1 = rdr1();
2398 dbregs->dr2 = rdr2();
2399 dbregs->dr3 = rdr3();
2400 dbregs->dr4 = rdr4();
2401 dbregs->dr5 = rdr5();
2402 dbregs->dr6 = rdr6();
2403 dbregs->dr7 = rdr7();
d64d3805
MD
2404 return (0);
2405 }
2406 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2407 return EINVAL;
2408 dbregs->dr0 = pcb->pcb_dr0;
2409 dbregs->dr1 = pcb->pcb_dr1;
2410 dbregs->dr2 = pcb->pcb_dr2;
2411 dbregs->dr3 = pcb->pcb_dr3;
2412 dbregs->dr4 = 0;
2413 dbregs->dr5 = 0;
2414 dbregs->dr6 = pcb->pcb_dr6;
2415 dbregs->dr7 = pcb->pcb_dr7;
984263bc
MD
2416 return (0);
2417}
2418
2419int
e9182c58 2420set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2421{
e9182c58 2422 if (lp == NULL) {
984263bc
MD
2423 load_dr0(dbregs->dr0);
2424 load_dr1(dbregs->dr1);
2425 load_dr2(dbregs->dr2);
2426 load_dr3(dbregs->dr3);
2427 load_dr4(dbregs->dr4);
2428 load_dr5(dbregs->dr5);
2429 load_dr6(dbregs->dr6);
2430 load_dr7(dbregs->dr7);
e9182c58
SZ
2431 } else {
2432 struct pcb *pcb;
2433 struct ucred *ucred;
2434 int i;
2435 uint32_t mask1, mask2;
2436
984263bc
MD
2437 /*
2438 * Don't let an illegal value for dr7 get set. Specifically,
2439 * check for undefined settings. Setting these bit patterns
2440 * result in undefined behaviour and can lead to an unexpected
2441 * TRCTRAP.
2442 */
2443 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2444 i++, mask1 <<= 2, mask2 <<= 2)
2445 if ((dbregs->dr7 & mask1) == mask2)
2446 return (EINVAL);
2447
e9182c58
SZ
2448 pcb = lp->lwp_thread->td_pcb;
2449 ucred = lp->lwp_proc->p_ucred;
2450
984263bc
MD
2451 /*
2452 * Don't let a process set a breakpoint that is not within the
2453 * process's address space. If a process could do this, it
2454 * could halt the system by setting a breakpoint in the kernel
2455 * (if ddb was enabled). Thus, we need to check to make sure
2456 * that no breakpoints are being enabled for addresses outside
2457 * process's address space, unless, perhaps, we were called by
2458 * uid 0.
2459 *
2460 * XXX - what about when the watched area of the user's
2461 * address space is written into from within the kernel
2462 * ... wouldn't that still cause a breakpoint to be generated
2463 * from within kernel mode?
2464 */
e9182c58 2465
895c1f85 2466 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD
2467 if (dbregs->dr7 & 0x3) {
2468 /* dr0 is enabled */
88181b08 2469 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2470 return (EINVAL);
2471 }
e9182c58 2472
984263bc
MD
2473 if (dbregs->dr7 & (0x3<<2)) {
2474 /* dr1 is enabled */
88181b08 2475 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2476 return (EINVAL);
2477 }
e9182c58 2478
984263bc
MD
2479 if (dbregs->dr7 & (0x3<<4)) {
2480 /* dr2 is enabled */
88181b08 2481 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2482 return (EINVAL);
2483 }
e9182c58 2484
984263bc
MD
2485 if (dbregs->dr7 & (0x3<<6)) {
2486 /* dr3 is enabled */
88181b08 2487 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2488 return (EINVAL);
2489 }
2490 }
e9182c58 2491
984263bc
MD
2492 pcb->pcb_dr0 = dbregs->dr0;
2493 pcb->pcb_dr1 = dbregs->dr1;
2494 pcb->pcb_dr2 = dbregs->dr2;
2495 pcb->pcb_dr3 = dbregs->dr3;
2496 pcb->pcb_dr6 = dbregs->dr6;
2497 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2498
984263bc
MD
2499 pcb->pcb_flags |= PCB_DBREGS;
2500 }
2501
2502 return (0);
2503}
2504
2505/*
2506 * Return > 0 if a hardware breakpoint has been hit, and the
2507 * breakpoint was in user space. Return 0, otherwise.
2508 */
2509int
2510user_dbreg_trap(void)
2511{
2512 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2513 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2514 int nbp; /* number of breakpoints that triggered */
2515 caddr_t addr[4]; /* breakpoint addresses */
2516 int i;
2517
2518 dr7 = rdr7();
2519 if ((dr7 & 0x000000ff) == 0) {
2520 /*
2521 * all GE and LE bits in the dr7 register are zero,
2522 * thus the trap couldn't have been caused by the
2523 * hardware debug registers
2524 */
2525 return 0;
2526 }
2527
2528 nbp = 0;
2529 dr6 = rdr6();
2530 bp = dr6 & 0x0000000f;
2531
2532 if (!bp) {
2533 /*
2534 * None of the breakpoint bits are set meaning this
2535 * trap was not caused by any of the debug registers
2536 */
2537 return 0;
2538 }
2539
2540 /*
2541 * at least one of the breakpoints were hit, check to see
2542 * which ones and if any of them are user space addresses
2543 */
2544
2545 if (bp & 0x01) {
2546 addr[nbp++] = (caddr_t)rdr0();
2547 }
2548 if (bp & 0x02) {
2549 addr[nbp++] = (caddr_t)rdr1();
2550 }
2551 if (bp & 0x04) {
2552 addr[nbp++] = (caddr_t)rdr2();
2553 }
2554 if (bp & 0x08) {
2555 addr[nbp++] = (caddr_t)rdr3();
2556 }
2557
2558 for (i=0; i<nbp; i++) {
2559 if (addr[i] <
88181b08 2560 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD
2561 /*
2562 * addr[i] is in user space
2563 */
2564 return nbp;
2565 }
2566 }
2567
2568 /*
2569 * None of the breakpoints are in user space.
2570 */
2571 return 0;
2572}
2573
2574
2575#ifndef DDB
2576void
2577Debugger(const char *msg)
2578{
26be20a0 2579 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD
2580}
2581#endif /* no DDB */
2582
984263bc
MD
2583#ifdef DDB
2584
2585/*
2586 * Provide inb() and outb() as functions. They are normally only
2587 * available as macros calling inlined functions, thus cannot be
2588 * called inside DDB.
2589 *
2590 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2591 */
2592
2593#undef inb
2594#undef outb
2595
2596/* silence compiler warnings */
2597u_char inb(u_int);
2598void outb(u_int, u_char);
2599
2600u_char
2601inb(u_int port)
2602{
2603 u_char data;
2604 /*
2605 * We use %%dx and not %1 here because i/o is done at %dx and not at
2606 * %edx, while gcc generates inferior code (movw instead of movl)
2607 * if we tell it to load (u_short) port.
2608 */
2609 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2610 return (data);
2611}
2612
2613void
2614outb(u_int port, u_char data)
2615{
2616 u_char al;
2617 /*
2618 * Use an unnecessary assignment to help gcc's register allocator.
2619 * This make a large difference for gcc-1.40 and a tiny difference
2620 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2621 * best results. gcc-2.6.0 can't handle this.
2622 */
2623 al = data;
2624 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2625}
2626
2627#endif /* DDB */
8a8d5d85
MD
2628
2629
2630
2631#include "opt_cpu.h"
8a8d5d85
MD
2632
2633
2634/*
2635 * initialize all the SMP locks
2636 */
2637
97359a5b 2638/* critical region when masking or unmasking interupts */
b1af91cb 2639struct spinlock_deprecated imen_spinlock;
8a8d5d85 2640
8a8d5d85 2641/* critical region for old style disable_intr/enable_intr */
b1af91cb 2642struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD
2643
2644/* critical region around INTR() routines */
b1af91cb 2645struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD
2646
2647/* lock region used by kernel profiling */
b1af91cb 2648struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD
2649
2650/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2651struct spinlock_deprecated com_spinlock;
8a8d5d85 2652
8a8d5d85 2653/* lock regions around the clock hardware */
b1af91cb 2654struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD
2655
2656/* lock around the MP rendezvous */
b1af91cb 2657struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD
2658
2659static void
2660init_locks(void)
2661{
2662 /*
b5d16701 2663 * Get the initial mplock with a count of 1 for the BSP.
8a8d5d85
MD
2664 * This uses a LOGICAL cpu ID, ie BSP == 0.
2665 */
8a8d5d85 2666 cpu_get_initial_mplock();
41a01a4d 2667 /* DEPRECATED */
8a8d5d85 2668 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD
2669 spin_lock_init(&intr_spinlock);
2670 spin_lock_init(&mpintr_spinlock);
2671 spin_lock_init(&imen_spinlock);
2672 spin_lock_init(&smp_rv_spinlock);
2673 spin_lock_init(&com_spinlock);
2674 spin_lock_init(&clock_spinlock);
41a01a4d
MD
2675
2676 /* our token pool needs to work early */
2677 lwkt_token_pool_init();
8a8d5d85 2678}