kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / pc32 / include / intr_machdep.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
34 */
35
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36#ifndef _ARCH_ISA_INTR_MACHDEP_H_
37#define _ARCH_ISA_INTR_MACHDEP_H_
984263bc 38
8a8d5d85 39#ifndef LOCORE
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40#ifndef _SYS_TYPES_H_
41#include <sys/types.h>
e9cb6d99 42#endif
8a8d5d85 43#endif
ef0fdad1 44
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45/*
46 * Low level interrupt code.
47 */
48
49#ifdef _KERNEL
50
507bf37b 51#define IDT_OFFSET 0x20
9caf58d7 52#define IDT_OFFSET_SYSCALL 0x80
507bf37b 53#define IDT_OFFSET_IPI 0xe0
5f456c40 54
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55#define IDT_HWI_VECTORS (IDT_OFFSET_IPI - IDT_OFFSET)
56
984263bc 57/*
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58 * Local APIC TPR priority vector levels:
59 *
60 * 0xff (255) +-------------+
61 * | | 15 (IPIs: Xcpustop, Xspuriousint)
62 * 0xf0 (240) +-------------+
63 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
64 * 0xe0 (224) +-------------+
65 * | | 13
66 * 0xd0 (208) +-------------+
67 * | | 12
68 * 0xc0 (192) +-------------+
69 * | | 11
70 * 0xb0 (176) +-------------+
71 * | | 10
72 * 0xa0 (160) +-------------+
73 * | | 9
74 * 0x90 (144) +-------------+
75 * | | 8 (syscall at 0x80)
76 * 0x80 (128) +-------------+
77 * | | 7
78 * 0x70 (112) +-------------+
79 * | | 6
80 * 0x60 (96) +-------------+
81 * | | 5
82 * 0x50 (80) +-------------+
83 * | | 4
84 * 0x40 (64) +-------------+
85 * | | 3
86 * 0x30 (48) +-------------+
87e3ca2d 87 * | | 2 (hardware INTs)
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88 * 0x20 (32) +-------------+
89 * | | 1 (exceptions, traps, etc.)
90 * 0x10 (16) +-------------+
91 * | | 0 (exceptions, traps, etc.)
92 * 0x00 (0) +-------------+
984263bc 93 */
507bf37b 94#define TPR_STEP 0x10
984263bc 95
6ab7c3af 96/* Local APIC Task Priority Register */
507bf37b 97#define TPR_IPI (IDT_OFFSET_IPI - 1)
984263bc 98
984263bc 99
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100/*
101 * IPI group1
102 */
103#define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
104
105/* TLB shootdowns */
106#define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
984263bc 107
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108/* IPI group1 1: unused (was inter-cpu clock handling) */
109/* IPI group1 2: unused (was inter-cpu rendezvous) */
984263bc 110
5971ceae 111/* IPIQ */
507bf37b 112#define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
96728c05 113
5971ceae 114/* Local APIC TIMER */
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115#define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
116
117/* IPI group1 5 ~ 15: unused */
78ea5a2a 118
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119
120/*
507bf37b 121 * IPI group2
984263bc 122 */
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123#define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
124
125/* IPI to signal CPUs to stop and wait for another CPU to restart them */
126#define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
127
128/* IPI group2 1 ~ 14: unused */
129
130/* NOTE: this vector MUST be xxxx1111 */
131#define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
984263bc 132
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133#ifndef LOCORE
134
135/*
136 * Type of the first (asm) part of an interrupt handler.
137 */
ef0fdad1 138typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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139
140#define IDTVEC(name) __CONCAT(X,name)
141
984263bc 142inthand_t
984263bc 143 Xspuriousint, /* handle APIC "spurious INTs" */
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144 Xtimer; /* handle LAPIC timer INT */
145
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146inthand_t
147 Xcpustop, /* CPU stops & waits for another CPU to restart it */
148 Xinvltlb, /* TLB shootdowns */
6819df07 149 Xipiq; /* handle lwkt_send_ipiq() requests */
984263bc 150
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151#endif /* LOCORE */
152
153#endif /* _KERNEL */
154
f8334305 155#endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */