kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / pc32 / isa / clock.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 */
39
40/*
41 * Routines to handle clock hardware.
42 */
43
44/*
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47 *
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 */
50
1f2de5d4 51#include "use_apm.h"
984263bc 52#include "opt_clock.h"
984263bc
MD
53
54#include <sys/param.h>
55#include <sys/systm.h>
13194089 56#include <sys/eventhandler.h>
984263bc
MD
57#include <sys/time.h>
58#include <sys/kernel.h>
e126caf1 59#include <sys/bus.h>
984263bc
MD
60#include <sys/sysctl.h>
61#include <sys/cons.h>
88c4d2f6
MD
62#include <sys/systimer.h>
63#include <sys/globaldata.h>
64#include <sys/thread2.h>
65#include <sys/systimer.h>
37e7efec 66#include <sys/machintr.h>
1b505979 67#include <sys/interrupt.h>
984263bc
MD
68
69#include <machine/clock.h>
70#ifdef CLK_CALIBRATION_LOOP
71#endif
72#include <machine/cputypes.h>
73#include <machine/frame.h>
74#include <machine/ipl.h>
75#include <machine/limits.h>
76#include <machine/md_var.h>
77#include <machine/psl.h>
984263bc 78#include <machine/segments.h>
984263bc 79#include <machine/smp.h>
984263bc
MD
80#include <machine/specialreg.h>
81
ed4d621d 82#include <machine_base/apic/ioapic.h>
6b809ec7 83#include <machine_base/apic/ioapic_abi.h>
a9295349 84#include <machine_base/icu/icu.h>
21ce0dfa 85#include <bus/isa/isa.h>
1f2de5d4 86#include <bus/isa/rtc.h>
a9295349 87#include <machine_base/isa/timerreg.h>
984263bc 88
87cf6827 89#include <machine/intr_machdep.h>
984263bc 90
88c4d2f6 91static void i8254_restore(void);
e63ac55d 92static void resettodr_on_shutdown(void *arg __unused);
984263bc
MD
93
94/*
95 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
96 * can use a simple formula for leap years.
97 */
98#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
99#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
100
88c4d2f6
MD
101#ifndef TIMER_FREQ
102#define TIMER_FREQ 1193182
103#endif
984263bc 104
e54beab0
JS
105static uint8_t i8254_walltimer_sel;
106static uint16_t i8254_walltimer_cntr;
984263bc
MD
107
108int adjkerntz; /* local offset from GMT in seconds */
984263bc 109int disable_rtc_set; /* disable resettodr() if != 0 */
8b3ec75a 110int tsc_present;
374133e3 111int64_t tsc_frequency;
984263bc
MD
112int tsc_is_broken;
113int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
88c4d2f6
MD
114int timer0_running;
115enum tstate { RELEASED, ACQUIRED };
116enum tstate timer0_state;
117enum tstate timer1_state;
118enum tstate timer2_state;
984263bc
MD
119
120static int beeping = 0;
984263bc 121static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
984263bc
MD
122static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
123static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
e63ac55d 124static int rtc_loaded;
984263bc 125
1636ba19
MD
126static int i8254_cputimer_div;
127
ef612539 128static int i8254_nointr;
4d517764 129static int i8254_intr_disable = 1;
e87376d9
SZ
130TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
131
b02bbab0
JS
132static struct callout sysbeepstop_ch;
133
044ee7c4
MD
134static sysclock_t i8254_cputimer_count(void);
135static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
136static void i8254_cputimer_destruct(struct cputimer *cputimer);
137
138static struct cputimer i8254_cputimer = {
d8fdd978 139 SLIST_ENTRY_INITIALIZER,
044ee7c4
MD
140 "i8254",
141 CPUTIMER_PRI_8254,
142 0,
143 i8254_cputimer_count,
144 cputimer_default_fromhz,
145 cputimer_default_fromus,
146 i8254_cputimer_construct,
147 i8254_cputimer_destruct,
148 TIMER_FREQ,
5ee041ae 149 0, 0, 0
044ee7c4
MD
150};
151
ef612539
SZ
152static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
153static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
154static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
155
156static struct cputimer_intr i8254_cputimer_intr = {
157 .freq = TIMER_FREQ,
158 .reload = i8254_intr_reload,
159 .enable = cputimer_intr_default_enable,
160 .config = i8254_intr_config,
161 .restart = cputimer_intr_default_restart,
162 .pmfixup = cputimer_intr_default_pmfixup,
163 .initclock = i8254_intr_initclock,
164 .next = SLIST_ENTRY_INITIALIZER,
165 .name = "i8254",
166 .type = CPUTIMER_INTR_8254,
167 .prio = CPUTIMER_INTR_PRIO_8254,
168 .caps = CPUTIMER_INTR_CAP_PS
169};
170
88c4d2f6
MD
171/*
172 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
173 * counting as of this interrupt. We use timer1 in free-running mode (not
174 * generating any interrupts) as our main counter. Each cpu has timeouts
175 * pending.
ec4812b0
MD
176 *
177 * This code is INTR_MPSAFE and may be called without the BGL held.
88c4d2f6 178 */
984263bc 179static void
477d3c1c 180clkintr(void *dummy, void *frame_arg)
984263bc 181{
ec4812b0 182 static sysclock_t sysclock_count; /* NOTE! Must be static */
88c4d2f6
MD
183 struct globaldata *gd = mycpu;
184 struct globaldata *gscan;
185 int n;
9a47427a 186
b505872f 187 /*
88c4d2f6 188 * SWSTROBE mode is a one-shot, the timer is no longer running
b505872f 189 */
88c4d2f6 190 timer0_running = 0;
b505872f 191
88c4d2f6 192 /*
774fc796
MD
193 * XXX the dispatcher needs work. right now we call systimer_intr()
194 * directly or via IPI for any cpu with systimers queued, which is
ec4812b0 195 * usually *ALL* of them. We need to use the LAPIC timer for this.
88c4d2f6 196 */
ec4812b0 197 sysclock_count = sys_cputimer->count();
88c4d2f6
MD
198 for (n = 0; n < ncpus; ++n) {
199 gscan = globaldata_find(n);
774fc796 200 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
88c4d2f6
MD
201 continue;
202 if (gscan != gd) {
b8a98473 203 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
96d52ac8 204 &sysclock_count, 1);
88c4d2f6 205 } else {
ec4812b0 206 systimer_intr(&sysclock_count, 0, frame_arg);
88c4d2f6 207 }
984263bc 208 }
984263bc
MD
209}
210
88c4d2f6 211
984263bc 212/*
88c4d2f6 213 * NOTE! not MP safe.
984263bc 214 */
984263bc
MD
215int
216acquire_timer2(int mode)
217{
984263bc
MD
218 if (timer2_state != RELEASED)
219 return (-1);
220 timer2_state = ACQUIRED;
221
222 /*
223 * This access to the timer registers is as atomic as possible
224 * because it is a single instruction. We could do better if we
88c4d2f6 225 * knew the rate.
984263bc
MD
226 */
227 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
984263bc
MD
228 return (0);
229}
230
231int
09e6e929 232release_timer2(void)
984263bc 233{
984263bc
MD
234 if (timer2_state != ACQUIRED)
235 return (-1);
984263bc 236 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
88c4d2f6 237 timer2_state = RELEASED;
984263bc
MD
238 return (0);
239}
240
984263bc
MD
241#include "opt_ddb.h"
242#ifdef DDB
243#include <ddb/ddb.h>
244
245DB_SHOW_COMMAND(rtc, rtc)
246{
26be20a0 247 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
984263bc
MD
248 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
249 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
250 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
251}
252#endif /* DDB */
253
88c4d2f6
MD
254/*
255 * Return the current cpu timer count as a 32 bit integer.
256 */
044ee7c4 257static
88c4d2f6 258sysclock_t
044ee7c4 259i8254_cputimer_count(void)
88c4d2f6 260{
88c4d2f6
MD
261 static __uint16_t cputimer_last;
262 __uint16_t count;
263 sysclock_t ret;
984263bc 264
88c4d2f6 265 clock_lock();
e54beab0
JS
266 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
267 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
268 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
88c4d2f6
MD
269 count = -count; /* -> countup */
270 if (count < cputimer_last) /* rollover */
044ee7c4
MD
271 i8254_cputimer.base += 0x00010000;
272 ret = i8254_cputimer.base | count;
88c4d2f6 273 cputimer_last = count;
8a8d5d85 274 clock_unlock();
88c4d2f6
MD
275 return(ret);
276}
277
1636ba19
MD
278/*
279 * This function is called whenever the system timebase changes, allowing
280 * us to calculate what is needed to convert a system timebase tick
281 * into an 8254 tick for the interrupt timer. If we can convert to a
282 * simple shift, multiplication, or division, we do so. Otherwise 64
283 * bit arithmatic is required every time the interrupt timer is reloaded.
284 */
ef612539
SZ
285static void
286i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
1636ba19
MD
287{
288 int freq;
289 int div;
290
291 /*
292 * Will a simple divide do the trick?
293 */
ef612539
SZ
294 div = (timer->freq + (cti->freq / 2)) / cti->freq;
295 freq = cti->freq * div;
1636ba19
MD
296
297 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
298 i8254_cputimer_div = div;
299 else
300 i8254_cputimer_div = 0;
301}
302
88c4d2f6
MD
303/*
304 * Reload for the next timeout. It is possible for the reload value
305 * to be 0 or negative, indicating that an immediate timer interrupt
306 * is desired. For now make the minimum 2 ticks.
1636ba19
MD
307 *
308 * We may have to convert from the system timebase to the 8254 timebase.
88c4d2f6 309 */
c5c70fac 310static void
ef612539 311i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
88c4d2f6
MD
312{
313 __uint16_t count;
314
1636ba19
MD
315 if (i8254_cputimer_div)
316 reload /= i8254_cputimer_div;
317 else
ef612539 318 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
5ee041ae 319
88c4d2f6
MD
320 if ((int)reload < 2)
321 reload = 2;
322
323 clock_lock();
324 if (timer0_running) {
325 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
326 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
327 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
328 if (reload < count) {
329 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
330 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
331 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
332 }
333 } else {
334 timer0_running = 1;
335 if (reload > 0xFFFF)
336 reload = 0; /* full count */
337 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
338 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
339 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
340 }
341 clock_unlock();
984263bc
MD
342}
343
344/*
dbcd0c9b
MD
345 * DELAY(usec) - Spin for the specified number of microseconds.
346 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
347 * but do a thread switch in the loop
348 *
88c4d2f6 349 * Relies on timer 1 counting down from (cputimer_freq / hz)
984263bc
MD
350 * Note: timer had better have been programmed before this is first used!
351 */
dbcd0c9b
MD
352static void
353DODELAY(int n, int doswitch)
984263bc
MD
354{
355 int delta, prev_tick, tick, ticks_left;
356
357#ifdef DELAYDEBUG
358 int getit_calls = 1;
359 int n1;
360 static int state = 0;
361
362 if (state == 0) {
363 state = 1;
364 for (n1 = 1; n1 <= 10000000; n1 *= 10)
365 DELAY(n1);
366 state = 2;
367 }
368 if (state == 1)
26be20a0 369 kprintf("DELAY(%d)...", n);
984263bc
MD
370#endif
371 /*
372 * Guard against the timer being uninitialized if we are called
373 * early for console i/o.
374 */
88c4d2f6
MD
375 if (timer0_state == RELEASED)
376 i8254_restore();
984263bc
MD
377
378 /*
379 * Read the counter first, so that the rest of the setup overhead is
1636ba19
MD
380 * counted. Then calculate the number of hardware timer ticks
381 * required, rounding up to be sure we delay at least the requested
382 * number of microseconds.
984263bc 383 */
044ee7c4 384 prev_tick = sys_cputimer->count();
1636ba19
MD
385 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
386 1000000;
387
984263bc 388 /*
1636ba19 389 * Loop until done.
984263bc 390 */
984263bc 391 while (ticks_left > 0) {
044ee7c4 392 tick = sys_cputimer->count();
984263bc
MD
393#ifdef DELAYDEBUG
394 ++getit_calls;
395#endif
88c4d2f6 396 delta = tick - prev_tick;
984263bc 397 prev_tick = tick;
88c4d2f6
MD
398 if (delta < 0)
399 delta = 0;
984263bc 400 ticks_left -= delta;
dbcd0c9b
MD
401 if (doswitch && ticks_left > 0)
402 lwkt_switch();
c5724852 403 cpu_pause();
984263bc
MD
404 }
405#ifdef DELAYDEBUG
406 if (state == 1)
26be20a0 407 kprintf(" %d calls to getit() at %d usec each\n",
984263bc
MD
408 getit_calls, (n + 5) / getit_calls);
409#endif
410}
411
77912481
MD
412/*
413 * DELAY() never switches
414 */
dbcd0c9b
MD
415void
416DELAY(int n)
417{
418 DODELAY(n, 0);
419}
420
d8129ed3
MD
421int
422CHECKTIMEOUT(TOTALDELAY *tdd)
423{
424 sysclock_t delta;
425 int us;
426
427 if (tdd->started == 0) {
428 if (timer0_state == RELEASED)
429 i8254_restore();
430 tdd->last_clock = sys_cputimer->count();
431 tdd->started = 1;
432 return(0);
433 }
434 delta = sys_cputimer->count() - tdd->last_clock;
435 us = (u_int64_t)delta * (u_int64_t)1000000 /
436 (u_int64_t)sys_cputimer->freq;
437 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
438 1000000;
439 tdd->us -= us;
440 return (tdd->us < 0);
441}
442
77912481
MD
443/*
444 * DRIVERSLEEP() does not switch if called with a spinlock held or
445 * from a hard interrupt.
446 */
dbcd0c9b
MD
447void
448DRIVERSLEEP(int usec)
449{
450 globaldata_t gd = mycpu;
451
0846e4ce 452 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
dbcd0c9b
MD
453 DODELAY(usec, 0);
454 } else {
455 DODELAY(usec, 1);
456 }
457}
458
984263bc
MD
459static void
460sysbeepstop(void *chan)
461{
462 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
984263bc 463 beeping = 0;
88c4d2f6 464 release_timer2();
984263bc
MD
465}
466
467int
468sysbeep(int pitch, int period)
469{
984263bc 470 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
88c4d2f6 471 return(-1);
7caeaffe
MD
472 if (sysbeep_enable == 0)
473 return(-1);
88c4d2f6
MD
474 /*
475 * Nobody else is using timer2, we do not need the clock lock
476 */
984263bc
MD
477 outb(TIMER_CNTR2, pitch);
478 outb(TIMER_CNTR2, (pitch>>8));
984263bc
MD
479 if (!beeping) {
480 /* enable counter2 output to speaker */
481 outb(IO_PPI, inb(IO_PPI) | 3);
482 beeping = period;
b02bbab0 483 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
984263bc 484 }
984263bc
MD
485 return (0);
486}
487
488/*
489 * RTC support routines
490 */
491
492int
09e6e929 493rtcin(int reg)
984263bc 494{
984263bc
MD
495 u_char val;
496
9acd5bbb 497 crit_enter();
984263bc
MD
498 outb(IO_RTC, reg);
499 inb(0x84);
500 val = inb(IO_RTC + 1);
501 inb(0x84);
9acd5bbb 502 crit_exit();
984263bc
MD
503 return (val);
504}
505
506static __inline void
507writertc(u_char reg, u_char val)
508{
9acd5bbb 509 crit_enter();
984263bc
MD
510 inb(0x84);
511 outb(IO_RTC, reg);
512 inb(0x84);
513 outb(IO_RTC + 1, val);
514 inb(0x84); /* XXX work around wrong order in rtcin() */
9acd5bbb 515 crit_exit();
984263bc
MD
516}
517
518static __inline int
519readrtc(int port)
520{
521 return(bcd2bin(rtcin(port)));
522}
523
524static u_int
525calibrate_clocks(void)
526{
527 u_int64_t old_tsc;
528 u_int count, prev_count, tot_count;
529 int sec, start_sec, timeout;
530
531 if (bootverbose)
26be20a0 532 kprintf("Calibrating clock(s) ... ");
984263bc
MD
533 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
534 goto fail;
535 timeout = 100000000;
536
537 /* Read the mc146818A seconds counter. */
538 for (;;) {
539 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
540 sec = rtcin(RTC_SEC);
541 break;
542 }
543 if (--timeout == 0)
544 goto fail;
545 }
546
547 /* Wait for the mC146818A seconds counter to change. */
548 start_sec = sec;
549 for (;;) {
550 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
551 sec = rtcin(RTC_SEC);
552 if (sec != start_sec)
553 break;
554 }
555 if (--timeout == 0)
556 goto fail;
557 }
558
559 /* Start keeping track of the i8254 counter. */
044ee7c4 560 prev_count = sys_cputimer->count();
984263bc
MD
561 tot_count = 0;
562
563 if (tsc_present)
564 old_tsc = rdtsc();
565 else
566 old_tsc = 0; /* shut up gcc */
567
568 /*
569 * Wait for the mc146818A seconds counter to change. Read the i8254
570 * counter for each iteration since this is convenient and only
571 * costs a few usec of inaccuracy. The timing of the final reads
572 * of the counters almost matches the timing of the initial reads,
573 * so the main cause of inaccuracy is the varying latency from
574 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
575 * rtcin(RTC_SEC) that returns a changed seconds count. The
576 * maximum inaccuracy from this cause is < 10 usec on 486's.
577 */
578 start_sec = sec;
579 for (;;) {
580 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
581 sec = rtcin(RTC_SEC);
044ee7c4 582 count = sys_cputimer->count();
88c4d2f6 583 tot_count += (int)(count - prev_count);
984263bc
MD
584 prev_count = count;
585 if (sec != start_sec)
586 break;
587 if (--timeout == 0)
588 goto fail;
589 }
590
591 /*
592 * Read the cpu cycle counter. The timing considerations are
593 * similar to those for the i8254 clock.
594 */
374133e3
MD
595 if (tsc_present) {
596 tsc_frequency = rdtsc() - old_tsc;
374133e3 597 }
984263bc 598
c17827b4 599 if (tsc_present)
870b0161 600 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
26be20a0 601 kprintf("i8254 clock: %u Hz\n", tot_count);
984263bc
MD
602 return (tot_count);
603
604fail:
26be20a0 605 kprintf("failed, using default i8254 clock of %u Hz\n",
044ee7c4
MD
606 i8254_cputimer.freq);
607 return (i8254_cputimer.freq);
984263bc
MD
608}
609
610static void
611i8254_restore(void)
612{
88c4d2f6 613 timer0_state = ACQUIRED;
e54beab0 614
044ee7c4
MD
615 clock_lock();
616
617 /*
618 * Timer0 is our fine-grained variable clock interrupt
619 */
620 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
621 outb(TIMER_CNTR0, 2); /* lsb */
622 outb(TIMER_CNTR0, 0); /* msb */
ee31250e 623 clock_unlock();
044ee7c4 624
ef612539
SZ
625 if (!i8254_nointr) {
626 cputimer_intr_register(&i8254_cputimer_intr);
627 cputimer_intr_select(&i8254_cputimer_intr, 0);
628 }
629
044ee7c4
MD
630 /*
631 * Timer1 or timer2 is our free-running clock, but only if another
632 * has not been selected.
633 */
5ee041ae
MD
634 cputimer_register(&i8254_cputimer);
635 cputimer_select(&i8254_cputimer, 0);
044ee7c4
MD
636}
637
638static void
639i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
640{
641 int which;
642
643 /*
644 * Should we use timer 1 or timer 2 ?
645 */
646 which = 0;
647 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
648 if (which != 1 && which != 2)
649 which = 2;
650
651 switch(which) {
652 case 1:
653 timer->name = "i8254_timer1";
654 timer->type = CPUTIMER_8254_SEL1;
e54beab0
JS
655 i8254_walltimer_sel = TIMER_SEL1;
656 i8254_walltimer_cntr = TIMER_CNTR1;
657 timer1_state = ACQUIRED;
044ee7c4
MD
658 break;
659 case 2:
660 timer->name = "i8254_timer2";
661 timer->type = CPUTIMER_8254_SEL2;
e54beab0
JS
662 i8254_walltimer_sel = TIMER_SEL2;
663 i8254_walltimer_cntr = TIMER_CNTR2;
664 timer2_state = ACQUIRED;
044ee7c4 665 break;
e54beab0 666 }
044ee7c4
MD
667
668 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
669
ee31250e 670 clock_lock();
e54beab0
JS
671 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
672 outb(i8254_walltimer_cntr, 0); /* lsb */
673 outb(i8254_walltimer_cntr, 0); /* msb */
88c4d2f6 674 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
ee31250e 675 clock_unlock();
044ee7c4
MD
676}
677
678static void
679i8254_cputimer_destruct(struct cputimer *timer)
680{
681 switch(timer->type) {
682 case CPUTIMER_8254_SEL1:
683 timer1_state = RELEASED;
684 break;
685 case CPUTIMER_8254_SEL2:
686 timer2_state = RELEASED;
687 break;
688 default:
689 break;
690 }
691 timer->type = 0;
984263bc
MD
692}
693
694static void
695rtc_restore(void)
696{
984263bc
MD
697 /* Restore all of the RTC's "status" (actually, control) registers. */
698 writertc(RTC_STATUSB, RTCSB_24HR);
699 writertc(RTC_STATUSA, rtc_statusa);
700 writertc(RTC_STATUSB, rtc_statusb);
701}
702
703/*
0284027e 704 * Restore all the timers.
984263bc 705 *
0d1dffdf
MD
706 * This function is called to resynchronize our core timekeeping after a
707 * long halt, e.g. from apm_default_resume() and friends. It is also
708 * called if after a BIOS call we have detected munging of the 8254.
709 * It is necessary because cputimer_count() counter's delta may have grown
710 * too large for nanouptime() and friends to handle, or (in the case of 8254
711 * munging) might cause the SYSTIMER code to prematurely trigger.
984263bc
MD
712 */
713void
714timer_restore(void)
715{
0284027e 716 crit_enter();
984263bc
MD
717 i8254_restore(); /* restore timer_freq and hz */
718 rtc_restore(); /* reenable RTC interrupts */
0284027e 719 crit_exit();
984263bc
MD
720}
721
722/*
723 * Initialize 8254 timer 0 early so that it can be used in DELAY().
984263bc
MD
724 */
725void
09e6e929 726startrtclock(void)
984263bc
MD
727{
728 u_int delta, freq;
729
88c4d2f6
MD
730 /*
731 * Can we use the TSC?
732 */
984263bc
MD
733 if (cpu_feature & CPUID_TSC)
734 tsc_present = 1;
735 else
736 tsc_present = 0;
737
88c4d2f6
MD
738 /*
739 * Initial RTC state, don't do anything unexpected
740 */
984263bc
MD
741 writertc(RTC_STATUSA, rtc_statusa);
742 writertc(RTC_STATUSB, RTCSB_24HR);
743
88c4d2f6
MD
744 /*
745 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
746 * generate an interrupt, which we will ignore for now.
747 *
748 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
749 * (so it counts a full 2^16 and repeats). We will use this timer
750 * for our counting.
751 */
752 i8254_restore();
984263bc
MD
753 freq = calibrate_clocks();
754#ifdef CLK_CALIBRATION_LOOP
755 if (bootverbose) {
26be20a0 756 kprintf(
984263bc
MD
757 "Press a key on the console to abort clock calibration\n");
758 while (cncheckc() == -1)
759 calibrate_clocks();
760 }
761#endif
762
763 /*
764 * Use the calibrated i8254 frequency if it seems reasonable.
765 * Otherwise use the default, and don't use the calibrated i586
766 * frequency.
767 */
044ee7c4
MD
768 delta = freq > i8254_cputimer.freq ?
769 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
770 if (delta < i8254_cputimer.freq / 100) {
984263bc
MD
771#ifndef CLK_USE_I8254_CALIBRATION
772 if (bootverbose)
26be20a0 773 kprintf(
984263bc 774"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
044ee7c4 775 freq = i8254_cputimer.freq;
984263bc 776#endif
ef612539
SZ
777 /*
778 * NOTE:
779 * Interrupt timer's freq must be adjusted
780 * before we change the cuptimer's frequency.
781 */
782 i8254_cputimer_intr.freq = freq;
5ee041ae 783 cputimer_set_frequency(&i8254_cputimer, freq);
984263bc
MD
784 } else {
785 if (bootverbose)
26be20a0 786 kprintf(
984263bc 787 "%d Hz differs from default of %d Hz by more than 1%%\n",
044ee7c4 788 freq, i8254_cputimer.freq);
374133e3 789 tsc_frequency = 0;
984263bc
MD
790 }
791
984263bc 792#ifndef CLK_USE_TSC_CALIBRATION
870b0161 793 if (tsc_frequency != 0) {
984263bc 794 if (bootverbose)
26be20a0 795 kprintf(
984263bc 796"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
374133e3 797 tsc_frequency = 0;
984263bc
MD
798 }
799#endif
374133e3 800 if (tsc_present && tsc_frequency == 0) {
984263bc
MD
801 /*
802 * Calibration of the i586 clock relative to the mc146818A
803 * clock failed. Do a less accurate calibration relative
804 * to the i8254 clock.
805 */
806 u_int64_t old_tsc = rdtsc();
807
808 DELAY(1000000);
374133e3 809 tsc_frequency = rdtsc() - old_tsc;
984263bc 810#ifdef CLK_USE_TSC_CALIBRATION
870b0161
MD
811 if (bootverbose) {
812 kprintf("TSC clock: %llu Hz (Method B)\n",
813 tsc_frequency);
814 }
984263bc
MD
815#endif
816 }
817
87e2fa7e 818 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
984263bc
MD
819}
820
e63ac55d
MD
821/*
822 * Sync the time of day back to the RTC on shutdown, but only if
823 * we have already loaded it and have not crashed.
824 */
825static void
826resettodr_on_shutdown(void *arg __unused)
827{
828 if (rtc_loaded && panicstr == NULL) {
829 resettodr();
830 }
831}
832
984263bc
MD
833/*
834 * Initialize the time of day register, based on the time base which is, e.g.
835 * from a filesystem.
836 */
837void
838inittodr(time_t base)
839{
840 unsigned long sec, days;
984263bc 841 int year, month;
88c4d2f6 842 int y, m;
984263bc
MD
843 struct timespec ts;
844
845 if (base) {
984263bc
MD
846 ts.tv_sec = base;
847 ts.tv_nsec = 0;
88c4d2f6 848 set_timeofday(&ts);
984263bc
MD
849 }
850
851 /* Look if we have a RTC present and the time is valid */
852 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
853 goto wrong_time;
854
855 /* wait for time update to complete */
856 /* If RTCSA_TUP is zero, we have at least 244us before next update */
88c4d2f6 857 crit_enter();
984263bc 858 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
88c4d2f6
MD
859 crit_exit();
860 crit_enter();
984263bc
MD
861 }
862
863 days = 0;
864#ifdef USE_RTC_CENTURY
865 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
866#else
867 year = readrtc(RTC_YEAR) + 1900;
868 if (year < 1970)
869 year += 100;
870#endif
871 if (year < 1970) {
88c4d2f6 872 crit_exit();
984263bc
MD
873 goto wrong_time;
874 }
875 month = readrtc(RTC_MONTH);
876 for (m = 1; m < month; m++)
877 days += daysinmonth[m-1];
878 if ((month > 2) && LEAPYEAR(year))
879 days ++;
880 days += readrtc(RTC_DAY) - 1;
984263bc
MD
881 for (y = 1970; y < year; y++)
882 days += DAYSPERYEAR + LEAPYEAR(y);
883 sec = ((( days * 24 +
884 readrtc(RTC_HRS)) * 60 +
885 readrtc(RTC_MIN)) * 60 +
886 readrtc(RTC_SEC));
887 /* sec now contains the number of seconds, since Jan 1 1970,
888 in the local time zone */
889
890 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
891
892 y = time_second - sec;
893 if (y <= -2 || y >= 2) {
894 /* badly off, adjust it */
895 ts.tv_sec = sec;
896 ts.tv_nsec = 0;
88c4d2f6 897 set_timeofday(&ts);
984263bc 898 }
e63ac55d 899 rtc_loaded = 1;
88c4d2f6 900 crit_exit();
984263bc
MD
901 return;
902
903wrong_time:
26be20a0
SW
904 kprintf("Invalid time in real time clock.\n");
905 kprintf("Check and reset the date immediately!\n");
984263bc
MD
906}
907
908/*
909 * Write system time back to RTC
910 */
911void
09e6e929 912resettodr(void)
984263bc 913{
2f70966e
MD
914 struct timeval tv;
915 unsigned long tm;
916 int m;
917 int y;
984263bc
MD
918
919 if (disable_rtc_set)
920 return;
921
2f70966e
MD
922 microtime(&tv);
923 tm = tv.tv_sec;
984263bc 924
88c4d2f6 925 crit_enter();
984263bc
MD
926 /* Disable RTC updates and interrupts. */
927 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
928
929 /* Calculate local time to put in RTC */
930
931 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
932
933 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
934 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
935 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
936
937 /* We have now the days since 01-01-1970 in tm */
938 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
939 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
940 tm >= m;
941 y++, m = DAYSPERYEAR + LEAPYEAR(y))
942 tm -= m;
943
944 /* Now we have the years in y and the day-of-the-year in tm */
945 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
946#ifdef USE_RTC_CENTURY
947 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
948#endif
949 for (m = 0; ; m++) {
950 int ml;
951
952 ml = daysinmonth[m];
953 if (m == 1 && LEAPYEAR(y))
954 ml++;
955 if (tm < ml)
956 break;
957 tm -= ml;
958 }
959
960 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
961 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
962
963 /* Reenable RTC updates and interrupts. */
964 writertc(RTC_STATUSB, rtc_statusb);
88c4d2f6 965 crit_exit();
984263bc
MD
966}
967
6b809ec7
SZ
968static int
969i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
970{
971 sysclock_t base;
972 long lastcnt;
973
974 /*
975 * Following code assumes the 8254 is the cpu timer,
976 * so make sure it is.
977 */
978 KKASSERT(sys_cputimer == &i8254_cputimer);
979 KKASSERT(cti == &i8254_cputimer_intr);
980
c83c147e 981 lastcnt = get_interrupt_counter(irq, mycpuid);
6b809ec7
SZ
982
983 /*
984 * Force an 8254 Timer0 interrupt and wait 1/100s for
985 * it to happen, then see if we got it.
986 */
987 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
988
989 i8254_intr_reload(cti, 2);
990 base = sys_cputimer->count();
991 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
992 ; /* nothing */
993
c83c147e 994 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
6b809ec7
SZ
995 return ENOENT;
996 return 0;
997}
998
984263bc 999/*
88c4d2f6
MD
1000 * Start both clocks running. DragonFly note: the stat clock is no longer
1001 * used. Instead, 8254 based systimers are used for all major clock
d426f67a 1002 * interrupts.
984263bc 1003 */
ef612539
SZ
1004static void
1005i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
984263bc 1006{
c79ae131 1007 void *clkdesc = NULL;
6b809ec7 1008 int irq = 0, mixed_mode = 0, error;
984263bc 1009
6355d931 1010 KKASSERT(mycpuid == 0);
38015462
SZ
1011 callout_init(&sysbeepstop_ch);
1012
6b809ec7
SZ
1013 if (!selected && i8254_intr_disable)
1014 goto nointr;
e87376d9 1015
d426f67a
SZ
1016 /*
1017 * The stat interrupt mask is different without the
1018 * statistics clock. Also, don't set the interrupt
1019 * flag which would normally cause the RTC to generate
1020 * interrupts.
1021 */
1022 rtc_statusb = RTCSB_24HR;
38015462 1023
984263bc 1024 /* Finish initializing 8253 timer 0. */
f45bfca0 1025 if (ioapic_enable) {
86d692fe 1026 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
6b809ec7
SZ
1027 INTR_POLARITY_HIGH);
1028 if (irq < 0) {
1029mixed_mode_setup:
027bbbfe 1030 error = ioapic_conf_legacy_extint(0);
6b809ec7 1031 if (!error) {
86d692fe 1032 irq = machintr_legacy_intr_find(0,
027bbbfe 1033 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
6b809ec7
SZ
1034 if (irq < 0)
1035 error = ENOENT;
1036 }
1037
1038 if (error) {
1039 if (!selected) {
1040 kprintf("IOAPIC: setup mixed mode for "
1041 "irq 0 failed: %d\n", error);
1042 goto nointr;
1043 } else {
1044 panic("IOAPIC: setup mixed mode for "
1045 "irq 0 failed: %d\n", error);
1046 }
1047 }
1048 mixed_mode = 1;
1049 }
1050 clkdesc = register_int(irq, clkintr, NULL, "clk",
1051 NULL,
1052 INTR_EXCL | INTR_CLOCK |
1053 INTR_NOPOLL | INTR_MPSAFE |
6355d931 1054 INTR_NOENTROPY, 0);
6ac31e9d 1055 } else {
1e7aaefa
SZ
1056 register_int(0, clkintr, NULL, "clk", NULL,
1057 INTR_EXCL | INTR_CLOCK |
1058 INTR_NOPOLL | INTR_MPSAFE |
6355d931 1059 INTR_NOENTROPY, 0);
6ac31e9d 1060 }
38015462
SZ
1061
1062 /* Initialize RTC. */
1063 writertc(RTC_STATUSA, rtc_statusa);
1064 writertc(RTC_STATUSB, RTCSB_24HR);
1065
f45bfca0 1066 if (ioapic_enable) {
6ac31e9d
SZ
1067 error = i8254_ioapic_trial(irq, cti);
1068 if (error) {
1069 if (mixed_mode) {
1070 if (!selected) {
1071 kprintf("IOAPIC: mixed mode for irq %d "
1072 "trial failed: %d\n",
1073 irq, error);
1074 goto nointr;
1075 } else {
1076 panic("IOAPIC: mixed mode for irq %d "
1077 "trial failed: %d\n", irq, error);
1078 }
6b809ec7 1079 } else {
6ac31e9d
SZ
1080 kprintf("IOAPIC: warning 8254 is not connected "
1081 "to the correct pin, try mixed mode\n");
6355d931 1082 unregister_int(clkdesc, 0);
6ac31e9d 1083 goto mixed_mode_setup;
6b809ec7 1084 }
6b809ec7
SZ
1085 }
1086 }
6b809ec7
SZ
1087 return;
1088
1089nointr:
1090 i8254_nointr = 1; /* don't try to register again */
1091 cputimer_intr_deregister(cti);
984263bc
MD
1092}
1093
984263bc
MD
1094void
1095setstatclockrate(int newhz)
1096{
1097 if (newhz == RTC_PROFRATE)
1098 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1099 else
1100 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1101 writertc(RTC_STATUSA, rtc_statusa);
1102}
1103
88c4d2f6 1104#if 0
984263bc
MD
1105static unsigned
1106tsc_get_timecount(struct timecounter *tc)
1107{
1108 return (rdtsc());
1109}
88c4d2f6 1110#endif
984263bc
MD
1111
1112#ifdef KERN_TIMESTAMP
1113#define KERN_TIMESTAMP_SIZE 16384
1114static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1115SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1116 sizeof(tsc), "LU", "Kernel timestamps");
1117void
1118_TSTMP(u_int32_t x)
1119{
1120 static int i;
1121
1122 tsc[i] = (u_int32_t)rdtsc();
1123 tsc[i+1] = x;
1124 i = i + 2;
1125 if (i >= KERN_TIMESTAMP_SIZE)
1126 i = 0;
1127 tsc[i] = 0; /* mark last entry */
1128}
6b08710e 1129#endif /* KERN_TIMESTAMP */
984263bc 1130
c17827b4
MD
1131/*
1132 *
1133 */
1134
1135static int
1136hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1137{
1138 sysclock_t count;
1139 __uint64_t tscval;
1140 char buf[32];
1141
1142 crit_enter();
044ee7c4
MD
1143 if (sys_cputimer == &i8254_cputimer)
1144 count = sys_cputimer->count();
1145 else
1146 count = 0;
c17827b4
MD
1147 if (tsc_present)
1148 tscval = rdtsc();
1149 else
1150 tscval = 0;
1151 crit_exit();
f8c7a42d 1152 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
c17827b4
MD
1153 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1154}
1155
1156SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
044ee7c4
MD
1157SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1158 "frequency");
c17827b4 1159SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
044ee7c4 1160 0, 0, hw_i8254_timestamp, "A", "");
c17827b4 1161
870b0161
MD
1162SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1163 &tsc_present, 0, "TSC Available");
1164SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1165 &tsc_frequency, 0, "TSC Frequency");
1166