kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / pc64 / include / intr_machdep.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
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35 */
36
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37#ifndef _ARCH_INTR_MACHDEP_H_
38#define _ARCH_INTR_MACHDEP_H_
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39
40#ifndef LOCORE
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41#ifndef _SYS_TYPES_H_
42#include <sys/types.h>
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43#endif
44#endif
45
46/*
47 * Low level interrupt code.
48 */
49
50#ifdef _KERNEL
51
617a6d43 52#define IDT_OFFSET 0x20
9caf58d7 53#define IDT_OFFSET_SYSCALL 0x80
617a6d43 54#define IDT_OFFSET_IPI 0xe0
c8fe38ae 55
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56#define IDT_HWI_VECTORS (IDT_OFFSET_IPI - IDT_OFFSET)
57
c8fe38ae 58/*
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59 * Local APIC TPR priority vector levels:
60 *
61 * 0xff (255) +-------------+
62 * | | 15 (IPIs: Xcpustop, Xspuriousint)
63 * 0xf0 (240) +-------------+
64 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
65 * 0xe0 (224) +-------------+
66 * | | 13
67 * 0xd0 (208) +-------------+
68 * | | 12
69 * 0xc0 (192) +-------------+
70 * | | 11
71 * 0xb0 (176) +-------------+
72 * | | 10
73 * 0xa0 (160) +-------------+
74 * | | 9
75 * 0x90 (144) +-------------+
76 * | | 8 (syscall at 0x80)
77 * 0x80 (128) +-------------+
78 * | | 7
79 * 0x70 (112) +-------------+
80 * | | 6
81 * 0x60 (96) +-------------+
82 * | | 5
83 * 0x50 (80) +-------------+
84 * | | 4
85 * 0x40 (64) +-------------+
86 * | | 3
87 * 0x30 (48) +-------------+
88 * | | 2 (hardware INTs)
89 * 0x20 (32) +-------------+
90 * | | 1 (exceptions, traps, etc.)
91 * 0x10 (16) +-------------+
92 * | | 0 (exceptions, traps, etc.)
93 * 0x00 (0) +-------------+
c8fe38ae 94 */
617a6d43 95#define TPR_STEP 0x10
c8fe38ae 96
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97/* Local APIC Task Priority Register */
98#define TPR_IPI (IDT_OFFSET_IPI - 1)
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99
100
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101/*
102 * IPI group1
103 */
104#define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
c8fe38ae 105
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106/* TLB shootdowns */
107#define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
c8fe38ae 108
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109/* IPI group1 1: unused (was inter-cpu clock handling) */
110/* IPI group1 2: unused (was inter-cpu rendezvous) */
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111
112/* IPIQ rendezvous */
617a6d43 113#define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
c8fe38ae 114
46d4e165 115/* TIMER rendezvous */
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116#define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
117
118/* IPI group1 5 ~ 15: unused */
46d4e165 119
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120
121/*
617a6d43 122 * IPI group2
c8fe38ae 123 */
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124#define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
125
126/* IPI to signal CPUs to stop and wait for another CPU to restart them */
127#define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
128
129/* IPI group2 1 ~ 14: unused */
130
131/* NOTE: this vector MUST be xxxx1111 */
132#define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
c8fe38ae 133
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134#ifndef LOCORE
135
136/*
137 * Type of the first (asm) part of an interrupt handler.
138 */
139#ifndef JG_defined_inthand_t
140#define JG_defined_inthand_t
141typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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142#endif
143
144#define IDTVEC(name) __CONCAT(X,name)
145
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146inthand_t
147 Xspuriousint, /* handle APIC "spurious INTs" */
148 Xtimer; /* handle LAPIC timer INT */
149
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150inthand_t
151 Xinvltlb, /* TLB shootdowns */
c8fe38ae 152 Xcpustop, /* CPU stops & waits for another CPU to restart it */
c8fe38ae 153 Xipiq; /* handle lwkt_send_ipiq() requests */
c8fe38ae 154
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155#endif /* LOCORE */
156
157#endif /* _KERNEL */
158
57a9c56b 159#endif /* !_ARCH_INTR_MACHDEP_H_ */