kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
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41 */
42
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43//#include "use_npx.h"
44#include "use_isa.h"
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45#include "opt_compat.h"
46#include "opt_cpu.h"
47#include "opt_ddb.h"
48#include "opt_directio.h"
49#include "opt_inet.h"
50#include "opt_ipx.h"
51#include "opt_msgbuf.h"
52#include "opt_swap.h"
53
54#include <sys/param.h>
55#include <sys/systm.h>
56#include <sys/sysproto.h>
57#include <sys/signalvar.h>
58#include <sys/kernel.h>
59#include <sys/linker.h>
60#include <sys/malloc.h>
61#include <sys/proc.h>
895c1f85 62#include <sys/priv.h>
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63#include <sys/buf.h>
64#include <sys/reboot.h>
65#include <sys/mbuf.h>
66#include <sys/msgbuf.h>
67#include <sys/sysent.h>
68#include <sys/sysctl.h>
69#include <sys/vmmeter.h>
70#include <sys/bus.h>
71#include <sys/upcall.h>
72#include <sys/usched.h>
73#include <sys/reg.h>
74
75#include <vm/vm.h>
76#include <vm/vm_param.h>
77#include <sys/lock.h>
78#include <vm/vm_kern.h>
79#include <vm/vm_object.h>
80#include <vm/vm_page.h>
81#include <vm/vm_map.h>
82#include <vm/vm_pager.h>
83#include <vm/vm_extern.h>
84
85#include <sys/thread2.h>
684a93c4 86#include <sys/mplock2.h>
320c681e 87#include <sys/mutex2.h>
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88
89#include <sys/user.h>
90#include <sys/exec.h>
91#include <sys/cons.h>
92
93#include <ddb/ddb.h>
94
95#include <machine/cpu.h>
96#include <machine/clock.h>
97#include <machine/specialreg.h>
98#if JG
99#include <machine/bootinfo.h>
100#endif
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101#include <machine/md_var.h>
102#include <machine/metadata.h>
103#include <machine/pc/bios.h>
104#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
105#include <machine/globaldata.h> /* CPU_prvspace */
106#include <machine/smp.h>
107#ifdef PERFMON
108#include <machine/perfmon.h>
109#endif
110#include <machine/cputypes.h>
57a9c56b 111#include <machine/intr_machdep.h>
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112
113#ifdef OLD_BUS_ARCH
46d4e165 114#include <bus/isa/isa_device.h>
c8fe38ae 115#endif
57a9c56b 116#include <machine_base/isa/isa_intr.h>
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117#include <bus/isa/rtc.h>
118#include <sys/random.h>
119#include <sys/ptrace.h>
120#include <machine/sigframe.h>
121
faaf4131 122#include <sys/machintr.h>
9284cddf 123#include <machine_base/icu/icu_abi.h>
7265a4fe 124#include <machine_base/icu/elcr_var.h>
2e0ed166 125#include <machine_base/apic/lapic.h>
ed4d621d 126#include <machine_base/apic/ioapic.h>
a3dd9120 127#include <machine_base/apic/ioapic_abi.h>
8cc9a8d1 128#include <machine/mptable.h>
faaf4131 129
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130#define PHYSMAP_ENTRIES 10
131
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132extern u_int64_t hammer_time(u_int64_t, u_int64_t);
133
134extern void printcpuinfo(void); /* XXX header file */
135extern void identify_cpu(void);
136#if JG
137extern void finishidentcpu(void);
138#endif
139extern void panicifcpuunsupported(void);
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140
141static void cpu_startup(void *);
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142static void pic_finish(void *);
143static void cpu_finish(void *);
144
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145#ifndef CPU_DISABLE_SSE
146static void set_fpregs_xmm(struct save87 *, struct savexmm *);
147static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
148#endif /* CPU_DISABLE_SSE */
149#ifdef DIRECTIO
150extern void ffs_rawread_setup(void);
151#endif /* DIRECTIO */
152static void init_locks(void);
153
7c006a9e 154SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
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155SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
156SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
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157
158#ifdef DDB
159extern vm_offset_t ksym_start, ksym_end;
160#endif
161
da23a592 162struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
48ffc236 163
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164int _udatasel, _ucodesel, _ucode32sel;
165u_long atdevbase;
c8fe38ae 166int64_t tsc_offsets[MAXCPU];
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167
168#if defined(SWTCH_OPTIM_STATS)
169extern int swtch_optim_stats;
170SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
171 CTLFLAG_RD, &swtch_optim_stats, 0, "");
172SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
173 CTLFLAG_RD, &tlb_flush_count, 0, "");
174#endif
175
39d69dae 176long physmem = 0;
c8fe38ae 177
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178u_long ebda_addr = 0;
179
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180int imcr_present = 0;
181
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182int naps = 0; /* # of Applications processors */
183
8936cd9b 184u_int base_memory;
320c681e 185struct mtx dt_lock; /* lock for GDT and LDT */
8936cd9b 186
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187static int
188sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
189{
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190 u_long pmem = ctob(physmem);
191
192 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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193 return (error);
194}
195
39d69dae 196SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 197 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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198
199static int
200sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
201{
202 int error = sysctl_handle_int(oidp, 0,
203 ctob(physmem - vmstats.v_wire_count), req);
204 return (error);
205}
206
207SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
208 0, 0, sysctl_hw_usermem, "IU", "");
209
210static int
211sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
212{
c8fe38ae 213 int error = sysctl_handle_int(oidp, 0,
b2b3ffcd 214 x86_64_btop(avail_end - avail_start), req);
c8fe38ae 215 return (error);
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216}
217
218SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
219 0, 0, sysctl_hw_availpages, "I", "");
220
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221vm_paddr_t Maxmem;
222vm_paddr_t Realmem;
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223
224/*
225 * The number of PHYSMAP entries must be one less than the number of
226 * PHYSSEG entries because the PHYSMAP entry that spans the largest
227 * physical address that is accessible by ISA DMA is split into two
228 * PHYSSEG entries.
229 */
230#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
231
232vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
233vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
234
235/* must be 2 less so 0 0 can signal end of chunks */
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236#define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
237#define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
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238
239static vm_offset_t buffer_sva, buffer_eva;
240vm_offset_t clean_sva, clean_eva;
241static vm_offset_t pager_sva, pager_eva;
242static struct trapframe proc0_tf;
243
244static void
245cpu_startup(void *dummy)
246{
247 caddr_t v;
248 vm_size_t size = 0;
249 vm_offset_t firstaddr;
250
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251 /*
252 * Good {morning,afternoon,evening,night}.
253 */
254 kprintf("%s", version);
255 startrtclock();
256 printcpuinfo();
257 panicifcpuunsupported();
258#ifdef PERFMON
259 perfmon_init();
260#endif
15dc6550 261 kprintf("real memory = %ju (%ju MB)\n",
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262 (intmax_t)Realmem,
263 (intmax_t)Realmem / 1024 / 1024);
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264 /*
265 * Display any holes after the first chunk of extended memory.
266 */
267 if (bootverbose) {
268 int indx;
269
270 kprintf("Physical memory chunk(s):\n");
271 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
272 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
273
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274 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
275 (intmax_t)phys_avail[indx],
276 (intmax_t)phys_avail[indx + 1] - 1,
277 (intmax_t)size1,
278 (intmax_t)(size1 / PAGE_SIZE));
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279 }
280 }
281
282 /*
283 * Allocate space for system data structures.
284 * The first available kernel virtual address is in "v".
285 * As pages of kernel virtual memory are allocated, "v" is incremented.
286 * As pages of memory are allocated and cleared,
287 * "firstaddr" is incremented.
288 * An index into the kernel page table corresponding to the
289 * virtual memory address maintained in "v" is kept in "mapaddr".
290 */
291
292 /*
293 * Make two passes. The first pass calculates how much memory is
294 * needed and allocates it. The second pass assigns virtual
295 * addresses to the various data structures.
296 */
297 firstaddr = 0;
298again:
299 v = (caddr_t)firstaddr;
300
301#define valloc(name, type, num) \
302 (name) = (type *)v; v = (caddr_t)((name)+(num))
303#define valloclim(name, type, num, lim) \
304 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
305
306 /*
307 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
308 * For the first 64MB of ram nominally allocate sufficient buffers to
309 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
310 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
311 * the buffer cache we limit the eventual kva reservation to
312 * maxbcache bytes.
313 *
314 * factor represents the 1/4 x ram conversion.
315 */
316 if (nbuf == 0) {
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317 long factor = 4 * BKVASIZE / 1024;
318 long kbytes = physmem * (PAGE_SIZE / 1024);
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319
320 nbuf = 50;
321 if (kbytes > 4096)
322 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
323 if (kbytes > 65536)
324 nbuf += (kbytes - 65536) * 2 / (factor * 5);
325 if (maxbcache && nbuf > maxbcache / BKVASIZE)
326 nbuf = maxbcache / BKVASIZE;
327 }
328
329 /*
330 * Do not allow the buffer_map to be more then 1/2 the size of the
331 * kernel_map.
332 */
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333 if (nbuf > (virtual_end - virtual_start +
334 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
335 nbuf = (virtual_end - virtual_start +
336 virtual2_end - virtual2_start) / (BKVASIZE * 2);
337 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
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338 }
339
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340 /*
341 * Do not allow the buffer_map to use more than 50% of available
342 * physical-equivalent memory. Since the VM pages which back
343 * individual buffers are typically wired, having too many bufs
344 * can prevent the system from paging properly.
345 */
346 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
347 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
348 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
349 }
350
351 /*
352 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
353 * the valloc space which is just the virtual_end - virtual_start
354 * section. We use valloc() to allocate the buf header array.
355 */
356 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
357 nbuf = (virtual_end - virtual_start) /
358 sizeof(struct buf) / 2;
359 kprintf("Warning: nbufs capped at %ld due to valloc "
360 "considerations", nbuf);
361 }
362
363 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
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364#ifdef NSWBUF_MIN
365 if (nswbuf < NSWBUF_MIN)
366 nswbuf = NSWBUF_MIN;
367#endif
368#ifdef DIRECTIO
369 ffs_rawread_setup();
370#endif
371
372 valloc(swbuf, struct buf, nswbuf);
373 valloc(buf, struct buf, nbuf);
374
375 /*
376 * End of first pass, size has been calculated so allocate memory
377 */
378 if (firstaddr == 0) {
379 size = (vm_size_t)(v - firstaddr);
380 firstaddr = kmem_alloc(&kernel_map, round_page(size));
381 if (firstaddr == 0)
382 panic("startup: no room for tables");
383 goto again;
384 }
385
386 /*
387 * End of second pass, addresses have been assigned
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388 *
389 * nbuf is an int, make sure we don't overflow the field.
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390 */
391 if ((vm_size_t)(v - firstaddr) != size)
392 panic("startup: table size inconsistency");
393
394 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
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395 ((vm_offset_t)nbuf * BKVASIZE) +
396 (nswbuf * MAXPHYS) + pager_map_size);
c8fe38ae 397 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
74d62460 398 ((vm_offset_t)nbuf * BKVASIZE));
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399 buffer_map.system_map = 1;
400 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
74d62460 401 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
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402 pager_map.system_map = 1;
403
404#if defined(USERCONFIG)
405 userconfig();
406 cninit(); /* the preferred console may have changed */
407#endif
408
361c5f22 409 kprintf("avail memory = %ju (%ju MB)\n",
79d182b0
MD
410 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
411 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
412 1024 / 1024);
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413
414 /*
415 * Set up buffers, so they can be used to read disk labels.
416 */
417 bufinit();
418 vm_pager_bufferinit();
1ebcbb29
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419}
420
421static void
422cpu_finish(void *dummy __unused)
423{
424 cpu_setregs();
425}
426
427static void
428pic_finish(void *dummy __unused)
429{
430 /* Log ELCR information */
431 elcr_dump();
8dc88f05 432
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433 /* Log MPTABLE information */
434 mptable_pci_int_dump();
435
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436 /* Finalize PCI */
437 MachIntrABI.finalize();
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438}
439
440/*
441 * Send an interrupt to process.
442 *
443 * Stack is set up to allow sigcode stored
444 * at top to call routine, followed by kcall
445 * to sigreturn routine below. After sigreturn
446 * resets the signal mask, the stack, and the
447 * frame pointer, it returns to the user
448 * specified pc, psl.
449 */
450void
451sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
452{
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453 struct lwp *lp = curthread->td_lwp;
454 struct proc *p = lp->lwp_proc;
455 struct trapframe *regs;
456 struct sigacts *psp = p->p_sigacts;
457 struct sigframe sf, *sfp;
458 int oonstack;
a6a09809 459 char *sp;
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460
461 regs = lp->lwp_md.md_regs;
462 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
463
a6a09809 464 /* Save user context */
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465 bzero(&sf, sizeof(struct sigframe));
466 sf.sf_uc.uc_sigmask = *mask;
467 sf.sf_uc.uc_stack = lp->lwp_sigstk;
468 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
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469 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
470 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
c8fe38ae 471
a6a09809 472 /* Make the size of the saved context visible to userland */
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473 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
474
c8fe38ae 475 /* Allocate and validate space for the signal handler context. */
4643740a 476 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
c8fe38ae 477 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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478 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
479 sizeof(struct sigframe));
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480 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
481 } else {
89954408
JG
482 /* We take red zone into account */
483 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
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MD
484 }
485
a6a09809 486 /* Align to 16 bytes */
4117f2fd 487 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
a6a09809 488
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489 /* Translate the signal is appropriate */
490 if (p->p_sysent->sv_sigtbl) {
491 if (sig <= p->p_sysent->sv_sigsize)
492 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
493 }
494
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495 /*
496 * Build the argument list for the signal handler.
497 *
498 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
499 */
500 regs->tf_rdi = sig; /* argument 1 */
501 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
502
c8fe38ae 503 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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MD
504 /*
505 * Signal handler installed with SA_SIGINFO.
506 *
507 * action(signo, siginfo, ucontext)
508 */
509 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
630d9ab4 510 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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511 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
512
513 /* fill siginfo structure */
514 sf.sf_si.si_signo = sig;
515 sf.sf_si.si_code = code;
630d9ab4 516 sf.sf_si.si_addr = (void *)regs->tf_addr;
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MD
517 } else {
518 /*
519 * Old FreeBSD-style arguments.
520 *
521 * handler (signo, code, [uc], addr)
522 */
523 regs->tf_rsi = (register_t)code; /* argument 2 */
630d9ab4 524 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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525 sf.sf_ahu.sf_handler = catcher;
526 }
527
528 /*
529 * If we're a vm86 process, we want to save the segment registers.
530 * We also change eflags to be our emulated eflags, not the actual
531 * eflags.
532 */
533#if JG
534 if (regs->tf_eflags & PSL_VM) {
535 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
536 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
537
538 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
539 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
540 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
541 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
542
543 if (vm86->vm86_has_vme == 0)
544 sf.sf_uc.uc_mcontext.mc_eflags =
545 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
546 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
547
548 /*
549 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
550 * syscalls made by the signal handler. This just avoids
551 * wasting time for our lazy fixup of such faults. PSL_NT
552 * does nothing in vm86 mode, but vm86 programs can set it
553 * almost legitimately in probes for old cpu types.
554 */
555 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
556 }
557#endif
558
559 /*
560 * Save the FPU state and reinit the FP unit
561 */
c8fe38ae 562 npxpush(&sf.sf_uc.uc_mcontext);
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563
564 /*
565 * Copy the sigframe out to the user's stack.
566 */
567 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
568 /*
569 * Something is wrong with the stack pointer.
570 * ...Kill the process.
571 */
572 sigexit(lp, SIGILL);
573 }
574
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575 regs->tf_rsp = (register_t)sfp;
576 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
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577
578 /*
579 * i386 abi specifies that the direction flag must be cleared
580 * on function entry
581 */
5b9f6cc4 582 regs->tf_rflags &= ~(PSL_T|PSL_D);
c8fe38ae 583
c8fe38ae 584 /*
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585 * 64 bit mode has a code and stack selector but
586 * no data or extra selector. %fs and %gs are not
587 * stored in-context.
c8fe38ae 588 */
a6a09809 589 regs->tf_cs = _ucodesel;
c8fe38ae 590 regs->tf_ss = _udatasel;
f2081646 591 clear_quickret();
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592}
593
594/*
595 * Sanitize the trapframe for a virtual kernel passing control to a custom
596 * VM context. Remove any items that would otherwise create a privilage
597 * issue.
598 *
599 * XXX at the moment we allow userland to set the resume flag. Is this a
600 * bad idea?
601 */
602int
603cpu_sanitize_frame(struct trapframe *frame)
604{
c8fe38ae 605 frame->tf_cs = _ucodesel;
c8fe38ae 606 frame->tf_ss = _udatasel;
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607 /* XXX VM (8086) mode not supported? */
608 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
609 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
610
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611 return(0);
612}
613
614/*
615 * Sanitize the tls so loading the descriptor does not blow up
b2b3ffcd 616 * on us. For x86_64 we don't have to do anything.
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617 */
618int
619cpu_sanitize_tls(struct savetls *tls)
620{
621 return(0);
622}
623
624/*
625 * sigreturn(ucontext_t *sigcntxp)
626 *
627 * System call to cleanup state after a signal
628 * has been taken. Reset signal mask and
629 * stack state from context left by sendsig (above).
630 * Return to previous pc and psl as specified by
631 * context left by sendsig. Check carefully to
632 * make sure that the user has not modified the
633 * state to gain improper privileges.
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634 *
635 * MPSAFE
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636 */
637#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
638#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
639
640int
641sys_sigreturn(struct sigreturn_args *uap)
642{
643 struct lwp *lp = curthread->td_lwp;
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644 struct trapframe *regs;
645 ucontext_t uc;
646 ucontext_t *ucp;
5b9f6cc4 647 register_t rflags;
c8fe38ae 648 int cs;
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649 int error;
650
651 /*
652 * We have to copy the information into kernel space so userland
653 * can't modify it while we are sniffing it.
654 */
655 regs = lp->lwp_md.md_regs;
656 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
657 if (error)
658 return (error);
659 ucp = &uc;
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660 rflags = ucp->uc_mcontext.mc_rflags;
661
662 /* VM (8086) mode not supported */
663 rflags &= ~PSL_VM_UNSUPP;
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664
665#if JG
666 if (eflags & PSL_VM) {
667 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
668 struct vm86_kernel *vm86;
669
670 /*
671 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
672 * set up the vm86 area, and we can't enter vm86 mode.
673 */
674 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
675 return (EINVAL);
676 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
677 if (vm86->vm86_inited == 0)
678 return (EINVAL);
679
680 /* go back to user mode if both flags are set */
681 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
682 trapsignal(lp, SIGBUS, 0);
683
684 if (vm86->vm86_has_vme) {
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685 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
686 (eflags & VME_USERCHANGE) | PSL_VM;
c8fe38ae 687 } else {
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688 vm86->vm86_eflags = eflags; /* save VIF, VIP */
689 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
690 (eflags & VM_USERCHANGE) | PSL_VM;
c8fe38ae 691 }
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692 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
693 tf->tf_eflags = eflags;
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694 tf->tf_vm86_ds = tf->tf_ds;
695 tf->tf_vm86_es = tf->tf_es;
696 tf->tf_vm86_fs = tf->tf_fs;
697 tf->tf_vm86_gs = tf->tf_gs;
698 tf->tf_ds = _udatasel;
699 tf->tf_es = _udatasel;
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700 tf->tf_fs = _udatasel;
701 tf->tf_gs = _udatasel;
5b9f6cc4 702 } else
c8fe38ae 703#endif
5b9f6cc4 704 {
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705 /*
706 * Don't allow users to change privileged or reserved flags.
707 */
708 /*
709 * XXX do allow users to change the privileged flag PSL_RF.
710 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
711 * should sometimes set it there too. tf_eflags is kept in
712 * the signal context during signal handling and there is no
713 * other place to remember it, so the PSL_RF bit may be
714 * corrupted by the signal handler without us knowing.
715 * Corruption of the PSL_RF bit at worst causes one more or
716 * one less debugger trap, so allowing it is fairly harmless.
717 */
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718 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
719 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
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720 return(EINVAL);
721 }
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722
723 /*
724 * Don't allow users to load a valid privileged %cs. Let the
725 * hardware check for invalid selectors, excess privilege in
726 * other selectors, invalid %eip's and invalid %esp's.
727 */
728 cs = ucp->uc_mcontext.mc_cs;
729 if (!CS_SECURE(cs)) {
730 kprintf("sigreturn: cs = 0x%x\n", cs);
731 trapsignal(lp, SIGBUS, T_PROTFLT);
732 return(EINVAL);
733 }
5b9f6cc4 734 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
c8fe38ae 735 }
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736
737 /*
738 * Restore the FPU state from the frame
739 */
3919ced0 740 crit_enter();
c8fe38ae 741 npxpop(&ucp->uc_mcontext);
c8fe38ae 742
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743 if (ucp->uc_mcontext.mc_onstack & 1)
744 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
745 else
746 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
747
748 lp->lwp_sigmask = ucp->uc_sigmask;
749 SIG_CANTMASK(lp->lwp_sigmask);
f2081646 750 clear_quickret();
3919ced0 751 crit_exit();
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752 return(EJUSTRETURN);
753}
754
755/*
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756 * Stack frame on entry to function. %rax will contain the function vector,
757 * %rcx will contain the function data. flags, rcx, and rax will have
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758 * already been pushed on the stack.
759 */
760struct upc_frame {
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761 register_t rax;
762 register_t rcx;
763 register_t rdx;
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764 register_t flags;
765 register_t oldip;
766};
767
768void
769sendupcall(struct vmupcall *vu, int morepending)
770{
771 struct lwp *lp = curthread->td_lwp;
772 struct trapframe *regs;
773 struct upcall upcall;
774 struct upc_frame upc_frame;
775 int crit_count = 0;
776
777 /*
778 * If we are a virtual kernel running an emulated user process
779 * context, switch back to the virtual kernel context before
780 * trying to post the signal.
781 */
782 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
783 lp->lwp_md.md_regs->tf_trapno = 0;
784 vkernel_trap(lp, lp->lwp_md.md_regs);
785 }
786
787 /*
788 * Get the upcall data structure
789 */
790 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
791 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
792 ) {
793 vu->vu_pending = 0;
794 kprintf("bad upcall address\n");
795 return;
796 }
797
798 /*
799 * If the data structure is already marked pending or has a critical
800 * section count, mark the data structure as pending and return
801 * without doing an upcall. vu_pending is left set.
802 */
803 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
804 if (upcall.upc_pending < vu->vu_pending) {
805 upcall.upc_pending = vu->vu_pending;
806 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
807 sizeof(upcall.upc_pending));
808 }
809 return;
810 }
811
812 /*
813 * We can run this upcall now, clear vu_pending.
814 *
815 * Bump our critical section count and set or clear the
816 * user pending flag depending on whether more upcalls are
817 * pending. The user will be responsible for calling
818 * upc_dispatch(-1) to process remaining upcalls.
819 */
820 vu->vu_pending = 0;
821 upcall.upc_pending = morepending;
f9235b6d 822 ++crit_count;
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823 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
824 sizeof(upcall.upc_pending));
825 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
826 sizeof(int));
827
828 /*
829 * Construct a stack frame and issue the upcall
830 */
831 regs = lp->lwp_md.md_regs;
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832 upc_frame.rax = regs->tf_rax;
833 upc_frame.rcx = regs->tf_rcx;
834 upc_frame.rdx = regs->tf_rdx;
835 upc_frame.flags = regs->tf_rflags;
836 upc_frame.oldip = regs->tf_rip;
2eddd927 837 if (copyout(&upc_frame, (void *)(regs->tf_rsp - sizeof(upc_frame) - 128),
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838 sizeof(upc_frame)) != 0) {
839 kprintf("bad stack on upcall\n");
840 } else {
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841 regs->tf_rax = (register_t)vu->vu_func;
842 regs->tf_rcx = (register_t)vu->vu_data;
843 regs->tf_rdx = (register_t)lp->lwp_upcall;
844 regs->tf_rip = (register_t)vu->vu_ctx;
2eddd927 845 regs->tf_rsp -= sizeof(upc_frame) + 128;
c8fe38ae 846 }
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847}
848
849/*
850 * fetchupcall occurs in the context of a system call, which means that
851 * we have to return EJUSTRETURN in order to prevent eax and edx from
852 * being overwritten by the syscall return value.
853 *
854 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
855 * and the function pointer in %eax.
856 */
857int
858fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
859{
860 struct upc_frame upc_frame;
861 struct lwp *lp = curthread->td_lwp;
862 struct trapframe *regs;
863 int error;
864 struct upcall upcall;
865 int crit_count;
866
867 regs = lp->lwp_md.md_regs;
868
869 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
870 if (error == 0) {
871 if (vu) {
872 /*
873 * This jumps us to the next ready context.
874 */
875 vu->vu_pending = 0;
876 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
877 crit_count = 0;
878 if (error == 0)
879 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 880 ++crit_count;
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881 if (error == 0)
882 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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883 regs->tf_rax = (register_t)vu->vu_func;
884 regs->tf_rcx = (register_t)vu->vu_data;
885 regs->tf_rdx = (register_t)lp->lwp_upcall;
886 regs->tf_rip = (register_t)vu->vu_ctx;
887 regs->tf_rsp = (register_t)rsp;
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888 } else {
889 /*
890 * This returns us to the originally interrupted code.
891 */
892 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
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893 regs->tf_rax = upc_frame.rax;
894 regs->tf_rcx = upc_frame.rcx;
895 regs->tf_rdx = upc_frame.rdx;
896 regs->tf_rflags = (regs->tf_rflags & ~PSL_USERCHANGE) |
c8fe38ae 897 (upc_frame.flags & PSL_USERCHANGE);
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898 regs->tf_rip = upc_frame.oldip;
899 regs->tf_rsp = (register_t)((char *)rsp + sizeof(upc_frame));
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900 }
901 }
902 if (error == 0)
903 error = EJUSTRETURN;
904 return(error);
905}
906
907/*
908 * Machine dependent boot() routine
909 *
910 * I haven't seen anything to put here yet
911 * Possibly some stuff might be grafted back here from boot()
912 */
913void
914cpu_boot(int howto)
915{
916}
917
918/*
919 * Shutdown the CPU as much as possible
920 */
921void
922cpu_halt(void)
923{
924 for (;;)
925 __asm__ __volatile("hlt");
926}
927
928/*
929 * cpu_idle() represents the idle LWKT. You cannot return from this function
930 * (unless you want to blow things up!). Instead we look for runnable threads
931 * and loop or halt as appropriate. Giant is not held on entry to the thread.
932 *
933 * The main loop is entered with a critical section held, we must release
934 * the critical section before doing anything else. lwkt_switch() will
935 * check for pending interrupts due to entering and exiting its own
936 * critical section.
937 *
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938 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
939 * However, there are cases where the idlethread will be entered with
940 * the possibility that no IPI will occur and in such cases
941 * lwkt_switch() sets TDF_IDLE_NOHLT.
942 *
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943 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
944 * 1 to just use hlt and for debugging purposes.
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945 *
946 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
947 * must occur before it starts using ACPI halt.
c8fe38ae 948 */
46e562ce 949static int cpu_idle_hlt = 2;
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950static int cpu_idle_hltcnt;
951static int cpu_idle_spincnt;
582fd846 952static u_int cpu_idle_repeat = 750;
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953SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
954 &cpu_idle_hlt, 0, "Idle loop HLT enable");
955SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
956 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
957SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
958 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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959SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
960 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
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961
962static void
963cpu_idle_default_hook(void)
964{
965 /*
966 * We must guarentee that hlt is exactly the instruction
967 * following the sti.
968 */
969 __asm __volatile("sti; hlt");
970}
971
972/* Other subsystems (e.g., ACPI) can hook this later. */
973void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
974
975void
976cpu_idle(void)
977{
0f0466c0 978 globaldata_t gd = mycpu;
86232a57 979 struct thread *td __debugvar = gd->gd_curthread;
0f0466c0 980 int reqflags;
be71787b 981 int quick;
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982
983 crit_exit();
f9235b6d 984 KKASSERT(td->td_critcount == 0);
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985 for (;;) {
986 /*
987 * See if there are any LWKTs ready to go.
988 */
989 lwkt_switch();
990
991 /*
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992 * When halting inside a cli we must check for reqflags
993 * races, particularly [re]schedule requests. Running
994 * splz() does the job.
995 *
996 * cpu_idle_hlt:
997 * 0 Never halt, just spin
998 *
999 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1000 * This typically eats more power than the
1001 * ACPI halt.
1002 *
1003 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1004 * use the ACPI halt (default). This is a hybrid
1005 * approach. See machdep.cpu_idle_repeat.
1006 *
1007 * 3 Always use the ACPI halt. This typically
1008 * eats the least amount of power but the cpu
1009 * will be slow waking up. Slows down e.g.
1010 * compiles and other pipe/event oriented stuff.
1011 *
1012 * NOTE: Interrupts are enabled and we are not in a critical
1013 * section.
1014 *
1015 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1016 * don't bother capping gd_idle_repeat, it is ok if
1017 * it overflows.
c8fe38ae 1018 */
be71787b 1019 ++gd->gd_idle_repeat;
0f0466c0 1020 reqflags = gd->gd_reqflags;
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1021 quick = (cpu_idle_hlt == 1) ||
1022 (cpu_idle_hlt < 3 &&
1023 gd->gd_idle_repeat < cpu_idle_repeat);
1024
1025 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
0f0466c0 1026 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
701c977e 1027 splz(); /* XXX */
0f0466c0 1028 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
be71787b 1029 ++cpu_idle_hltcnt;
0f0466c0 1030 } else if (cpu_idle_hlt) {
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1031 __asm __volatile("cli");
1032 splz();
0f0466c0 1033 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
be71787b 1034 if (quick)
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1035 cpu_idle_default_hook();
1036 else
1037 cpu_idle_hook();
1038 }
7d4d6fdb 1039 __asm __volatile("sti");
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1040 ++cpu_idle_hltcnt;
1041 } else {
c8fe38ae 1042 splz();
c5724852 1043 __asm __volatile("sti");
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1044 ++cpu_idle_spincnt;
1045 }
1046 }
1047}
1048
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1049/*
1050 * This routine is called if a spinlock has been held through the
1051 * exponential backoff period and is seriously contested. On a real cpu
1052 * we let it spin.
1053 */
1054void
1055cpu_spinlock_contested(void)
1056{
1057 cpu_pause();
1058}
1059
1060/*
1061 * Clear registers on exec
1062 */
1063void
1064exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1065{
1066 struct thread *td = curthread;
1067 struct lwp *lp = td->td_lwp;
1068 struct pcb *pcb = td->td_pcb;
1069 struct trapframe *regs = lp->lwp_md.md_regs;
1070
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1071 /* was i386_user_cleanup() in NetBSD */
1072 user_ldt_free(pcb);
1073
f2081646 1074 clear_quickret();
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1075 bzero((char *)regs, sizeof(struct trapframe));
1076 regs->tf_rip = entry;
1077 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1078 regs->tf_rdi = stack; /* argv */
1079 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1080 regs->tf_ss = _udatasel;
1081 regs->tf_cs = _ucodesel;
1082 regs->tf_rbx = ps_strings;
1083
1084 /*
1085 * Reset the hardware debug registers if they were in use.
1086 * They won't have any meaning for the newly exec'd process.
1087 */
1088 if (pcb->pcb_flags & PCB_DBREGS) {
1089 pcb->pcb_dr0 = 0;
1090 pcb->pcb_dr1 = 0;
1091 pcb->pcb_dr2 = 0;
1092 pcb->pcb_dr3 = 0;
1093 pcb->pcb_dr6 = 0;
0855a2af 1094 pcb->pcb_dr7 = 0; /* JG set bit 10? */
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1095 if (pcb == td->td_pcb) {
1096 /*
1097 * Clear the debug registers on the running
1098 * CPU, otherwise they will end up affecting
1099 * the next process we switch to.
1100 */
1101 reset_dbregs();
1102 }
1103 pcb->pcb_flags &= ~PCB_DBREGS;
1104 }
1105
1106 /*
1107 * Initialize the math emulator (if any) for the current process.
1108 * Actually, just clear the bit that says that the emulator has
1109 * been initialized. Initialization is delayed until the process
1110 * traps to the emulator (if it is done at all) mainly because
1111 * emulators don't provide an entry point for initialization.
1112 */
c8fe38ae 1113 pcb->pcb_flags &= ~FP_SOFTFP;
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1114
1115 /*
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1116 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1117 * gd_npxthread. Otherwise a preemptive interrupt thread
1118 * may panic in npxdna().
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1119 */
1120 crit_enter();
1121 load_cr0(rcr0() | CR0_MP);
1122
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1123 /*
1124 * NOTE: The MSR values must be correct so we can return to
1125 * userland. gd_user_fs/gs must be correct so the switch
1126 * code knows what the current MSR values are.
1127 */
1128 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
c8fe38ae 1129 pcb->pcb_gsbase = 0;
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1130 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1131 mdcpu->gd_user_gs = 0;
1132 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1133 wrmsr(MSR_KGSBASE, 0);
c8fe38ae 1134
c8fe38ae 1135 /* Initialize the npx (if any) for the current process. */
a8f1df17 1136 npxinit(__INITIAL_FPUCW__);
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1137 crit_exit();
1138
1139 pcb->pcb_ds = _udatasel;
1140 pcb->pcb_es = _udatasel;
1141 pcb->pcb_fs = _udatasel;
1142 pcb->pcb_gs = _udatasel;
1143}
1144
1145void
1146cpu_setregs(void)
1147{
1148 register_t cr0;
1149
1150 cr0 = rcr0();
1151 cr0 |= CR0_NE; /* Done by npxinit() */
1152 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1153 cr0 |= CR0_WP | CR0_AM;
1154 load_cr0(cr0);
1155 load_gs(_udatasel);
1156}
1157
1158static int
1159sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1160{
1161 int error;
1162 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1163 req);
1164 if (!error && req->newptr)
1165 resettodr();
1166 return (error);
1167}
1168
1169SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1170 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1171
c8fe38ae
MD
1172SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1173 CTLFLAG_RW, &disable_rtc_set, 0, "");
c8fe38ae
MD
1174
1175#if JG
1176SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1177 CTLFLAG_RD, &bootinfo, bootinfo, "");
1178#endif
1179
1180SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1181 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1182
1183extern u_long bootdev; /* not a cdev_t - encoding is different */
1184SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1185 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1186
1187/*
1188 * Initialize 386 and configure to run kernel
1189 */
1190
1191/*
1192 * Initialize segments & interrupt table
1193 */
1194
1195int _default_ldt;
1196struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
8a06c6ee 1197struct gate_descriptor idt_arr[MAXCPU][NIDT];
c8fe38ae
MD
1198#if JG
1199union descriptor ldt[NLDT]; /* local descriptor table */
1200#endif
1201
1202/* table descriptors - used to load tables by cpu */
8a06c6ee
SZ
1203struct region_descriptor r_gdt;
1204struct region_descriptor r_idt_arr[MAXCPU];
c8fe38ae 1205
c8fe38ae
MD
1206/* JG proc0paddr is a virtual address */
1207void *proc0paddr;
1208/* JG alignment? */
1209char proc0paddr_buff[LWKT_THREAD_STACK];
1210
1211
1212/* software prototypes -- in more palatable form */
1213struct soft_segment_descriptor gdt_segs[] = {
1214/* GNULL_SEL 0 Null Descriptor */
1215{ 0x0, /* segment base address */
1216 0x0, /* length */
1217 0, /* segment type */
1218 0, /* segment descriptor priority level */
1219 0, /* segment descriptor present */
1220 0, /* long */
1221 0, /* default 32 vs 16 bit size */
1222 0 /* limit granularity (byte/page units)*/ },
1223/* GCODE_SEL 1 Code Descriptor for kernel */
1224{ 0x0, /* segment base address */
1225 0xfffff, /* length - all address space */
1226 SDT_MEMERA, /* segment type */
1227 SEL_KPL, /* segment descriptor priority level */
1228 1, /* segment descriptor present */
1229 1, /* long */
1230 0, /* default 32 vs 16 bit size */
1231 1 /* limit granularity (byte/page units)*/ },
1232/* GDATA_SEL 2 Data Descriptor for kernel */
1233{ 0x0, /* segment base address */
1234 0xfffff, /* length - all address space */
1235 SDT_MEMRWA, /* segment type */
1236 SEL_KPL, /* segment descriptor priority level */
1237 1, /* segment descriptor present */
1238 1, /* long */
1239 0, /* default 32 vs 16 bit size */
1240 1 /* limit granularity (byte/page units)*/ },
1241/* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1242{ 0x0, /* segment base address */
1243 0xfffff, /* length - all address space */
1244 SDT_MEMERA, /* segment type */
1245 SEL_UPL, /* segment descriptor priority level */
1246 1, /* segment descriptor present */
1247 0, /* long */
1248 1, /* default 32 vs 16 bit size */
1249 1 /* limit granularity (byte/page units)*/ },
1250/* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1251{ 0x0, /* segment base address */
1252 0xfffff, /* length - all address space */
1253 SDT_MEMRWA, /* segment type */
1254 SEL_UPL, /* segment descriptor priority level */
1255 1, /* segment descriptor present */
1256 0, /* long */
1257 1, /* default 32 vs 16 bit size */
1258 1 /* limit granularity (byte/page units)*/ },
1259/* GUCODE_SEL 5 64 bit Code Descriptor for user */
1260{ 0x0, /* segment base address */
1261 0xfffff, /* length - all address space */
1262 SDT_MEMERA, /* segment type */
1263 SEL_UPL, /* segment descriptor priority level */
1264 1, /* segment descriptor present */
1265 1, /* long */
1266 0, /* default 32 vs 16 bit size */
1267 1 /* limit granularity (byte/page units)*/ },
1268/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1269{
1270 0x0, /* segment base address */
b2b3ffcd 1271 sizeof(struct x86_64tss)-1,/* length - all address space */
c8fe38ae
MD
1272 SDT_SYSTSS, /* segment type */
1273 SEL_KPL, /* segment descriptor priority level */
1274 1, /* segment descriptor present */
1275 0, /* long */
1276 0, /* unused - default 32 vs 16 bit size */
1277 0 /* limit granularity (byte/page units)*/ },
1278/* Actually, the TSS is a system descriptor which is double size */
1279{ 0x0, /* segment base address */
1280 0x0, /* length */
1281 0, /* segment type */
1282 0, /* segment descriptor priority level */
1283 0, /* segment descriptor present */
1284 0, /* long */
1285 0, /* default 32 vs 16 bit size */
1286 0 /* limit granularity (byte/page units)*/ },
1287/* GUGS32_SEL 8 32 bit GS Descriptor for user */
1288{ 0x0, /* segment base address */
1289 0xfffff, /* length - all address space */
1290 SDT_MEMRWA, /* segment type */
1291 SEL_UPL, /* segment descriptor priority level */
1292 1, /* segment descriptor present */
1293 0, /* long */
1294 1, /* default 32 vs 16 bit size */
1295 1 /* limit granularity (byte/page units)*/ },
1296};
1297
1298void
8a06c6ee 1299setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
c8fe38ae 1300{
8a06c6ee
SZ
1301 int cpu;
1302
1303 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1304 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1305
1306 ip->gd_looffset = (uintptr_t)func;
1307 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1308 ip->gd_ist = ist;
1309 ip->gd_xx = 0;
1310 ip->gd_type = typ;
1311 ip->gd_dpl = dpl;
1312 ip->gd_p = 1;
1313 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1314 }
c8fe38ae
MD
1315}
1316
8a782434
SZ
1317void
1318setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1319{
1320 struct gate_descriptor *ip;
1321
ed20d0e3 1322 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
8a782434
SZ
1323
1324 ip = &idt_arr[cpu][idx];
1325 ip->gd_looffset = (uintptr_t)func;
1326 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1327 ip->gd_ist = ist;
1328 ip->gd_xx = 0;
1329 ip->gd_type = typ;
1330 ip->gd_dpl = dpl;
1331 ip->gd_p = 1;
1332 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1333}
1334
c8fe38ae
MD
1335#define IDTVEC(name) __CONCAT(X,name)
1336
1337extern inthand_t
1338 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1339 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1340 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1341 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1342 IDTVEC(xmm), IDTVEC(dblfault),
1343 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1344
1345#ifdef DEBUG_INTERRUPTS
1346extern inthand_t *Xrsvdary[256];
1347#endif
1348
1349void
1350sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1351{
1352 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1353 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1354 ssd->ssd_type = sd->sd_type;
1355 ssd->ssd_dpl = sd->sd_dpl;
1356 ssd->ssd_p = sd->sd_p;
1357 ssd->ssd_def32 = sd->sd_def32;
1358 ssd->ssd_gran = sd->sd_gran;
1359}
1360
1361void
1362ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1363{
1364
1365 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1366 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1367 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1368 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1369 sd->sd_type = ssd->ssd_type;
1370 sd->sd_dpl = ssd->ssd_dpl;
1371 sd->sd_p = ssd->ssd_p;
1372 sd->sd_long = ssd->ssd_long;
1373 sd->sd_def32 = ssd->ssd_def32;
1374 sd->sd_gran = ssd->ssd_gran;
1375}
1376
1377void
1378ssdtosyssd(struct soft_segment_descriptor *ssd,
1379 struct system_segment_descriptor *sd)
1380{
1381
1382 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1383 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1384 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1385 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1386 sd->sd_type = ssd->ssd_type;
1387 sd->sd_dpl = ssd->ssd_dpl;
1388 sd->sd_p = ssd->ssd_p;
1389 sd->sd_gran = ssd->ssd_gran;
1390}
1391
c8fe38ae
MD
1392/*
1393 * Populate the (physmap) array with base/bound pairs describing the
1394 * available physical memory in the system, then test this memory and
1395 * build the phys_avail array describing the actually-available memory.
1396 *
1397 * If we cannot accurately determine the physical memory map, then use
1398 * value from the 0xE801 call, and failing that, the RTC.
1399 *
1400 * Total memory size may be set by the kernel environment variable
1401 * hw.physmem or the compile-time define MAXMEM.
1402 *
b4d9abe2
MD
1403 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1404 * of PAGE_SIZE. This also greatly reduces the memory test time
1405 * which would otherwise be excessive on machines with > 8G of ram.
1406 *
c8fe38ae
MD
1407 * XXX first should be vm_paddr_t.
1408 */
b4d9abe2
MD
1409
1410#define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1411#define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1412
c8fe38ae
MD
1413static void
1414getmemsize(caddr_t kmdp, u_int64_t first)
1415{
b4d9abe2
MD
1416 int off, physmap_idx, pa_indx, da_indx;
1417 int i, j;
1418 vm_paddr_t physmap[PHYSMAP_SIZE];
1419 vm_paddr_t pa;
1420 vm_paddr_t msgbuf_size;
c8fe38ae
MD
1421 u_long physmem_tunable;
1422 pt_entry_t *pte;
1423 struct bios_smap *smapbase, *smap, *smapend;
1424 u_int32_t smapsize;
1425 quad_t dcons_addr, dcons_size;
1426
1427 bzero(physmap, sizeof(physmap));
c8fe38ae
MD
1428 physmap_idx = 0;
1429
1430 /*
1431 * get memory map from INT 15:E820, kindly supplied by the loader.
1432 *
1433 * subr_module.c says:
1434 * "Consumer may safely assume that size value precedes data."
1435 * ie: an int32_t immediately precedes smap.
1436 */
1437 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1438 MODINFO_METADATA | MODINFOMD_SMAP);
1439 if (smapbase == NULL)
1440 panic("No BIOS smap info from loader!");
1441
1442 smapsize = *((u_int32_t *)smapbase - 1);
1443 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1444
1445 for (smap = smapbase; smap < smapend; smap++) {
1446 if (boothowto & RB_VERBOSE)
1447 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1448 smap->type, smap->base, smap->length);
1449
1450 if (smap->type != SMAP_TYPE_MEMORY)
1451 continue;
1452
1453 if (smap->length == 0)
1454 continue;
1455
1456 for (i = 0; i <= physmap_idx; i += 2) {
1457 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1458 if (boothowto & RB_VERBOSE) {
1459 kprintf("Overlapping or non-monotonic "
1460 "memory region, ignoring "
1461 "second region\n");
1462 }
2eddd927 1463 break;
c8fe38ae
MD
1464 }
1465 }
2eddd927
MD
1466 if (i <= physmap_idx)
1467 continue;
1468
1bda0d3d 1469 Realmem += smap->length;
c8fe38ae
MD
1470
1471 if (smap->base == physmap[physmap_idx + 1]) {
1472 physmap[physmap_idx + 1] += smap->length;
1473 continue;
1474 }
1475
1476 physmap_idx += 2;
1477 if (physmap_idx == PHYSMAP_SIZE) {
1bda0d3d
MD
1478 kprintf("Too many segments in the physical "
1479 "address map, giving up\n");
c8fe38ae
MD
1480 break;
1481 }
1482 physmap[physmap_idx] = smap->base;
1483 physmap[physmap_idx + 1] = smap->base + smap->length;
1484 }
1485
8936cd9b 1486 base_memory = physmap[1] / 1024;
c8fe38ae 1487 /* make hole for AP bootstrap code */
8936cd9b 1488 physmap[1] = mp_bootaddress(base_memory);
2331304b 1489
927c4c1f
MN
1490 /* Save EBDA address, if any */
1491 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1492 ebda_addr <<= 4;
c8fe38ae
MD
1493
1494 /*
1495 * Maxmem isn't the "maximum memory", it's one larger than the
1496 * highest page of the physical address space. It should be
1497 * called something like "Maxphyspage". We may adjust this
1498 * based on ``hw.physmem'' and the results of the memory test.
1499 */
1500 Maxmem = atop(physmap[physmap_idx + 1]);
1501
1502#ifdef MAXMEM
1503 Maxmem = MAXMEM / 4;
1504#endif
1505
1506 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1507 Maxmem = atop(physmem_tunable);
1508
1509 /*
1510 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1511 * in the system.
1512 */
1513 if (Maxmem > atop(physmap[physmap_idx + 1]))
1514 Maxmem = atop(physmap[physmap_idx + 1]);
1515
8e5ea5f7 1516 /*
b4d9abe2 1517 * Blowing out the DMAP will blow up the system.
8e5ea5f7
MD
1518 */
1519 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1520 kprintf("Limiting Maxmem due to DMAP size\n");
1521 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1522 }
1523
c8fe38ae 1524 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
b4d9abe2 1525 (boothowto & RB_VERBOSE)) {
c8fe38ae 1526 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
b4d9abe2 1527 }
c8fe38ae 1528
b4d9abe2
MD
1529 /*
1530 * Call pmap initialization to make new kernel address space
1531 *
1532 * Mask off page 0.
1533 */
48ffc236 1534 pmap_bootstrap(&first);
b4d9abe2
MD
1535 physmap[0] = PAGE_SIZE;
1536
1537 /*
1538 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1539 * exceeding Maxmem.
1540 */
1541 for (i = j = 0; i <= physmap_idx; i += 2) {
06bb314f
SW
1542 if (physmap[i+1] > ptoa(Maxmem))
1543 physmap[i+1] = ptoa(Maxmem);
b4d9abe2
MD
1544 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1545 ~PHYSMAP_ALIGN_MASK;
1546 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1547
1548 physmap[j] = physmap[i];
1549 physmap[j+1] = physmap[i+1];
1550
1551 if (physmap[i] < physmap[i+1])
1552 j += 2;
1553 }
1554 physmap_idx = j - 2;
1555
1556 /*
1557 * Align anything else used in the validation loop.
1558 */
1559 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
c8fe38ae
MD
1560
1561 /*
1562 * Size up each available chunk of physical memory.
1563 */
c8fe38ae
MD
1564 pa_indx = 0;
1565 da_indx = 1;
1566 phys_avail[pa_indx++] = physmap[0];
1567 phys_avail[pa_indx] = physmap[0];
1568 dump_avail[da_indx] = physmap[0];
1569 pte = CMAP1;
1570
1571 /*
1572 * Get dcons buffer address
1573 */
1574 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1575 kgetenv_quad("dcons.size", &dcons_size) == 0)
1576 dcons_addr = 0;
1577
1578 /*
b4d9abe2
MD
1579 * Validate the physical memory. The physical memory segments
1580 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1581 * of PAGE_SIZE.
c8fe38ae
MD
1582 */
1583 for (i = 0; i <= physmap_idx; i += 2) {
1584 vm_paddr_t end;
1585
b4d9abe2
MD
1586 end = physmap[i + 1];
1587
1588 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
c8fe38ae
MD
1589 int tmp, page_bad, full;
1590 int *ptr = (int *)CADDR1;
1591
1592 full = FALSE;
1593 /*
1594 * block out kernel memory as not available.
1595 */
0aefa526 1596 if (pa >= 0x200000 && pa < first)
c8fe38ae
MD
1597 goto do_dump_avail;
1598
1599 /*
1600 * block out dcons buffer
1601 */
1602 if (dcons_addr > 0
1603 && pa >= trunc_page(dcons_addr)
b4d9abe2 1604 && pa < dcons_addr + dcons_size) {
c8fe38ae 1605 goto do_dump_avail;
b4d9abe2 1606 }
c8fe38ae
MD
1607
1608 page_bad = FALSE;
1609
1610 /*
1611 * map page into kernel: valid, read/write,non-cacheable
1612 */
1613 *pte = pa | PG_V | PG_RW | PG_N;
1614 cpu_invltlb();
1615
06bb314f 1616 tmp = *ptr;
c8fe38ae
MD
1617 /*
1618 * Test for alternating 1's and 0's
1619 */
1620 *(volatile int *)ptr = 0xaaaaaaaa;
b4d9abe2 1621 cpu_mfence();
c8fe38ae
MD
1622 if (*(volatile int *)ptr != 0xaaaaaaaa)
1623 page_bad = TRUE;
1624 /*
1625 * Test for alternating 0's and 1's
1626 */
1627 *(volatile int *)ptr = 0x55555555;
b4d9abe2 1628 cpu_mfence();
c8fe38ae
MD
1629 if (*(volatile int *)ptr != 0x55555555)
1630 page_bad = TRUE;
1631 /*
1632 * Test for all 1's
1633 */
1634 *(volatile int *)ptr = 0xffffffff;
b4d9abe2 1635 cpu_mfence();
c8fe38ae
MD
1636 if (*(volatile int *)ptr != 0xffffffff)
1637 page_bad = TRUE;
1638 /*
1639 * Test for all 0's
1640 */
1641 *(volatile int *)ptr = 0x0;
b4d9abe2 1642 cpu_mfence();
c8fe38ae
MD
1643 if (*(volatile int *)ptr != 0x0)
1644 page_bad = TRUE;
1645 /*
1646 * Restore original value.
1647 */
06bb314f 1648 *ptr = tmp;
c8fe38ae
MD
1649
1650 /*
1651 * Adjust array of valid/good pages.
1652 */
1653 if (page_bad == TRUE)
1654 continue;
1655 /*
1656 * If this good page is a continuation of the
1657 * previous set of good pages, then just increase
1658 * the end pointer. Otherwise start a new chunk.
1659 * Note that "end" points one higher than end,
1660 * making the range >= start and < end.
1661 * If we're also doing a speculative memory
1662 * test and we at or past the end, bump up Maxmem
1663 * so that we keep going. The first bad page
1664 * will terminate the loop.
1665 */
1666 if (phys_avail[pa_indx] == pa) {
b4d9abe2 1667 phys_avail[pa_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1668 } else {
1669 pa_indx++;
1670 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1671 kprintf(
1672 "Too many holes in the physical address space, giving up\n");
1673 pa_indx--;
1674 full = TRUE;
1675 goto do_dump_avail;
1676 }
b4d9abe2
MD
1677 phys_avail[pa_indx++] = pa;
1678 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae 1679 }
7a3eee88 1680 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
c8fe38ae
MD
1681do_dump_avail:
1682 if (dump_avail[da_indx] == pa) {
b4d9abe2 1683 dump_avail[da_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1684 } else {
1685 da_indx++;
1686 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1687 da_indx--;
1688 goto do_next;
1689 }
b4d9abe2
MD
1690 dump_avail[da_indx++] = pa;
1691 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1692 }
1693do_next:
1694 if (full)
1695 break;
1696 }
1697 }
1698 *pte = 0;
1699 cpu_invltlb();
1700
1701 /*
c8fe38ae
MD
1702 * The last chunk must contain at least one page plus the message
1703 * buffer to avoid complicating other code (message buffer address
1704 * calculation, etc.).
1705 */
b4d9abe2
MD
1706 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1707
1708 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1709 msgbuf_size >= phys_avail[pa_indx]) {
c8fe38ae
MD
1710 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1711 phys_avail[pa_indx--] = 0;
1712 phys_avail[pa_indx--] = 0;
1713 }
1714
1715 Maxmem = atop(phys_avail[pa_indx]);
1716
1717 /* Trim off space for the message buffer. */
b4d9abe2 1718 phys_avail[pa_indx] -= msgbuf_size;
c8fe38ae 1719
1185babf
JG
1720 avail_end = phys_avail[pa_indx];
1721
c8fe38ae 1722 /* Map the message buffer. */
b4d9abe2
MD
1723 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1724 pmap_kenter((vm_offset_t)msgbufp + off,
1725 phys_avail[pa_indx] + off);
1726 }
c8fe38ae
MD
1727}
1728
faaf4131
MN
1729struct machintr_abi MachIntrABI;
1730
c8fe38ae
MD
1731/*
1732 * IDT VECTORS:
1733 * 0 Divide by zero
1734 * 1 Debug
1735 * 2 NMI
1736 * 3 BreakPoint
1737 * 4 OverFlow
1738 * 5 Bound-Range
1739 * 6 Invalid OpCode
1740 * 7 Device Not Available (x87)
1741 * 8 Double-Fault
1742 * 9 Coprocessor Segment overrun (unsupported, reserved)
1743 * 10 Invalid-TSS
1744 * 11 Segment not present
1745 * 12 Stack
1746 * 13 General Protection
1747 * 14 Page Fault
1748 * 15 Reserved
1749 * 16 x87 FP Exception pending
1750 * 17 Alignment Check
1751 * 18 Machine Check
1752 * 19 SIMD floating point
1753 * 20-31 reserved
1754 * 32-255 INTn/external sources
1755 */
1756u_int64_t
1757hammer_time(u_int64_t modulep, u_int64_t physfree)
1758{
1759 caddr_t kmdp;
8a06c6ee 1760 int gsel_tss, x, cpu;
5b9f6cc4
MD
1761#if JG
1762 int metadata_missing, off;
1763#endif
c8fe38ae
MD
1764 struct mdglobaldata *gd;
1765 u_int64_t msr;
c8fe38ae 1766
c8fe38ae
MD
1767 /*
1768 * Prevent lowering of the ipl if we call tsleep() early.
1769 */
1770 gd = &CPU_prvspace[0].mdglobaldata;
1771 bzero(gd, sizeof(*gd));
1772
1773 /*
1774 * Note: on both UP and SMP curthread must be set non-NULL
1775 * early in the boot sequence because the system assumes
1776 * that 'curthread' is never NULL.
1777 */
1778
1779 gd->mi.gd_curthread = &thread0;
1780 thread0.td_gd = &gd->mi;
1781
1782 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1783
1784#if JG
1785 metadata_missing = 0;
1786 if (bootinfo.bi_modulep) {
1787 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1788 preload_bootstrap_relocate(KERNBASE);
1789 } else {
1790 metadata_missing = 1;
1791 }
1792 if (bootinfo.bi_envp)
1793 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1794#endif
1795
1796 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1797 preload_bootstrap_relocate(PTOV_OFFSET);
1798 kmdp = preload_search_by_type("elf kernel");
1799 if (kmdp == NULL)
1800 kmdp = preload_search_by_type("elf64 kernel");
1801 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1802 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1803#ifdef DDB
1804 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1805 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1806#endif
1807
27af435a
SZ
1808 if (boothowto & RB_VERBOSE)
1809 bootverbose++;
1810
faaf4131 1811 /*
10db3cc6 1812 * Default MachIntrABI to ICU
faaf4131
MN
1813 */
1814 MachIntrABI = MachIntrABI_ICU;
9a4bd8f3 1815
c8fe38ae
MD
1816 /*
1817 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1818 * and ncpus_fit_mask remain 0.
1819 */
1820 ncpus = 1;
1821 ncpus2 = 1;
1822 ncpus_fit = 1;
1823 /* Init basic tunables, hz etc */
1824 init_param1();
1825
1826 /*
1827 * make gdt memory segments
1828 */
1829 gdt_segs[GPROC0_SEL].ssd_base =
1830 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1831
1832 gd->mi.gd_prvspace = &CPU_prvspace[0];
1833
1834 for (x = 0; x < NGDT; x++) {
1835 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1836 ssdtosd(&gdt_segs[x], &gdt[x]);
1837 }
1838 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1839 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
48ffc236 1840
c8fe38ae
MD
1841 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1842 r_gdt.rd_base = (long) gdt;
1843 lgdt(&r_gdt);
1844
1845 wrmsr(MSR_FSBASE, 0); /* User value */
1846 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1847 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1848
1849 mi_gdinit(&gd->mi, 0);
1850 cpu_gdinit(gd, 0);
1851 proc0paddr = proc0paddr_buff;
1852 mi_proc0init(&gd->mi, proc0paddr);
1853 safepri = TDPRI_MAX;
1854
1855 /* spinlocks and the BGL */
1856 init_locks();
1857
1858 /* exceptions */
1859 for (x = 0; x < NIDT; x++)
8a06c6ee
SZ
1860 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1861 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1862 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1863 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1864 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1865 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1866 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1867 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1868 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1869 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1870 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1871 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1872 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1873 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1874 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1875 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1876 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1877 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1878 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1879 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1880
1881 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1882 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
1883 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
1884 }
1885
1886 lidt(&r_idt_arr[0]);
c8fe38ae
MD
1887
1888 /*
1889 * Initialize the console before we print anything out.
1890 */
1891 cninit();
1892
1893#if JG
1894 if (metadata_missing)
1895 kprintf("WARNING: loader(8) metadata is missing!\n");
1896#endif
1897
1898#if NISA >0
e24dd6e0 1899 elcr_probe();
c8fe38ae
MD
1900 isa_defaultirq();
1901#endif
1902 rand_initialize();
1903
a3dd9120
SZ
1904 /*
1905 * Initialize IRQ mapping
1906 *
1907 * NOTE:
1908 * SHOULD be after elcr_probe()
1909 */
1910 MachIntrABI_ICU.initmap();
a3dd9120 1911 MachIntrABI_IOAPIC.initmap();
a3dd9120 1912
c8fe38ae
MD
1913#ifdef DDB
1914 kdb_init();
1915 if (boothowto & RB_KDB)
1916 Debugger("Boot flags requested debugger");
1917#endif
1918
1919#if JG
1920 finishidentcpu(); /* Final stage of CPU initialization */
2883d2d8
MD
1921 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1922 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
c8fe38ae
MD
1923#endif
1924 identify_cpu(); /* Final stage of CPU initialization */
1925 initializecpu(); /* Initialize CPU registers */
1926
e6dee928
SZ
1927 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1928 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1929 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
1930
1931 /*
08771751 1932 * Some of the virtual machines do not work w/ I/O APIC
e6dee928
SZ
1933 * enabled. If the user does not explicitly enable or
1934 * disable the I/O APIC (ioapic_enable < 0), then we
1935 * disable I/O APIC on all virtual machines.
1936 *
1937 * NOTE:
1938 * This must be done after identify_cpu(), which sets
1939 * 'cpu_feature2'
1940 */
1941 if (ioapic_enable < 0) {
1942 if (cpu_feature2 & CPUID2_VMM)
1943 ioapic_enable = 0;
1944 else
1945 ioapic_enable = 1;
1946 }
1947
c8fe38ae 1948 /* make an initial tss so cpu can get interrupt stack on syscall! */
5b9f6cc4
MD
1949 gd->gd_common_tss.tss_rsp0 =
1950 (register_t)(thread0.td_kstack +
1951 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
c8fe38ae 1952 /* Ensure the stack is aligned to 16 bytes */
2883d2d8 1953 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
c8fe38ae 1954
093565f2
MD
1955 /* double fault stack */
1956 gd->gd_common_tss.tss_ist1 =
1957 (long)&gd->mi.gd_prvspace->idlestack[
1958 sizeof(gd->mi.gd_prvspace->idlestack)];
c8fe38ae
MD
1959
1960 /* Set the IO permission bitmap (empty due to tss seg limit) */
b2b3ffcd 1961 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
c8fe38ae
MD
1962
1963 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1964 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1965 gd->gd_common_tssd = *gd->gd_tss_gdt;
1966 ltr(gsel_tss);
1967
1968 /* Set up the fast syscall stuff */
1969 msr = rdmsr(MSR_EFER) | EFER_SCE;
1970 wrmsr(MSR_EFER, msr);
1971 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1972 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1973 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1974 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1975 wrmsr(MSR_STAR, msr);
3338cc67 1976 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
c8fe38ae
MD
1977
1978 getmemsize(kmdp, physfree);
1979 init_param2(physmem);
1980
1981 /* now running on new page tables, configured,and u/iom is accessible */
1982
1983 /* Map the message buffer. */
1984#if JG
1985 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1986 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1987#endif
1988
1989 msgbufinit(msgbufp, MSGBUF_SIZE);
1990
1991
1992 /* transfer to user mode */
1993
1994 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1995 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1996 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1997
1998 load_ds(_udatasel);
1999 load_es(_udatasel);
2000 load_fs(_udatasel);
2001
2002 /* setup proc 0's pcb */
2003 thread0.td_pcb->pcb_flags = 0;
c8fe38ae 2004 thread0.td_pcb->pcb_cr3 = KPML4phys;
d8061892 2005 thread0.td_pcb->pcb_ext = NULL;
d1368d1a 2006 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
c8fe38ae
MD
2007
2008 /* Location of kernel stack for locore */
2009 return ((u_int64_t)thread0.td_pcb);
2010}
2011
2012/*
2013 * Initialize machine-dependant portions of the global data structure.
2014 * Note that the global data area and cpu0's idlestack in the private
2015 * data space were allocated in locore.
2016 *
2017 * Note: the idlethread's cpl is 0
2018 *
2019 * WARNING! Called from early boot, 'mycpu' may not work yet.
2020 */
2021void
2022cpu_gdinit(struct mdglobaldata *gd, int cpu)
2023{
2024 if (cpu)
2025 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2026
2027 lwkt_init_thread(&gd->mi.gd_idlethread,
2028 gd->mi.gd_prvspace->idlestack,
2029 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2030 0, &gd->mi);
c8fe38ae
MD
2031 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2032 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2033 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2034 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2035}
2036
2037int
2038is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2039{
2040 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2041 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2042 return (TRUE);
2043 }
616516c8
MD
2044 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2045 return (TRUE);
c8fe38ae
MD
2046 return (FALSE);
2047}
2048
2049struct globaldata *
2050globaldata_find(int cpu)
2051{
2052 KKASSERT(cpu >= 0 && cpu < ncpus);
2053 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2054}
2055
c8fe38ae
MD
2056int
2057ptrace_set_pc(struct lwp *lp, unsigned long addr)
2058{
5b9f6cc4 2059 lp->lwp_md.md_regs->tf_rip = addr;
c8fe38ae
MD
2060 return (0);
2061}
2062
2063int
2064ptrace_single_step(struct lwp *lp)
2065{
5b9f6cc4 2066 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
c8fe38ae
MD
2067 return (0);
2068}
2069
2070int
2071fill_regs(struct lwp *lp, struct reg *regs)
2072{
c8fe38ae
MD
2073 struct trapframe *tp;
2074
d64d3805
MD
2075 if ((tp = lp->lwp_md.md_regs) == NULL)
2076 return EINVAL;
5b9f6cc4 2077 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
c8fe38ae
MD
2078 return (0);
2079}
2080
2081int
2082set_regs(struct lwp *lp, struct reg *regs)
2083{
c8fe38ae
MD
2084 struct trapframe *tp;
2085
2086 tp = lp->lwp_md.md_regs;
5b9f6cc4 2087 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
c8fe38ae
MD
2088 !CS_SECURE(regs->r_cs))
2089 return (EINVAL);
5b9f6cc4 2090 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
f2081646 2091 clear_quickret();
c8fe38ae
MD
2092 return (0);
2093}
2094
2095#ifndef CPU_DISABLE_SSE
2096static void
2097fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2098{
2099 struct env87 *penv_87 = &sv_87->sv_env;
2100 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2101 int i;
2102
2103 /* FPU control/status */
2104 penv_87->en_cw = penv_xmm->en_cw;
2105 penv_87->en_sw = penv_xmm->en_sw;
2106 penv_87->en_tw = penv_xmm->en_tw;
2107 penv_87->en_fip = penv_xmm->en_fip;
2108 penv_87->en_fcs = penv_xmm->en_fcs;
2109 penv_87->en_opcode = penv_xmm->en_opcode;
2110 penv_87->en_foo = penv_xmm->en_foo;
2111 penv_87->en_fos = penv_xmm->en_fos;
2112
2113 /* FPU registers */
2114 for (i = 0; i < 8; ++i)
2115 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
c8fe38ae
MD
2116}
2117
2118static void
2119set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2120{
2121 struct env87 *penv_87 = &sv_87->sv_env;
2122 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2123 int i;
2124
2125 /* FPU control/status */
2126 penv_xmm->en_cw = penv_87->en_cw;
2127 penv_xmm->en_sw = penv_87->en_sw;
2128 penv_xmm->en_tw = penv_87->en_tw;
2129 penv_xmm->en_fip = penv_87->en_fip;
2130 penv_xmm->en_fcs = penv_87->en_fcs;
2131 penv_xmm->en_opcode = penv_87->en_opcode;
2132 penv_xmm->en_foo = penv_87->en_foo;
2133 penv_xmm->en_fos = penv_87->en_fos;
2134
2135 /* FPU registers */
2136 for (i = 0; i < 8; ++i)
2137 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
c8fe38ae
MD
2138}
2139#endif /* CPU_DISABLE_SSE */
2140
2141int
2142fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2143{
d64d3805
MD
2144 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2145 return EINVAL;
c8fe38ae
MD
2146#ifndef CPU_DISABLE_SSE
2147 if (cpu_fxsr) {
2148 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2149 (struct save87 *)fpregs);
2150 return (0);
2151 }
2152#endif /* CPU_DISABLE_SSE */
2153 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2154 return (0);
2155}
2156
2157int
2158set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2159{
2160#ifndef CPU_DISABLE_SSE
2161 if (cpu_fxsr) {
2162 set_fpregs_xmm((struct save87 *)fpregs,
2163 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2164 return (0);
2165 }
2166#endif /* CPU_DISABLE_SSE */
2167 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2168 return (0);
2169}
2170
2171int
2172fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2173{
d64d3805
MD
2174 struct pcb *pcb;
2175
c8fe38ae 2176 if (lp == NULL) {
0855a2af
JG
2177 dbregs->dr[0] = rdr0();
2178 dbregs->dr[1] = rdr1();
2179 dbregs->dr[2] = rdr2();
2180 dbregs->dr[3] = rdr3();
2181 dbregs->dr[4] = rdr4();
2182 dbregs->dr[5] = rdr5();
2183 dbregs->dr[6] = rdr6();
2184 dbregs->dr[7] = rdr7();
d64d3805 2185 return (0);
c8fe38ae 2186 }
d64d3805
MD
2187 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2188 return EINVAL;
2189 dbregs->dr[0] = pcb->pcb_dr0;
2190 dbregs->dr[1] = pcb->pcb_dr1;
2191 dbregs->dr[2] = pcb->pcb_dr2;
2192 dbregs->dr[3] = pcb->pcb_dr3;
2193 dbregs->dr[4] = 0;
2194 dbregs->dr[5] = 0;
2195 dbregs->dr[6] = pcb->pcb_dr6;
2196 dbregs->dr[7] = pcb->pcb_dr7;
c8fe38ae
MD
2197 return (0);
2198}
2199
2200int
2201set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2202{
2203 if (lp == NULL) {
0855a2af
JG
2204 load_dr0(dbregs->dr[0]);
2205 load_dr1(dbregs->dr[1]);
2206 load_dr2(dbregs->dr[2]);
2207 load_dr3(dbregs->dr[3]);
2208 load_dr4(dbregs->dr[4]);
2209 load_dr5(dbregs->dr[5]);
2210 load_dr6(dbregs->dr[6]);
2211 load_dr7(dbregs->dr[7]);
c8fe38ae
MD
2212 } else {
2213 struct pcb *pcb;
2214 struct ucred *ucred;
2215 int i;
0855a2af 2216 uint64_t mask1, mask2;
c8fe38ae
MD
2217
2218 /*
2219 * Don't let an illegal value for dr7 get set. Specifically,
2220 * check for undefined settings. Setting these bit patterns
2221 * result in undefined behaviour and can lead to an unexpected
2222 * TRCTRAP.
2223 */
0855a2af
JG
2224 /* JG this loop looks unreadable */
2225 /* Check 4 2-bit fields for invalid patterns.
2226 * These fields are R/Wi, for i = 0..3
2227 */
2228 /* Is 10 in LENi allowed when running in compatibility mode? */
2229 /* Pattern 10 in R/Wi might be used to indicate
2230 * breakpoint on I/O. Further analysis should be
2231 * carried to decide if it is safe and useful to
2232 * provide access to that capability
2233 */
2234 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2235 i++, mask1 <<= 4, mask2 <<= 4)
2236 if ((dbregs->dr[7] & mask1) == mask2)
c8fe38ae 2237 return (EINVAL);
c8fe38ae
MD
2238
2239 pcb = lp->lwp_thread->td_pcb;
2240 ucred = lp->lwp_proc->p_ucred;
2241
2242 /*
2243 * Don't let a process set a breakpoint that is not within the
2244 * process's address space. If a process could do this, it
2245 * could halt the system by setting a breakpoint in the kernel
2246 * (if ddb was enabled). Thus, we need to check to make sure
2247 * that no breakpoints are being enabled for addresses outside
2248 * process's address space, unless, perhaps, we were called by
2249 * uid 0.
2250 *
2251 * XXX - what about when the watched area of the user's
2252 * address space is written into from within the kernel
2253 * ... wouldn't that still cause a breakpoint to be generated
2254 * from within kernel mode?
2255 */
2256
895c1f85 2257 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
0855a2af 2258 if (dbregs->dr[7] & 0x3) {
c8fe38ae 2259 /* dr0 is enabled */
0855a2af 2260 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2261 return (EINVAL);
2262 }
2263
0855a2af 2264 if (dbregs->dr[7] & (0x3<<2)) {
c8fe38ae 2265 /* dr1 is enabled */
0855a2af 2266 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2267 return (EINVAL);
2268 }
2269
0855a2af 2270 if (dbregs->dr[7] & (0x3<<4)) {
c8fe38ae 2271 /* dr2 is enabled */
0855a2af 2272 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2273 return (EINVAL);
2274 }
2275
0855a2af 2276 if (dbregs->dr[7] & (0x3<<6)) {
c8fe38ae 2277 /* dr3 is enabled */
0855a2af 2278 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2279 return (EINVAL);
2280 }
c8fe38ae
MD
2281 }
2282
0855a2af
JG
2283 pcb->pcb_dr0 = dbregs->dr[0];
2284 pcb->pcb_dr1 = dbregs->dr[1];
2285 pcb->pcb_dr2 = dbregs->dr[2];
2286 pcb->pcb_dr3 = dbregs->dr[3];
2287 pcb->pcb_dr6 = dbregs->dr[6];
2288 pcb->pcb_dr7 = dbregs->dr[7];
c8fe38ae
MD
2289
2290 pcb->pcb_flags |= PCB_DBREGS;
2291 }
2292
2293 return (0);
2294}
2295
2296/*
2297 * Return > 0 if a hardware breakpoint has been hit, and the
2298 * breakpoint was in user space. Return 0, otherwise.
2299 */
2300int
2301user_dbreg_trap(void)
2302{
0855a2af
JG
2303 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2304 u_int64_t bp; /* breakpoint bits extracted from dr6 */
c8fe38ae
MD
2305 int nbp; /* number of breakpoints that triggered */
2306 caddr_t addr[4]; /* breakpoint addresses */
2307 int i;
2308
2309 dr7 = rdr7();
0855a2af 2310 if ((dr7 & 0xff) == 0) {
c8fe38ae
MD
2311 /*
2312 * all GE and LE bits in the dr7 register are zero,
2313 * thus the trap couldn't have been caused by the
2314 * hardware debug registers
2315 */
2316 return 0;
2317 }
2318
2319 nbp = 0;
2320 dr6 = rdr6();
0855a2af 2321 bp = dr6 & 0xf;
c8fe38ae 2322
0855a2af 2323 if (bp == 0) {
c8fe38ae
MD
2324 /*
2325 * None of the breakpoint bits are set meaning this
2326 * trap was not caused by any of the debug registers
2327 */
2328 return 0;
2329 }
2330
2331 /*
2332 * at least one of the breakpoints were hit, check to see
2333 * which ones and if any of them are user space addresses
2334 */
2335
2336 if (bp & 0x01) {
2337 addr[nbp++] = (caddr_t)rdr0();
2338 }
2339 if (bp & 0x02) {
2340 addr[nbp++] = (caddr_t)rdr1();
2341 }
2342 if (bp & 0x04) {
2343 addr[nbp++] = (caddr_t)rdr2();
2344 }
2345 if (bp & 0x08) {
2346 addr[nbp++] = (caddr_t)rdr3();
2347 }
2348
2349 for (i=0; i<nbp; i++) {
2350 if (addr[i] <
2351 (caddr_t)VM_MAX_USER_ADDRESS) {
2352 /*
2353 * addr[i] is in user space
2354 */
2355 return nbp;
2356 }
2357 }
2358
2359 /*
2360 * None of the breakpoints are in user space.
2361 */
2362 return 0;
2363}
2364
2365
2366#ifndef DDB
2367void
2368Debugger(const char *msg)
2369{
2370 kprintf("Debugger(\"%s\") called.\n", msg);
2371}
2372#endif /* no DDB */
2373
2374#ifdef DDB
2375
2376/*
2377 * Provide inb() and outb() as functions. They are normally only
2378 * available as macros calling inlined functions, thus cannot be
2379 * called inside DDB.
2380 *
2381 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2382 */
2383
2384#undef inb
2385#undef outb
2386
2387/* silence compiler warnings */
2388u_char inb(u_int);
2389void outb(u_int, u_char);
2390
2391u_char
2392inb(u_int port)
2393{
2394 u_char data;
2395 /*
2396 * We use %%dx and not %1 here because i/o is done at %dx and not at
2397 * %edx, while gcc generates inferior code (movw instead of movl)
2398 * if we tell it to load (u_short) port.
2399 */
2400 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2401 return (data);
2402}
2403
2404void
2405outb(u_int port, u_char data)
2406{
2407 u_char al;
2408 /*
2409 * Use an unnecessary assignment to help gcc's register allocator.
2410 * This make a large difference for gcc-1.40 and a tiny difference
2411 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2412 * best results. gcc-2.6.0 can't handle this.
2413 */
2414 al = data;
2415 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2416}
2417
2418#endif /* DDB */
2419
2420
2421
2422#include "opt_cpu.h"
2423
2424
2425/*
2426 * initialize all the SMP locks
2427 */
2428
2429/* critical region when masking or unmasking interupts */
2430struct spinlock_deprecated imen_spinlock;
2431
c8fe38ae
MD
2432/* critical region for old style disable_intr/enable_intr */
2433struct spinlock_deprecated mpintr_spinlock;
2434
2435/* critical region around INTR() routines */
2436struct spinlock_deprecated intr_spinlock;
2437
2438/* lock region used by kernel profiling */
2439struct spinlock_deprecated mcount_spinlock;
2440
2441/* locks com (tty) data/hardware accesses: a FASTINTR() */
2442struct spinlock_deprecated com_spinlock;
2443
c8fe38ae
MD
2444/* lock regions around the clock hardware */
2445struct spinlock_deprecated clock_spinlock;
2446
c8fe38ae
MD
2447static void
2448init_locks(void)
2449{
2450 /*
b5d16701 2451 * Get the initial mplock with a count of 1 for the BSP.
c8fe38ae
MD
2452 * This uses a LOGICAL cpu ID, ie BSP == 0.
2453 */
c8fe38ae 2454 cpu_get_initial_mplock();
c8fe38ae
MD
2455 /* DEPRECATED */
2456 spin_lock_init(&mcount_spinlock);
c8fe38ae
MD
2457 spin_lock_init(&intr_spinlock);
2458 spin_lock_init(&mpintr_spinlock);
2459 spin_lock_init(&imen_spinlock);
c8fe38ae
MD
2460 spin_lock_init(&com_spinlock);
2461 spin_lock_init(&clock_spinlock);
c8fe38ae
MD
2462
2463 /* our token pool needs to work early */
2464 lwkt_token_pool_init();
2465}
2466