kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / pc64 / x86_64 / swtch.s
CommitLineData
d7f50089 1/*
c8fe38ae
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2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved.
3 * Copyright (c) 2008 Jordan Gordeev.
d7f50089
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4 *
5 * This code is derived from software contributed to The DragonFly Project
6 * by Matthew Dillon <dillon@backplane.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
17 * distribution.
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * Copyright (c) 1990 The Regents of the University of California.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to Berkeley by
39 * William Jolitz.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by the University of
52 * California, Berkeley and its contributors.
53 * 4. Neither the name of the University nor the names of its contributors
54 * may be used to endorse or promote products derived from this software
55 * without specific prior written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 * SUCH DAMAGE.
68 *
69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $
d7f50089
YY
70 */
71
c8fe38ae 72//#include "use_npx.h"
d7f50089
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73
74#include <sys/rtprio.h>
75
76#include <machine/asmacros.h>
77#include <machine/segments.h>
78
79#include <machine/pmap.h>
c8fe38ae
MD
80#if JG
81#include <machine_base/apic/apicreg.h>
82#endif
d7f50089
YY
83#include <machine/lock.h>
84
85#include "assym.s"
86
d7f50089 87#define MPLOCKED lock ;
d7f50089
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88
89 .data
90
91 .globl panic
cc9b6223 92 .globl lwkt_switch_return
d7f50089
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93
94#if defined(SWTCH_OPTIM_STATS)
95 .globl swtch_optim_stats, tlb_flush_count
96swtch_optim_stats: .long 0 /* number of _swtch_optims */
97tlb_flush_count: .long 0
98#endif
99
100 .text
101
102
103/*
c8fe38ae 104 * cpu_heavy_switch(struct thread *next_thread)
d7f50089
YY
105 *
106 * Switch from the current thread to a new thread. This entry
107 * is normally called via the thread->td_switch function, and will
108 * only be called when the current thread is a heavy weight process.
109 *
110 * Some instructions have been reordered to reduce pipeline stalls.
111 *
112 * YYY disable interrupts once giant is removed.
113 */
114ENTRY(cpu_heavy_switch)
c8fe38ae
MD
115 /*
116 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15).
117 */
118 movq PCPU(curthread),%rcx
119 /* On top of the stack is the return adress. */
120 movq (%rsp),%rax /* (reorder optimization) */
121 movq TD_PCB(%rcx),%rdx /* RDX = PCB */
122 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */
123 movq %rbx,PCB_RBX(%rdx)
124 movq %rsp,PCB_RSP(%rdx)
125 movq %rbp,PCB_RBP(%rdx)
126 movq %r12,PCB_R12(%rdx)
127 movq %r13,PCB_R13(%rdx)
128 movq %r14,PCB_R14(%rdx)
129 movq %r15,PCB_R15(%rdx)
130
b25897b2
MD
131 /*
132 * Clear the cpu bit in the pmap active mask. The restore
133 * function will set the bit in the pmap active mask.
134 *
135 * Special case: when switching between threads sharing the
136 * same vmspace if we avoid clearing the bit we do not have
137 * to reload %cr3 (if we clear the bit we could race page
138 * table ops done by other threads and would have to reload
139 * %cr3, because those ops will not know to IPI us).
140 */
141 movq %rcx,%rbx /* RBX = oldthread */
142 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */
143 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */
144 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */
145 testq %r13,%r13 /* might not be a heavy */
146 jz 1f
147 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */
148 je 2f
1491:
da23a592
MD
150 movslq PCPU(cpuid), %rax
151 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx)
b25897b2 1522:
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MD
153
154 /*
155 * Push the LWKT switch restore function, which resumes a heavy
156 * weight process. Note that the LWKT switcher is based on
157 * TD_SP, while the heavy weight process switcher is based on
158 * PCB_RSP. TD_SP is usually two ints pushed relative to
159 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore.
160 */
161 pushfq
3338cc67 162 cli
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MD
163 movq $cpu_heavy_restore, %rax
164 pushq %rax
165 movq %rsp,TD_SP(%rbx)
166
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MD
167 /*
168 * Save debug regs if necessary
169 */
0855a2af
JG
170 movq PCB_FLAGS(%rdx),%rax
171 andq $PCB_DBREGS,%rax
c8fe38ae 172 jz 1f /* no, skip over */
0855a2af
JG
173 movq %dr7,%rax /* yes, do the save */
174 movq %rax,PCB_DR7(%rdx)
175 /* JG correct value? */
176 andq $0x0000fc00, %rax /* disable all watchpoints */
177 movq %rax,%dr7
178 movq %dr6,%rax
179 movq %rax,PCB_DR6(%rdx)
180 movq %dr3,%rax
181 movq %rax,PCB_DR3(%rdx)
182 movq %dr2,%rax
183 movq %rax,PCB_DR2(%rdx)
184 movq %dr1,%rax
185 movq %rax,PCB_DR1(%rdx)
186 movq %dr0,%rax
187 movq %rax,PCB_DR0(%rdx)
c8fe38ae 1881:
c8fe38ae 189
c4f8086e 190#if 1
c8fe38ae
MD
191 /*
192 * Save the FP state if we have used the FP. Note that calling
193 * npxsave will NULL out PCPU(npxthread).
194 */
9648fee1 195 cmpq %rbx,PCPU(npxthread)
c8fe38ae 196 jne 1f
9648fee1
JG
197 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */
198 movq TD_SAVEFPU(%rbx),%rdi
c8fe38ae 199 call npxsave /* do it in a big C function */
9648fee1 200 movq %r12,%rdi /* restore %rdi */
c8fe38ae 2011:
c4f8086e 202#endif
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MD
203
204 /*
205 * Switch to the next thread, which was passed as an argument
206 * to cpu_heavy_switch(). The argument is in %rdi.
207 * Set the current thread, load the stack pointer,
208 * and 'ret' into the switch-restore function.
209 *
210 * The switch restore function expects the new thread to be in %rax
211 * and the old one to be in %rbx.
212 *
213 * There is a one-instruction window where curthread is the new
214 * thread but %rsp still points to the old thread's stack, but
215 * we are protected by a critical section so it is ok.
216 */
217 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */
218 movq %rax,PCPU(curthread)
219 movq TD_SP(%rax),%rsp
c8fe38ae 220 ret
d7f50089
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221
222/*
c8fe38ae 223 * cpu_exit_switch(struct thread *next)
d7f50089
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224 *
225 * The switch function is changed to this when a thread is going away
226 * for good. We have to ensure that the MMU state is not cached, and
227 * we don't bother saving the existing thread state before switching.
228 *
229 * At this point we are in a critical section and this cpu owns the
230 * thread's token, which serves as an interlock until the switchout is
231 * complete.
232 */
233ENTRY(cpu_exit_switch)
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MD
234 /*
235 * Get us out of the vmspace
236 */
48ffc236 237 movq KPML4phys,%rcx
c8fe38ae 238 movq %cr3,%rax
d8d8c8c5 239#if 1
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MD
240 cmpq %rcx,%rax
241 je 1f
d8d8c8c5 242#endif
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MD
243 /* JG no increment of statistics counters? see cpu_heavy_restore */
244 movq %rcx,%cr3
2451:
c8fe38ae
MD
246 movq PCPU(curthread),%rbx
247
248 /*
249 * If this is a process/lwp, deactivate the pmap after we've
250 * switched it out.
251 */
252 movq TD_LWP(%rbx),%rcx
253 testq %rcx,%rcx
254 jz 2f
da23a592 255 movslq PCPU(cpuid), %rax
c8fe38ae 256 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */
da23a592 257 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx)
c8fe38ae
MD
2582:
259 /*
260 * Switch to the next thread. RET into the restore function, which
261 * expects the new thread in RAX and the old in RBX.
262 *
263 * There is a one-instruction window where curthread is the new
264 * thread but %rsp still points to the old thread's stack, but
265 * we are protected by a critical section so it is ok.
266 */
3338cc67 267 cli
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MD
268 movq %rdi,%rax
269 movq %rax,PCPU(curthread)
270 movq TD_SP(%rax),%rsp
c8fe38ae 271 ret
d7f50089
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272
273/*
0ae279a9 274 * cpu_heavy_restore() (current thread in %rax on entry, old thread in %rbx)
d7f50089
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275 *
276 * Restore the thread after an LWKT switch. This entry is normally
277 * called via the LWKT switch restore function, which was pulled
278 * off the thread stack and jumped to.
279 *
280 * This entry is only called if the thread was previously saved
281 * using cpu_heavy_switch() (the heavy weight process thread switcher),
cc9b6223 282 * or when a new process is initially scheduled.
d7f50089
YY
283 *
284 * NOTE: The lwp may be in any state, not necessarily LSRUN, because
285 * a preemption switch may interrupt the process and then return via
286 * cpu_heavy_restore.
287 *
288 * YYY theoretically we do not have to restore everything here, a lot
289 * of this junk can wait until we return to usermode. But for now
290 * we restore everything.
291 *
292 * YYY the PCB crap is really crap, it makes startup a bitch because
293 * we can't switch away.
294 *
295 * YYY note: spl check is done in mi_switch when it splx()'s.
296 */
297
298ENTRY(cpu_heavy_restore)
121f93bc
MD
299 movq TD_PCB(%rax),%rdx /* RDX = PCB */
300 movq %rdx, PCPU(common_tss) + TSS_RSP0
c8fe38ae 301 popfq
c8fe38ae
MD
302
303#if defined(SWTCH_OPTIM_STATS)
304 incl _swtch_optim_stats
305#endif
306 /*
307 * Tell the pmap that our cpu is using the VMSPACE now. We cannot
308 * safely test/reload %cr3 until after we have set the bit in the
d8d8c8c5 309 * pmap.
b25897b2 310 *
d8d8c8c5
MD
311 * We must do an interlocked test of the CPUMASK_BIT at the same
312 * time. If found to be set we will have to wait for it to clear
313 * and then do a forced reload of %cr3 (even if the value matches).
b25897b2 314 *
d8d8c8c5
MD
315 * XXX When switching between two LWPs sharing the same vmspace
316 * the cpu_heavy_switch() code currently avoids clearing the
317 * cpu bit in PM_ACTIVE. So if the bit is already set we can
318 * avoid checking for the interlock via CPUMASK_BIT. We currently
319 * do not perform this optimization.
320 *
321 * %rax is needed for the cmpxchgl so store newthread in %r12
322 * temporarily.
c8fe38ae 323 */
d8d8c8c5
MD
324 movq TD_LWP(%rax),%rcx
325 movq LWP_VMSPACE(%rcx),%rcx /* RCX = vmspace */
d8d8c8c5
MD
326 movq %rax,%r12 /* save newthread ptr */
3271:
328 movq VM_PMAP+PM_ACTIVE(%rcx),%rax /* old contents */
329 movq PCPU(cpumask),%rsi /* new contents */
330 orq %rax,%rsi
331 MPLOCKED cmpxchgq %rsi,VM_PMAP+PM_ACTIVE(%rcx)
332 jnz 1b
333
334 /*
335 * Check CPUMASK_BIT
336 */
337 btq $CPUMASK_BIT,%rax /* test interlock */
da23a592 338 jnc 1f
121f93bc
MD
339
340#if 0
341 movq TD_PCB(%r12),%rdx /* XXX debugging unconditional */
342 movq PCB_CR3(%rdx),%rdx /* reloading of %cr3 */
343 movq %rdx,%cr3
344#endif
345
d8d8c8c5
MD
346 movq %rcx,%rdi /* (found to be set) */
347 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */
348
349 /*
350 * Need unconditional load cr3
351 */
352 movq %r12,%rax
353 movq TD_PCB(%rax),%rdx /* RDX = PCB */
354 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */
355 jmp 2f /* unconditional reload */
c2fb025d 3561:
d8d8c8c5 357 movq %r12,%rax /* restore RAX = newthread */
c8fe38ae
MD
358 /*
359 * Restore the MMU address space. If it is the same as the last
360 * thread we don't have to invalidate the tlb (i.e. reload cr3).
361 * YYY which naturally also means that the PM_ACTIVE bit had better
362 * already have been set before we set it above, check? YYY
363 */
c2fb025d 364 movq TD_PCB(%rax),%rdx /* RDX = PCB */
d8d8c8c5
MD
365 movq %cr3,%rsi /* RSI = current CR3 */
366 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */
c8fe38ae
MD
367 cmpq %rsi,%rcx
368 je 4f
d8d8c8c5 3692:
c8fe38ae
MD
370#if defined(SWTCH_OPTIM_STATS)
371 decl _swtch_optim_stats
372 incl _tlb_flush_count
373#endif
374 movq %rcx,%cr3
3754:
d8d8c8c5 376
c8fe38ae 377 /*
0ae279a9 378 * NOTE: %rbx is the previous thread and %rax is the new thread.
cc9b6223
MD
379 * %rbx is retained throughout so we can return it.
380 *
381 * lwkt_switch[_return] is responsible for handling TDF_RUNNING.
c8fe38ae 382 */
c8fe38ae
MD
383
384 /*
385 * Deal with the PCB extension, restore the private tss
386 */
387 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */
cc9b6223 388 movq $1,%rcx /* maybe mark use of a private tss */
c8fe38ae
MD
389 testq %rdi,%rdi
390#if JG
391 jnz 2f
392#endif
393
2883d2d8
MD
394 /*
395 * Going back to the common_tss. We may need to update TSS_RSP0
c8fe38ae
MD
396 * which sets the top of the supervisor stack when entering from
397 * usermode. The PCB is at the top of the stack but we need another
398 * 16 bytes to take vm86 into account.
399 */
cc9b6223
MD
400 movq %rdx,%rcx
401 /*leaq -TF_SIZE(%rdx),%rcx*/
402 movq %rcx, PCPU(common_tss) + TSS_RSP0
c8fe38ae 403
0855a2af 404#if JG
c8fe38ae
MD
405 cmpl $0,PCPU(private_tss) /* don't have to reload if */
406 je 3f /* already using the common TSS */
407
408 /* JG? */
cc9b6223 409 subq %rcx,%rcx /* unmark use of private tss */
c8fe38ae
MD
410
411 /*
412 * Get the address of the common TSS descriptor for the ltr.
413 * There is no way to get the address of a segment-accessed variable
414 * so we store a self-referential pointer at the base of the per-cpu
415 * data area and add the appropriate offset.
416 */
417 /* JG movl? */
418 movq $gd_common_tssd, %rdi
419 /* JG name for "%gs:0"? */
420 addq %gs:0, %rdi
421
422 /*
423 * Move the correct TSS descriptor into the GDT slot, then reload
424 * ltr.
425 */
4262:
427 /* JG */
cc9b6223 428 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */
c8fe38ae
MD
429 movq PCPU(tss_gdt), %rbx /* entry in GDT */
430 movq 0(%rdi), %rax
431 movq %rax, 0(%rbx)
432 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */
433 ltr %si
434#endif
435
4363:
437 /*
438 * Restore the user %gs and %fs
439 */
440 movq PCB_FSBASE(%rdx),%r9
441 cmpq PCPU(user_fs),%r9
442 je 4f
443 movq %rdx,%r10
444 movq %r9,PCPU(user_fs)
445 movl $MSR_FSBASE,%ecx
446 movl PCB_FSBASE(%r10),%eax
447 movl PCB_FSBASE+4(%r10),%edx
448 wrmsr
449 movq %r10,%rdx
4504:
451 movq PCB_GSBASE(%rdx),%r9
452 cmpq PCPU(user_gs),%r9
453 je 5f
454 movq %rdx,%r10
455 movq %r9,PCPU(user_gs)
456 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */
457 movl PCB_GSBASE(%r10),%eax
458 movl PCB_GSBASE+4(%r10),%edx
459 wrmsr
460 movq %r10,%rdx
4615:
462
463 /*
cc9b6223 464 * Restore general registers. %rbx is restored later.
c8fe38ae 465 */
c8fe38ae
MD
466 movq PCB_RSP(%rdx), %rsp
467 movq PCB_RBP(%rdx), %rbp
468 movq PCB_R12(%rdx), %r12
469 movq PCB_R13(%rdx), %r13
470 movq PCB_R14(%rdx), %r14
471 movq PCB_R15(%rdx), %r15
472 movq PCB_RIP(%rdx), %rax
473 movq %rax, (%rsp)
3338cc67
MD
474 movw $KDSEL,%ax
475 movw %ax,%es
c8fe38ae
MD
476
477#if JG
478 /*
479 * Restore the user LDT if we have one
480 */
481 cmpl $0, PCB_USERLDT(%edx)
482 jnz 1f
483 movl _default_ldt,%eax
484 cmpl PCPU(currentldt),%eax
485 je 2f
486 lldt _default_ldt
487 movl %eax,PCPU(currentldt)
488 jmp 2f
4891: pushl %edx
490 call set_user_ldt
491 popl %edx
4922:
493#endif
494#if JG
495 /*
496 * Restore the user TLS if we have one
497 */
498 pushl %edx
499 call set_user_TLS
500 popl %edx
501#endif
502
c8fe38ae
MD
503 /*
504 * Restore the DEBUG register state if necessary.
505 */
0855a2af
JG
506 movq PCB_FLAGS(%rdx),%rax
507 andq $PCB_DBREGS,%rax
c8fe38ae 508 jz 1f /* no, skip over */
0855a2af
JG
509 movq PCB_DR6(%rdx),%rax /* yes, do the restore */
510 movq %rax,%dr6
511 movq PCB_DR3(%rdx),%rax
512 movq %rax,%dr3
513 movq PCB_DR2(%rdx),%rax
514 movq %rax,%dr2
515 movq PCB_DR1(%rdx),%rax
516 movq %rax,%dr1
517 movq PCB_DR0(%rdx),%rax
518 movq %rax,%dr0
519 movq %dr7,%rax /* load dr7 so as not to disturb */
520 /* JG correct value? */
521 andq $0x0000fc00,%rax /* reserved bits */
b2b3ffcd 522 /* JG we've got more registers on x86_64 */
cc9b6223 523 movq PCB_DR7(%rdx),%rcx
0855a2af 524 /* JG correct value? */
cc9b6223
MD
525 andq $~0x0000fc00,%rcx
526 orq %rcx,%rax
0855a2af 527 movq %rax,%dr7
f2081646
MD
528
529 /*
530 * Clear the QUICKRET flag when restoring a user process context
531 * so we don't try to do a quick syscall return.
532 */
c8fe38ae 5331:
f2081646 534 andl $~RQF_QUICKRET,PCPU(reqflags)
cc9b6223
MD
535 movq %rbx,%rax
536 movq PCB_RBX(%rdx),%rbx
c8fe38ae 537 ret
d7f50089
YY
538
539/*
c8fe38ae 540 * savectx(struct pcb *pcb)
d7f50089
YY
541 *
542 * Update pcb, saving current processor state.
543 */
544ENTRY(savectx)
c8fe38ae
MD
545 /* fetch PCB */
546 /* JG use %rdi instead of %rcx everywhere? */
547 movq %rdi,%rcx
548
549 /* caller's return address - child won't execute this routine */
550 movq (%rsp),%rax
551 movq %rax,PCB_RIP(%rcx)
552
553 movq %cr3,%rax
c8fe38ae
MD
554 movq %rax,PCB_CR3(%rcx)
555
556 movq %rbx,PCB_RBX(%rcx)
557 movq %rsp,PCB_RSP(%rcx)
558 movq %rbp,PCB_RBP(%rcx)
559 movq %r12,PCB_R12(%rcx)
560 movq %r13,PCB_R13(%rcx)
561 movq %r14,PCB_R14(%rcx)
562 movq %r15,PCB_R15(%rcx)
563
c4f8086e 564#if 1
c8fe38ae
MD
565 /*
566 * If npxthread == NULL, then the npx h/w state is irrelevant and the
567 * state had better already be in the pcb. This is true for forks
568 * but not for dumps (the old book-keeping with FP flags in the pcb
569 * always lost for dumps because the dump pcb has 0 flags).
570 *
571 * If npxthread != NULL, then we have to save the npx h/w state to
572 * npxthread's pcb and copy it to the requested pcb, or save to the
573 * requested pcb and reload. Copying is easier because we would
574 * have to handle h/w bugs for reloading. We used to lose the
575 * parent's npx state for forks by forgetting to reload.
576 */
9648fee1
JG
577 movq PCPU(npxthread),%rax
578 testq %rax,%rax
579 jz 1f
c8fe38ae 580
9648fee1
JG
581 pushq %rcx /* target pcb */
582 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */
583 pushq %rax
c8fe38ae 584
9648fee1 585 movq %rax,%rdi
c8fe38ae 586 call npxsave
c8fe38ae 587
9648fee1
JG
588 popq %rax
589 popq %rcx
c8fe38ae 590
9648fee1
JG
591 movq $PCB_SAVEFPU_SIZE,%rdx
592 leaq PCB_SAVEFPU(%rcx),%rcx
593 movq %rcx,%rsi
594 movq %rax,%rdi
c8fe38ae 595 call bcopy
c4f8086e 596#endif
c8fe38ae
MD
597
5981:
c8fe38ae 599 ret
d7f50089
YY
600
601/*
c8fe38ae 602 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution)
d7f50089 603 *
c8fe38ae 604 * Don't bother setting up any regs other than %rbp so backtraces
d7f50089
YY
605 * don't die. This restore function is used to bootstrap into the
606 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for
607 * switching.
608 *
609 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3.
cc9b6223
MD
610 * This only occurs during system boot so no special handling is
611 * required for migration.
d7f50089
YY
612 *
613 * If we are an AP we have to call ap_init() before jumping to
614 * cpu_idle(). ap_init() will synchronize with the BP and finish
615 * setting up various ncpu-dependant globaldata fields. This may
616 * happen on UP as well as SMP if we happen to be simulating multiple
617 * cpus.
618 */
619ENTRY(cpu_idle_restore)
c8fe38ae 620 /* cli */
48ffc236 621 movq KPML4phys,%rcx
c8fe38ae 622 /* JG xor? */
b25897b2 623 movq $0,%rbp
c8fe38ae
MD
624 /* JG push RBP? */
625 pushq $0
c8fe38ae
MD
626 movq %rcx,%cr3
627 andl $~TDF_RUNNING,TD_FLAGS(%rbx)
121f93bc 628 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */
c8fe38ae
MD
629 cmpl $0,PCPU(cpuid)
630 je 1f
631 call ap_init
6321:
c8fe38ae
MD
633 /*
634 * ap_init can decide to enable interrupts early, but otherwise, or if
635 * we are UP, do it here.
636 */
637 sti
638 jmp cpu_idle
d7f50089
YY
639
640/*
0ae279a9
MD
641 * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx)
642 * (one-time execution)
d7f50089 643 *
c8fe38ae 644 * Don't bother setting up any regs other then %rbp so backtraces
d7f50089
YY
645 * don't die. This restore function is used to bootstrap into an
646 * LWKT based kernel thread only. cpu_lwkt_switch() will be used
647 * after this.
648 *
cc9b6223
MD
649 * Because this switch target does not 'return' to lwkt_switch()
650 * we have to call lwkt_switch_return(otd) to clean up otd.
651 * otd is in %ebx.
652 *
d7f50089
YY
653 * Since all of our context is on the stack we are reentrant and
654 * we can release our critical section and enable interrupts early.
655 */
656ENTRY(cpu_kthread_restore)
c8fe38ae 657 sti
48ffc236 658 movq KPML4phys,%rcx
cc9b6223 659 movq TD_PCB(%rax),%r13
0ae279a9 660 xorq %rbp,%rbp
c8fe38ae 661 movq %rcx,%cr3
cc9b6223
MD
662
663 /*
664 * rax and rbx come from the switchout code. Call
665 * lwkt_switch_return(otd).
666 *
667 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs.
668 */
669 pushq %rax
670 movq %rbx,%rdi
671 call lwkt_switch_return
672 popq %rax
f9235b6d 673 decl TD_CRITCOUNT(%rax)
cc9b6223
MD
674 movq PCB_R12(%r13),%rdi /* argument to RBX function */
675 movq PCB_RBX(%r13),%rax /* thread function */
c8fe38ae 676 /* note: top of stack return address inherited by function */
c8fe38ae 677 jmp *%rax
d7f50089
YY
678
679/*
c8fe38ae 680 * cpu_lwkt_switch(struct thread *)
d7f50089
YY
681 *
682 * Standard LWKT switching function. Only non-scratch registers are
683 * saved and we don't bother with the MMU state or anything else.
684 *
685 * This function is always called while in a critical section.
686 *
687 * There is a one-instruction window where curthread is the new
c8fe38ae 688 * thread but %rsp still points to the old thread's stack, but
d7f50089 689 * we are protected by a critical section so it is ok.
d7f50089
YY
690 */
691ENTRY(cpu_lwkt_switch)
b25897b2 692 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */
c8fe38ae 693 pushq %rbx
0ae279a9 694 movq PCPU(curthread),%rbx /* becomes old thread in restore */
c8fe38ae
MD
695 pushq %r12
696 pushq %r13
697 pushq %r14
698 pushq %r15
699 pushfq
3338cc67 700 cli
c8fe38ae 701
c4f8086e 702#if 1
c8fe38ae
MD
703 /*
704 * Save the FP state if we have used the FP. Note that calling
705 * npxsave will NULL out PCPU(npxthread).
706 *
707 * We have to deal with the FP state for LWKT threads in case they
708 * happen to get preempted or block while doing an optimized
709 * bzero/bcopy/memcpy.
710 */
9648fee1 711 cmpq %rbx,PCPU(npxthread)
c8fe38ae 712 jne 1f
9648fee1
JG
713 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */
714 movq TD_SAVEFPU(%rbx),%rdi
c8fe38ae 715 call npxsave /* do it in a big C function */
9648fee1 716 movq %r12,%rdi /* restore %rdi */
c8fe38ae 7171:
c4f8086e 718#endif
c8fe38ae
MD
719
720 movq %rdi,%rax /* switch to this thread */
721 pushq $cpu_lwkt_restore
722 movq %rsp,TD_SP(%rbx)
c8fe38ae
MD
723 /*
724 * %rax contains new thread, %rbx contains old thread.
725 */
d8d8c8c5 726 movq %rax,PCPU(curthread)
0ae279a9 727 movq TD_SP(%rax),%rsp
c8fe38ae 728 ret
d7f50089
YY
729
730/*
c8fe38ae 731 * cpu_lwkt_restore() (current thread in %rax on entry)
d7f50089
YY
732 *
733 * Standard LWKT restore function. This function is always called
734 * while in a critical section.
735 *
736 * Warning: due to preemption the restore function can be used to
737 * 'return' to the original thread. Interrupt disablement must be
738 * protected through the switch so we cannot run splz here.
d7f50089 739 *
c8fe38ae
MD
740 * YYY we theoretically do not need to load KPML4phys into cr3, but if
741 * so we need a way to detect when the PTD we are using is being
742 * deleted due to a process exiting.
d7f50089 743 */
c8fe38ae 744ENTRY(cpu_lwkt_restore)
48ffc236 745 movq KPML4phys,%rcx /* YYY borrow but beware desched/cpuchg/exit */
c8fe38ae 746 movq %cr3,%rdx
d8d8c8c5 747#if 1
c8fe38ae
MD
748 cmpq %rcx,%rdx
749 je 1f
d8d8c8c5 750#endif
c8fe38ae
MD
751 movq %rcx,%cr3
7521:
121f93bc
MD
753 /*
754 * Safety, clear RSP0 in the tss so it isn't pointing at the
755 * previous thread's kstack (if a heavy weight user thread).
756 * RSP0 should only be used in ring 3 transitions and kernel
757 * threads run in ring 0 so there should be none.
758 */
759 xorq %rdx,%rdx
760 movq %rdx, PCPU(common_tss) + TSS_RSP0
761
cc9b6223 762 /*
0ae279a9 763 * NOTE: %rbx is the previous thread and %rax is the new thread.
cc9b6223
MD
764 * %rbx is retained throughout so we can return it.
765 *
766 * lwkt_switch[_return] is responsible for handling TDF_RUNNING.
767 */
768 movq %rbx,%rax
c8fe38ae
MD
769 popfq
770 popq %r15
771 popq %r14
772 popq %r13
773 popq %r12
774 popq %rbx
775 popq %rbp
776 ret