kernel: Make SMP support default (and non-optional).
[dragonfly.git] / sys / platform / vkernel / i386 / mp.c
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1/*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
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33 */
34
24eb47e0 35
6a8aa90e 36#include <sys/interrupt.h>
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37#include <sys/kernel.h>
38#include <sys/memrange.h>
39#include <sys/tls.h>
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40#include <sys/types.h>
41
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42#include <vm/vm_extern.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_object.h>
45#include <vm/vm_page.h>
46
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47#include <sys/mplock2.h>
48
702acf06 49#include <machine/cpu.h>
6a8aa90e 50#include <machine/cpufunc.h>
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51#include <machine/globaldata.h>
52#include <machine/md_var.h>
53#include <machine/pmap.h>
6a8aa90e 54#include <machine/smp.h>
24eb47e0 55#include <machine/tls.h>
6a8aa90e 56
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57#include <unistd.h>
58#include <pthread.h>
59#include <signal.h>
60#include <stdio.h>
61
62extern pt_entry_t *KPTphys;
63
da23a592 64volatile cpumask_t stopped_cpus;
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65cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
66static int boot_address;
67static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
68int mp_naps; /* # of Applications processors */
69static int mp_finish;
70
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71/* Local data for detecting CPU TOPOLOGY */
72static int core_bits = 0;
73static int logical_CPU_bits = 0;
74
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75/* function prototypes XXX these should go elsewhere */
76void bootstrap_idle(void);
77void single_cpu_ipi(int, int, int);
da23a592 78void selected_cpu_ipi(cpumask_t, int, int);
6a8aa90e 79#if 0
24eb47e0 80void ipi_handler(int);
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81#endif
82
24eb47e0 83pt_entry_t *SMPpt;
6a8aa90e 84
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85/* AP uses this during bootstrap. Do not staticize. */
86char *bootSTK;
87static int bootAP;
6a8aa90e 88
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89
90/* XXX these need to go into the appropriate header file */
91static int start_all_aps(u_int);
92void init_secondary(void);
93void *start_ap(void *);
94
95/*
96 * Get SMP fully working before we start initializing devices.
97 */
98static
6a8aa90e 99void
24eb47e0 100ap_finish(void)
6a8aa90e 101{
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102 int i;
103 cpumask_t ncpus_mask = 0;
104
105 for (i = 1; i <= ncpus; i++)
da23a592 106 ncpus_mask |= CPUMASK(i);
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107
108 mp_finish = 1;
109 if (bootverbose)
110 kprintf("Finish MP startup\n");
111
112 /* build our map of 'other' CPUs */
da23a592 113 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
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114
115 /*
116 * Let the other cpu's finish initializing and build their map
117 * of 'other' CPUs.
118 */
119 rel_mplock();
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120 while (smp_active_mask != smp_startup_mask) {
121 DELAY(100000);
24eb47e0 122 cpu_lfence();
057f0718 123 }
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124
125 while (try_mplock() == 0)
057f0718 126 DELAY(100000);
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127 if (bootverbose)
128 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
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129}
130
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131SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
132
133
134void *
135start_ap(void *arg __unused)
6a8aa90e 136{
24eb47e0 137 init_secondary();
702acf06 138 setrealcpu();
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139 bootstrap_idle();
140
141 return(NULL); /* NOTREACHED */
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142}
143
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144/* storage for AP thread IDs */
145pthread_t ap_tids[MAXCPU];
146
6a8aa90e 147void
24eb47e0 148mp_start(void)
6a8aa90e 149{
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150 int shift;
151
c5b0b0ba 152 ncpus = optcpus;
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153
154 mp_naps = ncpus - 1;
155
156 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
157 for (shift = 0; (1 << shift) <= ncpus; ++shift)
158 ;
159 --shift;
160 ncpus2_shift = shift;
161 ncpus2 = 1 << shift;
162 ncpus2_mask = ncpus2 - 1;
163
164 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
165 if ((1 << shift) < ncpus)
166 ++shift;
167 ncpus_fit = 1 << shift;
168 ncpus_fit_mask = ncpus_fit - 1;
169
170 /*
171 * cpu0 initialization
172 */
173 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map,
174 sizeof(lwkt_ipiq) * ncpus);
175 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
176
177 /*
178 * cpu 1-(n-1)
179 */
180 start_all_aps(boot_address);
6a8aa90e 181
6a8aa90e 182}
24eb47e0 183
6a8aa90e 184void
24eb47e0 185mp_announce(void)
6a8aa90e 186{
24eb47e0 187 int x;
6a8aa90e 188
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189 kprintf("DragonFly/MP: Multiprocessor\n");
190 kprintf(" cpu0 (BSP)\n");
191
192 for (x = 1; x <= mp_naps; ++x)
193 kprintf(" cpu%d (AP)\n", x);
194}
6a8aa90e 195
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196void
197cpu_send_ipiq(int dcpu)
198{
da23a592 199 if (CPUMASK(dcpu) & smp_active_mask)
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200 if (pthread_kill(ap_tids[dcpu], SIGUSR1) != 0)
201 panic("pthread_kill failed in cpu_send_ipiq");
202#if 0
6a8aa90e 203 panic("XXX cpu_send_ipiq()");
24eb47e0 204#endif
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205}
206
207void
208smp_invltlb(void)
209{
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210}
211
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212void
213single_cpu_ipi(int cpu, int vector, int delivery_mode)
214{
215 kprintf("XXX single_cpu_ipi\n");
216}
217
218void
da23a592 219selected_cpu_ipi(cpumask_t target, int vector, int delivery_mode)
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220{
221 crit_enter();
222 while (target) {
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223 int n = BSFCPUMASK(target);
224 target &= ~CPUMASK(n);
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225 single_cpu_ipi(n, vector, delivery_mode);
226 }
227 crit_exit();
228}
229
6a8aa90e 230int
da23a592 231stop_cpus(cpumask_t map)
6a8aa90e 232{
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233 map &= smp_active_mask;
234
235 crit_enter();
236 while (map) {
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237 int n = BSFCPUMASK(map);
238 map &= ~CPUMASK(n);
239 stopped_cpus |= CPUMASK(n);
8f66501e 240 if (pthread_kill(ap_tids[n], SIGXCPU) != 0)
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241 panic("stop_cpus: pthread_kill failed");
242 }
243 crit_exit();
244#if 0
6a8aa90e 245 panic("XXX stop_cpus()");
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246#endif
247
248 return(1);
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249}
250
251int
da23a592 252restart_cpus(cpumask_t map)
6a8aa90e 253{
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254 map &= smp_active_mask;
255
256 crit_enter();
257 while (map) {
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258 int n = BSFCPUMASK(map);
259 map &= ~CPUMASK(n);
260 stopped_cpus &= ~CPUMASK(n);
8f66501e 261 if (pthread_kill(ap_tids[n], SIGXCPU) != 0)
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262 panic("restart_cpus: pthread_kill failed");
263 }
264 crit_exit();
265#if 0
6a8aa90e 266 panic("XXX restart_cpus()");
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267#endif
268
269 return(1);
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270}
271
272void
273ap_init(void)
274{
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275 /*
276 * Adjust smp_startup_mask to signal the BSP that we have started
277 * up successfully. Note that we do not yet hold the BGL. The BSP
278 * is waiting for our signal.
279 *
280 * We can't set our bit in smp_active_mask yet because we are holding
281 * interrupts physically disabled and remote cpus could deadlock
282 * trying to send us an IPI.
283 */
da23a592 284 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
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285 cpu_mfence();
286
287 /*
288 * Interlock for finalization. Wait until mp_finish is non-zero,
289 * then get the MP lock.
290 *
291 * Note: We are in a critical section.
292 *
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293 * Note: we are the idle thread, we can only spin.
294 *
295 * Note: The load fence is memory volatile and prevents the compiler
296 * from improperly caching mp_finish, and the cpu from improperly
297 * caching it.
298 */
299
300 while (mp_finish == 0) {
301 cpu_lfence();
057f0718 302 DELAY(500000);
24eb47e0 303 }
b5d16701 304 while (try_mplock() == 0)
057f0718 305 DELAY(100000);
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306
307 /* BSP may have changed PTD while we're waiting for the lock */
308 cpu_invltlb();
309
310 /* Build our map of 'other' CPUs. */
da23a592 311 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
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312
313 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
314
315
316 /* Set memory range attributes for this CPU to match the BSP */
317 mem_range_AP_init();
318 /*
319 * Once we go active we must process any IPIQ messages that may
320 * have been queued, because no actual IPI will occur until we
321 * set our bit in the smp_active_mask. If we don't the IPI
322 * message interlock could be left set which would also prevent
323 * further IPIs.
324 *
325 * The idle loop doesn't expect the BGL to be held and while
326 * lwkt_switch() normally cleans things up this is a special case
327 * because we returning almost directly into the idle loop.
328 *
329 * The idle thread is never placed on the runq, make sure
330 * nothing we've done put it there.
331 */
b5d16701 332 KKASSERT(get_mplock_count(curthread) == 1);
da23a592 333 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
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334
335 mdcpu->gd_fpending = 0;
336 mdcpu->gd_ipending = 0;
337 initclocks_pcpu(); /* clock interrupts (via IPIs) */
338 lwkt_process_ipiq();
339
340 /*
341 * Releasing the mp lock lets the BSP finish up the SMP init
342 */
343 rel_mplock();
344 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
345}
346
347void
348init_secondary(void)
349{
350 int myid = bootAP;
351 struct mdglobaldata *md;
352 struct privatespace *ps;
353
354 ps = &CPU_prvspace[myid];
355
356 KKASSERT(ps->mdglobaldata.mi.gd_prvspace == ps);
357
358 /*
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359 * Setup the %fs for cpu #n. The mycpu macro works after this
360 * point. Note that %gs is used by pthreads.
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361 */
362 tls_set_fs(&CPU_prvspace[myid], sizeof(struct privatespace));
363
364 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
365
366 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
367 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
368 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
369
370 /*
371 * Set to a known state:
372 * Set by mpboot.s: CR0_PG, CR0_PE
373 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
374 */
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375}
376
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377static int
378start_all_aps(u_int boot_addr)
379{
380 int x, i;
381 struct mdglobaldata *gd;
382 struct privatespace *ps;
383 vm_page_t m;
384 vm_offset_t va;
385#if 0
386 struct lwp_params params;
387#endif
388
389 /*
390 * needed for ipis to initial thread
391 * FIXME: rename ap_tids?
392 */
393 ap_tids[0] = pthread_self();
394
b12defdc 395 vm_object_hold(&kernel_object);
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396 for (x = 1; x <= mp_naps; x++)
397 {
398 /* Allocate space for the CPU's private space. */
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399 for (i = 0; i < sizeof(struct mdglobaldata); i += PAGE_SIZE) {
400 va =(vm_offset_t)&CPU_prvspace[x].mdglobaldata + i;
401 m = vm_page_alloc(&kernel_object, va, VM_ALLOC_SYSTEM);
402 pmap_kenter_quick(va, m->phys_addr);
403 }
6a8aa90e 404
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405 for (i = 0; i < sizeof(CPU_prvspace[x].idlestack); i += PAGE_SIZE) {
406 va =(vm_offset_t)&CPU_prvspace[x].idlestack + i;
407 m = vm_page_alloc(&kernel_object, va, VM_ALLOC_SYSTEM);
408 pmap_kenter_quick(va, m->phys_addr);
409 }
410
411 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
412 bzero(gd, sizeof(*gd));
413 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
414
415 /* prime data page for it to use */
416 mi_gdinit(&gd->mi, x);
417 cpu_gdinit(gd, x);
418
419#if 0
420 gd->gd_CMAP1 = pmap_kpte((vm_offset_t)CPU_prvspace[x].CPAGE1);
421 gd->gd_CMAP2 = pmap_kpte((vm_offset_t)CPU_prvspace[x].CPAGE2);
422 gd->gd_CMAP3 = pmap_kpte((vm_offset_t)CPU_prvspace[x].CPAGE3);
423 gd->gd_PMAP1 = pmap_kpte((vm_offset_t)CPU_prvspace[x].PPAGE1);
424 gd->gd_CADDR1 = ps->CPAGE1;
425 gd->gd_CADDR2 = ps->CPAGE2;
426 gd->gd_CADDR3 = ps->CPAGE3;
427 gd->gd_PADDR1 = (vpte_t *)ps->PPAGE1;
428#endif
429
430 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
431 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
432
433 /*
434 * Setup the AP boot stack
435 */
436 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
437 bootAP = x;
438
439 /*
440 * Setup the AP's lwp, this is the 'cpu'
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441 *
442 * We have to make sure our signals are masked or the new LWP
443 * may pick up a signal that it isn't ready for yet. SMP
444 * startup occurs after SI_BOOT2_LEAVE_CRIT so interrupts
445 * have already been enabled.
24eb47e0 446 */
792a98ed 447 cpu_disable_intr();
24eb47e0 448 pthread_create(&ap_tids[x], NULL, start_ap, NULL);
792a98ed 449 cpu_enable_intr();
24eb47e0 450
da23a592 451 while((smp_startup_mask & CPUMASK(x)) == 0) {
24eb47e0 452 cpu_lfence(); /* XXX spin until the AP has started */
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453 DELAY(1000);
454 }
24eb47e0 455 }
b12defdc 456 vm_object_drop(&kernel_object);
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457
458 return(ncpus - 1);
459}
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460
461/*
462 * CPU TOPOLOGY DETECTION FUNCTIONS.
463 */
464
465void
466detect_cpu_topology(void)
467{
468 logical_CPU_bits = vkernel_b_arg;
469 core_bits = vkernel_B_arg;
470}
471
472int
473get_chip_ID(int cpuid)
474{
475 return get_apicid_from_cpuid(cpuid) >>
476 (logical_CPU_bits + core_bits);
477}
478
479int
480get_core_number_within_chip(int cpuid)
481{
482 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) &
483 ( (1 << core_bits) -1);
484}
485
486int
487get_logical_CPU_number_within_core(int cpuid)
488{
489 return get_apicid_from_cpuid(cpuid) &
490 ( (1 << logical_CPU_bits) -1);
491}