icu: Split out icu/icu.c
[dragonfly.git] / sys / platform / pc32 / isa / clock.c
CommitLineData
984263bc
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 */
39
40/*
41 * Routines to handle clock hardware.
42 */
43
44/*
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47 *
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 */
50
1f2de5d4 51#include "use_apm.h"
984263bc 52#include "opt_clock.h"
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53
54#include <sys/param.h>
55#include <sys/systm.h>
13194089 56#include <sys/eventhandler.h>
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57#include <sys/time.h>
58#include <sys/kernel.h>
e126caf1 59#include <sys/bus.h>
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60#ifndef SMP
61#include <sys/lock.h>
62#endif
63#include <sys/sysctl.h>
64#include <sys/cons.h>
88c4d2f6
MD
65#include <sys/systimer.h>
66#include <sys/globaldata.h>
67#include <sys/thread2.h>
68#include <sys/systimer.h>
37e7efec 69#include <sys/machintr.h>
1b505979 70#include <sys/interrupt.h>
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71
72#include <machine/clock.h>
73#ifdef CLK_CALIBRATION_LOOP
74#endif
75#include <machine/cputypes.h>
76#include <machine/frame.h>
77#include <machine/ipl.h>
78#include <machine/limits.h>
79#include <machine/md_var.h>
80#include <machine/psl.h>
984263bc 81#include <machine/segments.h>
984263bc 82#include <machine/smp.h>
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83#include <machine/specialreg.h>
84
a9295349 85#include <machine_base/icu/icu.h>
21ce0dfa 86#include <bus/isa/isa.h>
1f2de5d4 87#include <bus/isa/rtc.h>
a9295349 88#include <machine_base/isa/timerreg.h>
984263bc 89
a9295349 90#include <machine_base/isa/intr_machdep.h>
984263bc 91
30c5f287 92#ifdef SMP /* APIC-IO */
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93/* The interrupt triggered by the 8254 (timer) chip */
94int apic_8254_intr;
3ae0cd58 95static void setup_8254_mixed_mode (void);
984263bc 96#endif
88c4d2f6 97static void i8254_restore(void);
e63ac55d 98static void resettodr_on_shutdown(void *arg __unused);
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99
100/*
101 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
102 * can use a simple formula for leap years.
103 */
104#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
105#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
106
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107#ifndef TIMER_FREQ
108#define TIMER_FREQ 1193182
109#endif
984263bc 110
e54beab0
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111static uint8_t i8254_walltimer_sel;
112static uint16_t i8254_walltimer_cntr;
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113
114int adjkerntz; /* local offset from GMT in seconds */
984263bc 115int disable_rtc_set; /* disable resettodr() if != 0 */
8b3ec75a 116int tsc_present;
374133e3 117int64_t tsc_frequency;
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118int tsc_is_broken;
119int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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120int timer0_running;
121enum tstate { RELEASED, ACQUIRED };
122enum tstate timer0_state;
123enum tstate timer1_state;
124enum tstate timer2_state;
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125
126static int beeping = 0;
984263bc 127static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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128static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
129static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
e63ac55d 130static int rtc_loaded;
984263bc 131
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132static int i8254_cputimer_div;
133
ef612539 134static int i8254_nointr;
e87376d9
SZ
135static int i8254_intr_disable = 0;
136TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
137
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138static struct callout sysbeepstop_ch;
139
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140static sysclock_t i8254_cputimer_count(void);
141static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
142static void i8254_cputimer_destruct(struct cputimer *cputimer);
143
144static struct cputimer i8254_cputimer = {
d8fdd978 145 SLIST_ENTRY_INITIALIZER,
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146 "i8254",
147 CPUTIMER_PRI_8254,
148 0,
149 i8254_cputimer_count,
150 cputimer_default_fromhz,
151 cputimer_default_fromus,
152 i8254_cputimer_construct,
153 i8254_cputimer_destruct,
154 TIMER_FREQ,
5ee041ae 155 0, 0, 0
044ee7c4
MD
156};
157
ef612539
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158static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
159static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
160static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
161
162static struct cputimer_intr i8254_cputimer_intr = {
163 .freq = TIMER_FREQ,
164 .reload = i8254_intr_reload,
165 .enable = cputimer_intr_default_enable,
166 .config = i8254_intr_config,
167 .restart = cputimer_intr_default_restart,
168 .pmfixup = cputimer_intr_default_pmfixup,
169 .initclock = i8254_intr_initclock,
170 .next = SLIST_ENTRY_INITIALIZER,
171 .name = "i8254",
172 .type = CPUTIMER_INTR_8254,
173 .prio = CPUTIMER_INTR_PRIO_8254,
174 .caps = CPUTIMER_INTR_CAP_PS
175};
176
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177/*
178 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
179 * counting as of this interrupt. We use timer1 in free-running mode (not
180 * generating any interrupts) as our main counter. Each cpu has timeouts
181 * pending.
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182 *
183 * This code is INTR_MPSAFE and may be called without the BGL held.
88c4d2f6 184 */
984263bc 185static void
477d3c1c 186clkintr(void *dummy, void *frame_arg)
984263bc 187{
ec4812b0 188 static sysclock_t sysclock_count; /* NOTE! Must be static */
88c4d2f6 189 struct globaldata *gd = mycpu;
b8a98473 190#ifdef SMP
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191 struct globaldata *gscan;
192 int n;
b8a98473 193#endif
9a47427a 194
b505872f 195 /*
88c4d2f6 196 * SWSTROBE mode is a one-shot, the timer is no longer running
b505872f 197 */
88c4d2f6 198 timer0_running = 0;
b505872f 199
88c4d2f6 200 /*
774fc796
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201 * XXX the dispatcher needs work. right now we call systimer_intr()
202 * directly or via IPI for any cpu with systimers queued, which is
ec4812b0 203 * usually *ALL* of them. We need to use the LAPIC timer for this.
88c4d2f6 204 */
ec4812b0 205 sysclock_count = sys_cputimer->count();
b8a98473 206#ifdef SMP
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207 for (n = 0; n < ncpus; ++n) {
208 gscan = globaldata_find(n);
774fc796 209 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
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210 continue;
211 if (gscan != gd) {
b8a98473 212 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
ec4812b0 213 &sysclock_count, 0);
88c4d2f6 214 } else {
ec4812b0 215 systimer_intr(&sysclock_count, 0, frame_arg);
88c4d2f6 216 }
984263bc 217 }
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218#else
219 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
ec4812b0 220 systimer_intr(&sysclock_count, 0, frame_arg);
b8a98473 221#endif
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222}
223
88c4d2f6 224
984263bc 225/*
88c4d2f6 226 * NOTE! not MP safe.
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227 */
228int
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229acquire_timer2(int mode)
230{
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231 if (timer2_state != RELEASED)
232 return (-1);
233 timer2_state = ACQUIRED;
234
235 /*
236 * This access to the timer registers is as atomic as possible
237 * because it is a single instruction. We could do better if we
88c4d2f6 238 * knew the rate.
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239 */
240 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
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241 return (0);
242}
243
244int
09e6e929 245release_timer2(void)
984263bc 246{
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247 if (timer2_state != ACQUIRED)
248 return (-1);
984263bc 249 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
88c4d2f6 250 timer2_state = RELEASED;
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251 return (0);
252}
253
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254#include "opt_ddb.h"
255#ifdef DDB
256#include <ddb/ddb.h>
257
258DB_SHOW_COMMAND(rtc, rtc)
259{
26be20a0 260 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
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261 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
262 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
263 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
264}
265#endif /* DDB */
266
88c4d2f6 267/*
88c4d2f6
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268 * Return the current cpu timer count as a 32 bit integer.
269 */
044ee7c4 270static
88c4d2f6 271sysclock_t
044ee7c4 272i8254_cputimer_count(void)
88c4d2f6 273{
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MD
274 static __uint16_t cputimer_last;
275 __uint16_t count;
276 sysclock_t ret;
984263bc 277
88c4d2f6 278 clock_lock();
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279 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
280 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
281 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
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282 count = -count; /* -> countup */
283 if (count < cputimer_last) /* rollover */
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284 i8254_cputimer.base += 0x00010000;
285 ret = i8254_cputimer.base | count;
88c4d2f6 286 cputimer_last = count;
8a8d5d85 287 clock_unlock();
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288 return(ret);
289}
290
291/*
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292 * This function is called whenever the system timebase changes, allowing
293 * us to calculate what is needed to convert a system timebase tick
294 * into an 8254 tick for the interrupt timer. If we can convert to a
295 * simple shift, multiplication, or division, we do so. Otherwise 64
296 * bit arithmatic is required every time the interrupt timer is reloaded.
297 */
ef612539
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298static void
299i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
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MD
300{
301 int freq;
302 int div;
303
304 /*
305 * Will a simple divide do the trick?
306 */
ef612539
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307 div = (timer->freq + (cti->freq / 2)) / cti->freq;
308 freq = cti->freq * div;
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MD
309
310 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
311 i8254_cputimer_div = div;
312 else
313 i8254_cputimer_div = 0;
314}
315
316/*
88c4d2f6
MD
317 * Reload for the next timeout. It is possible for the reload value
318 * to be 0 or negative, indicating that an immediate timer interrupt
319 * is desired. For now make the minimum 2 ticks.
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320 *
321 * We may have to convert from the system timebase to the 8254 timebase.
88c4d2f6 322 */
c5c70fac 323static void
ef612539 324i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
88c4d2f6
MD
325{
326 __uint16_t count;
327
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MD
328 if (i8254_cputimer_div)
329 reload /= i8254_cputimer_div;
330 else
ef612539 331 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
5ee041ae 332
88c4d2f6
MD
333 if ((int)reload < 2)
334 reload = 2;
335
336 clock_lock();
337 if (timer0_running) {
338 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
339 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
340 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
341 if (reload < count) {
342 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
343 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
344 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
345 }
346 } else {
347 timer0_running = 1;
348 if (reload > 0xFFFF)
349 reload = 0; /* full count */
350 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
351 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
352 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
353 }
354 clock_unlock();
984263bc
MD
355}
356
357/*
dbcd0c9b
MD
358 * DELAY(usec) - Spin for the specified number of microseconds.
359 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
360 * but do a thread switch in the loop
361 *
88c4d2f6 362 * Relies on timer 1 counting down from (cputimer_freq / hz)
984263bc
MD
363 * Note: timer had better have been programmed before this is first used!
364 */
dbcd0c9b
MD
365static void
366DODELAY(int n, int doswitch)
984263bc
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367{
368 int delta, prev_tick, tick, ticks_left;
369
370#ifdef DELAYDEBUG
371 int getit_calls = 1;
372 int n1;
373 static int state = 0;
374
375 if (state == 0) {
376 state = 1;
377 for (n1 = 1; n1 <= 10000000; n1 *= 10)
378 DELAY(n1);
379 state = 2;
380 }
381 if (state == 1)
26be20a0 382 kprintf("DELAY(%d)...", n);
984263bc
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383#endif
384 /*
385 * Guard against the timer being uninitialized if we are called
386 * early for console i/o.
387 */
88c4d2f6
MD
388 if (timer0_state == RELEASED)
389 i8254_restore();
984263bc
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390
391 /*
392 * Read the counter first, so that the rest of the setup overhead is
1636ba19
MD
393 * counted. Then calculate the number of hardware timer ticks
394 * required, rounding up to be sure we delay at least the requested
395 * number of microseconds.
984263bc 396 */
044ee7c4 397 prev_tick = sys_cputimer->count();
1636ba19
MD
398 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
399 1000000;
400
984263bc 401 /*
1636ba19 402 * Loop until done.
984263bc 403 */
984263bc 404 while (ticks_left > 0) {
044ee7c4 405 tick = sys_cputimer->count();
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MD
406#ifdef DELAYDEBUG
407 ++getit_calls;
408#endif
88c4d2f6 409 delta = tick - prev_tick;
984263bc 410 prev_tick = tick;
88c4d2f6
MD
411 if (delta < 0)
412 delta = 0;
984263bc 413 ticks_left -= delta;
dbcd0c9b
MD
414 if (doswitch && ticks_left > 0)
415 lwkt_switch();
c5724852 416 cpu_pause();
984263bc
MD
417 }
418#ifdef DELAYDEBUG
419 if (state == 1)
26be20a0 420 kprintf(" %d calls to getit() at %d usec each\n",
984263bc
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421 getit_calls, (n + 5) / getit_calls);
422#endif
423}
424
77912481
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425/*
426 * DELAY() never switches
427 */
dbcd0c9b
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428void
429DELAY(int n)
430{
431 DODELAY(n, 0);
432}
433
d8129ed3
MD
434int
435CHECKTIMEOUT(TOTALDELAY *tdd)
436{
437 sysclock_t delta;
438 int us;
439
440 if (tdd->started == 0) {
441 if (timer0_state == RELEASED)
442 i8254_restore();
443 tdd->last_clock = sys_cputimer->count();
444 tdd->started = 1;
445 return(0);
446 }
447 delta = sys_cputimer->count() - tdd->last_clock;
448 us = (u_int64_t)delta * (u_int64_t)1000000 /
449 (u_int64_t)sys_cputimer->freq;
450 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
451 1000000;
452 tdd->us -= us;
453 return (tdd->us < 0);
454}
455
77912481
MD
456/*
457 * DRIVERSLEEP() does not switch if called with a spinlock held or
458 * from a hard interrupt.
459 */
dbcd0c9b
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460void
461DRIVERSLEEP(int usec)
462{
463 globaldata_t gd = mycpu;
464
8f165b8c 465 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
dbcd0c9b
MD
466 DODELAY(usec, 0);
467 } else {
468 DODELAY(usec, 1);
469 }
470}
471
984263bc
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472static void
473sysbeepstop(void *chan)
474{
475 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
984263bc 476 beeping = 0;
88c4d2f6 477 release_timer2();
984263bc
MD
478}
479
480int
481sysbeep(int pitch, int period)
482{
984263bc 483 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
88c4d2f6 484 return(-1);
7caeaffe
MD
485 if (sysbeep_enable == 0)
486 return(-1);
88c4d2f6
MD
487 /*
488 * Nobody else is using timer2, we do not need the clock lock
489 */
984263bc
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490 outb(TIMER_CNTR2, pitch);
491 outb(TIMER_CNTR2, (pitch>>8));
984263bc
MD
492 if (!beeping) {
493 /* enable counter2 output to speaker */
494 outb(IO_PPI, inb(IO_PPI) | 3);
495 beeping = period;
b02bbab0 496 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
984263bc 497 }
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MD
498 return (0);
499}
500
501/*
502 * RTC support routines
503 */
504
505int
09e6e929 506rtcin(int reg)
984263bc 507{
984263bc
MD
508 u_char val;
509
9acd5bbb 510 crit_enter();
984263bc
MD
511 outb(IO_RTC, reg);
512 inb(0x84);
513 val = inb(IO_RTC + 1);
514 inb(0x84);
9acd5bbb 515 crit_exit();
984263bc
MD
516 return (val);
517}
518
519static __inline void
520writertc(u_char reg, u_char val)
521{
9acd5bbb 522 crit_enter();
984263bc
MD
523 inb(0x84);
524 outb(IO_RTC, reg);
525 inb(0x84);
526 outb(IO_RTC + 1, val);
527 inb(0x84); /* XXX work around wrong order in rtcin() */
9acd5bbb 528 crit_exit();
984263bc
MD
529}
530
531static __inline int
532readrtc(int port)
533{
534 return(bcd2bin(rtcin(port)));
535}
536
537static u_int
538calibrate_clocks(void)
539{
540 u_int64_t old_tsc;
541 u_int count, prev_count, tot_count;
542 int sec, start_sec, timeout;
543
544 if (bootverbose)
26be20a0 545 kprintf("Calibrating clock(s) ... ");
984263bc
MD
546 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
547 goto fail;
548 timeout = 100000000;
549
550 /* Read the mc146818A seconds counter. */
551 for (;;) {
552 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
553 sec = rtcin(RTC_SEC);
554 break;
555 }
556 if (--timeout == 0)
557 goto fail;
558 }
559
560 /* Wait for the mC146818A seconds counter to change. */
561 start_sec = sec;
562 for (;;) {
563 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
564 sec = rtcin(RTC_SEC);
565 if (sec != start_sec)
566 break;
567 }
568 if (--timeout == 0)
569 goto fail;
570 }
571
572 /* Start keeping track of the i8254 counter. */
044ee7c4 573 prev_count = sys_cputimer->count();
984263bc
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574 tot_count = 0;
575
576 if (tsc_present)
577 old_tsc = rdtsc();
578 else
579 old_tsc = 0; /* shut up gcc */
580
581 /*
582 * Wait for the mc146818A seconds counter to change. Read the i8254
583 * counter for each iteration since this is convenient and only
584 * costs a few usec of inaccuracy. The timing of the final reads
585 * of the counters almost matches the timing of the initial reads,
586 * so the main cause of inaccuracy is the varying latency from
587 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
588 * rtcin(RTC_SEC) that returns a changed seconds count. The
589 * maximum inaccuracy from this cause is < 10 usec on 486's.
590 */
591 start_sec = sec;
592 for (;;) {
593 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
594 sec = rtcin(RTC_SEC);
044ee7c4 595 count = sys_cputimer->count();
88c4d2f6 596 tot_count += (int)(count - prev_count);
984263bc
MD
597 prev_count = count;
598 if (sec != start_sec)
599 break;
600 if (--timeout == 0)
601 goto fail;
602 }
603
604 /*
605 * Read the cpu cycle counter. The timing considerations are
606 * similar to those for the i8254 clock.
607 */
374133e3
MD
608 if (tsc_present) {
609 tsc_frequency = rdtsc() - old_tsc;
374133e3 610 }
984263bc 611
c17827b4 612 if (tsc_present)
870b0161 613 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
26be20a0 614 kprintf("i8254 clock: %u Hz\n", tot_count);
984263bc
MD
615 return (tot_count);
616
617fail:
26be20a0 618 kprintf("failed, using default i8254 clock of %u Hz\n",
044ee7c4
MD
619 i8254_cputimer.freq);
620 return (i8254_cputimer.freq);
984263bc
MD
621}
622
623static void
624i8254_restore(void)
625{
88c4d2f6 626 timer0_state = ACQUIRED;
e54beab0 627
044ee7c4
MD
628 clock_lock();
629
630 /*
631 * Timer0 is our fine-grained variable clock interrupt
632 */
633 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
634 outb(TIMER_CNTR0, 2); /* lsb */
635 outb(TIMER_CNTR0, 0); /* msb */
ee31250e 636 clock_unlock();
044ee7c4 637
ef612539
SZ
638 if (!i8254_nointr) {
639 cputimer_intr_register(&i8254_cputimer_intr);
640 cputimer_intr_select(&i8254_cputimer_intr, 0);
641 }
642
044ee7c4
MD
643 /*
644 * Timer1 or timer2 is our free-running clock, but only if another
645 * has not been selected.
646 */
5ee041ae
MD
647 cputimer_register(&i8254_cputimer);
648 cputimer_select(&i8254_cputimer, 0);
044ee7c4
MD
649}
650
651static void
652i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
653{
654 int which;
655
656 /*
657 * Should we use timer 1 or timer 2 ?
658 */
659 which = 0;
660 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
661 if (which != 1 && which != 2)
662 which = 2;
663
664 switch(which) {
665 case 1:
666 timer->name = "i8254_timer1";
667 timer->type = CPUTIMER_8254_SEL1;
e54beab0
JS
668 i8254_walltimer_sel = TIMER_SEL1;
669 i8254_walltimer_cntr = TIMER_CNTR1;
670 timer1_state = ACQUIRED;
044ee7c4
MD
671 break;
672 case 2:
673 timer->name = "i8254_timer2";
674 timer->type = CPUTIMER_8254_SEL2;
e54beab0
JS
675 i8254_walltimer_sel = TIMER_SEL2;
676 i8254_walltimer_cntr = TIMER_CNTR2;
677 timer2_state = ACQUIRED;
044ee7c4 678 break;
e54beab0 679 }
044ee7c4
MD
680
681 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
682
ee31250e 683 clock_lock();
e54beab0
JS
684 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
685 outb(i8254_walltimer_cntr, 0); /* lsb */
686 outb(i8254_walltimer_cntr, 0); /* msb */
88c4d2f6 687 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
ee31250e 688 clock_unlock();
044ee7c4
MD
689}
690
691static void
692i8254_cputimer_destruct(struct cputimer *timer)
693{
694 switch(timer->type) {
695 case CPUTIMER_8254_SEL1:
696 timer1_state = RELEASED;
697 break;
698 case CPUTIMER_8254_SEL2:
699 timer2_state = RELEASED;
700 break;
701 default:
702 break;
703 }
704 timer->type = 0;
984263bc
MD
705}
706
707static void
708rtc_restore(void)
709{
984263bc
MD
710 /* Restore all of the RTC's "status" (actually, control) registers. */
711 writertc(RTC_STATUSB, RTCSB_24HR);
712 writertc(RTC_STATUSA, rtc_statusa);
713 writertc(RTC_STATUSB, rtc_statusb);
714}
715
716/*
0284027e 717 * Restore all the timers.
984263bc 718 *
0d1dffdf
MD
719 * This function is called to resynchronize our core timekeeping after a
720 * long halt, e.g. from apm_default_resume() and friends. It is also
721 * called if after a BIOS call we have detected munging of the 8254.
722 * It is necessary because cputimer_count() counter's delta may have grown
723 * too large for nanouptime() and friends to handle, or (in the case of 8254
724 * munging) might cause the SYSTIMER code to prematurely trigger.
984263bc
MD
725 */
726void
727timer_restore(void)
728{
0284027e 729 crit_enter();
984263bc
MD
730 i8254_restore(); /* restore timer_freq and hz */
731 rtc_restore(); /* reenable RTC interrupts */
0284027e 732 crit_exit();
984263bc
MD
733}
734
735/*
736 * Initialize 8254 timer 0 early so that it can be used in DELAY().
984263bc
MD
737 */
738void
09e6e929 739startrtclock(void)
984263bc
MD
740{
741 u_int delta, freq;
742
88c4d2f6
MD
743 /*
744 * Can we use the TSC?
745 */
984263bc
MD
746 if (cpu_feature & CPUID_TSC)
747 tsc_present = 1;
748 else
749 tsc_present = 0;
750
88c4d2f6
MD
751 /*
752 * Initial RTC state, don't do anything unexpected
753 */
984263bc
MD
754 writertc(RTC_STATUSA, rtc_statusa);
755 writertc(RTC_STATUSB, RTCSB_24HR);
756
88c4d2f6
MD
757 /*
758 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
759 * generate an interrupt, which we will ignore for now.
760 *
761 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
762 * (so it counts a full 2^16 and repeats). We will use this timer
763 * for our counting.
764 */
765 i8254_restore();
984263bc
MD
766 freq = calibrate_clocks();
767#ifdef CLK_CALIBRATION_LOOP
768 if (bootverbose) {
26be20a0 769 kprintf(
984263bc
MD
770 "Press a key on the console to abort clock calibration\n");
771 while (cncheckc() == -1)
772 calibrate_clocks();
773 }
774#endif
775
776 /*
777 * Use the calibrated i8254 frequency if it seems reasonable.
778 * Otherwise use the default, and don't use the calibrated i586
779 * frequency.
780 */
044ee7c4
MD
781 delta = freq > i8254_cputimer.freq ?
782 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
783 if (delta < i8254_cputimer.freq / 100) {
984263bc
MD
784#ifndef CLK_USE_I8254_CALIBRATION
785 if (bootverbose)
26be20a0 786 kprintf(
984263bc 787"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
044ee7c4 788 freq = i8254_cputimer.freq;
984263bc 789#endif
ef612539
SZ
790 /*
791 * NOTE:
792 * Interrupt timer's freq must be adjusted
793 * before we change the cuptimer's frequency.
794 */
795 i8254_cputimer_intr.freq = freq;
5ee041ae 796 cputimer_set_frequency(&i8254_cputimer, freq);
984263bc
MD
797 } else {
798 if (bootverbose)
26be20a0 799 kprintf(
984263bc 800 "%d Hz differs from default of %d Hz by more than 1%%\n",
044ee7c4 801 freq, i8254_cputimer.freq);
374133e3 802 tsc_frequency = 0;
984263bc
MD
803 }
804
984263bc 805#ifndef CLK_USE_TSC_CALIBRATION
870b0161 806 if (tsc_frequency != 0) {
984263bc 807 if (bootverbose)
26be20a0 808 kprintf(
984263bc 809"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
374133e3 810 tsc_frequency = 0;
984263bc
MD
811 }
812#endif
374133e3 813 if (tsc_present && tsc_frequency == 0) {
984263bc
MD
814 /*
815 * Calibration of the i586 clock relative to the mc146818A
816 * clock failed. Do a less accurate calibration relative
817 * to the i8254 clock.
818 */
819 u_int64_t old_tsc = rdtsc();
820
821 DELAY(1000000);
374133e3 822 tsc_frequency = rdtsc() - old_tsc;
984263bc 823#ifdef CLK_USE_TSC_CALIBRATION
870b0161
MD
824 if (bootverbose) {
825 kprintf("TSC clock: %llu Hz (Method B)\n",
826 tsc_frequency);
827 }
984263bc
MD
828#endif
829 }
830
87e2fa7e 831 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
13194089 832
984263bc
MD
833#if !defined(SMP)
834 /*
835 * We can not use the TSC in SMP mode, until we figure out a
836 * cheap (impossible), reliable and precise (yeah right!) way
837 * to synchronize the TSCs of all the CPUs.
838 * Curse Intel for leaving the counter out of the I/O APIC.
839 */
840
841#if NAPM > 0
842 /*
843 * We can not use the TSC if we support APM. Precise timekeeping
844 * on an APM'ed machine is at best a fools pursuit, since
845 * any and all of the time spent in various SMM code can't
846 * be reliably accounted for. Reading the RTC is your only
847 * source of reliable time info. The i8254 looses too of course
848 * but we need to have some kind of time...
849 * We don't know at this point whether APM is going to be used
850 * or not, nor when it might be activated. Play it safe.
851 */
852 return;
853#endif /* NAPM > 0 */
854
984263bc
MD
855#endif /* !defined(SMP) */
856}
857
858/*
e63ac55d
MD
859 * Sync the time of day back to the RTC on shutdown, but only if
860 * we have already loaded it and have not crashed.
861 */
862static void
863resettodr_on_shutdown(void *arg __unused)
864{
865 if (rtc_loaded && panicstr == NULL) {
866 resettodr();
867 }
868}
869
870/*
984263bc
MD
871 * Initialize the time of day register, based on the time base which is, e.g.
872 * from a filesystem.
873 */
874void
875inittodr(time_t base)
876{
877 unsigned long sec, days;
984263bc 878 int year, month;
88c4d2f6 879 int y, m;
984263bc
MD
880 struct timespec ts;
881
882 if (base) {
984263bc
MD
883 ts.tv_sec = base;
884 ts.tv_nsec = 0;
88c4d2f6 885 set_timeofday(&ts);
984263bc
MD
886 }
887
888 /* Look if we have a RTC present and the time is valid */
889 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
890 goto wrong_time;
891
892 /* wait for time update to complete */
893 /* If RTCSA_TUP is zero, we have at least 244us before next update */
88c4d2f6 894 crit_enter();
984263bc 895 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
88c4d2f6
MD
896 crit_exit();
897 crit_enter();
984263bc
MD
898 }
899
900 days = 0;
901#ifdef USE_RTC_CENTURY
902 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
903#else
904 year = readrtc(RTC_YEAR) + 1900;
905 if (year < 1970)
906 year += 100;
907#endif
908 if (year < 1970) {
88c4d2f6 909 crit_exit();
984263bc
MD
910 goto wrong_time;
911 }
912 month = readrtc(RTC_MONTH);
913 for (m = 1; m < month; m++)
914 days += daysinmonth[m-1];
915 if ((month > 2) && LEAPYEAR(year))
916 days ++;
917 days += readrtc(RTC_DAY) - 1;
984263bc
MD
918 for (y = 1970; y < year; y++)
919 days += DAYSPERYEAR + LEAPYEAR(y);
920 sec = ((( days * 24 +
921 readrtc(RTC_HRS)) * 60 +
922 readrtc(RTC_MIN)) * 60 +
923 readrtc(RTC_SEC));
924 /* sec now contains the number of seconds, since Jan 1 1970,
925 in the local time zone */
926
927 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
928
929 y = time_second - sec;
930 if (y <= -2 || y >= 2) {
931 /* badly off, adjust it */
932 ts.tv_sec = sec;
933 ts.tv_nsec = 0;
88c4d2f6 934 set_timeofday(&ts);
984263bc 935 }
e63ac55d 936 rtc_loaded = 1;
88c4d2f6 937 crit_exit();
984263bc
MD
938 return;
939
940wrong_time:
26be20a0
SW
941 kprintf("Invalid time in real time clock.\n");
942 kprintf("Check and reset the date immediately!\n");
984263bc
MD
943}
944
945/*
946 * Write system time back to RTC
947 */
948void
09e6e929 949resettodr(void)
984263bc 950{
2f70966e
MD
951 struct timeval tv;
952 unsigned long tm;
953 int m;
954 int y;
984263bc
MD
955
956 if (disable_rtc_set)
957 return;
958
2f70966e
MD
959 microtime(&tv);
960 tm = tv.tv_sec;
984263bc 961
88c4d2f6 962 crit_enter();
984263bc
MD
963 /* Disable RTC updates and interrupts. */
964 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
965
966 /* Calculate local time to put in RTC */
967
968 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
969
970 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
971 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
972 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
973
974 /* We have now the days since 01-01-1970 in tm */
975 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
976 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
977 tm >= m;
978 y++, m = DAYSPERYEAR + LEAPYEAR(y))
979 tm -= m;
980
981 /* Now we have the years in y and the day-of-the-year in tm */
982 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
983#ifdef USE_RTC_CENTURY
984 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
985#endif
986 for (m = 0; ; m++) {
987 int ml;
988
989 ml = daysinmonth[m];
990 if (m == 1 && LEAPYEAR(y))
991 ml++;
992 if (tm < ml)
993 break;
994 tm -= ml;
995 }
996
997 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
998 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
999
1000 /* Reenable RTC updates and interrupts. */
1001 writertc(RTC_STATUSB, rtc_statusb);
88c4d2f6 1002 crit_exit();
984263bc
MD
1003}
1004
1005
1006/*
88c4d2f6
MD
1007 * Start both clocks running. DragonFly note: the stat clock is no longer
1008 * used. Instead, 8254 based systimers are used for all major clock
d426f67a 1009 * interrupts.
984263bc 1010 */
ef612539
SZ
1011static void
1012i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
984263bc 1013{
30c5f287 1014#ifdef SMP /* APIC-IO */
c79ae131
SW
1015 int apic_8254_trial = 0;
1016 void *clkdesc = NULL;
30c5f287 1017#endif
984263bc 1018
38015462
SZ
1019 callout_init(&sysbeepstop_ch);
1020
ef612539
SZ
1021 if (!selected && i8254_intr_disable) {
1022 i8254_nointr = 1; /* don't try to register again */
1023 cputimer_intr_deregister(cti);
e87376d9 1024 return;
ef612539 1025 }
e87376d9 1026
d426f67a
SZ
1027 /*
1028 * The stat interrupt mask is different without the
1029 * statistics clock. Also, don't set the interrupt
1030 * flag which would normally cause the RTC to generate
1031 * interrupts.
1032 */
1033 rtc_statusb = RTCSB_24HR;
38015462 1034
984263bc 1035 /* Finish initializing 8253 timer 0. */
30c5f287
MN
1036#ifdef SMP /* APIC-IO */
1037if (apic_io_enable) {
984263bc 1038 apic_8254_intr = isa_apic_irq(0);
984263bc
MD
1039 if (apic_8254_intr >= 0 ) {
1040 if (apic_int_type(0, 0) == 3)
1041 apic_8254_trial = 1;
1042 } else {
1043 /* look for ExtInt on pin 0 */
1044 if (apic_int_type(0, 0) == 3) {
1045 apic_8254_intr = apic_irq(0, 0);
1046 setup_8254_mixed_mode();
1047 } else
1048 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1049 }
1050
9d522d14
MD
1051 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1052 NULL,
f8a09be1 1053 INTR_EXCL | INTR_CLOCK |
8b3ec75a
MD
1054 INTR_NOPOLL | INTR_MPSAFE |
1055 INTR_NOENTROPY);
37e7efec 1056 machintr_intren(apic_8254_intr);
30c5f287
MN
1057} else {
1058#endif
38015462 1059 register_int(0, clkintr, NULL, "clk", NULL,
f8a09be1 1060 INTR_EXCL | INTR_CLOCK |
38015462
SZ
1061 INTR_NOPOLL | INTR_MPSAFE |
1062 INTR_NOENTROPY);
1063 machintr_intren(ICU_IRQ0);
30c5f287
MN
1064#ifdef SMP /* APIC-IO */
1065}
1066#endif
38015462
SZ
1067
1068 /* Initialize RTC. */
1069 writertc(RTC_STATUSA, rtc_statusa);
1070 writertc(RTC_STATUSB, RTCSB_24HR);
1071
30c5f287
MN
1072#ifdef SMP /* APIC-IO */
1073if (apic_io_enable) {
984263bc 1074 if (apic_8254_trial) {
88c4d2f6 1075 sysclock_t base;
477d3c1c
MD
1076 long lastcnt;
1077
c5c70fac
SZ
1078 /*
1079 * Following code assumes the 8254 is the cpu timer,
1080 * so make sure it is.
1081 */
1082 KKASSERT(sys_cputimer == &i8254_cputimer);
ef612539 1083 KKASSERT(cti == &i8254_cputimer_intr);
c5c70fac 1084
477d3c1c 1085 lastcnt = get_interrupt_counter(apic_8254_intr);
88c4d2f6
MD
1086
1087 /*
c5c70fac
SZ
1088 * Force an 8254 Timer0 interrupt and wait 1/100s for
1089 * it to happen, then see if we got it.
88c4d2f6 1090 */
26be20a0 1091 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
ef612539 1092 i8254_intr_reload(cti, 2);
044ee7c4
MD
1093 base = sys_cputimer->count();
1094 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
984263bc 1095 ; /* nothing */
477d3c1c 1096 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
984263bc
MD
1097 /*
1098 * The MP table is broken.
1099 * The 8254 was not connected to the specified pin
1100 * on the IO APIC.
1101 * Workaround: Limited variant of mixed mode.
1102 */
37e7efec 1103 machintr_intrdis(apic_8254_intr);
9d522d14 1104 unregister_int(clkdesc);
26be20a0 1105 kprintf("APIC_IO: Broken MP table detected: "
984263bc
MD
1106 "8254 is not connected to "
1107 "IOAPIC #%d intpin %d\n",
1108 int_to_apicintpin[apic_8254_intr].ioapic,
1109 int_to_apicintpin[apic_8254_intr].int_pin);
1110 /*
1111 * Revoke current ISA IRQ 0 assignment and
1112 * configure a fallback interrupt routing from
1113 * the 8254 Timer via the 8259 PIC to the
1114 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1115 * We reuse the low level interrupt handler number.
1116 */
1117 if (apic_irq(0, 0) < 0) {
1118 revoke_apic_irq(apic_8254_intr);
1119 assign_apic_irq(0, 0, apic_8254_intr);
1120 }
1121 apic_8254_intr = apic_irq(0, 0);
1122 setup_8254_mixed_mode();
9d522d14
MD
1123 register_int(apic_8254_intr, clkintr, NULL, "clk",
1124 NULL,
f8a09be1 1125 INTR_EXCL | INTR_CLOCK |
8b3ec75a
MD
1126 INTR_NOPOLL | INTR_MPSAFE |
1127 INTR_NOENTROPY);
37e7efec 1128 machintr_intren(apic_8254_intr);
984263bc 1129 }
984263bc
MD
1130 }
1131 if (apic_int_type(0, 0) != 3 ||
1132 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
88c4d2f6 1133 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
26be20a0 1134 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
984263bc
MD
1135 int_to_apicintpin[apic_8254_intr].ioapic,
1136 int_to_apicintpin[apic_8254_intr].int_pin);
88c4d2f6 1137 } else {
26be20a0 1138 kprintf("APIC_IO: "
984263bc 1139 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
88c4d2f6 1140 }
30c5f287 1141}
38015462 1142#endif
984263bc
MD
1143}
1144
30c5f287 1145#ifdef SMP /* APIC-IO */
984263bc
MD
1146
1147static void
09e6e929 1148setup_8254_mixed_mode(void)
984263bc
MD
1149{
1150 /*
1151 * Allow 8254 timer to INTerrupt 8259:
1152 * re-initialize master 8259:
1153 * reset; prog 4 bytes, single ICU, edge triggered
1154 */
1155 outb(IO_ICU1, 0x13);
97359a5b 1156 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
984263bc
MD
1157 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1158 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1159 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1160
1161 /* program IO APIC for type 3 INT on INT0 */
1162 if (ext_int_setup(0, 0) < 0)
1163 panic("8254 redirect via APIC pin0 impossible!");
1164}
1165#endif
1166
1167void
1168setstatclockrate(int newhz)
1169{
1170 if (newhz == RTC_PROFRATE)
1171 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1172 else
1173 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1174 writertc(RTC_STATUSA, rtc_statusa);
1175}
1176
88c4d2f6 1177#if 0
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1178static unsigned
1179tsc_get_timecount(struct timecounter *tc)
1180{
1181 return (rdtsc());
1182}
88c4d2f6 1183#endif
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1184
1185#ifdef KERN_TIMESTAMP
1186#define KERN_TIMESTAMP_SIZE 16384
1187static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1188SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1189 sizeof(tsc), "LU", "Kernel timestamps");
1190void
1191_TSTMP(u_int32_t x)
1192{
1193 static int i;
1194
1195 tsc[i] = (u_int32_t)rdtsc();
1196 tsc[i+1] = x;
1197 i = i + 2;
1198 if (i >= KERN_TIMESTAMP_SIZE)
1199 i = 0;
1200 tsc[i] = 0; /* mark last entry */
1201}
6b08710e 1202#endif /* KERN_TIMESTAMP */
984263bc 1203
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1204/*
1205 *
1206 */
1207
1208static int
1209hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1210{
1211 sysclock_t count;
1212 __uint64_t tscval;
1213 char buf[32];
1214
1215 crit_enter();
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1216 if (sys_cputimer == &i8254_cputimer)
1217 count = sys_cputimer->count();
1218 else
1219 count = 0;
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1220 if (tsc_present)
1221 tscval = rdtsc();
1222 else
1223 tscval = 0;
1224 crit_exit();
f8c7a42d 1225 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
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1226 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1227}
1228
1229SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
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1230SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1231 "frequency");
c17827b4 1232SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
044ee7c4 1233 0, 0, hw_i8254_timestamp, "A", "");
c17827b4 1234
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1235SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1236 &tsc_present, 0, "TSC Available");
1237SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1238 &tsc_frequency, 0, "TSC Frequency");
1239