icu: Split out icu/icu.c
[dragonfly.git] / sys / platform / pc32 / isa / intr_machdep.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
f8334305 34 * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.h,v 1.25 2006/10/23 21:50:31 dillon Exp $
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35 */
36
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37#ifndef _ARCH_ISA_INTR_MACHDEP_H_
38#define _ARCH_ISA_INTR_MACHDEP_H_
984263bc 39
8a8d5d85 40#ifndef LOCORE
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41#ifndef _SYS_TYPES_H_
42#include <sys/types.h>
e9cb6d99 43#endif
8a8d5d85 44#endif
ef0fdad1 45
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46/*
47 * Low level interrupt code.
48 */
49
50#ifdef _KERNEL
51
507bf37b 52#define IDT_OFFSET 0x20
9caf58d7 53#define IDT_OFFSET_SYSCALL 0x80
507bf37b 54#define IDT_OFFSET_IPI 0xe0
5f456c40 55
97359a5b 56#if defined(SMP)
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57
58/*
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59 * Local APIC TPR priority vector levels:
60 *
61 * 0xff (255) +-------------+
62 * | | 15 (IPIs: Xcpustop, Xspuriousint)
63 * 0xf0 (240) +-------------+
64 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
65 * 0xe0 (224) +-------------+
66 * | | 13
67 * 0xd0 (208) +-------------+
68 * | | 12
69 * 0xc0 (192) +-------------+
70 * | | 11
71 * 0xb0 (176) +-------------+
72 * | | 10
73 * 0xa0 (160) +-------------+
74 * | | 9
75 * 0x90 (144) +-------------+
76 * | | 8 (syscall at 0x80)
77 * 0x80 (128) +-------------+
78 * | | 7
79 * 0x70 (112) +-------------+
80 * | | 6
81 * 0x60 (96) +-------------+
82 * | | 5
83 * 0x50 (80) +-------------+
84 * | | 4
85 * 0x40 (64) +-------------+
86 * | | 3
87 * 0x30 (48) +-------------+
87e3ca2d 88 * | | 2 (hardware INTs)
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89 * 0x20 (32) +-------------+
90 * | | 1 (exceptions, traps, etc.)
91 * 0x10 (16) +-------------+
92 * | | 0 (exceptions, traps, etc.)
93 * 0x00 (0) +-------------+
984263bc 94 */
507bf37b 95#define TPR_STEP 0x10
984263bc 96
6ab7c3af 97/* Local APIC Task Priority Register */
507bf37b 98#define TPR_IPI (IDT_OFFSET_IPI - 1)
984263bc 99
984263bc 100
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101/*
102 * IPI group1
103 */
104#define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
105
106/* TLB shootdowns */
107#define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
984263bc 108
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109/* IPI group1 1: unused (was inter-cpu clock handling) */
110/* IPI group1 2: unused (was inter-cpu rendezvous) */
984263bc 111
5971ceae 112/* IPIQ */
507bf37b 113#define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
96728c05 114
5971ceae 115/* Local APIC TIMER */
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116#define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
117
118/* IPI group1 5 ~ 15: unused */
78ea5a2a 119
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120
121/*
507bf37b 122 * IPI group2
984263bc 123 */
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124#define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
125
126/* IPI to signal CPUs to stop and wait for another CPU to restart them */
127#define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
128
129/* IPI group2 1 ~ 14: unused */
130
131/* NOTE: this vector MUST be xxxx1111 */
132#define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
984263bc 133
97359a5b 134#endif /* SMP */
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135
136#ifndef LOCORE
137
138/*
139 * Type of the first (asm) part of an interrupt handler.
140 */
ef0fdad1 141typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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142
143#define IDTVEC(name) __CONCAT(X,name)
144
ef0fdad1 145#if defined(SMP)
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146inthand_t
147 Xinvltlb, /* TLB shootdowns */
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148 Xcpuast, /* Additional software trap on other cpu */
149 Xforward_irq, /* Forward irq to cpu holding ISR lock */
150 Xcpustop, /* CPU stops & waits for another CPU to restart it */
151 Xspuriousint, /* handle APIC "spurious INTs" */
78ea5a2a 152 Xtimer, /* handle LAPIC timer INT */
6819df07 153 Xipiq; /* handle lwkt_send_ipiq() requests */
ef0fdad1 154#endif /* SMP */
984263bc 155
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156void isa_defaultirq(void);
157int isa_nmi(int);
3ae0cd58 158
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159#endif /* LOCORE */
160
161#endif /* _KERNEL */
162
f8334305 163#endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */