icu: Split out icu/icu.c
[dragonfly.git] / sys / platform / pc64 / isa / clock.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
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39 */
40
41/*
42 * Routines to handle clock hardware.
43 */
44
45/*
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 *
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
50 */
51
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52#if 0
53#include "use_apm.h"
54#include "opt_clock.h"
55#endif
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56
57#include <sys/param.h>
58#include <sys/systm.h>
59#include <sys/eventhandler.h>
60#include <sys/time.h>
61#include <sys/kernel.h>
62#include <sys/bus.h>
63#ifndef SMP
64#include <sys/lock.h>
65#endif
66#include <sys/sysctl.h>
67#include <sys/cons.h>
68#include <sys/systimer.h>
69#include <sys/globaldata.h>
70#include <sys/thread2.h>
71#include <sys/systimer.h>
72#include <sys/machintr.h>
1b505979 73#include <sys/interrupt.h>
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74
75#include <machine/clock.h>
76#ifdef CLK_CALIBRATION_LOOP
77#endif
78#include <machine/cputypes.h>
79#include <machine/frame.h>
80#include <machine/ipl.h>
81#include <machine/limits.h>
82#include <machine/md_var.h>
83#include <machine/psl.h>
84#include <machine/segments.h>
85#include <machine/smp.h>
86#include <machine/specialreg.h>
87
88#include <machine_base/icu/icu.h>
0855a2af 89#include <bus/isa/isa.h>
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90#include <bus/isa/rtc.h>
91#include <machine_base/isa/timerreg.h>
92
93#include <machine_base/isa/intr_machdep.h>
94
faaf4131 95#ifdef SMP /* APIC-IO */
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96/* The interrupt triggered by the 8254 (timer) chip */
97int apic_8254_intr;
98static void setup_8254_mixed_mode (void);
99#endif
100static void i8254_restore(void);
101static void resettodr_on_shutdown(void *arg __unused);
102
103/*
104 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
105 * can use a simple formula for leap years.
106 */
107#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
108#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
109
110#ifndef TIMER_FREQ
111#define TIMER_FREQ 1193182
112#endif
113
114static uint8_t i8254_walltimer_sel;
115static uint16_t i8254_walltimer_cntr;
116
117int adjkerntz; /* local offset from GMT in seconds */
118int disable_rtc_set; /* disable resettodr() if != 0 */
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119int tsc_present;
120int64_t tsc_frequency;
121int tsc_is_broken;
122int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
123int timer0_running;
124enum tstate { RELEASED, ACQUIRED };
125enum tstate timer0_state;
126enum tstate timer1_state;
127enum tstate timer2_state;
128
129static int beeping = 0;
130static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
131static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
132static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
133static int rtc_loaded;
134
135static int i8254_cputimer_div;
136
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137static int i8254_nointr;
138static int i8254_intr_disable = 0;
139TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
140
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141static struct callout sysbeepstop_ch;
142
143static sysclock_t i8254_cputimer_count(void);
144static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
145static void i8254_cputimer_destruct(struct cputimer *cputimer);
146
147static struct cputimer i8254_cputimer = {
148 SLIST_ENTRY_INITIALIZER,
149 "i8254",
150 CPUTIMER_PRI_8254,
151 0,
152 i8254_cputimer_count,
153 cputimer_default_fromhz,
154 cputimer_default_fromus,
155 i8254_cputimer_construct,
156 i8254_cputimer_destruct,
157 TIMER_FREQ,
158 0, 0, 0
159};
160
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161static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
162static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
163static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
164
165static struct cputimer_intr i8254_cputimer_intr = {
166 .freq = TIMER_FREQ,
167 .reload = i8254_intr_reload,
168 .enable = cputimer_intr_default_enable,
169 .config = i8254_intr_config,
170 .restart = cputimer_intr_default_restart,
171 .pmfixup = cputimer_intr_default_pmfixup,
172 .initclock = i8254_intr_initclock,
173 .next = SLIST_ENTRY_INITIALIZER,
174 .name = "i8254",
175 .type = CPUTIMER_INTR_8254,
176 .prio = CPUTIMER_INTR_PRIO_8254,
177 .caps = CPUTIMER_INTR_CAP_PS
178};
179
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180/*
181 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
182 * counting as of this interrupt. We use timer1 in free-running mode (not
183 * generating any interrupts) as our main counter. Each cpu has timeouts
184 * pending.
185 *
186 * This code is INTR_MPSAFE and may be called without the BGL held.
187 */
188static void
189clkintr(void *dummy, void *frame_arg)
190{
191 static sysclock_t sysclock_count; /* NOTE! Must be static */
192 struct globaldata *gd = mycpu;
193#ifdef SMP
194 struct globaldata *gscan;
195 int n;
196#endif
197
198 /*
199 * SWSTROBE mode is a one-shot, the timer is no longer running
200 */
201 timer0_running = 0;
202
203 /*
204 * XXX the dispatcher needs work. right now we call systimer_intr()
205 * directly or via IPI for any cpu with systimers queued, which is
206 * usually *ALL* of them. We need to use the LAPIC timer for this.
207 */
208 sysclock_count = sys_cputimer->count();
209#ifdef SMP
210 for (n = 0; n < ncpus; ++n) {
211 gscan = globaldata_find(n);
212 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
213 continue;
214 if (gscan != gd) {
215 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
216 &sysclock_count, 0);
217 } else {
218 systimer_intr(&sysclock_count, 0, frame_arg);
219 }
220 }
221#else
222 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
223 systimer_intr(&sysclock_count, 0, frame_arg);
224#endif
225}
226
227
228/*
229 * NOTE! not MP safe.
230 */
231int
232acquire_timer2(int mode)
233{
234 if (timer2_state != RELEASED)
235 return (-1);
236 timer2_state = ACQUIRED;
237
238 /*
239 * This access to the timer registers is as atomic as possible
240 * because it is a single instruction. We could do better if we
241 * knew the rate.
242 */
243 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
244 return (0);
245}
246
247int
248release_timer2(void)
249{
250 if (timer2_state != ACQUIRED)
251 return (-1);
252 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
253 timer2_state = RELEASED;
254 return (0);
255}
256
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257#include "opt_ddb.h"
258#ifdef DDB
259#include <ddb/ddb.h>
260
261DB_SHOW_COMMAND(rtc, rtc)
262{
263 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
264 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
265 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
266 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
267}
268#endif /* DDB */
269
270/*
271 * Return the current cpu timer count as a 32 bit integer.
272 */
273static
274sysclock_t
275i8254_cputimer_count(void)
276{
277 static __uint16_t cputimer_last;
278 __uint16_t count;
279 sysclock_t ret;
280
281 clock_lock();
282 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
283 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
284 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
285 count = -count; /* -> countup */
286 if (count < cputimer_last) /* rollover */
287 i8254_cputimer.base += 0x00010000;
288 ret = i8254_cputimer.base | count;
289 cputimer_last = count;
290 clock_unlock();
291 return(ret);
292}
293
294/*
295 * This function is called whenever the system timebase changes, allowing
296 * us to calculate what is needed to convert a system timebase tick
297 * into an 8254 tick for the interrupt timer. If we can convert to a
298 * simple shift, multiplication, or division, we do so. Otherwise 64
299 * bit arithmatic is required every time the interrupt timer is reloaded.
300 */
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301static void
302i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
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303{
304 int freq;
305 int div;
306
307 /*
308 * Will a simple divide do the trick?
309 */
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310 div = (timer->freq + (cti->freq / 2)) / cti->freq;
311 freq = cti->freq * div;
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312
313 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
314 i8254_cputimer_div = div;
315 else
316 i8254_cputimer_div = 0;
317}
318
319/*
320 * Reload for the next timeout. It is possible for the reload value
321 * to be 0 or negative, indicating that an immediate timer interrupt
322 * is desired. For now make the minimum 2 ticks.
323 *
324 * We may have to convert from the system timebase to the 8254 timebase.
325 */
c5b8324c 326static void
40672791 327i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
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328{
329 __uint16_t count;
330
331 if (i8254_cputimer_div)
332 reload /= i8254_cputimer_div;
333 else
40672791 334 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
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335
336 if ((int)reload < 2)
337 reload = 2;
338
339 clock_lock();
340 if (timer0_running) {
341 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
342 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
343 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
344 if (reload < count) {
345 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
346 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
347 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
348 }
349 } else {
350 timer0_running = 1;
351 if (reload > 0xFFFF)
352 reload = 0; /* full count */
353 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
354 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
355 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
356 }
357 clock_unlock();
358}
359
360/*
361 * DELAY(usec) - Spin for the specified number of microseconds.
362 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
363 * but do a thread switch in the loop
364 *
365 * Relies on timer 1 counting down from (cputimer_freq / hz)
366 * Note: timer had better have been programmed before this is first used!
367 */
368static void
369DODELAY(int n, int doswitch)
370{
371 int delta, prev_tick, tick, ticks_left;
372
373#ifdef DELAYDEBUG
374 int getit_calls = 1;
375 int n1;
376 static int state = 0;
377
378 if (state == 0) {
379 state = 1;
380 for (n1 = 1; n1 <= 10000000; n1 *= 10)
381 DELAY(n1);
382 state = 2;
383 }
384 if (state == 1)
385 kprintf("DELAY(%d)...", n);
386#endif
387 /*
388 * Guard against the timer being uninitialized if we are called
389 * early for console i/o.
390 */
391 if (timer0_state == RELEASED)
392 i8254_restore();
393
394 /*
395 * Read the counter first, so that the rest of the setup overhead is
396 * counted. Then calculate the number of hardware timer ticks
397 * required, rounding up to be sure we delay at least the requested
398 * number of microseconds.
399 */
400 prev_tick = sys_cputimer->count();
401 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
402 1000000;
403
404 /*
405 * Loop until done.
406 */
407 while (ticks_left > 0) {
408 tick = sys_cputimer->count();
409#ifdef DELAYDEBUG
410 ++getit_calls;
411#endif
412 delta = tick - prev_tick;
413 prev_tick = tick;
414 if (delta < 0)
415 delta = 0;
416 ticks_left -= delta;
417 if (doswitch && ticks_left > 0)
418 lwkt_switch();
c5724852 419 cpu_pause();
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420 }
421#ifdef DELAYDEBUG
422 if (state == 1)
423 kprintf(" %d calls to getit() at %d usec each\n",
424 getit_calls, (n + 5) / getit_calls);
425#endif
426}
427
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428/*
429 * DELAY() never switches.
430 */
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431void
432DELAY(int n)
433{
434 DODELAY(n, 0);
435}
436
77912481 437/*
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438 * Returns non-zero if the specified time period has elapsed. Call
439 * first with last_clock set to 0.
440 */
441int
442CHECKTIMEOUT(TOTALDELAY *tdd)
443{
444 sysclock_t delta;
445 int us;
446
447 if (tdd->started == 0) {
448 if (timer0_state == RELEASED)
449 i8254_restore();
450 tdd->last_clock = sys_cputimer->count();
451 tdd->started = 1;
452 return(0);
453 }
454 delta = sys_cputimer->count() - tdd->last_clock;
455 us = (u_int64_t)delta * (u_int64_t)1000000 /
456 (u_int64_t)sys_cputimer->freq;
457 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
458 1000000;
459 tdd->us -= us;
460 return (tdd->us < 0);
461}
462
463
464/*
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465 * DRIVERSLEEP() does not switch if called with a spinlock held or
466 * from a hard interrupt.
467 */
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468void
469DRIVERSLEEP(int usec)
470{
471 globaldata_t gd = mycpu;
472
8f165b8c 473 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
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474 DODELAY(usec, 0);
475 } else {
476 DODELAY(usec, 1);
477 }
478}
479
480static void
481sysbeepstop(void *chan)
482{
483 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
484 beeping = 0;
485 release_timer2();
486}
487
488int
489sysbeep(int pitch, int period)
490{
491 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
492 return(-1);
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493 if (sysbeep_enable == 0)
494 return(-1);
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495 /*
496 * Nobody else is using timer2, we do not need the clock lock
497 */
498 outb(TIMER_CNTR2, pitch);
499 outb(TIMER_CNTR2, (pitch>>8));
500 if (!beeping) {
501 /* enable counter2 output to speaker */
502 outb(IO_PPI, inb(IO_PPI) | 3);
503 beeping = period;
504 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
505 }
506 return (0);
507}
508
509/*
510 * RTC support routines
511 */
512
513int
514rtcin(int reg)
515{
516 u_char val;
517
518 crit_enter();
519 outb(IO_RTC, reg);
520 inb(0x84);
521 val = inb(IO_RTC + 1);
522 inb(0x84);
523 crit_exit();
524 return (val);
525}
526
527static __inline void
528writertc(u_char reg, u_char val)
529{
530 crit_enter();
531 inb(0x84);
532 outb(IO_RTC, reg);
533 inb(0x84);
534 outb(IO_RTC + 1, val);
535 inb(0x84); /* XXX work around wrong order in rtcin() */
536 crit_exit();
537}
538
539static __inline int
540readrtc(int port)
541{
542 return(bcd2bin(rtcin(port)));
543}
544
545static u_int
546calibrate_clocks(void)
547{
548 u_int64_t old_tsc;
549 u_int count, prev_count, tot_count;
550 int sec, start_sec, timeout;
551
552 if (bootverbose)
553 kprintf("Calibrating clock(s) ... ");
554 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
555 goto fail;
556 timeout = 100000000;
557
558 /* Read the mc146818A seconds counter. */
559 for (;;) {
560 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
561 sec = rtcin(RTC_SEC);
562 break;
563 }
564 if (--timeout == 0)
565 goto fail;
566 }
567
568 /* Wait for the mC146818A seconds counter to change. */
569 start_sec = sec;
570 for (;;) {
571 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
572 sec = rtcin(RTC_SEC);
573 if (sec != start_sec)
574 break;
575 }
576 if (--timeout == 0)
577 goto fail;
578 }
579
580 /* Start keeping track of the i8254 counter. */
581 prev_count = sys_cputimer->count();
582 tot_count = 0;
583
584 if (tsc_present)
585 old_tsc = rdtsc();
586 else
587 old_tsc = 0; /* shut up gcc */
588
589 /*
590 * Wait for the mc146818A seconds counter to change. Read the i8254
591 * counter for each iteration since this is convenient and only
592 * costs a few usec of inaccuracy. The timing of the final reads
593 * of the counters almost matches the timing of the initial reads,
594 * so the main cause of inaccuracy is the varying latency from
595 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
596 * rtcin(RTC_SEC) that returns a changed seconds count. The
597 * maximum inaccuracy from this cause is < 10 usec on 486's.
598 */
599 start_sec = sec;
600 for (;;) {
601 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
602 sec = rtcin(RTC_SEC);
603 count = sys_cputimer->count();
604 tot_count += (int)(count - prev_count);
605 prev_count = count;
606 if (sec != start_sec)
607 break;
608 if (--timeout == 0)
609 goto fail;
610 }
611
612 /*
613 * Read the cpu cycle counter. The timing considerations are
614 * similar to those for the i8254 clock.
615 */
616 if (tsc_present) {
617 tsc_frequency = rdtsc() - old_tsc;
618 }
619
620 if (tsc_present)
973c11b9 621 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency);
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622 kprintf("i8254 clock: %u Hz\n", tot_count);
623 return (tot_count);
624
625fail:
626 kprintf("failed, using default i8254 clock of %u Hz\n",
627 i8254_cputimer.freq);
628 return (i8254_cputimer.freq);
629}
630
631static void
632i8254_restore(void)
633{
634 timer0_state = ACQUIRED;
635
636 clock_lock();
637
638 /*
639 * Timer0 is our fine-grained variable clock interrupt
640 */
641 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
642 outb(TIMER_CNTR0, 2); /* lsb */
643 outb(TIMER_CNTR0, 0); /* msb */
644 clock_unlock();
645
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646 if (!i8254_nointr) {
647 cputimer_intr_register(&i8254_cputimer_intr);
648 cputimer_intr_select(&i8254_cputimer_intr, 0);
649 }
650
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651 /*
652 * Timer1 or timer2 is our free-running clock, but only if another
653 * has not been selected.
654 */
655 cputimer_register(&i8254_cputimer);
656 cputimer_select(&i8254_cputimer, 0);
657}
658
659static void
660i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
661{
662 int which;
663
664 /*
665 * Should we use timer 1 or timer 2 ?
666 */
667 which = 0;
668 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
669 if (which != 1 && which != 2)
670 which = 2;
671
672 switch(which) {
673 case 1:
674 timer->name = "i8254_timer1";
675 timer->type = CPUTIMER_8254_SEL1;
676 i8254_walltimer_sel = TIMER_SEL1;
677 i8254_walltimer_cntr = TIMER_CNTR1;
678 timer1_state = ACQUIRED;
679 break;
680 case 2:
681 timer->name = "i8254_timer2";
682 timer->type = CPUTIMER_8254_SEL2;
683 i8254_walltimer_sel = TIMER_SEL2;
684 i8254_walltimer_cntr = TIMER_CNTR2;
685 timer2_state = ACQUIRED;
686 break;
687 }
688
689 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
690
691 clock_lock();
692 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
693 outb(i8254_walltimer_cntr, 0); /* lsb */
694 outb(i8254_walltimer_cntr, 0); /* msb */
695 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
696 clock_unlock();
697}
698
699static void
700i8254_cputimer_destruct(struct cputimer *timer)
701{
702 switch(timer->type) {
703 case CPUTIMER_8254_SEL1:
704 timer1_state = RELEASED;
705 break;
706 case CPUTIMER_8254_SEL2:
707 timer2_state = RELEASED;
708 break;
709 default:
710 break;
711 }
712 timer->type = 0;
713}
714
715static void
716rtc_restore(void)
717{
718 /* Restore all of the RTC's "status" (actually, control) registers. */
719 writertc(RTC_STATUSB, RTCSB_24HR);
720 writertc(RTC_STATUSA, rtc_statusa);
721 writertc(RTC_STATUSB, rtc_statusb);
722}
723
724/*
725 * Restore all the timers.
726 *
727 * This function is called to resynchronize our core timekeeping after a
728 * long halt, e.g. from apm_default_resume() and friends. It is also
729 * called if after a BIOS call we have detected munging of the 8254.
730 * It is necessary because cputimer_count() counter's delta may have grown
731 * too large for nanouptime() and friends to handle, or (in the case of 8254
732 * munging) might cause the SYSTIMER code to prematurely trigger.
733 */
734void
735timer_restore(void)
736{
737 crit_enter();
738 i8254_restore(); /* restore timer_freq and hz */
739 rtc_restore(); /* reenable RTC interrupts */
740 crit_exit();
741}
742
743/*
744 * Initialize 8254 timer 0 early so that it can be used in DELAY().
745 */
746void
747startrtclock(void)
748{
749 u_int delta, freq;
750
751 /*
752 * Can we use the TSC?
753 */
754 if (cpu_feature & CPUID_TSC)
755 tsc_present = 1;
756 else
757 tsc_present = 0;
758
759 /*
760 * Initial RTC state, don't do anything unexpected
761 */
762 writertc(RTC_STATUSA, rtc_statusa);
763 writertc(RTC_STATUSB, RTCSB_24HR);
764
765 /*
766 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
767 * generate an interrupt, which we will ignore for now.
768 *
769 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
770 * (so it counts a full 2^16 and repeats). We will use this timer
771 * for our counting.
772 */
773 i8254_restore();
774 freq = calibrate_clocks();
775#ifdef CLK_CALIBRATION_LOOP
776 if (bootverbose) {
777 kprintf(
778 "Press a key on the console to abort clock calibration\n");
779 while (cncheckc() == -1)
780 calibrate_clocks();
781 }
782#endif
783
784 /*
785 * Use the calibrated i8254 frequency if it seems reasonable.
786 * Otherwise use the default, and don't use the calibrated i586
787 * frequency.
788 */
789 delta = freq > i8254_cputimer.freq ?
790 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
791 if (delta < i8254_cputimer.freq / 100) {
792#ifndef CLK_USE_I8254_CALIBRATION
793 if (bootverbose)
794 kprintf(
795"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
796 freq = i8254_cputimer.freq;
797#endif
40672791
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798 /*
799 * NOTE:
800 * Interrupt timer's freq must be adjusted
801 * before we change the cuptimer's frequency.
802 */
803 i8254_cputimer_intr.freq = freq;
c8fe38ae
MD
804 cputimer_set_frequency(&i8254_cputimer, freq);
805 } else {
806 if (bootverbose)
807 kprintf(
808 "%d Hz differs from default of %d Hz by more than 1%%\n",
809 freq, i8254_cputimer.freq);
810 tsc_frequency = 0;
811 }
812
813#ifndef CLK_USE_TSC_CALIBRATION
814 if (tsc_frequency != 0) {
815 if (bootverbose)
816 kprintf(
817"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
818 tsc_frequency = 0;
819 }
820#endif
821 if (tsc_present && tsc_frequency == 0) {
822 /*
823 * Calibration of the i586 clock relative to the mc146818A
824 * clock failed. Do a less accurate calibration relative
825 * to the i8254 clock.
826 */
827 u_int64_t old_tsc = rdtsc();
828
829 DELAY(1000000);
830 tsc_frequency = rdtsc() - old_tsc;
831#ifdef CLK_USE_TSC_CALIBRATION
832 if (bootverbose) {
833 kprintf("TSC clock: %llu Hz (Method B)\n",
834 tsc_frequency);
835 }
836#endif
837 }
838
839 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
840
841#if !defined(SMP)
842 /*
843 * We can not use the TSC in SMP mode, until we figure out a
844 * cheap (impossible), reliable and precise (yeah right!) way
845 * to synchronize the TSCs of all the CPUs.
846 * Curse Intel for leaving the counter out of the I/O APIC.
847 */
848
849#if NAPM > 0
850 /*
851 * We can not use the TSC if we support APM. Precise timekeeping
852 * on an APM'ed machine is at best a fools pursuit, since
853 * any and all of the time spent in various SMM code can't
854 * be reliably accounted for. Reading the RTC is your only
855 * source of reliable time info. The i8254 looses too of course
856 * but we need to have some kind of time...
857 * We don't know at this point whether APM is going to be used
858 * or not, nor when it might be activated. Play it safe.
859 */
860 return;
861#endif /* NAPM > 0 */
862
863#endif /* !defined(SMP) */
864}
865
866/*
867 * Sync the time of day back to the RTC on shutdown, but only if
868 * we have already loaded it and have not crashed.
869 */
870static void
871resettodr_on_shutdown(void *arg __unused)
872{
873 if (rtc_loaded && panicstr == NULL) {
874 resettodr();
875 }
876}
877
878/*
879 * Initialize the time of day register, based on the time base which is, e.g.
880 * from a filesystem.
881 */
882void
883inittodr(time_t base)
884{
885 unsigned long sec, days;
c8fe38ae
MD
886 int year, month;
887 int y, m;
888 struct timespec ts;
889
890 if (base) {
891 ts.tv_sec = base;
892 ts.tv_nsec = 0;
893 set_timeofday(&ts);
894 }
895
896 /* Look if we have a RTC present and the time is valid */
897 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
898 goto wrong_time;
899
900 /* wait for time update to complete */
901 /* If RTCSA_TUP is zero, we have at least 244us before next update */
902 crit_enter();
903 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
904 crit_exit();
905 crit_enter();
906 }
907
908 days = 0;
909#ifdef USE_RTC_CENTURY
910 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
911#else
912 year = readrtc(RTC_YEAR) + 1900;
913 if (year < 1970)
914 year += 100;
915#endif
916 if (year < 1970) {
917 crit_exit();
918 goto wrong_time;
919 }
920 month = readrtc(RTC_MONTH);
921 for (m = 1; m < month; m++)
922 days += daysinmonth[m-1];
923 if ((month > 2) && LEAPYEAR(year))
924 days ++;
925 days += readrtc(RTC_DAY) - 1;
c8fe38ae
MD
926 for (y = 1970; y < year; y++)
927 days += DAYSPERYEAR + LEAPYEAR(y);
928 sec = ((( days * 24 +
929 readrtc(RTC_HRS)) * 60 +
930 readrtc(RTC_MIN)) * 60 +
931 readrtc(RTC_SEC));
932 /* sec now contains the number of seconds, since Jan 1 1970,
933 in the local time zone */
934
935 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
936
937 y = time_second - sec;
938 if (y <= -2 || y >= 2) {
939 /* badly off, adjust it */
940 ts.tv_sec = sec;
941 ts.tv_nsec = 0;
942 set_timeofday(&ts);
943 }
944 rtc_loaded = 1;
945 crit_exit();
946 return;
947
948wrong_time:
949 kprintf("Invalid time in real time clock.\n");
950 kprintf("Check and reset the date immediately!\n");
951}
952
953/*
954 * Write system time back to RTC
955 */
956void
957resettodr(void)
958{
959 struct timeval tv;
960 unsigned long tm;
961 int m;
962 int y;
963
964 if (disable_rtc_set)
965 return;
966
967 microtime(&tv);
968 tm = tv.tv_sec;
969
970 crit_enter();
971 /* Disable RTC updates and interrupts. */
972 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
973
974 /* Calculate local time to put in RTC */
975
976 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
977
978 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
979 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
980 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
981
982 /* We have now the days since 01-01-1970 in tm */
983 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
984 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
985 tm >= m;
986 y++, m = DAYSPERYEAR + LEAPYEAR(y))
987 tm -= m;
988
989 /* Now we have the years in y and the day-of-the-year in tm */
990 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
991#ifdef USE_RTC_CENTURY
992 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
993#endif
994 for (m = 0; ; m++) {
995 int ml;
996
997 ml = daysinmonth[m];
998 if (m == 1 && LEAPYEAR(y))
999 ml++;
1000 if (tm < ml)
1001 break;
1002 tm -= ml;
1003 }
1004
1005 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1006 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1007
1008 /* Reenable RTC updates and interrupts. */
1009 writertc(RTC_STATUSB, rtc_statusb);
1010 crit_exit();
1011}
1012
40672791
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1013
1014/*
1015 * Start both clocks running. DragonFly note: the stat clock is no longer
1016 * used. Instead, 8254 based systimers are used for all major clock
d426f67a 1017 * interrupts.
40672791
SZ
1018 */
1019static void
1020i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1021{
faaf4131 1022#ifdef SMP /* APIC-IO */
c79ae131
SW
1023 int apic_8254_trial = 0;
1024 void *clkdesc = NULL;
faaf4131 1025#endif
c8fe38ae 1026
adc34348
SZ
1027 callout_init(&sysbeepstop_ch);
1028
40672791
SZ
1029 if (!selected && i8254_intr_disable) {
1030 i8254_nointr = 1; /* don't try to register again */
1031 cputimer_intr_deregister(cti);
1032 return;
1033 }
1034
d426f67a
SZ
1035 /*
1036 * The stat interrupt mask is different without the
1037 * statistics clock. Also, don't set the interrupt
1038 * flag which would normally cause the RTC to generate
1039 * interrupts.
1040 */
1041 rtc_statusb = RTCSB_24HR;
adc34348 1042
da23a592 1043 /* Finish initializing 8254 timer 0. */
faaf4131
MN
1044#ifdef SMP /* APIC-IO */
1045if (apic_io_enable) {
c8fe38ae 1046 apic_8254_intr = isa_apic_irq(0);
c8fe38ae
MD
1047 if (apic_8254_intr >= 0 ) {
1048 if (apic_int_type(0, 0) == 3)
1049 apic_8254_trial = 1;
1050 } else {
1051 /* look for ExtInt on pin 0 */
1052 if (apic_int_type(0, 0) == 3) {
1053 apic_8254_intr = apic_irq(0, 0);
1054 setup_8254_mixed_mode();
1055 } else
1056 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1057 }
1058
1059 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1060 NULL,
f8a09be1 1061 INTR_EXCL | INTR_CLOCK |
c8fe38ae
MD
1062 INTR_NOPOLL | INTR_MPSAFE |
1063 INTR_NOENTROPY);
1064 machintr_intren(apic_8254_intr);
faaf4131
MN
1065} else {
1066#endif
adc34348 1067 register_int(0, clkintr, NULL, "clk", NULL,
f8a09be1 1068 INTR_EXCL | INTR_CLOCK |
adc34348
SZ
1069 INTR_NOPOLL | INTR_MPSAFE |
1070 INTR_NOENTROPY);
1071 machintr_intren(ICU_IRQ0);
faaf4131
MN
1072#ifdef SMP /* APIC-IO */
1073}
1074#endif
adc34348
SZ
1075
1076 /* Initialize RTC. */
1077 writertc(RTC_STATUSA, rtc_statusa);
1078 writertc(RTC_STATUSB, RTCSB_24HR);
1079
faaf4131
MN
1080#ifdef SMP /* APIC-IO */
1081if (apic_io_enable) {
c8fe38ae
MD
1082 if (apic_8254_trial) {
1083 sysclock_t base;
1084 long lastcnt;
1085
40672791
SZ
1086 /*
1087 * Following code assumes the 8254 is the cpu timer,
1088 * so make sure it is.
1089 */
1090 KKASSERT(sys_cputimer == &i8254_cputimer);
1091 KKASSERT(cti == &i8254_cputimer_intr);
1092
c8fe38ae
MD
1093 lastcnt = get_interrupt_counter(apic_8254_intr);
1094
1095 /*
40672791
SZ
1096 * Force an 8254 Timer0 interrupt and wait 1/100s for
1097 * it to happen, then see if we got it.
c8fe38ae
MD
1098 */
1099 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
40672791 1100 i8254_intr_reload(cti, 2);
c8fe38ae
MD
1101 base = sys_cputimer->count();
1102 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1103 ; /* nothing */
1104 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1105 /*
1106 * The MP table is broken.
1107 * The 8254 was not connected to the specified pin
1108 * on the IO APIC.
1109 * Workaround: Limited variant of mixed mode.
1110 */
1111 machintr_intrdis(apic_8254_intr);
1112 unregister_int(clkdesc);
1113 kprintf("APIC_IO: Broken MP table detected: "
1114 "8254 is not connected to "
1115 "IOAPIC #%d intpin %d\n",
1116 int_to_apicintpin[apic_8254_intr].ioapic,
1117 int_to_apicintpin[apic_8254_intr].int_pin);
1118 /*
1119 * Revoke current ISA IRQ 0 assignment and
1120 * configure a fallback interrupt routing from
1121 * the 8254 Timer via the 8259 PIC to the
1122 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1123 * We reuse the low level interrupt handler number.
1124 */
1125 if (apic_irq(0, 0) < 0) {
1126 revoke_apic_irq(apic_8254_intr);
1127 assign_apic_irq(0, 0, apic_8254_intr);
1128 }
1129 apic_8254_intr = apic_irq(0, 0);
1130 setup_8254_mixed_mode();
1131 register_int(apic_8254_intr, clkintr, NULL, "clk",
1132 NULL,
f8a09be1 1133 INTR_EXCL | INTR_CLOCK |
c8fe38ae
MD
1134 INTR_NOPOLL | INTR_MPSAFE |
1135 INTR_NOENTROPY);
1136 machintr_intren(apic_8254_intr);
1137 }
c8fe38ae
MD
1138 }
1139 if (apic_int_type(0, 0) != 3 ||
1140 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1141 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1142 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1143 int_to_apicintpin[apic_8254_intr].ioapic,
1144 int_to_apicintpin[apic_8254_intr].int_pin);
1145 } else {
1146 kprintf("APIC_IO: "
1147 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1148 }
faaf4131 1149}
adc34348 1150#endif
c8fe38ae 1151}
c8fe38ae 1152
faaf4131 1153#ifdef SMP /* APIC-IO */
c8fe38ae
MD
1154
1155static void
1156setup_8254_mixed_mode(void)
1157{
1158 /*
1159 * Allow 8254 timer to INTerrupt 8259:
1160 * re-initialize master 8259:
1161 * reset; prog 4 bytes, single ICU, edge triggered
1162 */
1163 outb(IO_ICU1, 0x13);
1164 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1165 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1166 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1167 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1168
1169 /* program IO APIC for type 3 INT on INT0 */
1170 if (ext_int_setup(0, 0) < 0)
1171 panic("8254 redirect via APIC pin0 impossible!");
1172}
1173#endif
1174
1175void
1176setstatclockrate(int newhz)
1177{
1178 if (newhz == RTC_PROFRATE)
1179 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1180 else
1181 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1182 writertc(RTC_STATUSA, rtc_statusa);
1183}
1184
1185#if 0
1186static unsigned
1187tsc_get_timecount(struct timecounter *tc)
1188{
1189 return (rdtsc());
1190}
1191#endif
1192
1193#ifdef KERN_TIMESTAMP
1194#define KERN_TIMESTAMP_SIZE 16384
1195static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1196SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1197 sizeof(tsc), "LU", "Kernel timestamps");
1198void
1199_TSTMP(u_int32_t x)
1200{
1201 static int i;
1202
1203 tsc[i] = (u_int32_t)rdtsc();
1204 tsc[i+1] = x;
1205 i = i + 2;
1206 if (i >= KERN_TIMESTAMP_SIZE)
1207 i = 0;
1208 tsc[i] = 0; /* mark last entry */
1209}
1210#endif /* KERN_TIMESTAMP */
1211
1212/*
1213 *
1214 */
1215
1216static int
1217hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1218{
1219 sysclock_t count;
1220 __uint64_t tscval;
1221 char buf[32];
1222
1223 crit_enter();
1224 if (sys_cputimer == &i8254_cputimer)
1225 count = sys_cputimer->count();
1226 else
1227 count = 0;
1228 if (tsc_present)
1229 tscval = rdtsc();
1230 else
1231 tscval = 0;
1232 crit_exit();
1233 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1234 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1235}
1236
1237SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1238SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1239 "frequency");
1240SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1241 0, 0, hw_i8254_timestamp, "A", "");
1242
1243SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1244 &tsc_present, 0, "TSC Available");
1245SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1246 &tsc_frequency, 0, "TSC Frequency");
1247