icu: Split out icu/icu.c
[dragonfly.git] / sys / platform / pc64 / isa / intr_machdep.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
35 * $DragonFly: src/sys/platform/pc64/isa/intr_machdep.h,v 1.1 2008/08/29 17:07:19 dillon Exp $
36 */
37
38#ifndef _ARCH_ISA_INTR_MACHDEP_H_
39#define _ARCH_ISA_INTR_MACHDEP_H_
40
41#ifndef LOCORE
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42#ifndef _SYS_TYPES_H_
43#include <sys/types.h>
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44#endif
45#endif
46
47/*
48 * Low level interrupt code.
49 */
50
51#ifdef _KERNEL
52
617a6d43 53#define IDT_OFFSET 0x20
9caf58d7 54#define IDT_OFFSET_SYSCALL 0x80
617a6d43 55#define IDT_OFFSET_IPI 0xe0
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56
57#if defined(SMP)
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58
59/*
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60 * Local APIC TPR priority vector levels:
61 *
62 * 0xff (255) +-------------+
63 * | | 15 (IPIs: Xcpustop, Xspuriousint)
64 * 0xf0 (240) +-------------+
65 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
66 * 0xe0 (224) +-------------+
67 * | | 13
68 * 0xd0 (208) +-------------+
69 * | | 12
70 * 0xc0 (192) +-------------+
71 * | | 11
72 * 0xb0 (176) +-------------+
73 * | | 10
74 * 0xa0 (160) +-------------+
75 * | | 9
76 * 0x90 (144) +-------------+
77 * | | 8 (syscall at 0x80)
78 * 0x80 (128) +-------------+
79 * | | 7
80 * 0x70 (112) +-------------+
81 * | | 6
82 * 0x60 (96) +-------------+
83 * | | 5
84 * 0x50 (80) +-------------+
85 * | | 4
86 * 0x40 (64) +-------------+
87 * | | 3
88 * 0x30 (48) +-------------+
89 * | | 2 (hardware INTs)
90 * 0x20 (32) +-------------+
91 * | | 1 (exceptions, traps, etc.)
92 * 0x10 (16) +-------------+
93 * | | 0 (exceptions, traps, etc.)
94 * 0x00 (0) +-------------+
c8fe38ae 95 */
617a6d43 96#define TPR_STEP 0x10
c8fe38ae 97
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98/* Local APIC Task Priority Register */
99#define TPR_IPI (IDT_OFFSET_IPI - 1)
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100
101
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102/*
103 * IPI group1
104 */
105#define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
c8fe38ae 106
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107/* TLB shootdowns */
108#define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
c8fe38ae 109
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110/* IPI group1 1: unused (was inter-cpu clock handling) */
111/* IPI group1 2: unused (was inter-cpu rendezvous) */
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112
113/* IPIQ rendezvous */
617a6d43 114#define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
c8fe38ae 115
46d4e165 116/* TIMER rendezvous */
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117#define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
118
119/* IPI group1 5 ~ 15: unused */
46d4e165 120
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121
122/*
617a6d43 123 * IPI group2
c8fe38ae 124 */
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125#define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
126
127/* IPI to signal CPUs to stop and wait for another CPU to restart them */
128#define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
129
130/* IPI group2 1 ~ 14: unused */
131
132/* NOTE: this vector MUST be xxxx1111 */
133#define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
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134
135#endif /* SMP */
136
137#ifndef LOCORE
138
139/*
140 * Type of the first (asm) part of an interrupt handler.
141 */
142#ifndef JG_defined_inthand_t
143#define JG_defined_inthand_t
144typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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145#endif
146
147#define IDTVEC(name) __CONCAT(X,name)
148
149#if defined(SMP)
150inthand_t
151 Xinvltlb, /* TLB shootdowns */
152 Xcpuast, /* Additional software trap on other cpu */
153 Xforward_irq, /* Forward irq to cpu holding ISR lock */
154 Xcpustop, /* CPU stops & waits for another CPU to restart it */
155 Xspuriousint, /* handle APIC "spurious INTs" */
46d4e165 156 Xtimer, /* handle LAPIC timer INT */
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157 Xipiq; /* handle lwkt_send_ipiq() requests */
158#endif /* SMP */
159
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160void isa_defaultirq(void);
161int isa_nmi(int);
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162
163#endif /* LOCORE */
164
165#endif /* _KERNEL */
166
167#endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */