i386: Prepare mp_enable() for multi-stage procedure segmentation
[dragonfly.git] / sys / platform / pc32 / apic / lapic.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
b12a1521 30#include <sys/kernel.h>
23b08e03 31#include <sys/bus.h>
e0918665 32#include <sys/machintr.h>
72740893 33#include <machine/globaldata.h>
984263bc 34#include <machine/smp.h>
90e8a35b 35#include <machine/cputypes.h>
d595a6c0 36#include <machine/md_var.h>
ad52b37b 37#include <machine/pmap.h>
3340ac41 38#include <machine_base/apic/lapic.h>
ed4d621d 39#include <machine_base/apic/ioapic.h>
929c940f 40#include <machine_base/apic/ioapic_abi.h>
984263bc 41#include <machine/segments.h>
96728c05 42#include <sys/thread2.h>
984263bc 43
87cf6827 44#include <machine/intr_machdep.h>
984263bc 45
2abaa030
SZ
46extern int naps;
47
cb7d6921 48volatile lapic_t *lapic;
ad52b37b 49
b52c8db0 50static void lapic_timer_calibrate(void);
086575e9 51static void lapic_timer_set_divisor(int);
a9e511df 52static void lapic_timer_fixup_handler(void *);
76c58571 53static void lapic_timer_restart_handler(void *);
c5b8324c 54
78ea5a2a
SZ
55void lapic_timer_process(void);
56void lapic_timer_process_frame(struct intrframe *);
c5b8324c 57
ef612539 58static int lapic_timer_enable = 1;
c5b8324c 59TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 60
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61static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
62static void lapic_timer_intr_enable(struct cputimer_intr *);
63static void lapic_timer_intr_restart(struct cputimer_intr *);
64static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
65
66static struct cputimer_intr lapic_cputimer_intr = {
67 .freq = 0,
68 .reload = lapic_timer_intr_reload,
69 .enable = lapic_timer_intr_enable,
70 .config = cputimer_intr_default_config,
71 .restart = lapic_timer_intr_restart,
72 .pmfixup = lapic_timer_intr_pmfixup,
73 .initclock = cputimer_intr_default_initclock,
74 .next = SLIST_ENTRY_INITIALIZER,
75 .name = "lapic",
76 .type = CPUTIMER_INTR_LAPIC,
77 .prio = CPUTIMER_INTR_PRIO_LAPIC,
78 .caps = CPUTIMER_INTR_CAP_NONE
79};
80
086575e9
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81static int lapic_timer_divisor_idx = -1;
82static const uint32_t lapic_timer_divisors[] = {
83 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
84 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
85};
c157ff7a 86#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
086575e9 87
984263bc 88/*
2d901d56 89 * APIC ID <-> CPU ID mapping structures.
68d62ec3 90 */
2d901d56
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91int cpu_id_to_apic_id[NAPICID];
92int apic_id_to_cpu_id[NAPICID];
1d6d7089 93int lapic_enable = 1;
68d62ec3
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94
95/*
d99d4acb 96 * Enable LAPIC, configure interrupts.
984263bc
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97 */
98void
5ddeabb9 99lapic_init(boolean_t bsp)
984263bc 100{
78ea5a2a 101 uint32_t timer;
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102 u_int temp;
103
9d6bf2df 104 /*
dbfb3a5a
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105 * Install vectors
106 *
107 * Since IDT is shared between BSP and APs, these vectors
108 * only need to be installed once; we do it on BSP.
109 */
110 if (bsp) {
111 /* Install a 'Spurious INTerrupt' vector */
112 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
113 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
114
115 /* Install an inter-CPU IPI for TLB invalidation */
116 setidt(XINVLTLB_OFFSET, Xinvltlb,
117 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
118
119 /* Install an inter-CPU IPI for IPIQ messaging */
120 setidt(XIPIQ_OFFSET, Xipiq,
121 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
122
123 /* Install a timer vector */
124 setidt(XTIMER_OFFSET, Xtimer,
125 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
126
127 /* Install an inter-CPU IPI for CPU stop/restart */
128 setidt(XCPUSTOP_OFFSET, Xcpustop,
129 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
130 }
131
132 /*
d99d4acb 133 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
97359a5b
MD
134 * aggregate interrupt input from the 8259. The INTA cycle
135 * will be routed to the external controller (the 8259) which
136 * is expected to supply the vector.
137 *
138 * Must be setup edge triggered, active high.
139 *
4d08e038
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140 * Disable LINT0 on BSP, if I/O APIC is enabled.
141 *
d99d4acb 142 * Disable LINT0 on the APs. It doesn't matter what delivery
97359a5b 143 * mode we use because we leave it masked.
9d6bf2df 144 */
cb7d6921 145 temp = lapic->lvt_lint0;
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MD
146 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
147 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
4d08e038 148 if (bsp) {
9d6bf2df 149 temp |= APIC_LVT_DM_EXTINT;
f45bfca0 150 if (ioapic_enable)
4d08e038
SZ
151 temp |= APIC_LVT_MASKED;
152 } else {
97359a5b 153 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
4d08e038 154 }
cb7d6921 155 lapic->lvt_lint0 = temp;
984263bc 156
9d6bf2df 157 /*
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158 * Setup LINT1 as NMI.
159 *
160 * Must be setup edge trigger, active high.
161 *
162 * Enable LINT1 on BSP, if I/O APIC is enabled.
163 *
164 * Disable LINT1 on the APs.
9d6bf2df 165 */
cb7d6921 166 temp = lapic->lvt_lint1;
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167 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
168 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
169 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
f45bfca0 170 if (bsp && ioapic_enable)
4d08e038 171 temp &= ~APIC_LVT_MASKED;
cb7d6921 172 lapic->lvt_lint1 = temp;
984263bc 173
d9eea1a5 174 /*
d99d4acb 175 * Mask the LAPIC error interrupt, LAPIC performance counter
78ea5a2a 176 * interrupt.
c6a1aabe 177 */
cb7d6921
SZ
178 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
179 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
78ea5a2a 180
d99d4acb
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181 /*
182 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
183 */
cb7d6921 184 timer = lapic->lvt_timer;
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185 timer &= ~APIC_LVTT_VECTOR;
186 timer |= XTIMER_OFFSET;
187 timer |= APIC_LVTT_MASKED;
cb7d6921 188 lapic->lvt_timer = timer;
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189
190 /*
d9eea1a5
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191 * Set the Task Priority Register as needed. At the moment allow
192 * interrupts on all cpus (the APs will remain CLId until they are
1971051d 193 * ready to deal).
d9eea1a5 194 */
cb7d6921 195 temp = lapic->tpr;
984263bc 196 temp &= ~APIC_TPR_PRIO; /* clear priority field */
cb7d6921 197 lapic->tpr = temp;
984263bc 198
97359a5b 199 /*
d99d4acb 200 * Enable the LAPIC
97359a5b 201 */
cb7d6921 202 temp = lapic->svr;
d99d4acb 203 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
97359a5b 204 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 205
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MD
206 /*
207 * Set the spurious interrupt vector. The low 4 bits of the vector
208 * must be 1111.
209 */
210 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 211 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
9d6bf2df
MD
212 temp &= ~APIC_SVR_VECTOR;
213 temp |= XSPURIOUSINT_OFFSET;
984263bc 214
cb7d6921 215 lapic->svr = temp;
984263bc 216
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217 /*
218 * Pump out a few EOIs to clean out interrupts that got through
219 * before we were able to set the TPR.
220 */
cb7d6921
SZ
221 lapic->eoi = 0;
222 lapic->eoi = 0;
223 lapic->eoi = 0;
0b692e79 224
c5b8324c 225 if (bsp) {
b52c8db0 226 lapic_timer_calibrate();
ef612539
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227 if (lapic_timer_enable) {
228 cputimer_intr_register(&lapic_cputimer_intr);
229 cputimer_intr_select(&lapic_cputimer_intr, 0);
230 }
c5b8324c 231 } else {
086575e9 232 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 233 }
b52c8db0 234
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235 if (bootverbose)
236 apic_dump("apic_initialize()");
237}
238
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239static void
240lapic_timer_set_divisor(int divisor_idx)
241{
242 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
cb7d6921 243 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
b52c8db0
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244}
245
246static void
247lapic_timer_oneshot(u_int count)
248{
249 uint32_t value;
250
cb7d6921 251 value = lapic->lvt_timer;
b52c8db0 252 value &= ~APIC_LVTT_PERIODIC;
cb7d6921
SZ
253 lapic->lvt_timer = value;
254 lapic->icr_timer = count;
b52c8db0
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255}
256
257static void
6198c499
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258lapic_timer_oneshot_quick(u_int count)
259{
cb7d6921 260 lapic->icr_timer = count;
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261}
262
263static void
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264lapic_timer_calibrate(void)
265{
47bdf646 266 sysclock_t value;
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267
268 /* Try to calibrate the local APIC timer. */
269 for (lapic_timer_divisor_idx = 0;
270 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
271 lapic_timer_divisor_idx++) {
272 lapic_timer_set_divisor(lapic_timer_divisor_idx);
273 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
274 DELAY(2000000);
cb7d6921 275 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
b52c8db0
SZ
276 if (value != APIC_TIMER_MAX_COUNT)
277 break;
278 }
279 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
280 panic("lapic: no proper timer divisor?!\n");
ef612539 281 lapic_cputimer_intr.freq = value / 2;
b52c8db0 282
47bdf646 283 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 284 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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285}
286
c5b8324c
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287static void
288lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
289{
290 sysclock_t count;
291
292 gd->gd_timer_running = 0;
293
294 count = sys_cputimer->count();
295 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
296 systimer_intr(&count, 0, frame);
297}
298
78ea5a2a
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299void
300lapic_timer_process(void)
301{
ae48d6cd 302 lapic_timer_process_oncpu(mycpu, NULL);
78ea5a2a
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303}
304
305void
306lapic_timer_process_frame(struct intrframe *frame)
307{
ae48d6cd 308 lapic_timer_process_oncpu(mycpu, frame);
b12a1521
SZ
309}
310
c5b8324c 311static void
ef612539 312lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
c5b8324c
SZ
313{
314 struct globaldata *gd = mycpu;
315
ef612539 316 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
c5b8324c
SZ
317 if (reload < 2)
318 reload = 2;
319
320 if (gd->gd_timer_running) {
cb7d6921 321 if (reload < lapic->ccr_timer)
c5b8324c
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322 lapic_timer_oneshot_quick(reload);
323 } else {
324 gd->gd_timer_running = 1;
325 lapic_timer_oneshot_quick(reload);
326 }
327}
328
ef612539
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329static void
330lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
6198c499
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331{
332 uint32_t timer;
333
cb7d6921 334 timer = lapic->lvt_timer;
6198c499 335 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
cb7d6921 336 lapic->lvt_timer = timer;
a9e511df
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337
338 lapic_timer_fixup_handler(NULL);
339}
340
341static void
76c58571 342lapic_timer_fixup_handler(void *arg)
a9e511df 343{
76c58571
SZ
344 int *started = arg;
345
346 if (started != NULL)
347 *started = 0;
348
90e8a35b 349 if (cpu_vendor_id == CPU_VENDOR_AMD) {
a9e511df
SZ
350 /*
351 * Detect the presence of C1E capability mostly on latest
352 * dual-cores (or future) k8 family. This feature renders
353 * the local APIC timer dead, so we disable it by reading
354 * the Interrupt Pending Message register and clearing both
355 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
356 *
357 * Reference:
358 * "BIOS and Kernel Developer's Guide for AMD NPT
359 * Family 0Fh Processors"
360 * #32559 revision 3.00
361 */
362 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
363 (cpu_id & 0x0fff0000) >= 0x00040000) {
364 uint64_t msr;
365
366 msr = rdmsr(0xc0010055);
367 if (msr & 0x18000000) {
368 struct globaldata *gd = mycpu;
369
370 kprintf("cpu%d: AMD C1E detected\n",
371 gd->gd_cpuid);
372 wrmsr(0xc0010055, msr & ~0x18000000ULL);
373
374 /*
375 * We are kinda stalled;
376 * kick start again.
377 */
378 gd->gd_timer_running = 1;
379 lapic_timer_oneshot_quick(2);
76c58571
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380
381 if (started != NULL)
382 *started = 1;
a9e511df
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383 }
384 }
385 }
386}
387
76c58571
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388static void
389lapic_timer_restart_handler(void *dummy __unused)
390{
391 int started;
392
393 lapic_timer_fixup_handler(&started);
394 if (!started) {
395 struct globaldata *gd = mycpu;
396
397 gd->gd_timer_running = 1;
398 lapic_timer_oneshot_quick(2);
399 }
400}
401
a9e511df
SZ
402/*
403 * This function is called only by ACPI-CA code currently:
404 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
405 * module controls PM. So once ACPI-CA is attached, we try
406 * to apply the fixup to prevent LAPIC timer from hanging.
407 */
ef612539
SZ
408static void
409lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 410{
ef612539
SZ
411 lwkt_send_ipiq_mask(smp_active_mask,
412 lapic_timer_fixup_handler, NULL);
6198c499
SZ
413}
414
ef612539
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415static void
416lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 417{
76c58571
SZ
418 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
419}
420
b52c8db0 421
984263bc
MD
422/*
423 * dump contents of local APIC registers
424 */
425void
426apic_dump(char* str)
427{
26be20a0
SW
428 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
429 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
cb7d6921 430 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
984263bc
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431}
432
984263bc
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433/*
434 * Inter Processor Interrupt functions.
435 */
436
984263bc
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437/*
438 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
439 *
440 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
441 * vector is any valid SYSTEM INT vector
442 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
MD
443 *
444 * A backlog of requests can create a deadlock between cpus. To avoid this
445 * we have to be able to accept IPIs at the same time we are trying to send
446 * them. The critical section prevents us from attempting to send additional
447 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
448 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
449 * to occur but fortunately it does not happen too often.
984263bc 450 */
984263bc
MD
451int
452apic_ipi(int dest_type, int vector, int delivery_mode)
453{
454 u_long icr_lo;
455
96728c05 456 crit_enter();
cb7d6921 457 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
458 unsigned int eflags = read_eflags();
459 cpu_enable_intr();
cfaeae2a 460 DEBUG_PUSH_INFO("apic_ipi");
cb7d6921 461 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
462 lwkt_process_ipiq();
463 }
cfaeae2a 464 DEBUG_POP_INFO();
96728c05 465 write_eflags(eflags);
984263bc 466 }
984263bc 467
cb7d6921 468 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 469 delivery_mode | vector;
cb7d6921 470 lapic->icr_lo = icr_lo;
96728c05 471 crit_exit();
984263bc
MD
472 return 0;
473}
474
41a01a4d
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475void
476single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
MD
477{
478 u_long icr_lo;
479 u_long icr_hi;
984263bc 480
41a01a4d 481 crit_enter();
cb7d6921 482 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
483 unsigned int eflags = read_eflags();
484 cpu_enable_intr();
cfaeae2a 485 DEBUG_PUSH_INFO("single_apic_ipi");
cb7d6921 486 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
487 lwkt_process_ipiq();
488 }
cfaeae2a 489 DEBUG_POP_INFO();
96728c05 490 write_eflags(eflags);
984263bc 491 }
cb7d6921 492 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2d901d56 493 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
cb7d6921 494 lapic->icr_hi = icr_hi;
984263bc 495
b2f93ae9 496 /* build ICR_LOW */
cb7d6921 497 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
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MD
498 | APIC_DEST_DESTFLD | delivery_mode | vector;
499
500 /* write APIC ICR */
cb7d6921 501 lapic->icr_lo = icr_lo;
41a01a4d 502 crit_exit();
984263bc
MD
503}
504
41a01a4d
MD
505#if 0
506
507/*
508 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
509 *
510 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
511 * to the target, and the scheduler does not 'poll' for IPI messages.
512 */
513int
514single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
515{
516 u_long icr_lo;
517 u_long icr_hi;
518
519 crit_enter();
cb7d6921 520 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
41a01a4d
MD
521 crit_exit();
522 return(0);
523 }
cb7d6921 524 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2d901d56 525 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
cb7d6921 526 lapic->icr_hi = icr_hi;
41a01a4d
MD
527
528 /* build IRC_LOW */
cb7d6921 529 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
41a01a4d
MD
530 | APIC_DEST_DESTFLD | delivery_mode | vector;
531
532 /* write APIC ICR */
cb7d6921 533 lapic->icr_lo = icr_lo;
41a01a4d
MD
534 crit_exit();
535 return(1);
536}
537
538#endif
539
984263bc
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540/*
541 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
542 *
96728c05
MD
543 * target is a bitmask of destination cpus. Vector is any
544 * valid system INT vector. Delivery mode may be either
545 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 546 */
41a01a4d 547void
da23a592 548selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
984263bc 549{
96728c05
MD
550 crit_enter();
551 while (target) {
da23a592
MD
552 int n = BSFCPUMASK(target);
553 target &= ~CPUMASK(n);
41a01a4d 554 single_apic_ipi(n, vector, delivery_mode);
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555 }
556 crit_exit();
984263bc 557}
984263bc 558
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559/*
560 * Timer code, in development...
561 * - suggested by rgrimes@gndrsh.aac.dev.com
562 */
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563int
564get_apic_timer_frequency(void)
565{
566 return(lapic_cputimer_intr.freq);
567}
984263bc 568
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569/*
570 * Load a 'downcount time' in uSeconds.
571 */
572void
2942ed63 573set_apic_timer(int us)
984263bc 574{
2942ed63 575 u_int count;
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576
577 /*
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578 * When we reach here, lapic timer's frequency
579 * must have been calculated as well as the
580 * divisor (lapic.dcr_timer is setup during the
581 * divisor calculation).
984263bc 582 */
ef612539 583 KKASSERT(lapic_cputimer_intr.freq != 0 &&
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584 lapic_timer_divisor_idx >= 0);
585
ef612539 586 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 587 lapic_timer_oneshot(count);
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588}
589
590
591/*
592 * Read remaining time in timer.
593 */
594int
595read_apic_timer(void)
596{
597#if 0
598 /** XXX FIXME: we need to return the actual remaining time,
599 * for now we just return the remaining count.
600 */
601#else
cb7d6921 602 return lapic->ccr_timer;
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603#endif
604}
605
606
607/*
608 * Spin-style delay, set delay time in uS, spin till it drains.
609 */
610void
611u_sleep(int count)
612{
613 set_apic_timer(count);
614 while (read_apic_timer())
615 /* spin */ ;
616}
ad52b37b 617
11bae9b8 618int
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619lapic_unused_apic_id(int start)
620{
621 int i;
622
623 for (i = start; i < NAPICID; ++i) {
2d901d56 624 if (APICID_TO_CPUID(i) == -1)
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625 return i;
626 }
627 return NAPICID;
628}
629
ad52b37b 630void
84cc808b 631lapic_map(vm_offset_t lapic_addr)
ad52b37b 632{
cb7d6921 633 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
ad52b37b 634
d557216f 635 kprintf("lapic: at %p\n", (void *)lapic_addr);
ad52b37b 636}
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637
638static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
639 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
640
ac032dad 641int
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642lapic_config(void)
643{
644 struct lapic_enumerator *e;
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645 int error, i, ap_max;
646
647 KKASSERT(lapic_enable);
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648
649 for (i = 0; i < NAPICID; ++i)
2d901d56 650 APICID_TO_CPUID(i) = -1;
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651
652 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
653 error = e->lapic_probe(e);
654 if (!error)
655 break;
656 }
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657 if (e == NULL) {
658 kprintf("LAPIC: Can't find LAPIC\n");
659 return ENXIO;
660 }
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661
662 e->lapic_enumerate(e);
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663
664 ap_max = MAXCPU - 1;
665 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
666 if (ap_max > MAXCPU - 1)
667 ap_max = MAXCPU - 1;
668
2abaa030 669 if (naps > ap_max) {
fdab6c5c 670 kprintf("LAPIC: Warning use only %d out of %d "
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671 "available APs\n", ap_max, naps);
672 naps = ap_max;
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673 }
674
ac032dad 675 return 0;
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676}
677
678void
679lapic_enumerator_register(struct lapic_enumerator *ne)
680{
681 struct lapic_enumerator *e;
682
683 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
684 if (e->lapic_prio < ne->lapic_prio) {
685 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
686 return;
687 }
688 }
689 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
690}
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691
692void
693lapic_set_cpuid(int cpu_id, int apic_id)
694{
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695 CPUID_TO_APICID(cpu_id) = apic_id;
696 APICID_TO_CPUID(apic_id) = cpu_id;
41e2c7e0 697}
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698
699void
700lapic_fixup_noioapic(void)
701{
702 u_int temp;
703
704 /* Only allowed on BSP */
705 KKASSERT(mycpuid == 0);
f45bfca0 706 KKASSERT(!ioapic_enable);
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707
708 temp = lapic->lvt_lint0;
709 temp &= ~APIC_LVT_MASKED;
710 lapic->lvt_lint0 = temp;
711
712 temp = lapic->lvt_lint1;
713 temp |= APIC_LVT_MASKED;
714 lapic->lvt_lint1 = temp;
715}