i386: Prepare mp_enable() for multi-stage procedure segmentation
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
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41#include "use_npx.h"
42#include "use_isa.h"
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43#include "opt_atalk.h"
44#include "opt_compat.h"
45#include "opt_cpu.h"
46#include "opt_ddb.h"
47#include "opt_directio.h"
48#include "opt_inet.h"
49#include "opt_ipx.h"
50#include "opt_maxmem.h"
51#include "opt_msgbuf.h"
52#include "opt_perfmon.h"
53#include "opt_swap.h"
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54#include "opt_userconfig.h"
55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/sysproto.h>
59#include <sys/signalvar.h>
60#include <sys/kernel.h>
61#include <sys/linker.h>
62#include <sys/malloc.h>
63#include <sys/proc.h>
895c1f85 64#include <sys/priv.h>
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65#include <sys/buf.h>
66#include <sys/reboot.h>
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67#include <sys/mbuf.h>
68#include <sys/msgbuf.h>
69#include <sys/sysent.h>
70#include <sys/sysctl.h>
71#include <sys/vmmeter.h>
72#include <sys/bus.h>
a722be49 73#include <sys/upcall.h>
cb7f4ab1 74#include <sys/usched.h>
527fddf7 75#include <sys/reg.h>
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76
77#include <vm/vm.h>
78#include <vm/vm_param.h>
79#include <sys/lock.h>
80#include <vm/vm_kern.h>
81#include <vm/vm_object.h>
82#include <vm/vm_page.h>
83#include <vm/vm_map.h>
84#include <vm/vm_pager.h>
85#include <vm/vm_extern.h>
86
4b5f931b 87#include <sys/thread2.h>
684a93c4 88#include <sys/mplock2.h>
4b5f931b 89
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90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
984263bc 96#include <machine/cpu.h>
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97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#include <machine/bootinfo.h>
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100#include <machine/md_var.h>
101#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 102#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 103#include <machine/smp.h>
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104#ifdef PERFMON
105#include <machine/perfmon.h>
106#endif
107#include <machine/cputypes.h>
87cf6827 108#include <machine/intr_machdep.h>
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109
110#ifdef OLD_BUS_ARCH
21ce0dfa 111#include <bus/isa/isa_device.h>
984263bc 112#endif
87cf6827 113#include <machine_base/isa/isa_intr.h>
1f2de5d4 114#include <bus/isa/rtc.h>
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115#include <machine/vm86.h>
116#include <sys/random.h>
117#include <sys/ptrace.h>
118#include <machine/sigframe.h>
119
30c5f287 120#include <sys/machintr.h>
9284cddf 121#include <machine_base/icu/icu_abi.h>
7265a4fe 122#include <machine_base/icu/elcr_var.h>
1d6d7089 123#include <machine_base/apic/lapic.h>
ed4d621d 124#include <machine_base/apic/ioapic.h>
a3dd9120 125#include <machine_base/apic/ioapic_abi.h>
30c5f287 126
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127#define PHYSMAP_ENTRIES 10
128
d678dc17
MN
129extern void init386(int first);
130extern void dblfault_handler(void);
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131
132extern void printcpuinfo(void); /* XXX header file */
133extern void finishidentcpu(void);
134extern void panicifcpuunsupported(void);
135extern void initializecpu(void);
136
d678dc17 137static void cpu_startup(void *);
642a6e88 138#ifndef CPU_DISABLE_SSE
d678dc17
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139static void set_fpregs_xmm(struct save87 *, struct savexmm *);
140static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 141#endif /* CPU_DISABLE_SSE */
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142#ifdef DIRECTIO
143extern void ffs_rawread_setup(void);
144#endif /* DIRECTIO */
8a8d5d85 145static void init_locks(void);
984263bc 146
7c006a9e 147SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
984263bc 148
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149int _udatasel, _ucodesel;
150u_int atdevbase;
c2751817
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151#ifdef SMP
152int64_t tsc_offsets[MAXCPU];
153#else
154int64_t tsc_offsets[1];
155#endif
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156
157#if defined(SWTCH_OPTIM_STATS)
158extern int swtch_optim_stats;
159SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
160 CTLFLAG_RD, &swtch_optim_stats, 0, "");
161SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
162 CTLFLAG_RD, &tlb_flush_count, 0, "");
163#endif
164
39d69dae 165long physmem = 0;
984263bc 166
1876681a
SZ
167u_long ebda_addr = 0;
168
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169int imcr_present = 0;
170
2abaa030
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171int naps = 0; /* # of Applications processors */
172
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173u_int base_memory;
174
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175static int
176sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
177{
39d69dae
AH
178 u_long pmem = ctob(physmem);
179
180 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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181 return (error);
182}
183
39d69dae 184SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 185 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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186
187static int
188sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
189{
190 int error = sysctl_handle_int(oidp, 0,
12e4aaff 191 ctob(physmem - vmstats.v_wire_count), req);
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192 return (error);
193}
194
195SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
196 0, 0, sysctl_hw_usermem, "IU", "");
197
198static int
199sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
200{
201 int error = sysctl_handle_int(oidp, 0,
202 i386_btop(avail_end - avail_start), req);
203 return (error);
204}
205
206SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
207 0, 0, sysctl_hw_availpages, "I", "");
208
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209vm_paddr_t Maxmem;
210vm_paddr_t Realmem;
984263bc 211
ff1a75a1 212vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH
213vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
214
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215
216static vm_offset_t buffer_sva, buffer_eva;
217vm_offset_t clean_sva, clean_eva;
218static vm_offset_t pager_sva, pager_eva;
219static struct trapframe proc0_tf;
220
221static void
f123d5a1 222cpu_startup(void *dummy)
984263bc 223{
c9faf524 224 caddr_t v;
984263bc 225 vm_size_t size = 0;
e4846942 226 vm_offset_t firstaddr;
984263bc 227
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228 /*
229 * Good {morning,afternoon,evening,night}.
230 */
26be20a0 231 kprintf("%s", version);
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232 startrtclock();
233 printcpuinfo();
234 panicifcpuunsupported();
235#ifdef PERFMON
236 perfmon_init();
237#endif
15dc6550 238 kprintf("real memory = %ju (%ju MB)\n",
1bda0d3d
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239 (intmax_t)Realmem,
240 (intmax_t)Realmem / 1024 / 1024);
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241 /*
242 * Display any holes after the first chunk of extended memory.
243 */
244 if (bootverbose) {
245 int indx;
246
26be20a0 247 kprintf("Physical memory chunk(s):\n");
984263bc 248 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 249 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 250
26be20a0 251 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
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252 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
253 size1 / PAGE_SIZE);
254 }
255 }
256
257 /*
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258 * Allocate space for system data structures.
259 * The first available kernel virtual address is in "v".
260 * As pages of kernel virtual memory are allocated, "v" is incremented.
261 * As pages of memory are allocated and cleared,
262 * "firstaddr" is incremented.
263 * An index into the kernel page table corresponding to the
264 * virtual memory address maintained in "v" is kept in "mapaddr".
265 */
266
267 /*
268 * Make two passes. The first pass calculates how much memory is
269 * needed and allocates it. The second pass assigns virtual
270 * addresses to the various data structures.
271 */
272 firstaddr = 0;
273again:
274 v = (caddr_t)firstaddr;
275
276#define valloc(name, type, num) \
277 (name) = (type *)v; v = (caddr_t)((name)+(num))
278#define valloclim(name, type, num, lim) \
279 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
280
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281 /*
282 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
283 * For the first 64MB of ram nominally allocate sufficient buffers to
284 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
285 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
286 * the buffer cache we limit the eventual kva reservation to
287 * maxbcache bytes.
288 *
289 * factor represents the 1/4 x ram conversion.
290 */
291 if (nbuf == 0) {
292 int factor = 4 * BKVASIZE / 1024;
293 int kbytes = physmem * (PAGE_SIZE / 1024);
294
295 nbuf = 50;
296 if (kbytes > 4096)
297 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
298 if (kbytes > 65536)
299 nbuf += (kbytes - 65536) * 2 / (factor * 5);
300 if (maxbcache && nbuf > maxbcache / BKVASIZE)
301 nbuf = maxbcache / BKVASIZE;
302 }
303
304 /*
305 * Do not allow the buffer_map to be more then 1/2 the size of the
306 * kernel_map.
307 */
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308 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
309 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
26be20a0 310 kprintf("Warning: nbufs capped at %d\n", nbuf);
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311 }
312
948209ce
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313 /* limit to 128 on i386 */
314 nswbuf = max(min(nbuf/4, 128), 16);
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315#ifdef NSWBUF_MIN
316 if (nswbuf < NSWBUF_MIN)
317 nswbuf = NSWBUF_MIN;
318#endif
319#ifdef DIRECTIO
320 ffs_rawread_setup();
321#endif
322
323 valloc(swbuf, struct buf, nswbuf);
324 valloc(buf, struct buf, nbuf);
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325
326 /*
327 * End of first pass, size has been calculated so allocate memory
328 */
329 if (firstaddr == 0) {
330 size = (vm_size_t)(v - firstaddr);
e4846942 331 firstaddr = kmem_alloc(&kernel_map, round_page(size));
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332 if (firstaddr == 0)
333 panic("startup: no room for tables");
334 goto again;
335 }
336
337 /*
338 * End of second pass, addresses have been assigned
339 */
340 if ((vm_size_t)(v - firstaddr) != size)
341 panic("startup: table size inconsistency");
342
e4846942
MD
343 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
344 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
345 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
346 (nbuf*BKVASIZE));
347 buffer_map.system_map = 1;
348 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
349 (nswbuf*MAXPHYS) + pager_map_size);
350 pager_map.system_map = 1;
984263bc 351
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352#if defined(USERCONFIG)
353 userconfig();
354 cninit(); /* the preferred console may have changed */
355#endif
356
15dc6550 357 kprintf("avail memory = %ju (%ju MB)\n",
f9ab53b8 358 (intmax_t)ptoa(vmstats.v_free_count),
15dc6550 359 (intmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
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360
361 /*
362 * Set up buffers, so they can be used to read disk labels.
363 */
364 bufinit();
365 vm_pager_bufferinit();
366
e24dd6e0
SZ
367 /* Log ELCR information */
368 elcr_dump();
369
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370#ifdef SMP
371 /*
372 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
373 */
374 mp_start(); /* fire up the APs and APICs */
375 mp_announce();
376#endif /* SMP */
be1519b3
SZ
377
378 /* Finalize PIC */
379 MachIntrABI.finalize();
380
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381 cpu_setregs();
382}
383
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384/*
385 * Send an interrupt to process.
386 *
387 * Stack is set up to allow sigcode stored
388 * at top to call routine, followed by kcall
389 * to sigreturn routine below. After sigreturn
390 * resets the signal mask, the stack, and the
391 * frame pointer, it returns to the user
392 * specified pc, psl.
393 */
984263bc 394void
f123d5a1 395sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 396{
065b709a
SS
397 struct lwp *lp = curthread->td_lwp;
398 struct proc *p = lp->lwp_proc;
984263bc
MD
399 struct trapframe *regs;
400 struct sigacts *psp = p->p_sigacts;
401 struct sigframe sf, *sfp;
402 int oonstack;
403
065b709a
SS
404 regs = lp->lwp_md.md_regs;
405 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
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406
407 /* save user context */
408 bzero(&sf, sizeof(struct sigframe));
409 sf.sf_uc.uc_sigmask = *mask;
065b709a 410 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 411 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 412 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 413
ce3d8c4d
MD
414 /* make the size of the saved context visible to userland */
415 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
416
4b486183
MD
417 /* save mailbox pending state for syscall interlock semantics */
418 if (p->p_flag & P_MAILBOX)
419 sf.sf_uc.uc_mcontext.mc_xflags |= PGEX_MAILBOX;
420
984263bc 421 /* Allocate and validate space for the signal handler context. */
08f2f1bb 422 if ((lp->lwp_flag & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 423 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS
424 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
425 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
426 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 427 } else {
984263bc 428 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 429 }
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MD
430
431 /* Translate the signal is appropriate */
432 if (p->p_sysent->sv_sigtbl) {
433 if (sig <= p->p_sysent->sv_sigsize)
434 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
435 }
436
437 /* Build the argument list for the signal handler. */
438 sf.sf_signum = sig;
439 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 440 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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MD
441 /* Signal handler installed with SA_SIGINFO. */
442 sf.sf_siginfo = (register_t)&sfp->sf_si;
443 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
444
445 /* fill siginfo structure */
446 sf.sf_si.si_signo = sig;
447 sf.sf_si.si_code = code;
448 sf.sf_si.si_addr = (void*)regs->tf_err;
449 }
450 else {
451 /* Old FreeBSD-style arguments. */
452 sf.sf_siginfo = code;
453 sf.sf_addr = regs->tf_err;
454 sf.sf_ahu.sf_handler = catcher;
455 }
456
457 /*
458 * If we're a vm86 process, we want to save the segment registers.
459 * We also change eflags to be our emulated eflags, not the actual
460 * eflags.
461 */
462 if (regs->tf_eflags & PSL_VM) {
463 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 464 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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465
466 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
467 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
468 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
469 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
470
471 if (vm86->vm86_has_vme == 0)
472 sf.sf_uc.uc_mcontext.mc_eflags =
473 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
474 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
475
476 /*
477 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
478 * syscalls made by the signal handler. This just avoids
479 * wasting time for our lazy fixup of such faults. PSL_NT
480 * does nothing in vm86 mode, but vm86 programs can set it
481 * almost legitimately in probes for old cpu types.
482 */
483 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
484 }
485
486 /*
1b251f0a
MD
487 * Save the FPU state and reinit the FP unit
488 */
489 npxpush(&sf.sf_uc.uc_mcontext);
490
491 /*
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492 * Copy the sigframe out to the user's stack.
493 */
494 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
495 /*
496 * Something is wrong with the stack pointer.
497 * ...Kill the process.
498 */
b276424c 499 sigexit(lp, SIGILL);
984263bc
MD
500 }
501
502 regs->tf_esp = (int)sfp;
503 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE
504
505 /*
506 * i386 abi specifies that the direction flag must be cleared
507 * on function entry
508 */
509 regs->tf_eflags &= ~(PSL_T|PSL_D);
510
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511 regs->tf_cs = _ucodesel;
512 regs->tf_ds = _udatasel;
513 regs->tf_es = _udatasel;
dd4ad62d
MD
514
515 /*
516 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD
517 * the userland program might be using both.
518 *
519 * However, if a T_PROTFLT occured the segment registers could be
520 * totally broken. They must be reset in order to be able to
521 * return to userland.
dd4ad62d 522 */
4e7c41c5
MD
523 if (regs->tf_trapno == T_PROTFLT) {
524 regs->tf_fs = _udatasel;
525 regs->tf_gs = _udatasel;
526 }
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MD
527 regs->tf_ss = _udatasel;
528}
529
530/*
4a22e893 531 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD
532 * VM context. Remove any items that would otherwise create a privilage
533 * issue.
4a22e893 534 *
4e7c41c5
MD
535 * XXX at the moment we allow userland to set the resume flag. Is this a
536 * bad idea?
4a22e893
MD
537 */
538int
539cpu_sanitize_frame(struct trapframe *frame)
540{
541 frame->tf_cs = _ucodesel;
542 frame->tf_ds = _udatasel;
4e7c41c5
MD
543 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
544#if 0
4a22e893 545 frame->tf_fs = _udatasel;
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MD
546 frame->tf_gs = _udatasel;
547#endif
4a22e893 548 frame->tf_ss = _udatasel;
4e7c41c5 549 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD
550 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
551 return(0);
552}
553
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MD
554int
555cpu_sanitize_tls(struct savetls *tls)
556{
557 struct segment_descriptor *desc;
558 int i;
559
560 for (i = 0; i < NGTLS; ++i) {
561 desc = &tls->tls[i];
562 if (desc->sd_dpl == 0 && desc->sd_type == 0)
563 continue;
564 if (desc->sd_def32 == 0)
565 return(ENXIO);
566 if (desc->sd_type != SDT_MEMRWA)
567 return(ENXIO);
568 if (desc->sd_dpl != SEL_UPL)
569 return(ENXIO);
570 if (desc->sd_xx != 0 || desc->sd_p != 1)
571 return(ENXIO);
572 }
573 return(0);
574}
575
4a22e893 576/*
65957d54 577 * sigreturn(ucontext_t *sigcntxp)
41c20dac 578 *
984263bc
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579 * System call to cleanup state after a signal
580 * has been taken. Reset signal mask and
581 * stack state from context left by sendsig (above).
582 * Return to previous pc and psl as specified by
583 * context left by sendsig. Check carefully to
584 * make sure that the user has not modified the
585 * state to gain improper privileges.
3919ced0
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586 *
587 * MPSAFE
984263bc
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588 */
589#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
590#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
591
592int
753fd850 593sys_sigreturn(struct sigreturn_args *uap)
984263bc 594{
065b709a 595 struct lwp *lp = curthread->td_lwp;
4b486183 596 struct proc *p = lp->lwp_proc;
984263bc 597 struct trapframe *regs;
1b251f0a 598 ucontext_t uc;
984263bc 599 ucontext_t *ucp;
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MD
600 int cs;
601 int eflags;
602 int error;
984263bc 603
1b251f0a
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604 /*
605 * We have to copy the information into kernel space so userland
606 * can't modify it while we are sniffing it.
607 */
065b709a 608 regs = lp->lwp_md.md_regs;
1b251f0a
MD
609 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
610 if (error)
611 return (error);
612 ucp = &uc;
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613 eflags = ucp->uc_mcontext.mc_eflags;
614
615 if (eflags & PSL_VM) {
616 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
617 struct vm86_kernel *vm86;
618
619 /*
620 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
621 * set up the vm86 area, and we can't enter vm86 mode.
622 */
065b709a 623 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 624 return (EINVAL);
065b709a 625 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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MD
626 if (vm86->vm86_inited == 0)
627 return (EINVAL);
628
629 /* go back to user mode if both flags are set */
630 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 631 trapsignal(lp, SIGBUS, 0);
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MD
632
633 if (vm86->vm86_has_vme) {
634 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
635 (eflags & VME_USERCHANGE) | PSL_VM;
636 } else {
637 vm86->vm86_eflags = eflags; /* save VIF, VIP */
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MD
638 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
639 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 640 }
4e7c41c5 641 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
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MD
642 tf->tf_eflags = eflags;
643 tf->tf_vm86_ds = tf->tf_ds;
644 tf->tf_vm86_es = tf->tf_es;
645 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 646 tf->tf_vm86_gs = tf->tf_gs;
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647 tf->tf_ds = _udatasel;
648 tf->tf_es = _udatasel;
4e7c41c5 649#if 0
984263bc 650 tf->tf_fs = _udatasel;
4e7c41c5
MD
651 tf->tf_gs = _udatasel;
652#endif
984263bc
MD
653 } else {
654 /*
655 * Don't allow users to change privileged or reserved flags.
656 */
657 /*
658 * XXX do allow users to change the privileged flag PSL_RF.
659 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
660 * should sometimes set it there too. tf_eflags is kept in
661 * the signal context during signal handling and there is no
662 * other place to remember it, so the PSL_RF bit may be
663 * corrupted by the signal handler without us knowing.
664 * Corruption of the PSL_RF bit at worst causes one more or
665 * one less debugger trap, so allowing it is fairly harmless.
666 */
667 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 668 kprintf("sigreturn: eflags = 0x%x\n", eflags);
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669 return(EINVAL);
670 }
671
672 /*
673 * Don't allow users to load a valid privileged %cs. Let the
674 * hardware check for invalid selectors, excess privilege in
675 * other selectors, invalid %eip's and invalid %esp's.
676 */
677 cs = ucp->uc_mcontext.mc_cs;
678 if (!CS_SECURE(cs)) {
26be20a0 679 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 680 trapsignal(lp, SIGBUS, T_PROTFLT);
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MD
681 return(EINVAL);
682 }
4e7c41c5 683 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
984263bc
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684 }
685
4b486183 686 /*
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687 * Restore the FPU state from the frame
688 */
3919ced0 689 crit_enter();
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690 npxpop(&ucp->uc_mcontext);
691
692 /*
4b486183
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693 * Merge saved signal mailbox pending flag to maintain interlock
694 * semantics against system calls.
695 */
696 if (ucp->uc_mcontext.mc_xflags & PGEX_MAILBOX)
697 p->p_flag |= P_MAILBOX;
698
984263bc 699 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 700 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 701 else
065b709a 702 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 703
065b709a
SS
704 lp->lwp_sigmask = ucp->uc_sigmask;
705 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 706 crit_exit();
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707 return(EJUSTRETURN);
708}
709
710/*
a722be49
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711 * Stack frame on entry to function. %eax will contain the function vector,
712 * %ecx will contain the function data. flags, ecx, and eax will have
713 * already been pushed on the stack.
714 */
715struct upc_frame {
716 register_t eax;
717 register_t ecx;
0a455ac5 718 register_t edx;
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719 register_t flags;
720 register_t oldip;
721};
722
723void
724sendupcall(struct vmupcall *vu, int morepending)
725{
065b709a 726 struct lwp *lp = curthread->td_lwp;
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727 struct trapframe *regs;
728 struct upcall upcall;
729 struct upc_frame upc_frame;
6e58b5df 730 int crit_count = 0;
a722be49
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731
732 /*
69c61fbe
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733 * If we are a virtual kernel running an emulated user process
734 * context, switch back to the virtual kernel context before
735 * trying to post the signal.
736 */
39005e16 737 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
69c61fbe 738 lp->lwp_md.md_regs->tf_trapno = 0;
287ebb09 739 vkernel_trap(lp, lp->lwp_md.md_regs);
69c61fbe
MD
740 }
741
742 /*
a722be49
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743 * Get the upcall data structure
744 */
065b709a 745 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
6e58b5df
MD
746 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
747 ) {
a722be49 748 vu->vu_pending = 0;
26be20a0 749 kprintf("bad upcall address\n");
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MD
750 return;
751 }
752
753 /*
754 * If the data structure is already marked pending or has a critical
755 * section count, mark the data structure as pending and return
756 * without doing an upcall. vu_pending is left set.
757 */
6e58b5df
MD
758 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
759 if (upcall.upc_pending < vu->vu_pending) {
760 upcall.upc_pending = vu->vu_pending;
065b709a 761 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 762 sizeof(upcall.upc_pending));
a722be49
MD
763 }
764 return;
765 }
766
767 /*
768 * We can run this upcall now, clear vu_pending.
769 *
770 * Bump our critical section count and set or clear the
771 * user pending flag depending on whether more upcalls are
772 * pending. The user will be responsible for calling
773 * upc_dispatch(-1) to process remaining upcalls.
774 */
775 vu->vu_pending = 0;
6e58b5df 776 upcall.upc_pending = morepending;
f9235b6d 777 ++crit_count;
065b709a 778 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df
MD
779 sizeof(upcall.upc_pending));
780 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
781 sizeof(int));
a722be49
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782
783 /*
784 * Construct a stack frame and issue the upcall
785 */
065b709a 786 regs = lp->lwp_md.md_regs;
a722be49
MD
787 upc_frame.eax = regs->tf_eax;
788 upc_frame.ecx = regs->tf_ecx;
0a455ac5 789 upc_frame.edx = regs->tf_edx;
a722be49
MD
790 upc_frame.flags = regs->tf_eflags;
791 upc_frame.oldip = regs->tf_eip;
792 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
793 sizeof(upc_frame)) != 0) {
26be20a0 794 kprintf("bad stack on upcall\n");
a722be49
MD
795 } else {
796 regs->tf_eax = (register_t)vu->vu_func;
797 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 798 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
799 regs->tf_eip = (register_t)vu->vu_ctx;
800 regs->tf_esp -= sizeof(upc_frame);
801 }
802}
803
804/*
805 * fetchupcall occurs in the context of a system call, which means that
0a455ac5
MD
806 * we have to return EJUSTRETURN in order to prevent eax and edx from
807 * being overwritten by the syscall return value.
a722be49
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808 *
809 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
810 * and the function pointer in %eax.
811 */
812int
d678dc17 813fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
a722be49
MD
814{
815 struct upc_frame upc_frame;
065b709a 816 struct lwp *lp = curthread->td_lwp;
a722be49
MD
817 struct trapframe *regs;
818 int error;
6e58b5df
MD
819 struct upcall upcall;
820 int crit_count;
a722be49 821
065b709a 822 regs = lp->lwp_md.md_regs;
a722be49 823
065b709a 824 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
a722be49
MD
825 if (error == 0) {
826 if (vu) {
827 /*
828 * This jumps us to the next ready context.
829 */
830 vu->vu_pending = 0;
065b709a 831 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
6e58b5df
MD
832 crit_count = 0;
833 if (error == 0)
834 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 835 ++crit_count;
a722be49 836 if (error == 0)
6e58b5df 837 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
a722be49
MD
838 regs->tf_eax = (register_t)vu->vu_func;
839 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 840 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD
841 regs->tf_eip = (register_t)vu->vu_ctx;
842 regs->tf_esp = (register_t)rsp;
843 } else {
844 /*
845 * This returns us to the originally interrupted code.
846 */
847 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
848 regs->tf_eax = upc_frame.eax;
849 regs->tf_ecx = upc_frame.ecx;
0a455ac5 850 regs->tf_edx = upc_frame.edx;
6e58b5df
MD
851 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
852 (upc_frame.flags & PSL_USERCHANGE);
a722be49
MD
853 regs->tf_eip = upc_frame.oldip;
854 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
855 }
856 }
857 if (error == 0)
858 error = EJUSTRETURN;
859 return(error);
860}
861
862/*
984263bc
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863 * Machine dependent boot() routine
864 *
865 * I haven't seen anything to put here yet
866 * Possibly some stuff might be grafted back here from boot()
867 */
868void
869cpu_boot(int howto)
870{
871}
872
873/*
874 * Shutdown the CPU as much as possible
875 */
876void
877cpu_halt(void)
878{
879 for (;;)
1184892f 880 __asm__ __volatile("hlt");
984263bc
MD
881}
882
883/*
8ad65e08
MD
884 * cpu_idle() represents the idle LWKT. You cannot return from this function
885 * (unless you want to blow things up!). Instead we look for runnable threads
886 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 887 *
26a0694b 888 * The main loop is entered with a critical section held, we must release
a2a5ad0d
MD
889 * the critical section before doing anything else. lwkt_switch() will
890 * check for pending interrupts due to entering and exiting its own
891 * critical section.
26a0694b 892 *
7d4d6fdb
MD
893 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
894 * However, there are cases where the idlethread will be entered with
895 * the possibility that no IPI will occur and in such cases
cbdd23b1
MD
896 * lwkt_switch() sets RQF_WAKEUP. We usually check
897 * RQF_IDLECHECK_WK_MASK.
7d4d6fdb 898 *
46e562ce
MD
899 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
900 * 1 to just use hlt and for debugging purposes.
984263bc 901 */
46e562ce 902static int cpu_idle_hlt = 2;
60f945af
MD
903static int cpu_idle_hltcnt;
904static int cpu_idle_spincnt;
be71787b 905static u_int cpu_idle_repeat = 4;
984263bc
MD
906SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
907 &cpu_idle_hlt, 0, "Idle loop HLT enable");
60f945af
MD
908SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
909 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
910SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
911 &cpu_idle_spincnt, 0, "Idle loop entry spins");
be71787b
MD
912SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
913 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
984263bc 914
f9d8cd12
MD
915static void
916cpu_idle_default_hook(void)
917{
918 /*
919 * We must guarentee that hlt is exactly the instruction
920 * following the sti.
921 */
922 __asm __volatile("sti; hlt");
923}
924
925/* Other subsystems (e.g., ACPI) can hook this later. */
926void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
927
984263bc
MD
928void
929cpu_idle(void)
930{
be71787b 931 globaldata_t gd = mycpu;
10662728 932 struct thread *td __debugvar = gd->gd_curthread;
be71787b
MD
933 int reqflags;
934 int quick;
a2a5ad0d 935
26a0694b 936 crit_exit();
f9235b6d 937 KKASSERT(td->td_critcount == 0);
8ad65e08 938 for (;;) {
a2a5ad0d
MD
939 /*
940 * See if there are any LWKTs ready to go.
941 */
8ad65e08 942 lwkt_switch();
a2a5ad0d
MD
943
944 /*
be71787b
MD
945 * When halting inside a cli we must check for reqflags
946 * races, particularly [re]schedule requests. Running
947 * splz() does the job.
948 *
949 * cpu_idle_hlt:
950 * 0 Never halt, just spin
951 *
952 * 1 Always use HLT (or MONITOR/MWAIT if avail).
953 * This typically eats more power than the
954 * ACPI halt.
955 *
956 * 2 Use HLT/MONITOR/MWAIT up to a point and then
957 * use the ACPI halt (default). This is a hybrid
958 * approach. See machdep.cpu_idle_repeat.
959 *
960 * 3 Always use the ACPI halt. This typically
961 * eats the least amount of power but the cpu
962 * will be slow waking up. Slows down e.g.
963 * compiles and other pipe/event oriented stuff.
964 *
965 *
966 * NOTE: Interrupts are enabled and we are not in a critical
967 * section.
968 *
969 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
970 * don't bother capping gd_idle_repeat, it is ok if
971 * it overflows.
a2a5ad0d 972 */
be71787b
MD
973 ++gd->gd_idle_repeat;
974 reqflags = gd->gd_reqflags;
975 quick = (cpu_idle_hlt == 1) ||
976 (cpu_idle_hlt < 3 &&
977 gd->gd_idle_repeat < cpu_idle_repeat);
978
979 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
980 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
981 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
982 ++cpu_idle_hltcnt;
983 } else if (cpu_idle_hlt) {
a2a5ad0d
MD
984 __asm __volatile("cli");
985 splz();
be71787b
MD
986 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
987 if (quick)
7d4d6fdb
MD
988 cpu_idle_default_hook();
989 else
990 cpu_idle_hook();
991 }
7d4d6fdb 992 __asm __volatile("sti");
60f945af 993 ++cpu_idle_hltcnt;
8ad65e08 994 } else {
60f945af 995 splz();
c5724852 996 __asm __volatile("sti");
60f945af 997 ++cpu_idle_spincnt;
8ad65e08 998 }
984263bc
MD
999 }
1000}
1001
7ad8cc6c
SW
1002#ifdef SMP
1003
984263bc 1004/*
06615ccb
MD
1005 * This routine is called if a spinlock has been held through the
1006 * exponential backoff period and is seriously contested. On a real cpu
1007 * we let it spin.
1008 */
1009void
1010cpu_spinlock_contested(void)
1011{
1012 cpu_pause();
1013}
1014
7ad8cc6c
SW
1015#endif
1016
06615ccb 1017/*
984263bc
MD
1018 * Clear registers on exec
1019 */
1020void
08f2f1bb 1021exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 1022{
08f2f1bb
SS
1023 struct thread *td = curthread;
1024 struct lwp *lp = td->td_lwp;
1025 struct pcb *pcb = td->td_pcb;
bb3cd951 1026 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 1027
984263bc
MD
1028 /* was i386_user_cleanup() in NetBSD */
1029 user_ldt_free(pcb);
984263bc
MD
1030
1031 bzero((char *)regs, sizeof(struct trapframe));
1032 regs->tf_eip = entry;
1033 regs->tf_esp = stack;
1034 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1035 regs->tf_ss = _udatasel;
1036 regs->tf_ds = _udatasel;
1037 regs->tf_es = _udatasel;
1038 regs->tf_fs = _udatasel;
4e7c41c5 1039 regs->tf_gs = _udatasel;
984263bc
MD
1040 regs->tf_cs = _ucodesel;
1041
1042 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1043 regs->tf_ebx = ps_strings;
1044
1045 /*
1046 * Reset the hardware debug registers if they were in use.
1047 * They won't have any meaning for the newly exec'd process.
1048 */
1049 if (pcb->pcb_flags & PCB_DBREGS) {
1050 pcb->pcb_dr0 = 0;
1051 pcb->pcb_dr1 = 0;
1052 pcb->pcb_dr2 = 0;
1053 pcb->pcb_dr3 = 0;
1054 pcb->pcb_dr6 = 0;
1055 pcb->pcb_dr7 = 0;
08f2f1bb 1056 if (pcb == td->td_pcb) {
984263bc
MD
1057 /*
1058 * Clear the debug registers on the running
1059 * CPU, otherwise they will end up affecting
1060 * the next process we switch to.
1061 */
1062 reset_dbregs();
1063 }
1064 pcb->pcb_flags &= ~PCB_DBREGS;
1065 }
1066
1067 /*
1068 * Initialize the math emulator (if any) for the current process.
1069 * Actually, just clear the bit that says that the emulator has
1070 * been initialized. Initialization is delayed until the process
1071 * traps to the emulator (if it is done at all) mainly because
1072 * emulators don't provide an entry point for initialization.
1073 */
08f2f1bb 1074 pcb->pcb_flags &= ~FP_SOFTFP;
984263bc
MD
1075
1076 /*
a02705a9
MD
1077 * note: do not set CR0_TS here. npxinit() must do it after clearing
1078 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
1079 * in npxdna().
984263bc 1080 */
a02705a9
MD
1081 crit_enter();
1082 load_cr0(rcr0() | CR0_MP);
984263bc
MD
1083
1084#if NNPX > 0
1085 /* Initialize the npx (if any) for the current process. */
1086 npxinit(__INITIAL_NPXCW__);
1087#endif
a02705a9 1088 crit_exit();
984263bc 1089
90b9818c
MD
1090 /*
1091 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
MD
1092 * handled in execve simply by setting the 64 bit syscall
1093 * return value to 0.
90b9818c 1094 */
984263bc
MD
1095}
1096
1097void
1098cpu_setregs(void)
1099{
1100 unsigned int cr0;
1101
1102 cr0 = rcr0();
1103 cr0 |= CR0_NE; /* Done by npxinit() */
1104 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 1105 cr0 |= CR0_WP | CR0_AM;
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MD
1106 load_cr0(cr0);
1107 load_gs(_udatasel);
1108}
1109
1110static int
1111sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1112{
1113 int error;
1114 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1115 req);
1116 if (!error && req->newptr)
1117 resettodr();
1118 return (error);
1119}
1120
1121SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1122 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1123
1124SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1125 CTLFLAG_RW, &disable_rtc_set, 0, "");
1126
1127SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1128 CTLFLAG_RD, &bootinfo, bootinfo, "");
1129
1130SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1131 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1132
b13267a5 1133extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 1134SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 1135 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
984263bc
MD
1136
1137/*
1138 * Initialize 386 and configure to run kernel
1139 */
1140
1141/*
1142 * Initialize segments & interrupt table
1143 */
1144
1145int _default_ldt;
1146union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1147static struct gate_descriptor idt0[NIDT];
1148struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1149union descriptor ldt[NLDT]; /* local descriptor table */
17a9f566
MD
1150
1151/* table descriptors - used to load tables by cpu */
984263bc 1152struct region_descriptor r_gdt, r_idt;
984263bc 1153
984263bc
MD
1154#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1155extern int has_f00f_bug;
1156#endif
1157
1158static struct i386tss dblfault_tss;
1159static char dblfault_stack[PAGE_SIZE];
1160
1161extern struct user *proc0paddr;
1162
1163
1164/* software prototypes -- in more palatable form */
1165struct soft_segment_descriptor gdt_segs[] = {
1166/* GNULL_SEL 0 Null Descriptor */
1167{ 0x0, /* segment base address */
1168 0x0, /* length */
1169 0, /* segment type */
1170 0, /* segment descriptor priority level */
1171 0, /* segment descriptor present */
1172 0, 0,
1173 0, /* default 32 vs 16 bit size */
1174 0 /* limit granularity (byte/page units)*/ },
1175/* GCODE_SEL 1 Code Descriptor for kernel */
1176{ 0x0, /* segment base address */
1177 0xfffff, /* length - all address space */
1178 SDT_MEMERA, /* segment type */
1179 0, /* segment descriptor priority level */
1180 1, /* segment descriptor present */
1181 0, 0,
1182 1, /* default 32 vs 16 bit size */
1183 1 /* limit granularity (byte/page units)*/ },
1184/* GDATA_SEL 2 Data Descriptor for kernel */
1185{ 0x0, /* segment base address */
1186 0xfffff, /* length - all address space */
1187 SDT_MEMRWA, /* segment type */
1188 0, /* segment descriptor priority level */
1189 1, /* segment descriptor present */
1190 0, 0,
1191 1, /* default 32 vs 16 bit size */
1192 1 /* limit granularity (byte/page units)*/ },
1193/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1194{ 0x0, /* segment base address */
1195 0xfffff, /* length - all address space */
1196 SDT_MEMRWA, /* segment type */
1197 0, /* segment descriptor priority level */
1198 1, /* segment descriptor present */
1199 0, 0,
1200 1, /* default 32 vs 16 bit size */
1201 1 /* limit granularity (byte/page units)*/ },
1202/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1203{
1204 0x0, /* segment base address */
1205 sizeof(struct i386tss)-1,/* length - all address space */
1206 SDT_SYS386TSS, /* segment type */
1207 0, /* segment descriptor priority level */
1208 1, /* segment descriptor present */
1209 0, 0,
1210 0, /* unused - default 32 vs 16 bit size */
1211 0 /* limit granularity (byte/page units)*/ },
1212/* GLDT_SEL 5 LDT Descriptor */
1213{ (int) ldt, /* segment base address */
1214 sizeof(ldt)-1, /* length - all address space */
1215 SDT_SYSLDT, /* segment type */
1216 SEL_UPL, /* segment descriptor priority level */
1217 1, /* segment descriptor present */
1218 0, 0,
1219 0, /* unused - default 32 vs 16 bit size */
1220 0 /* limit granularity (byte/page units)*/ },
1221/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1222{ (int) ldt, /* segment base address */
1223 (512 * sizeof(union descriptor)-1), /* length */
1224 SDT_SYSLDT, /* segment type */
1225 0, /* segment descriptor priority level */
1226 1, /* segment descriptor present */
1227 0, 0,
1228 0, /* unused - default 32 vs 16 bit size */
1229 0 /* limit granularity (byte/page units)*/ },
1230/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1231{ 0x0, /* segment base address */
1232 0x0, /* length - all address space */
1233 0, /* segment type */
1234 0, /* segment descriptor priority level */
1235 0, /* segment descriptor present */
1236 0, 0,
1237 0, /* default 32 vs 16 bit size */
1238 0 /* limit granularity (byte/page units)*/ },
1239/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1240{ 0x400, /* segment base address */
1241 0xfffff, /* length */
1242 SDT_MEMRWA, /* segment type */
1243 0, /* segment descriptor priority level */
1244 1, /* segment descriptor present */
1245 0, 0,
1246 1, /* default 32 vs 16 bit size */
1247 1 /* limit granularity (byte/page units)*/ },
1248/* GPANIC_SEL 9 Panic Tss Descriptor */
1249{ (int) &dblfault_tss, /* segment base address */
1250 sizeof(struct i386tss)-1,/* length - all address space */
1251 SDT_SYS386TSS, /* segment type */
1252 0, /* segment descriptor priority level */
1253 1, /* segment descriptor present */
1254 0, 0,
1255 0, /* unused - default 32 vs 16 bit size */
1256 0 /* limit granularity (byte/page units)*/ },
1257/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1258{ 0, /* segment base address (overwritten) */
1259 0xfffff, /* length */
1260 SDT_MEMERA, /* segment type */
1261 0, /* segment descriptor priority level */
1262 1, /* segment descriptor present */
1263 0, 0,
1264 0, /* default 32 vs 16 bit size */
1265 1 /* limit granularity (byte/page units)*/ },
1266/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1267{ 0, /* segment base address (overwritten) */
1268 0xfffff, /* length */
1269 SDT_MEMERA, /* segment type */
1270 0, /* segment descriptor priority level */
1271 1, /* segment descriptor present */
1272 0, 0,
1273 0, /* default 32 vs 16 bit size */
1274 1 /* limit granularity (byte/page units)*/ },
1275/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1276{ 0, /* segment base address (overwritten) */
1277 0xfffff, /* length */
1278 SDT_MEMRWA, /* segment type */
1279 0, /* segment descriptor priority level */
1280 1, /* segment descriptor present */
1281 0, 0,
1282 1, /* default 32 vs 16 bit size */
1283 1 /* limit granularity (byte/page units)*/ },
1284/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1285{ 0, /* segment base address (overwritten) */
1286 0xfffff, /* length */
1287 SDT_MEMRWA, /* segment type */
1288 0, /* segment descriptor priority level */
1289 1, /* segment descriptor present */
1290 0, 0,
1291 0, /* default 32 vs 16 bit size */
1292 1 /* limit granularity (byte/page units)*/ },
1293/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1294{ 0, /* segment base address (overwritten) */
1295 0xfffff, /* length */
1296 SDT_MEMRWA, /* segment type */
1297 0, /* segment descriptor priority level */
1298 1, /* segment descriptor present */
1299 0, 0,
1300 0, /* default 32 vs 16 bit size */
1301 1 /* limit granularity (byte/page units)*/ },
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MD
1302/* GTLS_START 15 TLS */
1303{ 0x0, /* segment base address */
1304 0x0, /* length */
1305 0, /* segment type */
1306 0, /* segment descriptor priority level */
1307 0, /* segment descriptor present */
1308 0, 0,
1309 0, /* default 32 vs 16 bit size */
1310 0 /* limit granularity (byte/page units)*/ },
1311/* GTLS_START+1 16 TLS */
1312{ 0x0, /* segment base address */
1313 0x0, /* length */
1314 0, /* segment type */
1315 0, /* segment descriptor priority level */
1316 0, /* segment descriptor present */
1317 0, 0,
1318 0, /* default 32 vs 16 bit size */
1319 0 /* limit granularity (byte/page units)*/ },
1320/* GTLS_END 17 TLS */
1321{ 0x0, /* segment base address */
1322 0x0, /* length */
1323 0, /* segment type */
1324 0, /* segment descriptor priority level */
1325 0, /* segment descriptor present */
1326 0, 0,
1327 0, /* default 32 vs 16 bit size */
1328 0 /* limit granularity (byte/page units)*/ },
984263bc
MD
1329};
1330
1331static struct soft_segment_descriptor ldt_segs[] = {
1332 /* Null Descriptor - overwritten by call gate */
1333{ 0x0, /* segment base address */
1334 0x0, /* length - all address space */
1335 0, /* segment type */
1336 0, /* segment descriptor priority level */
1337 0, /* segment descriptor present */
1338 0, 0,
1339 0, /* default 32 vs 16 bit size */
1340 0 /* limit granularity (byte/page units)*/ },
1341 /* Null Descriptor - overwritten by call gate */
1342{ 0x0, /* segment base address */
1343 0x0, /* length - all address space */
1344 0, /* segment type */
1345 0, /* segment descriptor priority level */
1346 0, /* segment descriptor present */
1347 0, 0,
1348 0, /* default 32 vs 16 bit size */
1349 0 /* limit granularity (byte/page units)*/ },
1350 /* Null Descriptor - overwritten by call gate */
1351{ 0x0, /* segment base address */
1352 0x0, /* length - all address space */
1353 0, /* segment type */
1354 0, /* segment descriptor priority level */
1355 0, /* segment descriptor present */
1356 0, 0,
1357 0, /* default 32 vs 16 bit size */
1358 0 /* limit granularity (byte/page units)*/ },
1359 /* Code Descriptor for user */
1360{ 0x0, /* segment base address */
1361 0xfffff, /* length - all address space */
1362 SDT_MEMERA, /* segment type */
1363 SEL_UPL, /* segment descriptor priority level */
1364 1, /* segment descriptor present */
1365 0, 0,
1366 1, /* default 32 vs 16 bit size */
1367 1 /* limit granularity (byte/page units)*/ },
1368 /* Null Descriptor - overwritten by call gate */
1369{ 0x0, /* segment base address */
1370 0x0, /* length - all address space */
1371 0, /* segment type */
1372 0, /* segment descriptor priority level */
1373 0, /* segment descriptor present */
1374 0, 0,
1375 0, /* default 32 vs 16 bit size */
1376 0 /* limit granularity (byte/page units)*/ },
1377 /* Data Descriptor for user */
1378{ 0x0, /* segment base address */
1379 0xfffff, /* length - all address space */
1380 SDT_MEMRWA, /* segment type */
1381 SEL_UPL, /* segment descriptor priority level */
1382 1, /* segment descriptor present */
1383 0, 0,
1384 1, /* default 32 vs 16 bit size */
1385 1 /* limit granularity (byte/page units)*/ },
1386};
1387
1388void
f123d5a1 1389setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD
1390{
1391 struct gate_descriptor *ip;
1392
1393 ip = idt + idx;
1394 ip->gd_looffset = (int)func;
1395 ip->gd_selector = selec;
1396 ip->gd_stkcpy = 0;
1397 ip->gd_xx = 0;
1398 ip->gd_type = typ;
1399 ip->gd_dpl = dpl;
1400 ip->gd_p = 1;
1401 ip->gd_hioffset = ((int)func)>>16 ;
1402}
1403
1404#define IDTVEC(name) __CONCAT(X,name)
1405
1406extern inthand_t
1407 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1408 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1409 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1410 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1411 IDTVEC(xmm), IDTVEC(syscall),
1412 IDTVEC(rsvd0);
a64ba182 1413extern inthand_t
f9a13fc4 1414 IDTVEC(int0x80_syscall);
984263bc 1415
f7bc9806
MD
1416#ifdef DEBUG_INTERRUPTS
1417extern inthand_t *Xrsvdary[256];
1418#endif
1419
984263bc 1420void
f123d5a1 1421sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD
1422{
1423 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1424 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1425 ssd->ssd_type = sd->sd_type;
1426 ssd->ssd_dpl = sd->sd_dpl;
1427 ssd->ssd_p = sd->sd_p;
1428 ssd->ssd_def32 = sd->sd_def32;
1429 ssd->ssd_gran = sd->sd_gran;
1430}
1431
984263bc
MD
1432/*
1433 * Populate the (physmap) array with base/bound pairs describing the
1434 * available physical memory in the system, then test this memory and
1435 * build the phys_avail array describing the actually-available memory.
1436 *
1437 * If we cannot accurately determine the physical memory map, then use
1438 * value from the 0xE801 call, and failing that, the RTC.
1439 *
1440 * Total memory size may be set by the kernel environment variable
1441 * hw.physmem or the compile-time define MAXMEM.
1442 */
1443static void
1444getmemsize(int first)
1445{
b24cd69c 1446 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD
1447 int hasbrokenint12;
1448 u_int basemem, extmem;
1449 struct vm86frame vmf;
1450 struct vm86context vmc;
ff1a75a1
MD
1451 vm_offset_t pa;
1452 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1453 pt_entry_t *pte;
555da584 1454 quad_t maxmem;
984263bc
MD
1455 struct {
1456 u_int64_t base;
1457 u_int64_t length;
1458 u_int32_t type;
1459 } *smap;
28abdbbb 1460 quad_t dcons_addr, dcons_size;
984263bc 1461
984263bc
MD
1462 bzero(&vmf, sizeof(struct vm86frame));
1463 bzero(physmap, sizeof(physmap));
1464 basemem = 0;
1465
1466 /*
1467 * Some newer BIOSes has broken INT 12H implementation which cause
1468 * kernel panic immediately. In this case, we need to scan SMAP
1469 * with INT 15:E820 first, then determine base memory size.
1470 */
2ed482dc
MN
1471 hasbrokenint12 = 0;
1472 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD
1473 if (hasbrokenint12) {
1474 goto int15e820;
1475 }
1476
1477 /*
7febcc6e
MD
1478 * Perform "base memory" related probes & setup. If we get a crazy
1479 * value give the bios some scribble space just in case.
984263bc
MD
1480 */
1481 vm86_intcall(0x12, &vmf);
1482 basemem = vmf.vmf_ax;
1483 if (basemem > 640) {
26be20a0 1484 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD
1485 "truncating to < 640K\n", basemem);
1486 basemem = 636;
984263bc
MD
1487 }
1488
1489 /*
1490 * XXX if biosbasemem is now < 640, there is a `hole'
1491 * between the end of base memory and the start of
1492 * ISA memory. The hole may be empty or it may
1493 * contain BIOS code or data. Map it read/write so
1494 * that the BIOS can write to it. (Memory from 0 to
1495 * the physical end of the kernel is mapped read-only
1496 * to begin with and then parts of it are remapped.
1497 * The parts that aren't remapped form holes that
1498 * remain read-only and are unused by the kernel.
1499 * The base memory area is below the physical end of
1500 * the kernel and right now forms a read-only hole.
1501 * The part of it from PAGE_SIZE to
1502 * (trunc_page(biosbasemem * 1024) - 1) will be
1503 * remapped and used by the kernel later.)
1504 *
1505 * This code is similar to the code used in
1506 * pmap_mapdev, but since no memory needs to be
1507 * allocated we simply change the mapping.
1508 */
1509 for (pa = trunc_page(basemem * 1024);
1510 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1511 pte = vtopte(pa + KERNBASE);
984263bc
MD
1512 *pte = pa | PG_RW | PG_V;
1513 }
1514
1515 /*
1516 * if basemem != 640, map pages r/w into vm86 page table so
1517 * that the bios can scribble on it.
1518 */
b5b32410 1519 pte = vm86paddr;
984263bc
MD
1520 for (i = basemem / 4; i < 160; i++)
1521 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1522
1523int15e820:
1524 /*
1525 * map page 1 R/W into the kernel page table so we can use it
1526 * as a buffer. The kernel will unmap this page later.
1527 */
b5b32410 1528 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1529 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1530
1531 /*
1532 * get memory map with INT 15:E820
1533 */
1534#define SMAPSIZ sizeof(*smap)
1535#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1536
1537 vmc.npages = 0;
1538 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1539 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1540
1541 physmap_idx = 0;
1542 vmf.vmf_ebx = 0;
1543 do {
1544 vmf.vmf_eax = 0xE820;
1545 vmf.vmf_edx = SMAP_SIG;
1546 vmf.vmf_ecx = SMAPSIZ;
1547 i = vm86_datacall(0x15, &vmf, &vmc);
1548 if (i || vmf.vmf_eax != SMAP_SIG)
1549 break;
1550 if (boothowto & RB_VERBOSE)
26be20a0 1551 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD
1552 smap->type,
1553 *(u_int32_t *)((char *)&smap->base + 4),
1554 (u_int32_t)smap->base,
1555 *(u_int32_t *)((char *)&smap->length + 4),
1556 (u_int32_t)smap->length);
1557
1558 if (smap->type != 0x01)
1559 goto next_run;
1560
1561 if (smap->length == 0)
1562 goto next_run;
1563
1bda0d3d
MD
1564 Realmem += smap->length;
1565
1566 if (smap->base >= 0xffffffffLLU) {
9c3db322 1567 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1568 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD
1569 goto next_run;
1570 }
1571
1572 for (i = 0; i <= physmap_idx; i += 2) {
1573 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1574 if (boothowto & RB_VERBOSE) {
1575 kprintf("Overlapping or non-montonic "
1576 "memory region, ignoring "
1577 "second region\n");
1578 }
1579 Realmem -= smap->length;
984263bc
MD
1580 goto next_run;
1581 }
1582 }
1583
1584 if (smap->base == physmap[physmap_idx + 1]) {
1585 physmap[physmap_idx + 1] += smap->length;
1586 goto next_run;
1587 }
1588
1589 physmap_idx += 2;
ff1a75a1 1590 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD
1591 kprintf("Too many segments in the physical "
1592 "address map, giving up\n");
984263bc
MD
1593 break;
1594 }
1595 physmap[physmap_idx] = smap->base;
1596 physmap[physmap_idx + 1] = smap->base + smap->length;
1597next_run:
6b08710e 1598 ; /* fix GCC3.x warning */
984263bc
MD
1599 } while (vmf.vmf_ebx != 0);
1600
1601 /*
1602 * Perform "base memory" related probes & setup based on SMAP
1603 */
1604 if (basemem == 0) {
1605 for (i = 0; i <= physmap_idx; i += 2) {
1606 if (physmap[i] == 0x00000000) {
1607 basemem = physmap[i + 1] / 1024;
1608 break;
1609 }
1610 }
1611
1612 if (basemem == 0) {
1613 basemem = 640;
1614 }
1615
1616 if (basemem > 640) {
1bda0d3d
MD
1617 kprintf("Preposterous BIOS basemem of %uK, "
1618 "truncating to 640K\n", basemem);
984263bc
MD
1619 basemem = 640;
1620 }
1621
1622 for (pa = trunc_page(basemem * 1024);
1623 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1624 pte = vtopte(pa + KERNBASE);
984263bc
MD
1625 *pte = pa | PG_RW | PG_V;
1626 }
1627
b5b32410 1628 pte = vm86paddr;
984263bc
MD
1629 for (i = basemem / 4; i < 160; i++)
1630 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1631 }
1632
1633 if (physmap[1] != 0)
1634 goto physmap_done;
1635
1636 /*
1637 * If we failed above, try memory map with INT 15:E801
1638 */
1639 vmf.vmf_ax = 0xE801;
1640 if (vm86_intcall(0x15, &vmf) == 0) {
1641 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1642 } else {
1643#if 0
1644 vmf.vmf_ah = 0x88;
1645 vm86_intcall(0x15, &vmf);
1646 extmem = vmf.vmf_ax;
1647#else
1648 /*
1649 * Prefer the RTC value for extended memory.
1650 */
1651 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1652#endif
1653 }
1654
1655 /*
1656 * Special hack for chipsets that still remap the 384k hole when
1657 * there's 16MB of memory - this really confuses people that
1658 * are trying to use bus mastering ISA controllers with the
1659 * "16MB limit"; they only have 16MB, but the remapping puts
1660 * them beyond the limit.
1661 *
1662 * If extended memory is between 15-16MB (16-17MB phys address range),
1663 * chop it to 15MB.
1664 */
1665 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1666 extmem = 15 * 1024;
1667
1668 physmap[0] = 0;
1669 physmap[1] = basemem * 1024;
1670 physmap_idx = 2;
1671 physmap[physmap_idx] = 0x100000;
1672 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1673
1674physmap_done:
1675 /*
1676 * Now, physmap contains a map of physical memory.
1677 */
1678
ed721f0f 1679 base_memory = physmap[1];
984263bc 1680#ifdef SMP
17a9f566 1681 /* make hole for AP bootstrap code YYY */
ed721f0f 1682 physmap[1] = mp_bootaddress(base_memory);
7d676a89 1683#endif
984263bc 1684
1876681a
SZ
1685 /* Save EBDA address, if any */
1686 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1687 ebda_addr <<= 4;
984263bc
MD
1688
1689 /*
1690 * Maxmem isn't the "maximum memory", it's one larger than the
1691 * highest page of the physical address space. It should be
1692 * called something like "Maxphyspage". We may adjust this
1693 * based on ``hw.physmem'' and the results of the memory test.
1694 */
1695 Maxmem = atop(physmap[physmap_idx + 1]);
1696
1697#ifdef MAXMEM
1698 Maxmem = MAXMEM / 4;
1699#endif
1700
555da584
MD
1701 if (kgetenv_quad("hw.physmem", &maxmem))
1702 Maxmem = atop(maxmem);
984263bc
MD
1703
1704 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1705 (boothowto & RB_VERBOSE))
26be20a0 1706 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1707
1708 /*
1709 * If Maxmem has been increased beyond what the system has detected,
1710 * extend the last memory segment to the new limit.
1711 */
1712 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1713 physmap[physmap_idx + 1] = ptoa(Maxmem);
1714
1715 /* call pmap initialization to make new kernel address space */
1716 pmap_bootstrap(first, 0);
1717
1718 /*
1719 * Size up each available chunk of physical memory.
1720 */
1721 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1722 pa_indx = 0;
b24cd69c 1723 da_indx = 1;
984263bc
MD
1724 phys_avail[pa_indx++] = physmap[0];
1725 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH
1726 dump_avail[da_indx] = physmap[0];
1727
b5b32410 1728 pte = CMAP1;
984263bc
MD
1729
1730 /*
28abdbbb
HS
1731 * Get dcons buffer address
1732 */
bc01a404
MD
1733 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1734 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS
1735 dcons_addr = 0;
1736
1737 /*
984263bc
MD
1738 * physmap is in bytes, so when converting to page boundaries,
1739 * round up the start address and round down the end address.
1740 */
1741 for (i = 0; i <= physmap_idx; i += 2) {
1742 vm_offset_t end;
1743
1744 end = ptoa(Maxmem);
1745 if (physmap[i + 1] < end)
1746 end = trunc_page(physmap[i + 1]);
1747 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1748 int tmp, page_bad, full;
984263bc
MD
1749#if 0
1750 int *ptr = 0;
1751#else
1752 int *ptr = (int *)CADDR1;
1753#endif
b24cd69c 1754 full = FALSE;
984263bc
MD
1755
1756 /*
1757 * block out kernel memory as not available.
1758 */
1759 if (pa >= 0x100000 && pa < first)
b24cd69c 1760 goto do_dump_avail;
984263bc 1761
28abdbbb
HS
1762 /*
1763 * block out dcons buffer
1764 */
1765 if (dcons_addr > 0
1766 && pa >= trunc_page(dcons_addr)
1767 && pa < dcons_addr + dcons_size)
b24cd69c 1768 goto do_dump_avail;
28abdbbb 1769
984263bc
MD
1770 page_bad = FALSE;
1771
1772 /*
1773 * map page into kernel: valid, read/write,non-cacheable
1774 */
1775 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1776 cpu_invltlb();
984263bc
MD
1777
1778 tmp = *(int *)ptr;
1779 /*
1780 * Test for alternating 1's and 0's
1781 */
1782 *(volatile int *)ptr = 0xaaaaaaaa;
1783 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1784 page_bad = TRUE;
1785 }
1786 /*
1787 * Test for alternating 0's and 1's
1788 */
1789 *(volatile int *)ptr = 0x55555555;
1790 if (*(volatile int *)ptr != 0x55555555) {
1791 page_bad = TRUE;
1792 }
1793 /*
1794 * Test for all 1's
1795 */
1796 *(volatile int *)ptr = 0xffffffff;
1797 if (*(volatile int *)ptr != 0xffffffff) {
1798 page_bad = TRUE;
1799 }
1800 /*
1801 * Test for all 0's
1802 */
1803 *(volatile int *)ptr = 0x0;
1804 if (*(volatile int *)ptr != 0x0) {
1805 page_bad = TRUE;
1806 }
1807 /*
1808 * Restore original value.
1809 */
1810 *(int *)ptr = tmp;
1811
1812 /*
1813 * Adjust array of valid/good pages.
1814 */
1815 if (page_bad == TRUE) {
1816 continue;
1817 }
1818 /*
1819 * If this good page is a continuation of the
1820 * previous set of good pages, then just increase
1821 * the end pointer. Otherwise start a new chunk.
1822 * Note that "end" points one higher than end,
1823 * making the range >= start and < end.
1824 * If we're also doing a speculative memory
1825 * test and we at or past the end, bump up Maxmem
1826 * so that we keep going. The first bad page
1827 * will terminate the loop.
1828 */
1829 if (phys_avail[pa_indx] == pa) {
1830 phys_avail[pa_indx] += PAGE_SIZE;
1831 } else {
1832 pa_indx++;
ff1a75a1 1833 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1834 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1835 pa_indx--;
b24cd69c
AH
1836 full = TRUE;
1837 goto do_dump_avail;
984263bc
MD
1838 }
1839 phys_avail[pa_indx++] = pa; /* start */
1840 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1841 }
1842 physmem++;
b24cd69c
AH
1843do_dump_avail:
1844 if (dump_avail[da_indx] == pa) {
1845 dump_avail[da_indx] += PAGE_SIZE;
1846 } else {
1847 da_indx++;
1848 if (da_indx >= PHYSMAP_ENTRIES*2) {
1849 da_indx--;
1850 goto do_next;
1851 }
1852 dump_avail[da_indx++] = pa; /* start */
1853 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1854 }
1855do_next:
1856 if (full)
1857 break;
1858
984263bc
MD
1859 }
1860 }
1861 *pte = 0;
0f7a3396 1862 cpu_invltlb();
984263bc
MD
1863
1864 /*
1865 * XXX
1866 * The last chunk must contain at least one page plus the message
1867 * buffer to avoid complicating other code (message buffer address
1868 * calculation, etc.).
1869 */
1870 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1871 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1872 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1873 phys_avail[pa_indx--] = 0;
1874 phys_avail[pa_indx--] = 0;
1875 }
1876
1877 Maxmem = atop(phys_avail[pa_indx]);
1878
1879 /* Trim off space for the message buffer. */
1880 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1881
1882 avail_end = phys_avail[pa_indx];
1883}
1884
30c5f287
MN
1885struct machintr_abi MachIntrABI;
1886
f7bc9806
MD
1887/*
1888 * IDT VECTORS:
1889 * 0 Divide by zero
1890 * 1 Debug
1891 * 2 NMI
1892 * 3 BreakPoint
1893 * 4 OverFlow
1894 * 5 Bound-Range
1895 * 6 Invalid OpCode
1896 * 7 Device Not Available (x87)
1897 * 8 Double-Fault
1898 * 9 Coprocessor Segment overrun (unsupported, reserved)
1899 * 10 Invalid-TSS
1900 * 11 Segment not present
1901 * 12 Stack
1902 * 13 General Protection
1903 * 14 Page Fault
1904 * 15 Reserved
1905 * 16 x87 FP Exception pending
1906 * 17 Alignment Check
1907 * 18 Machine Check
1908 * 19 SIMD floating point
1909 * 20-31 reserved
1910 * 32-255 INTn/external sources
1911 */
984263bc 1912void
17a9f566 1913init386(int first)
984263bc
MD
1914{
1915 struct gate_descriptor *gdp;
1916 int gsel_tss, metadata_missing, off, x;
85100692 1917 struct mdglobaldata *gd;
984263bc
MD
1918
1919 /*
1920 * Prevent lowering of the ipl if we call tsleep() early.
1921 */
85100692 1922 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1923 bzero(gd, sizeof(*gd));
984263bc 1924
85100692 1925 gd->mi.gd_curthread = &thread0;
4e7c41c5 1926 thread0.td_gd = &gd->mi;
984263bc
MD
1927
1928 atdevbase = ISA_HOLE_START + KERNBASE;
1929
1930 metadata_missing = 0;
1931 if (bootinfo.bi_modulep) {
1932 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1933 preload_bootstrap_relocate(KERNBASE);
1934 } else {
1935 metadata_missing = 1;
1936 }
1937 if (bootinfo.bi_envp)
1938 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1939
27af435a
SZ
1940 if (boothowto & RB_VERBOSE)
1941 bootverbose++;
1942
c5cc06e3 1943 /*
10db3cc6 1944 * Default MachIntrABI to ICU
30c5f287
MN
1945 */
1946 MachIntrABI = MachIntrABI_ICU;
1947#ifdef SMP
d745d2b8
SZ
1948 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1949 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1d6d7089 1950 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
30c5f287
MN
1951#endif
1952
1953 /*
b45759e1
MD
1954 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1955 * and ncpus_fit_mask remain 0.
c5cc06e3 1956 */
4e8e646b 1957 ncpus = 1;
c5cc06e3 1958 ncpus2 = 1;
b45759e1 1959 ncpus_fit = 1;
984263bc
MD
1960 /* Init basic tunables, hz etc */
1961 init_param1();
1962
1963 /*
1964 * make gdt memory segments, the code segment goes up to end of the
1965 * page with etext in it, the data segment goes to the end of
1966 * the address space
1967 */
1968 /*
1969 * XXX text protection is temporarily (?) disabled. The limit was
1970 * i386_btop(round_page(etext)) - 1.
1971 */
1972 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1973 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1974
984263bc
MD
1975 gdt_segs[GPRIV_SEL].ssd_limit =
1976 atop(sizeof(struct privatespace) - 1);
8ad65e08 1977 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1978 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1979 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1980
85100692 1981 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1982
84b592ba
MD
1983 /*
1984 * Note: on both UP and SMP curthread must be set non-NULL
1985 * early in the boot sequence because the system assumes
1986 * that 'curthread' is never NULL.
1987 */
984263bc
MD
1988
1989 for (x = 0; x < NGDT; x++) {
1990#ifdef BDE_DEBUGGER
1991 /* avoid overwriting db entries with APM ones */
1992 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1993 continue;
1994#endif
1995 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1996 }
1997
1998 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1999 r_gdt.rd_base = (int) gdt;
2000 lgdt(&r_gdt);
2001
73e4f7b9
MD
2002 mi_gdinit(&gd->mi, 0);
2003 cpu_gdinit(gd, 0);
6bf59cd2 2004 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 2005 safepri = TDPRI_MAX;
73e4f7b9 2006
984263bc
MD
2007 /* make ldt memory segments */
2008 /*
88181b08 2009 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD
2010 * should be spelled ...MAX_USER...
2011 */
88181b08
MD
2012 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
2013 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
984263bc
MD
2014 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
2015 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2016
2017 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
2018 lldt(_default_ldt);
17a9f566 2019 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
2020 /* spinlocks and the BGL */
2021 init_locks();
984263bc 2022
2f839e54
MD
2023 /*
2024 * Setup the hardware exception table. Most exceptions use
2025 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
2026 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
2027 * an 'interrupt trap gate', which disables interrupts on entry,
2028 * in order to be able to poll the appropriate CRn register to
2029 * determine the fault address.
2030 */
f7bc9806
MD
2031 for (x = 0; x < NIDT; x++) {
2032#ifdef DEBUG_INTERRUPTS
2033 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2034#else
2035 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2036#endif
2037 }
984263bc
MD
2038 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2039 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2040 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2041 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2042 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2043 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2044 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2045 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2046 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2047 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2048 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2049 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2050 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2051 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2052 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 2053 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
2054 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2055 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2056 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2057 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2058 setidt(0x80, &IDTVEC(int0x80_syscall),
2059 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2060
2061 r_idt.rd_limit = sizeof(idt0) - 1;
2062 r_idt.rd_base = (int) idt;
2063 lidt(&r_idt);
2064
2065 /*
2066 * Initialize the console before we print anything out.
2067 */
2068 cninit();
2069
2070 if (metadata_missing)
26be20a0 2071 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 2072
984263bc 2073#if NISA >0
e24dd6e0 2074 elcr_probe();
984263bc
MD
2075 isa_defaultirq();
2076#endif
2077 rand_initialize();
2078
a3dd9120
SZ
2079 /*
2080 * Initialize IRQ mapping
2081 *
2082 * NOTE:
2083 * SHOULD be after elcr_probe()
2084 */
2085 MachIntrABI_ICU.initmap();
2086#ifdef SMP
2087 MachIntrABI_IOAPIC.initmap();
2088#endif
2089
984263bc
MD
2090#ifdef DDB
2091 kdb_init();
2092 if (boothowto & RB_KDB)
2093 Debugger("Boot flags requested debugger");
2094#endif
2095
2096 finishidentcpu(); /* Final stage of CPU initialization */
2097 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2098 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2099 initializecpu(); /* Initialize CPU registers */
2100
b7c628e4
MD
2101 /*
2102 * make an initial tss so cpu can get interrupt stack on syscall!
2103 * The 16 bytes is to save room for a VM86 context.
2104 */
17a9f566
MD
2105 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
2106 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 2107 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
2108 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
2109 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 2110 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
2111 ltr(gsel_tss);
2112
2113 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2114 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
2115 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2116 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2117 dblfault_tss.tss_cr3 = (int)IdlePTD;
2118 dblfault_tss.tss_eip = (int) dblfault_handler;
2119 dblfault_tss.tss_eflags = PSL_KERNEL;
2120 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2121 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2122 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2123 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2124 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2125
2126 vm86_initialize();
2127 getmemsize(first);
2128 init_param2(physmem);
2129
2130 /* now running on new page tables, configured,and u/iom is accessible */
2131
2132 /* Map the message buffer. */
2133 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2134 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2135
2136 msgbufinit(msgbufp, MSGBUF_SIZE);
2137
2138 /* make a call gate to reenter kernel with */
2139 gdp = &ldt[LSYS5CALLS_SEL].gd;
2140
2141 x = (int) &IDTVEC(syscall);
2142 gdp->gd_looffset = x++;
2143 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2144 gdp->gd_stkcpy = 1;
2145 gdp->gd_type = SDT_SYS386CGT;
2146 gdp->gd_dpl = SEL_UPL;
2147 gdp->gd_p = 1;
2148 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2149
2150 /* XXX does this work? */
2151 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2152 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2153
2154 /* transfer to user mode */
2155
2156 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2157 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2158
2159 /* setup proc 0's pcb */
b7c628e4
MD
2160 thread0.td_pcb->pcb_flags = 0;
2161 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2162 thread0.td_pcb->pcb_ext = 0;
08f2f1bb 2163 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD
2164}
2165
8ad65e08 2166/*
17a9f566
MD
2167 * Initialize machine-dependant portions of the global data structure.
2168 * Note that the global data area and cpu0's idlestack in the private
2169 * data space were allocated in locore.
ef0fdad1
MD
2170 *
2171 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2172 *
2173 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2174 */
2175void
85100692 2176cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2177{
7d0bac62 2178 if (cpu)
a2a5ad0d 2179 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2180
f470d0c8
MD
2181 lwkt_init_thread(&gd->mi.gd_idlethread,
2182 gd->mi.gd_prvspace->idlestack,
d3d32139 2183 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2184 0, &gd->mi);
a2a5ad0d
MD
2185 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2186 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2187 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2188 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2189}
2190
0cd275af
MD
2191int
2192is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2193{
2194 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2195 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2196 return (TRUE);
2197 }
2198 return (FALSE);
2199}
2200
12e4aaff
MD
2201struct globaldata *
2202globaldata_find(int cpu)
2203{
2204 KKASSERT(cpu >= 0 && cpu < ncpus);
2205 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2206}
2207
984263bc
MD
2208#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2209static void f00f_hack(void *unused);
ba39e2e0 2210SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD
2211
2212static void
17a9f566
MD
2213f00f_hack(void *unused)
2214{
984263bc 2215 struct gate_descriptor *new_idt;
984263bc
MD
2216 vm_offset_t tmp;
2217
2218 if (!has_f00f_bug)
2219 return;
2220
26be20a0 2221 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD
2222
2223 r_idt.rd_limit = sizeof(idt0) - 1;
2224
e4846942 2225 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD
2226 if (tmp == 0)
2227 panic("kmem_alloc returned 0");
2228 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2229 panic("kmem_alloc returned non-page-aligned memory");
2230 /* Put the first seven entries in the lower page */
2231 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2232 bcopy(idt, new_idt, sizeof(idt0));
2233 r_idt.rd_base = (int)new_idt;
2234 lidt(&r_idt);
2235 idt = new_idt;
e4846942 2236 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD
2237 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2238 panic("vm_map_protect failed");
2239 return;
2240}
2241#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2242
2243int
08f2f1bb 2244ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2245{
08f2f1bb 2246 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD
2247 return (0);
2248}
2249
2250int
e9182c58 2251ptrace_single_step(struct lwp *lp)
984263bc 2252{
e9182c58 2253 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD
2254 return (0);
2255}
2256
f123d5a1 2257int
e9182c58 2258fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2259{
984263bc
MD
2260 struct trapframe *tp;
2261
e9182c58 2262 tp = lp->lwp_md.md_regs;
4e7c41c5 2263 regs->r_gs = tp->tf_gs;
984263bc
MD
2264 regs->r_fs = tp->tf_fs;
2265 regs->r_es = tp->tf_es;
2266 regs->r_ds = tp->tf_ds;
2267 regs->r_edi = tp->tf_edi;
2268 regs->r_esi = tp->tf_esi;
2269 regs->r_ebp = tp->tf_ebp;
2270 regs->r_ebx = tp->tf_ebx;
2271 regs->r_edx = tp->tf_edx;
2272 regs->r_ecx = tp->tf_ecx;
2273 regs->r_eax = tp->tf_eax;
2274 regs->r_eip = tp->tf_eip;
2275 regs->r_cs = tp->tf_cs;
2276 regs->r_eflags = tp->tf_eflags;
2277 regs->r_esp = tp->tf_esp;
2278 regs->r_ss = tp->tf_ss;
984263bc
MD
2279 return (0);
2280}
2281
2282int
e9182c58 2283set_regs(struct lwp *lp, struct reg *regs)
984263bc 2284{
984263bc
MD
2285 struct trapframe *tp;
2286
e9182c58 2287 tp = lp->lwp_md.md_regs;
984263bc
MD
2288 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2289 !CS_SECURE(regs->r_cs))
2290 return (EINVAL);
4e7c41c5 2291 tp->tf_gs = regs->r_gs;
984263bc
MD
2292 tp->tf_fs = regs->r_fs;
2293 tp->tf_es = regs->r_es;
2294 tp->tf_ds = regs->r_ds;
2295 tp->tf_edi = regs->r_edi;
2296 tp->tf_esi = regs->r_esi;
2297 tp->tf_ebp = regs->r_ebp;
2298 tp->tf_ebx = regs->r_ebx;
2299 tp->tf_edx = regs->r_edx;
2300 tp->tf_ecx = regs->r_ecx;
2301 tp->tf_eax = regs->r_eax;
2302 tp->tf_eip = regs->r_eip;
2303 tp->tf_cs = regs->r_cs;
2304 tp->tf_eflags = regs->r_eflags;
2305 tp->tf_esp = regs->r_esp;
2306 tp->tf_ss = regs->r_ss;
984263bc
MD
2307 return (0);
2308}
2309
642a6e88 2310#ifndef CPU_DISABLE_SSE
984263bc 2311static void
f123d5a1 2312fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2313{
c9faf524
RG
2314 struct env87 *penv_87 = &sv_87->sv_env;
2315 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2316 int i;
2317
2318 /* FPU control/status */
2319 penv_87->en_cw = penv_xmm->en_cw;
2320 penv_87->en_sw = penv_xmm->en_sw;
2321 penv_87->en_tw = penv_xmm->en_tw;
2322 penv_87->en_fip = penv_xmm->en_fip;
2323 penv_87->en_fcs = penv_xmm->en_fcs;
2324 penv_87->en_opcode = penv_xmm->en_opcode;
2325 penv_87->en_foo = penv_xmm->en_foo;
2326 penv_87->en_fos = penv_xmm->en_fos;
2327
2328 /* FPU registers */
2329 for (i = 0; i < 8; ++i)
2330 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
984263bc
MD
2331}
2332
2333static void
f123d5a1 2334set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2335{
c9faf524
RG
2336 struct env87 *penv_87 = &sv_87->sv_env;
2337 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2338 int i;
2339
2340 /* FPU control/status */
2341 penv_xmm->en_cw = penv_87->en_cw;
2342 penv_xmm->en_sw = penv_87->en_sw;
2343 penv_xmm->en_tw = penv_87->en_tw;
2344 penv_xmm->en_fip = penv_87->en_fip;
2345 penv_xmm->en_fcs = penv_87->en_fcs;
2346 penv_xmm->en_opcode = penv_87->en_opcode;
2347 penv_xmm->en_foo = penv_87->en_foo;
2348 penv_xmm->en_fos = penv_87->en_fos;
2349
2350 /* FPU registers */
2351 for (i = 0; i < 8; ++i)
2352 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
984263bc 2353}
642a6e88 2354#endif /* CPU_DISABLE_SSE */
984263bc
MD
2355
2356int
e9182c58 2357fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2358{
642a6e88 2359#ifndef CPU_DISABLE_SSE
984263bc 2360 if (cpu_fxsr) {
e9182c58
SZ
2361 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2362 (struct save87 *)fpregs);
984263bc
MD
2363 return (0);
2364 }
642a6e88 2365#endif /* CPU_DISABLE_SSE */
e9182c58 2366 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2367 return (0);
2368}
2369
2370int
e9182c58 2371set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2372{
642a6e88 2373#ifndef CPU_DISABLE_SSE
984263bc
MD
2374 if (cpu_fxsr) {
2375 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2376 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD
2377 return (0);
2378 }
642a6e88 2379#endif /* CPU_DISABLE_SSE */
e9182c58 2380 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2381 return (0);
2382}
2383
2384int
e9182c58 2385fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2386{
e9182c58 2387 if (lp == NULL) {
984263bc
MD
2388 dbregs->dr0 = rdr0();
2389 dbregs->dr1 = rdr1();
2390 dbregs->dr2 = rdr2();
2391 dbregs->dr3 = rdr3();
2392 dbregs->dr4 = rdr4();
2393 dbregs->dr5 = rdr5();
2394 dbregs->dr6 = rdr6();
2395 dbregs->dr7 = rdr7();
e9182c58
SZ
2396 } else {
2397 struct pcb *pcb;
2398
2399 pcb = lp->lwp_thread->td_pcb;
984263bc
MD
2400 dbregs->dr0 = pcb->pcb_dr0;
2401 dbregs->dr1 = pcb->pcb_dr1;
2402 dbregs->dr2 = pcb->pcb_dr2;
2403 dbregs->dr3 = pcb->pcb_dr3;
2404 dbregs->dr4 = 0;
2405 dbregs->dr5 = 0;
2406 dbregs->dr6 = pcb->pcb_dr6;
2407 dbregs->dr7 = pcb->pcb_dr7;
2408 }
2409 return (0);
2410}
2411
2412int
e9182c58 2413set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2414{
e9182c58 2415 if (lp == NULL) {
984263bc
MD
2416 load_dr0(dbregs->dr0);
2417 load_dr1(dbregs->dr1);
2418 load_dr2(dbregs->dr2);
2419 load_dr3(dbregs->dr3);
2420 load_dr4(dbregs->dr4);
2421 load_dr5(dbregs->dr5);
2422 load_dr6(dbregs->dr6);
2423 load_dr7(dbregs->dr7);
e9182c58
SZ
2424 } else {
2425 struct pcb *pcb;
2426 struct ucred *ucred;
2427 int i;
2428 uint32_t mask1, mask2;
2429
984263bc
MD
2430 /*
2431 * Don't let an illegal value for dr7 get set. Specifically,
2432 * check for undefined settings. Setting these bit patterns
2433 * result in undefined behaviour and can lead to an unexpected
2434 * TRCTRAP.
2435 */
2436 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2437 i++, mask1 <<= 2, mask2 <<= 2)
2438 if ((dbregs->dr7 & mask1) == mask2)
2439 return (EINVAL);
2440
e9182c58
SZ
2441 pcb = lp->lwp_thread->td_pcb;
2442 ucred = lp->lwp_proc->p_ucred;
2443
984263bc
MD
2444 /*
2445 * Don't let a process set a breakpoint that is not within the
2446 * process's address space. If a process could do this, it
2447 * could halt the system by setting a breakpoint in the kernel
2448 * (if ddb was enabled). Thus, we need to check to make sure
2449 * that no breakpoints are being enabled for addresses outside
2450 * process's address space, unless, perhaps, we were called by
2451 * uid 0.
2452 *
2453 * XXX - what about when the watched area of the user's
2454 * address space is written into from within the kernel
2455 * ... wouldn't that still cause a breakpoint to be generated
2456 * from within kernel mode?
2457 */
e9182c58 2458
895c1f85 2459 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD
2460 if (dbregs->dr7 & 0x3) {
2461 /* dr0 is enabled */
88181b08 2462 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2463 return (EINVAL);
2464 }
e9182c58 2465
984263bc
MD
2466 if (dbregs->dr7 & (0x3<<2)) {
2467 /* dr1 is enabled */
88181b08 2468 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2469 return (EINVAL);
2470 }
e9182c58 2471
984263bc
MD
2472 if (dbregs->dr7 & (0x3<<4)) {
2473 /* dr2 is enabled */
88181b08 2474 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2475 return (EINVAL);
2476 }
e9182c58 2477
984263bc
MD
2478 if (dbregs->dr7 & (0x3<<6)) {
2479 /* dr3 is enabled */
88181b08 2480 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD
2481 return (EINVAL);
2482 }
2483 }
e9182c58 2484
984263bc
MD
2485 pcb->pcb_dr0 = dbregs->dr0;
2486 pcb->pcb_dr1 = dbregs->dr1;
2487 pcb->pcb_dr2 = dbregs->dr2;
2488 pcb->pcb_dr3 = dbregs->dr3;
2489 pcb->pcb_dr6 = dbregs->dr6;
2490 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2491
984263bc
MD
2492 pcb->pcb_flags |= PCB_DBREGS;
2493 }
2494
2495 return (0);
2496}
2497
2498/*
2499 * Return > 0 if a hardware breakpoint has been hit, and the
2500 * breakpoint was in user space. Return 0, otherwise.
2501 */
2502int
2503user_dbreg_trap(void)
2504{
2505 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2506 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2507 int nbp; /* number of breakpoints that triggered */
2508 caddr_t addr[4]; /* breakpoint addresses */
2509 int i;
2510
2511 dr7 = rdr7();
2512 if ((dr7 & 0x000000ff) == 0) {
2513 /*
2514 * all GE and LE bits in the dr7 register are zero,
2515 * thus the trap couldn't have been caused by the
2516 * hardware debug registers
2517 */
2518 return 0;
2519 }
2520
2521 nbp = 0;
2522 dr6 = rdr6();
2523 bp = dr6 & 0x0000000f;
2524
2525 if (!bp) {
2526 /*
2527 * None of the breakpoint bits are set meaning this
2528 * trap was not caused by any of the debug registers
2529 */
2530 return 0;
2531 }
2532
2533 /*
2534 * at least one of the breakpoints were hit, check to see
2535 * which ones and if any of them are user space addresses
2536 */
2537
2538 if (bp & 0x01) {
2539 addr[nbp++] = (caddr_t)rdr0();
2540 }
2541 if (bp & 0x02) {
2542 addr[nbp++] = (caddr_t)rdr1();
2543 }
2544 if (bp & 0x04) {
2545 addr[nbp++] = (caddr_t)rdr2();
2546 }
2547 if (bp & 0x08) {
2548 addr[nbp++] = (caddr_t)rdr3();
2549 }
2550
2551 for (i=0; i<nbp; i++) {
2552 if (addr[i] <
88181b08 2553 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD
2554 /*
2555 * addr[i] is in user space
2556 */
2557 return nbp;
2558 }
2559 }
2560
2561 /*
2562 * None of the breakpoints are in user space.
2563 */
2564 return 0;
2565}
2566
2567
2568#ifndef DDB
2569void
2570Debugger(const char *msg)
2571{
26be20a0 2572 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD
2573}
2574#endif /* no DDB */
2575
984263bc
MD
2576#ifdef DDB
2577
2578/*
2579 * Provide inb() and outb() as functions. They are normally only
2580 * available as macros calling inlined functions, thus cannot be
2581 * called inside DDB.
2582 *
2583 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2584 */
2585
2586#undef inb
2587#undef outb
2588
2589/* silence compiler warnings */
2590u_char inb(u_int);
2591void outb(u_int, u_char);
2592
2593u_char
2594inb(u_int port)
2595{
2596 u_char data;
2597 /*
2598 * We use %%dx and not %1 here because i/o is done at %dx and not at
2599 * %edx, while gcc generates inferior code (movw instead of movl)
2600 * if we tell it to load (u_short) port.
2601 */
2602 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2603 return (data);
2604}
2605
2606void
2607outb(u_int port, u_char data)
2608{
2609 u_char al;
2610 /*
2611 * Use an unnecessary assignment to help gcc's register allocator.
2612 * This make a large difference for gcc-1.40 and a tiny difference
2613 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2614 * best results. gcc-2.6.0 can't handle this.
2615 */
2616 al = data;
2617 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2618}
2619
2620#endif /* DDB */
8a8d5d85
MD
2621
2622
2623
2624#include "opt_cpu.h"
8a8d5d85
MD
2625
2626
2627/*
2628 * initialize all the SMP locks
2629 */
2630
97359a5b 2631/* critical region when masking or unmasking interupts */
b1af91cb 2632struct spinlock_deprecated imen_spinlock;
8a8d5d85 2633
8a8d5d85 2634/* critical region for old style disable_intr/enable_intr */
b1af91cb 2635struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD
2636
2637/* critical region around INTR() routines */
b1af91cb 2638struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD
2639
2640/* lock region used by kernel profiling */
b1af91cb 2641struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD
2642
2643/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2644struct spinlock_deprecated com_spinlock;
8a8d5d85 2645
8a8d5d85 2646/* lock regions around the clock hardware */
b1af91cb 2647struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD
2648
2649/* lock around the MP rendezvous */
b1af91cb 2650struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD
2651
2652static void
2653init_locks(void)
2654{
b5d16701 2655#ifdef SMP
8a8d5d85 2656 /*
b5d16701 2657 * Get the initial mplock with a count of 1 for the BSP.
8a8d5d85
MD
2658 * This uses a LOGICAL cpu ID, ie BSP == 0.
2659 */
8a8d5d85
MD
2660 cpu_get_initial_mplock();
2661#endif
41a01a4d 2662 /* DEPRECATED */
8a8d5d85 2663 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD
2664 spin_lock_init(&intr_spinlock);
2665 spin_lock_init(&mpintr_spinlock);
2666 spin_lock_init(&imen_spinlock);
2667 spin_lock_init(&smp_rv_spinlock);
2668 spin_lock_init(&com_spinlock);
2669 spin_lock_init(&clock_spinlock);
41a01a4d
MD
2670
2671 /* our token pool needs to work early */
2672 lwkt_token_pool_init();
8a8d5d85 2673}