i386: Allow UP kernel to use LAPIC timer and I/O APIC
[dragonfly.git] / sys / platform / pc32 / apic / ioapic_abi.c
CommitLineData
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
10ff1029
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3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
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6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
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9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
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12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
37e7efec 39 *
0b692e79 40 * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
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41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
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47#include <sys/interrupt.h>
48#include <sys/bus.h>
0b692e79 49
37e7efec 50#include <machine/smp.h>
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51#include <machine/segments.h>
52#include <machine/md_var.h>
87cf6827 53#include <machine/intr_machdep.h>
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54#include <machine/globaldata.h>
55
56#include <sys/thread2.h>
57
4298586a 58#include <machine_base/icu/icu.h>
6b809ec7 59#include <machine_base/icu/icu_var.h>
4298586a 60#include <machine_base/apic/ioapic.h>
929c940f 61#include <machine_base/apic/ioapic_abi.h>
77f86d14 62#include <machine_base/apic/ioapic_ipl.h>
1e7aaefa 63#include <machine_base/apic/apicreg.h>
37e7efec 64
10ff1029 65extern inthand_t
9e0e3f85
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66 IDTVEC(ioapic_intr0),
67 IDTVEC(ioapic_intr1),
68 IDTVEC(ioapic_intr2),
69 IDTVEC(ioapic_intr3),
70 IDTVEC(ioapic_intr4),
71 IDTVEC(ioapic_intr5),
72 IDTVEC(ioapic_intr6),
73 IDTVEC(ioapic_intr7),
74 IDTVEC(ioapic_intr8),
75 IDTVEC(ioapic_intr9),
76 IDTVEC(ioapic_intr10),
77 IDTVEC(ioapic_intr11),
78 IDTVEC(ioapic_intr12),
79 IDTVEC(ioapic_intr13),
80 IDTVEC(ioapic_intr14),
81 IDTVEC(ioapic_intr15),
82 IDTVEC(ioapic_intr16),
83 IDTVEC(ioapic_intr17),
84 IDTVEC(ioapic_intr18),
85 IDTVEC(ioapic_intr19),
86 IDTVEC(ioapic_intr20),
87 IDTVEC(ioapic_intr21),
88 IDTVEC(ioapic_intr22),
89 IDTVEC(ioapic_intr23),
90 IDTVEC(ioapic_intr24),
91 IDTVEC(ioapic_intr25),
92 IDTVEC(ioapic_intr26),
93 IDTVEC(ioapic_intr27),
94 IDTVEC(ioapic_intr28),
95 IDTVEC(ioapic_intr29),
96 IDTVEC(ioapic_intr30),
97 IDTVEC(ioapic_intr31),
98 IDTVEC(ioapic_intr32),
99 IDTVEC(ioapic_intr33),
100 IDTVEC(ioapic_intr34),
101 IDTVEC(ioapic_intr35),
102 IDTVEC(ioapic_intr36),
103 IDTVEC(ioapic_intr37),
104 IDTVEC(ioapic_intr38),
105 IDTVEC(ioapic_intr39),
106 IDTVEC(ioapic_intr40),
107 IDTVEC(ioapic_intr41),
108 IDTVEC(ioapic_intr42),
109 IDTVEC(ioapic_intr43),
110 IDTVEC(ioapic_intr44),
111 IDTVEC(ioapic_intr45),
112 IDTVEC(ioapic_intr46),
113 IDTVEC(ioapic_intr47),
114 IDTVEC(ioapic_intr48),
115 IDTVEC(ioapic_intr49),
116 IDTVEC(ioapic_intr50),
117 IDTVEC(ioapic_intr51),
118 IDTVEC(ioapic_intr52),
119 IDTVEC(ioapic_intr53),
120 IDTVEC(ioapic_intr54),
121 IDTVEC(ioapic_intr55),
122 IDTVEC(ioapic_intr56),
123 IDTVEC(ioapic_intr57),
124 IDTVEC(ioapic_intr58),
125 IDTVEC(ioapic_intr59),
126 IDTVEC(ioapic_intr60),
127 IDTVEC(ioapic_intr61),
128 IDTVEC(ioapic_intr62),
129 IDTVEC(ioapic_intr63),
130 IDTVEC(ioapic_intr64),
131 IDTVEC(ioapic_intr65),
132 IDTVEC(ioapic_intr66),
133 IDTVEC(ioapic_intr67),
134 IDTVEC(ioapic_intr68),
135 IDTVEC(ioapic_intr69),
136 IDTVEC(ioapic_intr70),
137 IDTVEC(ioapic_intr71),
138 IDTVEC(ioapic_intr72),
139 IDTVEC(ioapic_intr73),
140 IDTVEC(ioapic_intr74),
141 IDTVEC(ioapic_intr75),
142 IDTVEC(ioapic_intr76),
143 IDTVEC(ioapic_intr77),
144 IDTVEC(ioapic_intr78),
145 IDTVEC(ioapic_intr79),
146 IDTVEC(ioapic_intr80),
147 IDTVEC(ioapic_intr81),
148 IDTVEC(ioapic_intr82),
149 IDTVEC(ioapic_intr83),
150 IDTVEC(ioapic_intr84),
151 IDTVEC(ioapic_intr85),
152 IDTVEC(ioapic_intr86),
153 IDTVEC(ioapic_intr87),
154 IDTVEC(ioapic_intr88),
155 IDTVEC(ioapic_intr89),
156 IDTVEC(ioapic_intr90),
157 IDTVEC(ioapic_intr91),
158 IDTVEC(ioapic_intr92),
159 IDTVEC(ioapic_intr93),
160 IDTVEC(ioapic_intr94),
161 IDTVEC(ioapic_intr95),
162 IDTVEC(ioapic_intr96),
163 IDTVEC(ioapic_intr97),
164 IDTVEC(ioapic_intr98),
165 IDTVEC(ioapic_intr99),
166 IDTVEC(ioapic_intr100),
167 IDTVEC(ioapic_intr101),
168 IDTVEC(ioapic_intr102),
169 IDTVEC(ioapic_intr103),
170 IDTVEC(ioapic_intr104),
171 IDTVEC(ioapic_intr105),
172 IDTVEC(ioapic_intr106),
173 IDTVEC(ioapic_intr107),
174 IDTVEC(ioapic_intr108),
175 IDTVEC(ioapic_intr109),
176 IDTVEC(ioapic_intr110),
177 IDTVEC(ioapic_intr111),
178 IDTVEC(ioapic_intr112),
179 IDTVEC(ioapic_intr113),
180 IDTVEC(ioapic_intr114),
181 IDTVEC(ioapic_intr115),
182 IDTVEC(ioapic_intr116),
183 IDTVEC(ioapic_intr117),
184 IDTVEC(ioapic_intr118),
185 IDTVEC(ioapic_intr119),
186 IDTVEC(ioapic_intr120),
187 IDTVEC(ioapic_intr121),
188 IDTVEC(ioapic_intr122),
189 IDTVEC(ioapic_intr123),
190 IDTVEC(ioapic_intr124),
191 IDTVEC(ioapic_intr125),
192 IDTVEC(ioapic_intr126),
193 IDTVEC(ioapic_intr127),
194 IDTVEC(ioapic_intr128),
195 IDTVEC(ioapic_intr129),
196 IDTVEC(ioapic_intr130),
197 IDTVEC(ioapic_intr131),
198 IDTVEC(ioapic_intr132),
199 IDTVEC(ioapic_intr133),
200 IDTVEC(ioapic_intr134),
201 IDTVEC(ioapic_intr135),
202 IDTVEC(ioapic_intr136),
203 IDTVEC(ioapic_intr137),
204 IDTVEC(ioapic_intr138),
205 IDTVEC(ioapic_intr139),
206 IDTVEC(ioapic_intr140),
207 IDTVEC(ioapic_intr141),
208 IDTVEC(ioapic_intr142),
209 IDTVEC(ioapic_intr143),
210 IDTVEC(ioapic_intr144),
211 IDTVEC(ioapic_intr145),
212 IDTVEC(ioapic_intr146),
213 IDTVEC(ioapic_intr147),
214 IDTVEC(ioapic_intr148),
215 IDTVEC(ioapic_intr149),
216 IDTVEC(ioapic_intr150),
217 IDTVEC(ioapic_intr151),
218 IDTVEC(ioapic_intr152),
219 IDTVEC(ioapic_intr153),
220 IDTVEC(ioapic_intr154),
221 IDTVEC(ioapic_intr155),
222 IDTVEC(ioapic_intr156),
223 IDTVEC(ioapic_intr157),
224 IDTVEC(ioapic_intr158),
225 IDTVEC(ioapic_intr159),
226 IDTVEC(ioapic_intr160),
227 IDTVEC(ioapic_intr161),
228 IDTVEC(ioapic_intr162),
229 IDTVEC(ioapic_intr163),
230 IDTVEC(ioapic_intr164),
231 IDTVEC(ioapic_intr165),
232 IDTVEC(ioapic_intr166),
233 IDTVEC(ioapic_intr167),
234 IDTVEC(ioapic_intr168),
235 IDTVEC(ioapic_intr169),
236 IDTVEC(ioapic_intr170),
237 IDTVEC(ioapic_intr171),
238 IDTVEC(ioapic_intr172),
239 IDTVEC(ioapic_intr173),
240 IDTVEC(ioapic_intr174),
241 IDTVEC(ioapic_intr175),
242 IDTVEC(ioapic_intr176),
243 IDTVEC(ioapic_intr177),
244 IDTVEC(ioapic_intr178),
245 IDTVEC(ioapic_intr179),
246 IDTVEC(ioapic_intr180),
247 IDTVEC(ioapic_intr181),
248 IDTVEC(ioapic_intr182),
249 IDTVEC(ioapic_intr183),
250 IDTVEC(ioapic_intr184),
251 IDTVEC(ioapic_intr185),
252 IDTVEC(ioapic_intr186),
253 IDTVEC(ioapic_intr187),
254 IDTVEC(ioapic_intr188),
255 IDTVEC(ioapic_intr189),
256 IDTVEC(ioapic_intr190),
257 IDTVEC(ioapic_intr191);
258
259static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
260 &IDTVEC(ioapic_intr0),
261 &IDTVEC(ioapic_intr1),
262 &IDTVEC(ioapic_intr2),
263 &IDTVEC(ioapic_intr3),
264 &IDTVEC(ioapic_intr4),
265 &IDTVEC(ioapic_intr5),
266 &IDTVEC(ioapic_intr6),
267 &IDTVEC(ioapic_intr7),
268 &IDTVEC(ioapic_intr8),
269 &IDTVEC(ioapic_intr9),
270 &IDTVEC(ioapic_intr10),
271 &IDTVEC(ioapic_intr11),
272 &IDTVEC(ioapic_intr12),
273 &IDTVEC(ioapic_intr13),
274 &IDTVEC(ioapic_intr14),
275 &IDTVEC(ioapic_intr15),
276 &IDTVEC(ioapic_intr16),
277 &IDTVEC(ioapic_intr17),
278 &IDTVEC(ioapic_intr18),
279 &IDTVEC(ioapic_intr19),
280 &IDTVEC(ioapic_intr20),
281 &IDTVEC(ioapic_intr21),
282 &IDTVEC(ioapic_intr22),
283 &IDTVEC(ioapic_intr23),
284 &IDTVEC(ioapic_intr24),
285 &IDTVEC(ioapic_intr25),
286 &IDTVEC(ioapic_intr26),
287 &IDTVEC(ioapic_intr27),
288 &IDTVEC(ioapic_intr28),
289 &IDTVEC(ioapic_intr29),
290 &IDTVEC(ioapic_intr30),
291 &IDTVEC(ioapic_intr31),
292 &IDTVEC(ioapic_intr32),
293 &IDTVEC(ioapic_intr33),
294 &IDTVEC(ioapic_intr34),
295 &IDTVEC(ioapic_intr35),
296 &IDTVEC(ioapic_intr36),
297 &IDTVEC(ioapic_intr37),
298 &IDTVEC(ioapic_intr38),
299 &IDTVEC(ioapic_intr39),
300 &IDTVEC(ioapic_intr40),
301 &IDTVEC(ioapic_intr41),
302 &IDTVEC(ioapic_intr42),
303 &IDTVEC(ioapic_intr43),
304 &IDTVEC(ioapic_intr44),
305 &IDTVEC(ioapic_intr45),
306 &IDTVEC(ioapic_intr46),
307 &IDTVEC(ioapic_intr47),
308 &IDTVEC(ioapic_intr48),
309 &IDTVEC(ioapic_intr49),
310 &IDTVEC(ioapic_intr50),
311 &IDTVEC(ioapic_intr51),
312 &IDTVEC(ioapic_intr52),
313 &IDTVEC(ioapic_intr53),
314 &IDTVEC(ioapic_intr54),
315 &IDTVEC(ioapic_intr55),
316 &IDTVEC(ioapic_intr56),
317 &IDTVEC(ioapic_intr57),
318 &IDTVEC(ioapic_intr58),
319 &IDTVEC(ioapic_intr59),
320 &IDTVEC(ioapic_intr60),
321 &IDTVEC(ioapic_intr61),
322 &IDTVEC(ioapic_intr62),
323 &IDTVEC(ioapic_intr63),
324 &IDTVEC(ioapic_intr64),
325 &IDTVEC(ioapic_intr65),
326 &IDTVEC(ioapic_intr66),
327 &IDTVEC(ioapic_intr67),
328 &IDTVEC(ioapic_intr68),
329 &IDTVEC(ioapic_intr69),
330 &IDTVEC(ioapic_intr70),
331 &IDTVEC(ioapic_intr71),
332 &IDTVEC(ioapic_intr72),
333 &IDTVEC(ioapic_intr73),
334 &IDTVEC(ioapic_intr74),
335 &IDTVEC(ioapic_intr75),
336 &IDTVEC(ioapic_intr76),
337 &IDTVEC(ioapic_intr77),
338 &IDTVEC(ioapic_intr78),
339 &IDTVEC(ioapic_intr79),
340 &IDTVEC(ioapic_intr80),
341 &IDTVEC(ioapic_intr81),
342 &IDTVEC(ioapic_intr82),
343 &IDTVEC(ioapic_intr83),
344 &IDTVEC(ioapic_intr84),
345 &IDTVEC(ioapic_intr85),
346 &IDTVEC(ioapic_intr86),
347 &IDTVEC(ioapic_intr87),
348 &IDTVEC(ioapic_intr88),
349 &IDTVEC(ioapic_intr89),
350 &IDTVEC(ioapic_intr90),
351 &IDTVEC(ioapic_intr91),
352 &IDTVEC(ioapic_intr92),
353 &IDTVEC(ioapic_intr93),
354 &IDTVEC(ioapic_intr94),
355 &IDTVEC(ioapic_intr95),
356 &IDTVEC(ioapic_intr96),
357 &IDTVEC(ioapic_intr97),
358 &IDTVEC(ioapic_intr98),
359 &IDTVEC(ioapic_intr99),
360 &IDTVEC(ioapic_intr100),
361 &IDTVEC(ioapic_intr101),
362 &IDTVEC(ioapic_intr102),
363 &IDTVEC(ioapic_intr103),
364 &IDTVEC(ioapic_intr104),
365 &IDTVEC(ioapic_intr105),
366 &IDTVEC(ioapic_intr106),
367 &IDTVEC(ioapic_intr107),
368 &IDTVEC(ioapic_intr108),
369 &IDTVEC(ioapic_intr109),
370 &IDTVEC(ioapic_intr110),
371 &IDTVEC(ioapic_intr111),
372 &IDTVEC(ioapic_intr112),
373 &IDTVEC(ioapic_intr113),
374 &IDTVEC(ioapic_intr114),
375 &IDTVEC(ioapic_intr115),
376 &IDTVEC(ioapic_intr116),
377 &IDTVEC(ioapic_intr117),
378 &IDTVEC(ioapic_intr118),
379 &IDTVEC(ioapic_intr119),
380 &IDTVEC(ioapic_intr120),
381 &IDTVEC(ioapic_intr121),
382 &IDTVEC(ioapic_intr122),
383 &IDTVEC(ioapic_intr123),
384 &IDTVEC(ioapic_intr124),
385 &IDTVEC(ioapic_intr125),
386 &IDTVEC(ioapic_intr126),
387 &IDTVEC(ioapic_intr127),
388 &IDTVEC(ioapic_intr128),
389 &IDTVEC(ioapic_intr129),
390 &IDTVEC(ioapic_intr130),
391 &IDTVEC(ioapic_intr131),
392 &IDTVEC(ioapic_intr132),
393 &IDTVEC(ioapic_intr133),
394 &IDTVEC(ioapic_intr134),
395 &IDTVEC(ioapic_intr135),
396 &IDTVEC(ioapic_intr136),
397 &IDTVEC(ioapic_intr137),
398 &IDTVEC(ioapic_intr138),
399 &IDTVEC(ioapic_intr139),
400 &IDTVEC(ioapic_intr140),
401 &IDTVEC(ioapic_intr141),
402 &IDTVEC(ioapic_intr142),
403 &IDTVEC(ioapic_intr143),
404 &IDTVEC(ioapic_intr144),
405 &IDTVEC(ioapic_intr145),
406 &IDTVEC(ioapic_intr146),
407 &IDTVEC(ioapic_intr147),
408 &IDTVEC(ioapic_intr148),
409 &IDTVEC(ioapic_intr149),
410 &IDTVEC(ioapic_intr150),
411 &IDTVEC(ioapic_intr151),
412 &IDTVEC(ioapic_intr152),
413 &IDTVEC(ioapic_intr153),
414 &IDTVEC(ioapic_intr154),
415 &IDTVEC(ioapic_intr155),
416 &IDTVEC(ioapic_intr156),
417 &IDTVEC(ioapic_intr157),
418 &IDTVEC(ioapic_intr158),
419 &IDTVEC(ioapic_intr159),
420 &IDTVEC(ioapic_intr160),
421 &IDTVEC(ioapic_intr161),
422 &IDTVEC(ioapic_intr162),
423 &IDTVEC(ioapic_intr163),
424 &IDTVEC(ioapic_intr164),
425 &IDTVEC(ioapic_intr165),
426 &IDTVEC(ioapic_intr166),
427 &IDTVEC(ioapic_intr167),
428 &IDTVEC(ioapic_intr168),
429 &IDTVEC(ioapic_intr169),
430 &IDTVEC(ioapic_intr170),
431 &IDTVEC(ioapic_intr171),
432 &IDTVEC(ioapic_intr172),
433 &IDTVEC(ioapic_intr173),
434 &IDTVEC(ioapic_intr174),
435 &IDTVEC(ioapic_intr175),
436 &IDTVEC(ioapic_intr176),
437 &IDTVEC(ioapic_intr177),
438 &IDTVEC(ioapic_intr178),
439 &IDTVEC(ioapic_intr179),
440 &IDTVEC(ioapic_intr180),
441 &IDTVEC(ioapic_intr181),
442 &IDTVEC(ioapic_intr182),
443 &IDTVEC(ioapic_intr183),
444 &IDTVEC(ioapic_intr184),
445 &IDTVEC(ioapic_intr185),
446 &IDTVEC(ioapic_intr186),
447 &IDTVEC(ioapic_intr187),
448 &IDTVEC(ioapic_intr188),
449 &IDTVEC(ioapic_intr189),
450 &IDTVEC(ioapic_intr190),
451 &IDTVEC(ioapic_intr191)
c571da4a 452};
10ff1029 453
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454#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
455
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456static struct ioapic_irqmap {
457 int im_type; /* IOAPIC_IMT_ */
458 enum intr_trigger im_trig;
f6915355 459 enum intr_polarity im_pola;
a3dd9120 460 int im_gsi;
d1ae7328 461 uint32_t im_flags; /* IOAPIC_IMF_ */
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462} ioapic_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
463
464#define IOAPIC_IMT_UNUSED 0
465#define IOAPIC_IMT_RESERVED 1
466#define IOAPIC_IMT_LINE 2
474ba684 467#define IOAPIC_IMT_SYSCALL 3
a3dd9120 468
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469#define IOAPIC_IMF_CONF 0x1
470
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471extern void IOAPIC_INTREN(int);
472extern void IOAPIC_INTRDIS(int);
473
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474extern int imcr_present;
475
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476static int ioapic_setvar(int, const void *);
477static int ioapic_getvar(int, void *);
478static int ioapic_vectorctl(int, int, int);
479static void ioapic_finalize(void);
480static void ioapic_cleanup(void);
481static void ioapic_setdefault(void);
7bf5fa56 482static void ioapic_stabilize(void);
a3dd9120 483static void ioapic_initmap(void);
d1ae7328 484static void ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
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485static void ioapic_abi_intren(int);
486static void ioapic_abi_intrdis(int);
9e0e3f85 487
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488struct machintr_abi MachIntrABI_IOAPIC = {
489 MACHINTR_IOAPIC,
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490 .intrdis = ioapic_abi_intrdis,
491 .intren = ioapic_abi_intren,
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492 .vectorctl = ioapic_vectorctl,
493 .setvar = ioapic_setvar,
494 .getvar = ioapic_getvar,
495 .finalize = ioapic_finalize,
496 .cleanup = ioapic_cleanup,
7bf5fa56 497 .setdefault = ioapic_setdefault,
a3dd9120 498 .stabilize = ioapic_stabilize,
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499 .initmap = ioapic_initmap,
500 .intr_config = ioapic_intr_config
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501};
502
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503static int ioapic_abi_extint_irq = -1;
504
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505struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
506
507static void
508ioapic_abi_intren(int irq)
509{
510 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
511 kprintf("ioapic_abi_intren invalid irq %d\n", irq);
512 return;
513 }
514 IOAPIC_INTREN(irq);
515}
516
517static void
518ioapic_abi_intrdis(int irq)
519{
520 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
521 kprintf("ioapic_abi_intrdis invalid irq %d\n", irq);
522 return;
523 }
524 IOAPIC_INTRDIS(irq);
525}
526
37e7efec 527static int
9e0e3f85 528ioapic_setvar(int varid, const void *buf)
37e7efec 529{
9d758cc4 530 return ENOENT;
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531}
532
533static int
9e0e3f85 534ioapic_getvar(int varid, void *buf)
37e7efec 535{
9d758cc4 536 return ENOENT;
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537}
538
37e7efec 539static void
9e0e3f85 540ioapic_finalize(void)
37e7efec 541{
e0918665 542 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 543 KKASSERT(ioapic_enable);
10db3cc6 544
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545 /*
546 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 547 * from the BSP.
54e1df6b 548 */
9d758cc4 549 if (imcr_present) {
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550 outb(0x22, 0x70); /* select IMCR */
551 outb(0x23, 0x01); /* disconnect 8259 */
552 }
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553}
554
0b692e79
MD
555/*
556 * This routine is called after physical interrupts are enabled but before
557 * the critical section is released. We need to clean out any interrupts
558 * that had already been posted to the cpu.
559 */
560static void
9e0e3f85 561ioapic_cleanup(void)
0b692e79 562{
c263294b 563 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
0b692e79
MD
564}
565
7bf5fa56
SZ
566/* Must never be called */
567static void
568ioapic_stabilize(void)
569{
570 panic("ioapic_stabilize() is called\n");
571}
572
54e1df6b 573static int
9e0e3f85 574ioapic_vectorctl(int op, int intr, int flags)
10ff1029 575{
54e1df6b
SZ
576 int error;
577 int vector;
578 int select;
579 uint32_t value;
580 u_long ef;
10ff1029 581
9e0e3f85 582 if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
474ba684 583 intr == IOAPIC_HWI_SYSCALL)
54e1df6b 584 return EINVAL;
10ff1029 585
54e1df6b
SZ
586 ef = read_eflags();
587 cpu_disable_intr();
588 error = 0;
10ff1029 589
54e1df6b
SZ
590 switch(op) {
591 case MACHINTR_VECTOR_SETUP:
592 vector = IDT_OFFSET + intr;
9e0e3f85 593 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT,
54e1df6b 594 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
35408d22 595
54e1df6b
SZ
596 /*
597 * Now reprogram the vector in the IO APIC. In order to avoid
598 * losing an EOI for a level interrupt, which is vector based,
599 * make sure that the IO APIC is programmed for edge-triggering
600 * first, then reprogrammed with the new vector. This should
601 * clear the IRR bit.
602 */
603 if (int_to_apicintpin[intr].ioapic >= 0) {
54e1df6b
SZ
604 imen_lock();
605
606 select = int_to_apicintpin[intr].redirindex;
e17120aa 607 value = ioapic_read(int_to_apicintpin[intr].apic_address,
9e0e3f85 608 select);
54e1df6b
SZ
609 value |= IOART_INTMSET;
610
e17120aa 611 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 612 select, (value & ~APIC_TRIGMOD_MASK));
e17120aa 613 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 614 select, (value & ~IOART_INTVEC) | vector);
54e1df6b
SZ
615
616 imen_unlock();
617 }
618
619 machintr_intren(intr);
620 break;
621
622 case MACHINTR_VECTOR_TEARDOWN:
623 /*
624 * Teardown an interrupt vector. The vector should already be
625 * installed in the cpu's IDT, but make sure.
626 */
627 machintr_intrdis(intr);
628
629 vector = IDT_OFFSET + intr;
9e0e3f85 630 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT, SEL_KPL,
54e1df6b
SZ
631 GSEL(GCODE_SEL, SEL_KPL));
632
633 /*
54e1df6b
SZ
634 * In order to avoid losing an EOI for a level interrupt, which
635 * is vector based, make sure that the IO APIC is programmed for
636 * edge-triggering first, then reprogrammed with the new vector.
637 * This should clear the IRR bit.
638 */
639 if (int_to_apicintpin[intr].ioapic >= 0) {
640 imen_lock();
641
642 select = int_to_apicintpin[intr].redirindex;
e17120aa 643 value = ioapic_read(int_to_apicintpin[intr].apic_address,
9e0e3f85 644 select);
54e1df6b 645
e17120aa 646 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 647 select, (value & ~APIC_TRIGMOD_MASK));
e17120aa 648 ioapic_write(int_to_apicintpin[intr].apic_address,
9e0e3f85 649 select, (value & ~IOART_INTVEC) | vector);
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SZ
650
651 imen_unlock();
652 }
653 break;
654
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SZ
655 default:
656 error = EOPNOTSUPP;
657 break;
35408d22 658 }
10ff1029 659
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660 write_eflags(ef);
661 return error;
662}
06f5be02 663
10db3cc6 664static void
9e0e3f85 665ioapic_setdefault(void)
10db3cc6
SZ
666{
667 int intr;
668
9e0e3f85 669 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 670 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 671 continue;
9e0e3f85 672 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
10db3cc6
SZ
673 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
674 }
675}
676
a3dd9120
SZ
677static void
678ioapic_initmap(void)
679{
680 int i;
681
c36b581c
SZ
682 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
683 ioapic_irqmaps[i].im_gsi = -1;
474ba684 684 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
a3dd9120
SZ
685}
686
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687void
688ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
689 enum intr_polarity pola)
690{
691 struct apic_intmapinfo *info;
692 struct ioapic_irqmap *map;
693 void *ioaddr;
694 int pin;
695
696 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
697 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ
698
699 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
700 map = &ioapic_irqmaps[irq];
701
702 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
703 map->im_type = IOAPIC_IMT_LINE;
704
705 map->im_gsi = gsi;
706 map->im_trig = trig;
707 map->im_pola = pola;
708
709 if (bootverbose) {
4ecd5d4d
SZ
710 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
711 irq, map->im_gsi,
712 intr_str_trigger(map->im_trig),
713 intr_str_polarity(map->im_pola));
929c940f
SZ
714 }
715
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SZ
716 pin = ioapic_gsi_pin(map->im_gsi);
717 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
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SZ
718
719 info = &int_to_apicintpin[irq];
720
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SZ
721 imen_lock();
722
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SZ
723 info->ioapic = 0; /* XXX unused */
724 info->int_pin = pin;
725 info->apic_address = ioaddr;
726 info->redirindex = IOAPIC_REDTBL + (2 * pin);
727 info->flags = IOAPIC_IM_FLAG_MASKED;
d1ae7328
SZ
728 if (map->im_trig == INTR_TRIGGER_LEVEL)
729 info->flags |= IOAPIC_IM_FLAG_LEVEL;
730
731 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
732 map->im_trig, map->im_pola);
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733
734 imen_unlock();
d1ae7328
SZ
735}
736
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737void
738ioapic_abi_fixup_irqmap(void)
739{
740 int i;
741
742 for (i = 0; i < 16; ++i) {
743 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
744
745 if (map->im_type == IOAPIC_IMT_UNUSED) {
746 map->im_type = IOAPIC_IMT_RESERVED;
747 if (bootverbose)
748 kprintf("IOAPIC: irq %d reserved\n", i);
749 }
750 }
751}
752
e90e7ac4
SZ
753int
754ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
755{
756 int irq;
757
758 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
759 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
760
761 for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
762 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
763
764 if (map->im_gsi == gsi) {
765 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
766
767 if (map->im_flags & IOAPIC_IMF_CONF) {
768 if (map->im_trig != trig ||
769 map->im_pola != pola)
770 return -1;
771 }
772 return irq;
773 }
774 }
775 return -1;
776}
777
778int
779ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
780{
781 const struct ioapic_irqmap *map;
782
783 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
784 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
785
786 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
787 return -1;
788 map = &ioapic_irqmaps[irq];
789
790 if (map->im_type != IOAPIC_IMT_LINE)
791 return -1;
792
793 if (map->im_flags & IOAPIC_IMF_CONF) {
794 if (map->im_trig != trig || map->im_pola != pola)
795 return -1;
796 }
797 return irq;
798}
799
d1ae7328
SZ
800static void
801ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
802{
803 struct apic_intmapinfo *info;
804 struct ioapic_irqmap *map;
805 void *ioaddr;
806 int pin;
807
d1ae7328
SZ
808 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
809 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328
SZ
810
811 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
812 map = &ioapic_irqmaps[irq];
813
814 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
815
7962296e 816#ifdef notyet
d1ae7328
SZ
817 if (map->im_flags & IOAPIC_IMF_CONF) {
818 if (trig != map->im_trig) {
4ecd5d4d
SZ
819 panic("ioapic_intr_config: trig %s -> %s\n",
820 intr_str_trigger(map->im_trig),
821 intr_str_trigger(trig));
d1ae7328
SZ
822 }
823 if (pola != map->im_pola) {
824 panic("ioapic_intr_config: pola %s -> %s\n",
4ecd5d4d
SZ
825 intr_str_polarity(map->im_pola),
826 intr_str_polarity(pola));
d1ae7328
SZ
827 }
828 return;
829 }
7962296e 830#endif
d1ae7328
SZ
831 map->im_flags |= IOAPIC_IMF_CONF;
832
833 if (trig == map->im_trig && pola == map->im_pola)
834 return;
835
836 if (bootverbose) {
4ecd5d4d
SZ
837 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
838 irq, map->im_gsi,
839 intr_str_trigger(map->im_trig),
840 intr_str_polarity(map->im_pola),
841 intr_str_trigger(trig),
842 intr_str_polarity(pola));
d1ae7328 843 }
d1ae7328
SZ
844 map->im_trig = trig;
845 map->im_pola = pola;
846
847 pin = ioapic_gsi_pin(map->im_gsi);
848 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
849
850 info = &int_to_apicintpin[irq];
851
7bceaa10
SZ
852 imen_lock();
853
d1ae7328
SZ
854 info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
855 if (map->im_trig == INTR_TRIGGER_LEVEL)
929c940f
SZ
856 info->flags |= IOAPIC_IM_FLAG_LEVEL;
857
ecec8ddc
SZ
858 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
859 map->im_trig, map->im_pola);
7bceaa10
SZ
860
861 imen_unlock();
929c940f
SZ
862}
863
6b809ec7
SZ
864int
865ioapic_abi_extint_irqmap(int irq)
866{
867 struct apic_intmapinfo *info;
868 struct ioapic_irqmap *map;
869 void *ioaddr;
870 int pin, error, vec;
871
872 vec = IDT_OFFSET + irq;
873
874 if (ioapic_abi_extint_irq == irq)
875 return 0;
876 else if (ioapic_abi_extint_irq >= 0)
877 return EEXIST;
878
879 error = icu_ioapic_extint(irq, vec);
880 if (error)
881 return error;
882
883 map = &ioapic_irqmaps[irq];
884
885 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
886 map->im_type == IOAPIC_IMT_LINE);
887 if (map->im_type == IOAPIC_IMT_LINE) {
888 if (map->im_flags & IOAPIC_IMF_CONF)
889 return EEXIST;
890 }
891 ioapic_abi_extint_irq = irq;
892
893 map->im_type = IOAPIC_IMT_LINE;
894 map->im_trig = INTR_TRIGGER_EDGE;
895 map->im_pola = INTR_POLARITY_HIGH;
896 map->im_flags = IOAPIC_IMF_CONF;
897
898 map->im_gsi = ioapic_extpin_gsi();
899 KKASSERT(map->im_gsi >= 0);
900
901 if (bootverbose) {
4ecd5d4d
SZ
902 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
903 irq, map->im_gsi,
904 intr_str_trigger(map->im_trig),
905 intr_str_polarity(map->im_pola));
6b809ec7
SZ
906 }
907
908 pin = ioapic_gsi_pin(map->im_gsi);
909 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
910
911 info = &int_to_apicintpin[irq];
912
913 imen_lock();
914
915 info->ioapic = 0; /* XXX unused */
916 info->int_pin = pin;
917 info->apic_address = ioaddr;
918 info->redirindex = IOAPIC_REDTBL + (2 * pin);
919 info->flags = IOAPIC_IM_FLAG_MASKED;
920
921 ioapic_extpin_setup(ioaddr, pin, vec);
922
923 imen_unlock();
924
925 return 0;
926}