i386: Allow UP kernel to use LAPIC timer and I/O APIC
[dragonfly.git] / sys / platform / pc32 / apic / lapic.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
b12a1521 30#include <sys/kernel.h>
23b08e03 31#include <sys/bus.h>
e0918665 32#include <sys/machintr.h>
72740893 33#include <machine/globaldata.h>
984263bc 34#include <machine/smp.h>
90e8a35b 35#include <machine/cputypes.h>
d595a6c0 36#include <machine/md_var.h>
ad52b37b 37#include <machine/pmap.h>
3340ac41 38#include <machine_base/apic/lapic.h>
ed4d621d 39#include <machine_base/apic/ioapic.h>
929c940f 40#include <machine_base/apic/ioapic_abi.h>
d631ab59 41#include <machine_base/icu/icu_var.h>
984263bc 42#include <machine/segments.h>
96728c05 43#include <sys/thread2.h>
984263bc 44
87cf6827 45#include <machine/intr_machdep.h>
984263bc 46
2abaa030
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47extern int naps;
48
cb7d6921 49volatile lapic_t *lapic;
ad52b37b 50
b52c8db0 51static void lapic_timer_calibrate(void);
086575e9 52static void lapic_timer_set_divisor(int);
a9e511df 53static void lapic_timer_fixup_handler(void *);
76c58571 54static void lapic_timer_restart_handler(void *);
c5b8324c 55
78ea5a2a
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56void lapic_timer_process(void);
57void lapic_timer_process_frame(struct intrframe *);
c5b8324c 58
ef612539 59static int lapic_timer_enable = 1;
c5b8324c 60TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 61
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62static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
63static void lapic_timer_intr_enable(struct cputimer_intr *);
64static void lapic_timer_intr_restart(struct cputimer_intr *);
65static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
66
67static struct cputimer_intr lapic_cputimer_intr = {
68 .freq = 0,
69 .reload = lapic_timer_intr_reload,
70 .enable = lapic_timer_intr_enable,
71 .config = cputimer_intr_default_config,
72 .restart = lapic_timer_intr_restart,
73 .pmfixup = lapic_timer_intr_pmfixup,
74 .initclock = cputimer_intr_default_initclock,
75 .next = SLIST_ENTRY_INITIALIZER,
76 .name = "lapic",
77 .type = CPUTIMER_INTR_LAPIC,
78 .prio = CPUTIMER_INTR_PRIO_LAPIC,
79 .caps = CPUTIMER_INTR_CAP_NONE
80};
81
086575e9
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82static int lapic_timer_divisor_idx = -1;
83static const uint32_t lapic_timer_divisors[] = {
84 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
85 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
86};
c157ff7a 87#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
086575e9 88
68d62ec3 89/*
2d901d56 90 * APIC ID <-> CPU ID mapping structures.
68d62ec3 91 */
2d901d56
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92int cpu_id_to_apic_id[NAPICID];
93int apic_id_to_cpu_id[NAPICID];
1d6d7089 94int lapic_enable = 1;
68d62ec3 95
984263bc 96/*
d99d4acb 97 * Enable LAPIC, configure interrupts.
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98 */
99void
5ddeabb9 100lapic_init(boolean_t bsp)
984263bc 101{
78ea5a2a 102 uint32_t timer;
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103 u_int temp;
104
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105 /*
106 * Install vectors
107 *
108 * Since IDT is shared between BSP and APs, these vectors
109 * only need to be installed once; we do it on BSP.
110 */
111 if (bsp) {
112 /* Install a 'Spurious INTerrupt' vector */
113 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
114 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
115
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116 /* Install a timer vector */
117 setidt(XTIMER_OFFSET, Xtimer,
118 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
119
120#ifdef SMP
dbfb3a5a
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121 /* Install an inter-CPU IPI for TLB invalidation */
122 setidt(XINVLTLB_OFFSET, Xinvltlb,
123 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
124
125 /* Install an inter-CPU IPI for IPIQ messaging */
126 setidt(XIPIQ_OFFSET, Xipiq,
127 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
128
dbfb3a5a
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129 /* Install an inter-CPU IPI for CPU stop/restart */
130 setidt(XCPUSTOP_OFFSET, Xcpustop,
131 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1e7aaefa 132#endif
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133 }
134
9d6bf2df 135 /*
d99d4acb 136 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
97359a5b
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137 * aggregate interrupt input from the 8259. The INTA cycle
138 * will be routed to the external controller (the 8259) which
139 * is expected to supply the vector.
140 *
141 * Must be setup edge triggered, active high.
142 *
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143 * Disable LINT0 on BSP, if I/O APIC is enabled.
144 *
d99d4acb 145 * Disable LINT0 on the APs. It doesn't matter what delivery
97359a5b 146 * mode we use because we leave it masked.
9d6bf2df 147 */
cb7d6921 148 temp = lapic->lvt_lint0;
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149 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
150 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
4d08e038 151 if (bsp) {
9d6bf2df 152 temp |= APIC_LVT_DM_EXTINT;
f45bfca0 153 if (ioapic_enable)
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154 temp |= APIC_LVT_MASKED;
155 } else {
97359a5b 156 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
4d08e038 157 }
cb7d6921 158 lapic->lvt_lint0 = temp;
984263bc 159
9d6bf2df 160 /*
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161 * Setup LINT1 as NMI.
162 *
163 * Must be setup edge trigger, active high.
164 *
165 * Enable LINT1 on BSP, if I/O APIC is enabled.
166 *
167 * Disable LINT1 on the APs.
9d6bf2df 168 */
cb7d6921 169 temp = lapic->lvt_lint1;
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170 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
171 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
172 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
f45bfca0 173 if (bsp && ioapic_enable)
4d08e038 174 temp &= ~APIC_LVT_MASKED;
cb7d6921 175 lapic->lvt_lint1 = temp;
984263bc 176
c6a1aabe 177 /*
d99d4acb 178 * Mask the LAPIC error interrupt, LAPIC performance counter
78ea5a2a 179 * interrupt.
c6a1aabe 180 */
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SZ
181 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
182 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
78ea5a2a 183
d99d4acb
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184 /*
185 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
186 */
cb7d6921 187 timer = lapic->lvt_timer;
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188 timer &= ~APIC_LVTT_VECTOR;
189 timer |= XTIMER_OFFSET;
190 timer |= APIC_LVTT_MASKED;
cb7d6921 191 lapic->lvt_timer = timer;
c6a1aabe 192
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193 /*
194 * Set the Task Priority Register as needed. At the moment allow
195 * interrupts on all cpus (the APs will remain CLId until they are
1971051d 196 * ready to deal).
d9eea1a5 197 */
cb7d6921 198 temp = lapic->tpr;
984263bc 199 temp &= ~APIC_TPR_PRIO; /* clear priority field */
cb7d6921 200 lapic->tpr = temp;
984263bc 201
97359a5b 202 /*
d99d4acb 203 * Enable the LAPIC
97359a5b 204 */
cb7d6921 205 temp = lapic->svr;
d99d4acb 206 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
97359a5b 207 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 208
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209 /*
210 * Set the spurious interrupt vector. The low 4 bits of the vector
211 * must be 1111.
212 */
213 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 214 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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MD
215 temp &= ~APIC_SVR_VECTOR;
216 temp |= XSPURIOUSINT_OFFSET;
984263bc 217
cb7d6921 218 lapic->svr = temp;
984263bc 219
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220 /*
221 * Pump out a few EOIs to clean out interrupts that got through
222 * before we were able to set the TPR.
223 */
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224 lapic->eoi = 0;
225 lapic->eoi = 0;
226 lapic->eoi = 0;
0b692e79 227
c5b8324c 228 if (bsp) {
b52c8db0 229 lapic_timer_calibrate();
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230 if (lapic_timer_enable) {
231 cputimer_intr_register(&lapic_cputimer_intr);
232 cputimer_intr_select(&lapic_cputimer_intr, 0);
233 }
c5b8324c 234 } else {
086575e9 235 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 236 }
b52c8db0 237
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238 if (bootverbose)
239 apic_dump("apic_initialize()");
240}
241
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242static void
243lapic_timer_set_divisor(int divisor_idx)
244{
245 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
cb7d6921 246 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
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247}
248
249static void
250lapic_timer_oneshot(u_int count)
251{
252 uint32_t value;
253
cb7d6921 254 value = lapic->lvt_timer;
b52c8db0 255 value &= ~APIC_LVTT_PERIODIC;
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256 lapic->lvt_timer = value;
257 lapic->icr_timer = count;
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258}
259
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260static void
261lapic_timer_oneshot_quick(u_int count)
262{
cb7d6921 263 lapic->icr_timer = count;
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264}
265
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266static void
267lapic_timer_calibrate(void)
268{
47bdf646 269 sysclock_t value;
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270
271 /* Try to calibrate the local APIC timer. */
272 for (lapic_timer_divisor_idx = 0;
273 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
274 lapic_timer_divisor_idx++) {
275 lapic_timer_set_divisor(lapic_timer_divisor_idx);
276 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
277 DELAY(2000000);
cb7d6921 278 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
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279 if (value != APIC_TIMER_MAX_COUNT)
280 break;
281 }
282 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
283 panic("lapic: no proper timer divisor?!\n");
ef612539 284 lapic_cputimer_intr.freq = value / 2;
b52c8db0 285
47bdf646 286 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 287 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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288}
289
c5b8324c
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290static void
291lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
292{
293 sysclock_t count;
294
295 gd->gd_timer_running = 0;
296
297 count = sys_cputimer->count();
298 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
299 systimer_intr(&count, 0, frame);
300}
301
78ea5a2a
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302void
303lapic_timer_process(void)
304{
ae48d6cd 305 lapic_timer_process_oncpu(mycpu, NULL);
78ea5a2a
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306}
307
308void
309lapic_timer_process_frame(struct intrframe *frame)
310{
ae48d6cd 311 lapic_timer_process_oncpu(mycpu, frame);
b12a1521
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312}
313
c5b8324c 314static void
ef612539 315lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
c5b8324c
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316{
317 struct globaldata *gd = mycpu;
318
ef612539 319 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
c5b8324c
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320 if (reload < 2)
321 reload = 2;
322
323 if (gd->gd_timer_running) {
cb7d6921 324 if (reload < lapic->ccr_timer)
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325 lapic_timer_oneshot_quick(reload);
326 } else {
327 gd->gd_timer_running = 1;
328 lapic_timer_oneshot_quick(reload);
329 }
330}
331
ef612539
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332static void
333lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
6198c499
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334{
335 uint32_t timer;
336
cb7d6921 337 timer = lapic->lvt_timer;
6198c499 338 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
cb7d6921 339 lapic->lvt_timer = timer;
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340
341 lapic_timer_fixup_handler(NULL);
342}
343
344static void
76c58571 345lapic_timer_fixup_handler(void *arg)
a9e511df 346{
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SZ
347 int *started = arg;
348
349 if (started != NULL)
350 *started = 0;
351
90e8a35b 352 if (cpu_vendor_id == CPU_VENDOR_AMD) {
a9e511df
SZ
353 /*
354 * Detect the presence of C1E capability mostly on latest
355 * dual-cores (or future) k8 family. This feature renders
356 * the local APIC timer dead, so we disable it by reading
357 * the Interrupt Pending Message register and clearing both
358 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
359 *
360 * Reference:
361 * "BIOS and Kernel Developer's Guide for AMD NPT
362 * Family 0Fh Processors"
363 * #32559 revision 3.00
364 */
365 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
366 (cpu_id & 0x0fff0000) >= 0x00040000) {
367 uint64_t msr;
368
369 msr = rdmsr(0xc0010055);
370 if (msr & 0x18000000) {
371 struct globaldata *gd = mycpu;
372
373 kprintf("cpu%d: AMD C1E detected\n",
374 gd->gd_cpuid);
375 wrmsr(0xc0010055, msr & ~0x18000000ULL);
376
377 /*
378 * We are kinda stalled;
379 * kick start again.
380 */
381 gd->gd_timer_running = 1;
382 lapic_timer_oneshot_quick(2);
76c58571
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383
384 if (started != NULL)
385 *started = 1;
a9e511df
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386 }
387 }
388 }
389}
390
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391static void
392lapic_timer_restart_handler(void *dummy __unused)
393{
394 int started;
395
396 lapic_timer_fixup_handler(&started);
397 if (!started) {
398 struct globaldata *gd = mycpu;
399
400 gd->gd_timer_running = 1;
401 lapic_timer_oneshot_quick(2);
402 }
403}
404
a9e511df
SZ
405/*
406 * This function is called only by ACPI-CA code currently:
407 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
408 * module controls PM. So once ACPI-CA is attached, we try
409 * to apply the fixup to prevent LAPIC timer from hanging.
410 */
ef612539
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411static void
412lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 413{
1e7aaefa 414#ifdef SMP
ef612539
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415 lwkt_send_ipiq_mask(smp_active_mask,
416 lapic_timer_fixup_handler, NULL);
1e7aaefa
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417#else
418 lapic_timer_fixup_handler(NULL);
419#endif
6198c499
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420}
421
ef612539
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422static void
423lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 424{
1e7aaefa 425#ifdef SMP
76c58571 426 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
1e7aaefa
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427#else
428 lapic_timer_restart_handler(NULL);
429#endif
76c58571
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430}
431
b52c8db0 432
984263bc
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433/*
434 * dump contents of local APIC registers
435 */
436void
437apic_dump(char* str)
438{
26be20a0
SW
439 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
440 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
cb7d6921 441 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
984263bc
MD
442}
443
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444#ifdef SMP
445
984263bc
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446/*
447 * Inter Processor Interrupt functions.
448 */
449
984263bc
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450/*
451 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
452 *
453 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
454 * vector is any valid SYSTEM INT vector
455 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
MD
456 *
457 * A backlog of requests can create a deadlock between cpus. To avoid this
458 * we have to be able to accept IPIs at the same time we are trying to send
459 * them. The critical section prevents us from attempting to send additional
460 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
461 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
462 * to occur but fortunately it does not happen too often.
984263bc 463 */
984263bc
MD
464int
465apic_ipi(int dest_type, int vector, int delivery_mode)
466{
467 u_long icr_lo;
468
96728c05 469 crit_enter();
cb7d6921 470 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
471 unsigned int eflags = read_eflags();
472 cpu_enable_intr();
cfaeae2a 473 DEBUG_PUSH_INFO("apic_ipi");
cb7d6921 474 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
475 lwkt_process_ipiq();
476 }
cfaeae2a 477 DEBUG_POP_INFO();
96728c05 478 write_eflags(eflags);
984263bc 479 }
984263bc 480
cb7d6921 481 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 482 delivery_mode | vector;
cb7d6921 483 lapic->icr_lo = icr_lo;
96728c05 484 crit_exit();
984263bc
MD
485 return 0;
486}
487
41a01a4d
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488void
489single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
MD
490{
491 u_long icr_lo;
492 u_long icr_hi;
984263bc 493
41a01a4d 494 crit_enter();
cb7d6921 495 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
496 unsigned int eflags = read_eflags();
497 cpu_enable_intr();
cfaeae2a 498 DEBUG_PUSH_INFO("single_apic_ipi");
cb7d6921 499 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
500 lwkt_process_ipiq();
501 }
cfaeae2a 502 DEBUG_POP_INFO();
96728c05 503 write_eflags(eflags);
984263bc 504 }
cb7d6921 505 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2d901d56 506 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
cb7d6921 507 lapic->icr_hi = icr_hi;
984263bc 508
b2f93ae9 509 /* build ICR_LOW */
cb7d6921 510 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
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MD
511 | APIC_DEST_DESTFLD | delivery_mode | vector;
512
513 /* write APIC ICR */
cb7d6921 514 lapic->icr_lo = icr_lo;
41a01a4d 515 crit_exit();
984263bc
MD
516}
517
41a01a4d
MD
518#if 0
519
520/*
521 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
522 *
523 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
524 * to the target, and the scheduler does not 'poll' for IPI messages.
525 */
526int
527single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
528{
529 u_long icr_lo;
530 u_long icr_hi;
531
532 crit_enter();
cb7d6921 533 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
41a01a4d
MD
534 crit_exit();
535 return(0);
536 }
cb7d6921 537 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2d901d56 538 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
cb7d6921 539 lapic->icr_hi = icr_hi;
41a01a4d
MD
540
541 /* build IRC_LOW */
cb7d6921 542 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
41a01a4d
MD
543 | APIC_DEST_DESTFLD | delivery_mode | vector;
544
545 /* write APIC ICR */
cb7d6921 546 lapic->icr_lo = icr_lo;
41a01a4d
MD
547 crit_exit();
548 return(1);
549}
550
551#endif
552
984263bc
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553/*
554 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
555 *
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556 * target is a bitmask of destination cpus. Vector is any
557 * valid system INT vector. Delivery mode may be either
558 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 559 */
41a01a4d 560void
da23a592 561selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
984263bc 562{
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563 crit_enter();
564 while (target) {
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565 int n = BSFCPUMASK(target);
566 target &= ~CPUMASK(n);
41a01a4d 567 single_apic_ipi(n, vector, delivery_mode);
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568 }
569 crit_exit();
984263bc 570}
984263bc 571
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572#endif /* SMP */
573
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574/*
575 * Timer code, in development...
576 * - suggested by rgrimes@gndrsh.aac.dev.com
577 */
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578int
579get_apic_timer_frequency(void)
580{
581 return(lapic_cputimer_intr.freq);
582}
984263bc 583
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584/*
585 * Load a 'downcount time' in uSeconds.
586 */
587void
2942ed63 588set_apic_timer(int us)
984263bc 589{
2942ed63 590 u_int count;
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591
592 /*
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593 * When we reach here, lapic timer's frequency
594 * must have been calculated as well as the
595 * divisor (lapic.dcr_timer is setup during the
596 * divisor calculation).
984263bc 597 */
ef612539 598 KKASSERT(lapic_cputimer_intr.freq != 0 &&
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599 lapic_timer_divisor_idx >= 0);
600
ef612539 601 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 602 lapic_timer_oneshot(count);
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603}
604
605
606/*
607 * Read remaining time in timer.
608 */
609int
610read_apic_timer(void)
611{
612#if 0
613 /** XXX FIXME: we need to return the actual remaining time,
614 * for now we just return the remaining count.
615 */
616#else
cb7d6921 617 return lapic->ccr_timer;
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618#endif
619}
620
621
622/*
623 * Spin-style delay, set delay time in uS, spin till it drains.
624 */
625void
626u_sleep(int count)
627{
628 set_apic_timer(count);
629 while (read_apic_timer())
630 /* spin */ ;
631}
ad52b37b 632
11bae9b8 633int
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634lapic_unused_apic_id(int start)
635{
636 int i;
637
638 for (i = start; i < NAPICID; ++i) {
2d901d56 639 if (APICID_TO_CPUID(i) == -1)
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640 return i;
641 }
642 return NAPICID;
643}
644
ad52b37b 645void
84cc808b 646lapic_map(vm_offset_t lapic_addr)
ad52b37b 647{
cb7d6921 648 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
ad52b37b 649
d557216f 650 kprintf("lapic: at %p\n", (void *)lapic_addr);
ad52b37b 651}
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652
653static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
654 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
655
ac032dad 656int
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657lapic_config(void)
658{
659 struct lapic_enumerator *e;
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660 int error, i, ap_max;
661
662 KKASSERT(lapic_enable);
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663
664 for (i = 0; i < NAPICID; ++i)
2d901d56 665 APICID_TO_CPUID(i) = -1;
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666
667 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
668 error = e->lapic_probe(e);
669 if (!error)
670 break;
671 }
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672 if (e == NULL) {
673 kprintf("LAPIC: Can't find LAPIC\n");
674 return ENXIO;
675 }
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676
677 e->lapic_enumerate(e);
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678
679 ap_max = MAXCPU - 1;
680 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
681 if (ap_max > MAXCPU - 1)
682 ap_max = MAXCPU - 1;
683
2abaa030 684 if (naps > ap_max) {
fdab6c5c 685 kprintf("LAPIC: Warning use only %d out of %d "
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686 "available APs\n", ap_max, naps);
687 naps = ap_max;
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688 }
689
ac032dad 690 return 0;
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691}
692
693void
694lapic_enumerator_register(struct lapic_enumerator *ne)
695{
696 struct lapic_enumerator *e;
697
698 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
699 if (e->lapic_prio < ne->lapic_prio) {
700 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
701 return;
702 }
703 }
704 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
705}
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706
707void
708lapic_set_cpuid(int cpu_id, int apic_id)
709{
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710 CPUID_TO_APICID(cpu_id) = apic_id;
711 APICID_TO_CPUID(apic_id) = cpu_id;
41e2c7e0 712}
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713
714void
715lapic_fixup_noioapic(void)
716{
717 u_int temp;
718
719 /* Only allowed on BSP */
720 KKASSERT(mycpuid == 0);
f45bfca0 721 KKASSERT(!ioapic_enable);
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722
723 temp = lapic->lvt_lint0;
724 temp &= ~APIC_LVT_MASKED;
725 lapic->lvt_lint0 = temp;
726
727 temp = lapic->lvt_lint1;
728 temp |= APIC_LVT_MASKED;
729 lapic->lvt_lint1 = temp;
730}
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731
732static void
733lapic_sysinit(void *dummy __unused)
734{
735 if (lapic_enable) {
736 int error;
737
738 error = lapic_config();
739 if (error)
740 lapic_enable = 0;
741 }
742
743 if (lapic_enable) {
744 /* Initialize BSP's local APIC */
745 lapic_init(TRUE);
746 } else if (ioapic_enable) {
747 ioapic_enable = 0;
748 icu_reinit_noioapic();
749 }
750}
751SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL)