i386: Allow UP kernel to use LAPIC timer and I/O APIC
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
d916dbc1 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
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46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
87cf6827 51#include <machine/intr_machdep.h>
0b692e79 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
5f456c40 56
7265a4fe 57#include <machine_base/icu/elcr_var.h>
9e0e3f85 58
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59#include <machine_base/icu/icu.h>
60#include <machine_base/icu/icu_ipl.h>
ed4d621d 61#include <machine_base/apic/ioapic.h>
37e7efec 62
10ff1029 63extern inthand_t
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64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029 72
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73static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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82};
83
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84static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
87} icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
88
89#define ICU_IMT_UNUSED 0 /* KEEP THIS */
90#define ICU_IMT_RESERVED 1
91#define ICU_IMT_LINE 2
474ba684 92#define ICU_IMT_SYSCALL 3
a3dd9120 93
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94extern void ICU_INTREN(int);
95extern void ICU_INTRDIS(int);
96
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97extern int imcr_present;
98
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99static int icu_vectorctl(int, int, int);
100static int icu_setvar(int, const void *);
101static int icu_getvar(int, void *);
102static void icu_finalize(void);
103static void icu_cleanup(void);
104static void icu_setdefault(void);
7bf5fa56 105static void icu_stabilize(void);
a3dd9120 106static void icu_initmap(void);
d1ae7328 107static void icu_intr_config(int, enum intr_trigger, enum intr_polarity);
10db3cc6 108
30c5f287 109struct machintr_abi MachIntrABI_ICU = {
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110 MACHINTR_ICU,
111 .intrdis = ICU_INTRDIS,
112 .intren = ICU_INTREN,
113 .vectorctl = icu_vectorctl,
114 .setvar = icu_setvar,
115 .getvar = icu_getvar,
116 .finalize = icu_finalize,
10db3cc6 117 .cleanup = icu_cleanup,
7bf5fa56 118 .setdefault = icu_setdefault,
a3dd9120 119 .stabilize = icu_stabilize,
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120 .initmap = icu_initmap,
121 .intr_config = icu_intr_config
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122};
123
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124/*
125 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
126 */
54e1df6b 127static int
d916dbc1 128icu_setvar(int varid, const void *buf)
37e7efec 129{
9d758cc4 130 return ENOENT;
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131}
132
54e1df6b 133static int
d916dbc1 134icu_getvar(int varid, void *buf)
37e7efec 135{
9d758cc4 136 return ENOENT;
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137}
138
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139/*
140 * Called before interrupts are physically enabled
141 */
37e7efec 142static void
7bf5fa56 143icu_stabilize(void)
37e7efec 144{
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145 int intr;
146
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147 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
148 machintr_intrdis(intr);
149 machintr_intren(ICU_IRQ_SLAVE);
150}
151
152/*
153 * Called after interrupts physically enabled but before the
154 * critical section is released.
155 */
156static void
157icu_cleanup(void)
158{
159 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
160}
161
162/*
163 * Called after stablize and cleanup; critical section is not
164 * held and interrupts are not physically disabled.
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165 */
166static void
167icu_finalize(void)
168{
169 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
f45bfca0 170 KKASSERT(!ioapic_enable);
54e1df6b 171
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172 /*
173 * If an IMCR is present, programming bit 0 disconnects the 8259
174 * from the BSP. The 8259 may still be connected to LINT0 on the
175 * BSP's LAPIC.
176 *
177 * If we are running SMP the LAPIC is active, try to use virtual
178 * wire mode so we can use other interrupt sources within the LAPIC
179 * in addition to the 8259.
180 */
9d758cc4 181 if (imcr_present) {
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182 outb(0x22, 0x70);
183 outb(0x23, 0x01);
7bf5fa56 184 }
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185}
186
54e1df6b 187static int
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188icu_vectorctl(int op, int intr, int flags)
189{
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190 int error;
191 u_long ef;
192
193 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
194 return EINVAL;
195
196 ef = read_eflags();
197 cpu_disable_intr();
198 error = 0;
199
200 switch (op) {
201 case MACHINTR_VECTOR_SETUP:
081be8a5 202 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
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203 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
204 machintr_intren(intr);
205 break;
206
207 case MACHINTR_VECTOR_TEARDOWN:
10db3cc6 208 machintr_intrdis(intr);
081be8a5 209 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
54e1df6b 210 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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211 break;
212
213 default:
214 error = EOPNOTSUPP;
215 break;
216 }
217 write_eflags(ef);
218 return error;
10ff1029 219}
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220
221static void
222icu_setdefault(void)
223{
224 int intr;
225
226 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
227 if (intr == ICU_IRQ_SLAVE)
228 continue;
229 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
230 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
231 }
232}
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233
234static void
235icu_initmap(void)
236{
237 int i;
238
239 for (i = 0; i < ICU_HWI_VECTORS; ++i)
240 icu_irqmaps[i].im_type = ICU_IMT_LINE;
241 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
242
243 if (elcr_found) {
244 for (i = 0; i < ICU_HWI_VECTORS; ++i)
245 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
246 } else {
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247 /*
248 * NOTE: Trigger mode does not matter at all
249 */
250 for (i = 0; i < ICU_HWI_VECTORS; ++i)
251 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
a3dd9120 252 }
474ba684 253 icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
a3dd9120 254}
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255
256static void
16437a92 257icu_intr_config(int irq, enum intr_trigger trig,
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258 enum intr_polarity pola __unused)
259{
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260 struct icu_irqmap *map;
261
262 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
263
264 KKASSERT(irq >= 0 && irq < MAX_HARDINTS);
265 map = &icu_irqmaps[irq];
266
267 KKASSERT(map->im_type == ICU_IMT_LINE);
268
269 /* TODO: Check whether it is configured or not */
270
271 if (trig == map->im_trig)
272 return;
273
274 if (bootverbose) {
275 kprintf("ICU: irq %d, %s -> %s\n", irq,
276 intr_str_trigger(map->im_trig),
277 intr_str_trigger(trig));
278 }
279 map->im_trig = trig;
280
281 if (!elcr_found) {
282 if (bootverbose)
283 kprintf("ICU: no ELCR, skip irq %d config\n", irq);
284 return;
285 }
286 elcr_write_trigger(irq, map->im_trig);
d1ae7328 287}