Do a major clean-up of the BUSDMA architecture. A large number of
[dragonfly.git] / sys / contrib / dev / ath / dragonfly / ah_osdep.h
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1/*-
2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
3 * Communications, Inc. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms are permitted
6 * provided that the following conditions are met:
7 * 1. The materials contained herein are unmodified and are used
8 * unmodified.
9 * 2. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following NO
11 * ''WARRANTY'' disclaimer below (''Disclaimer''), without
12 * modification.
13 * 3. Redistributions in binary form must reproduce at minimum a
14 * disclaimer similar to the Disclaimer below and any redistribution
15 * must be conditioned upon including a substantially similar
16 * Disclaimer requirement for further binary redistribution.
17 * 4. Neither the names of the above-listed copyright holders nor the
18 * names of any contributors may be used to endorse or promote
19 * product derived from this software without specific prior written
20 * permission.
21 *
22 * NO WARRANTY
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
26 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
28 * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGES.
35 *
36 * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/freebsd/ah_osdep.h#17 $
37 */
38#ifndef _ATH_AH_OSDEP_H_
39#define _ATH_AH_OSDEP_H_
40/*
41 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
42 */
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/endian.h>
1f7ab7c9 46#include <sys/bus.h>
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47
48typedef void* HAL_SOFTC;
49typedef bus_space_tag_t HAL_BUS_TAG;
50typedef bus_space_handle_t HAL_BUS_HANDLE;
51typedef bus_addr_t HAL_BUS_ADDR;
52
53/*
54 * Delay n microseconds.
55 */
56extern void ath_hal_delay(int);
57#define OS_DELAY(_n) ath_hal_delay(_n)
58
59#define OS_INLINE __inline
60#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
61extern void ath_hal_memzero(void *, size_t);
62#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
63extern void *ath_hal_memcpy(void *, const void *, size_t);
64
65#define abs(_a) __builtin_abs(_a)
66
67struct ath_hal;
68extern u_int32_t ath_hal_getuptime(struct ath_hal *);
69#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
70
71/*
72 * Register read/write; we assume the registers will always
73 * be memory-mapped. Note that register accesses are done
74 * using target-specific functions when debugging is enabled
75 * (AH_DEBUG) or we are explicitly configured this way. The
76 * latter is used on some platforms where the full i/o space
77 * cannot be directly mapped.
78 */
79#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
80#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
81#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
82
83extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
84extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
85#else
86/*
87 * The hardware registers are native little-endian byte order.
88 * Big-endian hosts are handled by enabling hardware byte-swap
89 * of register reads and writes at reset. But the PCI clock
90 * domain registers are not byte swapped! Thus, on big-endian
91 * platforms we have to byte-swap thoese registers specifically.
92 * Most of this code is collapsed at compile time because the
93 * register values are constants.
94 */
95#define AH_LITTLE_ENDIAN 1234
96#define AH_BIG_ENDIAN 4321
97
98#if _BYTE_ORDER == _BIG_ENDIAN
99#define OS_REG_WRITE(_ah, _reg, _val) do { \
100 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
101 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
102 (_reg), htole32(_val)); \
103 else \
104 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
105 (_reg), (_val)); \
106} while (0)
107#define OS_REG_READ(_ah, _reg) \
108 (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
109 le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \
110 (_reg))) : \
111 bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
112#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
113#define OS_REG_WRITE(_ah, _reg, _val) \
114 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
115#define OS_REG_READ(_ah, _reg) \
116 ((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
117#endif /* _BYTE_ORDER */
118#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
119
120#ifdef AH_DEBUG_ALQ
121extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
122#else
123#define OS_MARK(_ah, _id, _v)
124#endif
125
126#endif /* _ATH_AH_OSDEP_H_ */