Do a major clean-up of the BUSDMA architecture. A large number of
[dragonfly.git] / sys / dev / disk / advansys / adv_pci.c
CommitLineData
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1/*
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * Connectivity Products:
6 * ABP902/3902 - Bus-Master PCI (16 CDB)
7 * ABP3905 - Bus-Master PCI (16 CDB)
8 * ABP915 - Bus-Master PCI (16 CDB)
9 * ABP920 - Bus-Master PCI (16 CDB)
10 * ABP3922 - Bus-Master PCI (16 CDB)
11 * ABP3925 - Bus-Master PCI (16 CDB)
12 * ABP930 - Bus-Master PCI (16 CDB) *
13 * ABP930U - Bus-Master PCI Ultra (16 CDB)
14 * ABP930UA - Bus-Master PCI Ultra (16 CDB)
15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) **
17 *
18 * Single Channel Products:
19 * ABP940 - Bus-Master PCI (240 CDB)
20 * ABP940U - Bus-Master PCI Ultra (240 CDB)
21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB)
23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB)
24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
25 *
26 * Dual Channel Products:
27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
31 *
32 * Footnotes:
33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI.
34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
35 *
36 * Copyright (c) 1997 Justin Gibbs.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions, and the following disclaimer,
44 * without modification.
45 * 2. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
52 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 *
60 * $FreeBSD: src/sys/dev/advansys/adv_pci.c,v 1.11.2.3 2001/06/02 04:38:10 nyan Exp $
1f7ab7c9 61 * $DragonFly: src/sys/dev/disk/advansys/adv_pci.c,v 1.6 2006/10/25 20:55:52 dillon Exp $
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62 */
63
64#include <sys/param.h>
65#include <sys/systm.h>
66#include <sys/kernel.h>
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67#include <sys/bus.h>
68#include <sys/rman.h>
69
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70#include <bus/pci/pcireg.h>
71#include <bus/pci/pcivar.h>
984263bc 72
1f2de5d4 73#include "advansys.h"
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74
75#define PCI_BASEADR0 PCIR_MAPS /* I/O Address */
76#define PCI_BASEADR1 PCIR_MAPS + 4 /* Mem I/O Address */
77
78#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
79#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
80#define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD
81#define PCI_DEVICE_REV_ADVANSYS_3150 0x02
82#define PCI_DEVICE_REV_ADVANSYS_3050 0x03
83
84#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
85#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
86
87static int adv_pci_probe(device_t);
88static int adv_pci_attach(device_t);
89
90/*
91 * The overrun buffer shared amongst all PCI adapters.
92 */
93static u_int8_t* overrun_buf;
94static bus_dma_tag_t overrun_dmat;
95static bus_dmamap_t overrun_dmamap;
96static bus_addr_t overrun_physbase;
97
98static int
99adv_pci_probe(device_t dev)
100{
101 int rev = pci_get_revid(dev);
102
103 switch (pci_get_devid(dev)) {
104 case PCI_DEVICE_ID_ADVANSYS_1200A:
105 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
106 return 0;
107 case PCI_DEVICE_ID_ADVANSYS_1200B:
108 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
109 return 0;
110 case PCI_DEVICE_ID_ADVANSYS_3000:
111 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
112 device_set_desc(dev,
113 "AdvanSys ASC3150 SCSI controller");
114 return 0;
115 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
116 device_set_desc(dev,
117 "AdvanSys ASC3030/50 SCSI controller");
118 return 0;
119 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
120 device_set_desc(dev, "Unknown AdvanSys controller");
121 return 0;
122 }
123 break;
124 default:
125 break;
126 }
127 return ENXIO;
128}
129
130static int
131adv_pci_attach(device_t dev)
132{
133 struct adv_softc *adv;
134 u_int32_t id;
135 u_int32_t command;
136 int error, rid, irqrid;
137 void *ih;
138 struct resource *iores, *irqres;
139
140 /*
141 * Determine the chip version.
142 */
143 id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4);
144 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
145
146 /*
147 * These cards do not allow memory mapped accesses, so we must
148 * ensure that I/O accesses are available or we won't be able
149 * to talk to them.
150 */
151 if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
152 != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
153 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
154 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
155 }
156
157 /*
158 * Early chips can't handle non-zero latency timer settings.
159 */
160 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
161 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
162 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
163 }
164
165 rid = PCI_BASEADR0;
166 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
167 RF_ACTIVE);
168 if (iores == NULL)
169 return ENXIO;
170
171 if (adv_find_signature(rman_get_bustag(iores),
172 rman_get_bushandle(iores)) == 0) {
173 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
174 return ENXIO;
175 }
176
177 adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores));
178 if (adv == NULL) {
179 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
180 return ENXIO;
181 }
182
183 /* Allocate a dmatag for our transfer DMA maps */
184 /* XXX Should be a child of the PCI bus dma tag */
185 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
186 /*boundary*/0,
187 /*lowaddr*/ADV_PCI_MAX_DMA_ADDR,
188 /*highaddr*/BUS_SPACE_MAXADDR,
189 /*filter*/NULL, /*filterarg*/NULL,
190 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
191 /*nsegments*/BUS_SPACE_UNRESTRICTED,
192 /*maxsegsz*/ADV_PCI_MAX_DMA_COUNT,
193 /*flags*/0,
194 &adv->parent_dmat);
195
196 if (error != 0) {
197 printf("%s: Could not allocate DMA tag - error %d\n",
198 adv_name(adv), error);
199 adv_free(adv);
200 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
201 return ENXIO;
202 }
203
204 adv->init_level++;
205
206 if (overrun_buf == NULL) {
207 /* Need to allocate our overrun buffer */
208 if (bus_dma_tag_create(adv->parent_dmat,
209 /*alignment*/8, /*boundary*/0,
210 ADV_PCI_MAX_DMA_ADDR, BUS_SPACE_MAXADDR,
211 /*filter*/NULL, /*filterarg*/NULL,
212 ADV_OVERRUN_BSIZE, /*nsegments*/1,
213 BUS_SPACE_MAXSIZE_32BIT, /*flags*/0,
214 &overrun_dmat) != 0) {
215 bus_dma_tag_destroy(adv->parent_dmat);
216 adv_free(adv);
217 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
218 return ENXIO;
219 }
220 if (bus_dmamem_alloc(overrun_dmat,
221 (void **)&overrun_buf,
222 BUS_DMA_NOWAIT,
223 &overrun_dmamap) != 0) {
224 bus_dma_tag_destroy(overrun_dmat);
225 bus_dma_tag_destroy(adv->parent_dmat);
226 adv_free(adv);
227 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
228 return ENXIO;
229 }
230 /* And permanently map it in */
231 bus_dmamap_load(overrun_dmat, overrun_dmamap,
232 overrun_buf, ADV_OVERRUN_BSIZE,
233 adv_map, &overrun_physbase,
234 /*flags*/0);
235 }
236
237 adv->overrun_physbase = overrun_physbase;
238
239 /*
240 * Stop the chip.
241 */
242 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
243 ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
244
245 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
246 adv->type = ADV_PCI;
247
248 /*
249 * Setup active negation and signal filtering.
250 */
251 {
252 u_int8_t extra_cfg;
253
254 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
255 adv->type |= ADV_ULTRA;
256 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
257 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
258 else
259 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
260 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
261 }
262
263 if (adv_init(adv) != 0) {
264 adv_free(adv);
265 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
266 return ENXIO;
267 }
268
269 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
270 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
271
272#if CC_DISABLE_PCI_PARITY_INT
273 {
274 u_int16_t config_msw;
275
276 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
277 config_msw &= 0xFFC0;
278 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
279 }
280#endif
281
282 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
283 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
284 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
285 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
286 adv->fix_asyn_xfer = ~0;
287 }
288
289 irqrid = 0;
290 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &irqrid, 0, ~0, 1,
291 RF_SHAREABLE | RF_ACTIVE);
292 if (irqres == NULL ||
ee61f228 293 bus_setup_intr(dev, irqres, 0, adv_intr, adv, &ih, NULL)) {
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294 adv_free(adv);
295 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
296 return ENXIO;
297 }
298
299 adv_attach(adv);
300 return 0;
301}
302
303static device_method_t adv_pci_methods[] = {
304 /* Device interface */
305 DEVMETHOD(device_probe, adv_pci_probe),
306 DEVMETHOD(device_attach, adv_pci_attach),
307 { 0, 0 }
308};
309
310static driver_t adv_pci_driver = {
311 "adv", adv_pci_methods, sizeof(struct adv_softc)
312};
313
314static devclass_t adv_pci_devclass;
315DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);