Do a major clean-up of the BUSDMA architecture. A large number of
[dragonfly.git] / sys / dev / netif / mii_layer / rgephy.c
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1/* $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $ */
2
3/*
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4 * Copyright (c) 2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
1f7ab7c9 35 * $DragonFly: src/sys/dev/netif/mii_layer/rgephy.c,v 1.4 2006/10/25 20:55:57 dillon Exp $
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36 */
37
38/*
39 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/module.h>
46#include <sys/socket.h>
47#include <sys/bus.h>
48
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49#include <machine/clock.h>
50
51#include <net/if.h>
52#include <net/if_arp.h>
53#include <net/if_media.h>
54
55#include <dev/netif/mii_layer/mii.h>
56#include <dev/netif/mii_layer/miivar.h>
57#include <dev/netif/mii_layer/miidevs.h>
58
59#include <dev/netif/re/if_rereg.h>
60#include <dev/netif/mii_layer/rgephyreg.h>
61
62#include "miibus_if.h"
63
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64static int rgephy_probe(device_t);
65static int rgephy_attach(device_t);
66
67static device_method_t rgephy_methods[] = {
68 /* device interface */
69 DEVMETHOD(device_probe, rgephy_probe),
70 DEVMETHOD(device_attach, rgephy_attach),
71 DEVMETHOD(device_detach, ukphy_detach),
72 DEVMETHOD(device_shutdown, bus_generic_shutdown),
73 { 0, 0 }
74};
75
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76static const struct mii_phydesc rgephys[] = {
77 MII_PHYDESC(REALTEK2, RTL8169S),
78 MII_PHYDESC(xxREALTEK, RTL8169S),
79 MII_PHYDESC_NULL
80};
81
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82static devclass_t rgephy_devclass;
83
84static driver_t rgephy_driver = {
85 "rgephy",
86 rgephy_methods,
87 sizeof(struct mii_softc)
88};
89
90DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
91
92static int rgephy_service(struct mii_softc *, struct mii_data *, int);
93static void rgephy_status(struct mii_softc *);
94static int rgephy_mii_phy_auto(struct mii_softc *);
95static void rgephy_reset(struct mii_softc *);
96static void rgephy_loop(struct mii_softc *);
97static void rgephy_load_dspcode(struct mii_softc *);
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98
99static int
100rgephy_probe(device_t dev)
101{
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102 struct mii_attach_args *ma = device_get_ivars(dev);
103 const struct mii_phydesc *mpd;
eb2ada2e 104
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105 mpd = mii_phy_match(ma, rgephys);
106 if (mpd != NULL) {
107 device_set_desc(dev, mpd->mpd_name);
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108 if (bootverbose)
109 device_printf(dev, "rev: %d\n", MII_REV(ma->mii_id2));
46ad174e 110 return (0);
eb2ada2e 111 }
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112 return(ENXIO);
113}
114
115static int
116rgephy_attach(device_t dev)
117{
118 struct mii_softc *sc;
119 struct mii_attach_args *ma;
120 struct mii_data *mii;
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121
122 sc = device_get_softc(dev);
123 ma = device_get_ivars(dev);
124 mii_softc_init(sc, ma);
125 sc->mii_dev = device_get_parent(dev);
126
127 mii = device_get_softc(sc->mii_dev);
128 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
129
130 sc->mii_inst = mii->mii_instance;
131 sc->mii_service = rgephy_service;
46ad174e 132 sc->mii_reset = rgephy_reset;
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133 sc->mii_pdata = mii;
134
135 sc->mii_flags |= MIIF_NOISOLATE;
136 mii->mii_instance++;
137
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138 rgephy_reset(sc);
139
140 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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141 if (sc->mii_capabilities & BMSR_EXTSTAT)
142 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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143
144 device_printf(dev, " ");
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145 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
146 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
147 printf("no media present");
148 else
149 mii_phy_add_media(sc);
eb2ada2e 150 printf("\n");
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151
152 MIIBUS_MEDIAINIT(sc->mii_dev);
153 return(0);
154}
155
156static int
157rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
158{
159 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
160 int reg, speed, gig;
161
162 switch (cmd) {
163 case MII_POLLSTAT:
164 /*
165 * If we're not polling our PHY instance, just return.
166 */
167 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
168 return (0);
169 break;
170
171 case MII_MEDIACHG:
172 /*
173 * If the media indicates a different PHY instance,
174 * isolate ourselves.
175 */
176 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
177 reg = PHY_READ(sc, MII_BMCR);
178 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
179 return (0);
180 }
181
182 /*
183 * If the interface is not up, don't do anything.
184 */
185 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
186 break;
187
188 rgephy_reset(sc); /* XXX hardware bug work-around */
189
190 switch (IFM_SUBTYPE(ife->ifm_media)) {
191 case IFM_AUTO:
192#ifdef foo
193 /*
194 * If we're already in auto mode, just return.
195 */
196 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
197 return (0);
198#endif
199 rgephy_mii_phy_auto(sc);
200 break;
201 case IFM_1000_T:
202 speed = RGEPHY_S1000;
203 goto setit;
204 case IFM_100_TX:
205 speed = RGEPHY_S100;
206 goto setit;
207 case IFM_10_T:
208 speed = RGEPHY_S10;
209setit:
210 rgephy_loop(sc);
211 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
212 speed |= RGEPHY_BMCR_FDX;
213 gig = RGEPHY_1000CTL_AFD;
214 } else {
215 gig = RGEPHY_1000CTL_AHD;
216 }
217
218 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
219 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
220 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
221
222 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
223 break;
224
225 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
226 PHY_WRITE(sc, RGEPHY_MII_BMCR,
227 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
228
229 /*
230 * When settning the link manually, one side must
231 * be the master and the other the slave. However
232 * ifmedia doesn't give us a good way to specify
233 * this, so we fake it by using one of the LINK
234 * flags. If LINK0 is set, we program the PHY to
235 * be a master, otherwise it's a slave.
236 */
237 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
238 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
239 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
240 } else {
241 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
242 gig|RGEPHY_1000CTL_MSE);
243 }
244 break;
245#ifdef foo
246 case IFM_NONE:
247 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
248 break;
249#endif
250 case IFM_100_T4:
251 default:
252 return (EINVAL);
253 }
254 break;
255
256 case MII_TICK:
257 /*
258 * If we're not currently selected, just return.
259 */
260 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
261 return (0);
262
263 /*
264 * Is the interface even up?
265 */
266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
267 return (0);
268
269 /*
270 * Only used for autonegotiation.
271 */
272 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
46ad174e 273 break;
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274
275 /*
276 * Check to see if we have link. If we do, we don't
277 * need to restart the autonegotiation process.
278 *
279 * XXX Read the BMSR twice in case it's latched?
280 */
281 reg = PHY_READ(sc, RE_GMEDIASTAT);
282 if (reg & RE_GMEDIASTAT_LINK)
283 break;
284
285 /*
46ad174e 286 * Only retry autonegotiation every mii_anegticks seconds.
eb2ada2e 287 */
46ad174e 288 if (++sc->mii_ticks <= sc->mii_anegticks)
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289 break;
290
291 sc->mii_ticks = 0;
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292
293 /*
294 * Although rgephy_mii_phy_auto() always returns EJUSTRETURN,
295 * we should not rely on that.
296 */
297 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN)
298 return (0);
299 break;
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300 }
301
302 /* Update the media status. */
303 rgephy_status(sc);
304
305 /*
306 * Callback if something changed. Note that we need to poke
307 * the DSP on the RealTek PHYs if the media changes.
308 */
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309 if (sc->mii_media_active != mii->mii_media_active ||
310 sc->mii_media_status != mii->mii_media_status ||
311 cmd == MII_MEDIACHG)
eb2ada2e 312 rgephy_load_dspcode(sc);
46ad174e 313 mii_phy_update(sc, cmd);
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314 return (0);
315}
316
317static void
318rgephy_status(struct mii_softc *sc)
319{
320 struct mii_data *mii = sc->mii_pdata;
321 int bmsr, bmcr;
322
323 mii->mii_media_status = IFM_AVALID;
324 mii->mii_media_active = IFM_ETHER;
325
326 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
327
328 if (bmsr & RE_GMEDIASTAT_LINK)
329 mii->mii_media_status |= IFM_ACTIVE;
330 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
331
332 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
333
334 if (bmcr & RGEPHY_BMCR_LOOP)
335 mii->mii_media_active |= IFM_LOOP;
336
337 if (bmcr & RGEPHY_BMCR_AUTOEN) {
338 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
339 /* Erg, still trying, I guess... */
340 mii->mii_media_active |= IFM_NONE;
341 return;
342 }
343 }
344
345 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
346
347 if (bmsr & RE_GMEDIASTAT_1000MBPS) {
348 mii->mii_media_active |= IFM_1000_T;
349 } else if (bmsr & RE_GMEDIASTAT_100MBPS) {
350 mii->mii_media_active |= IFM_100_TX;
351 } else if (bmsr & RE_GMEDIASTAT_10MBPS) {
352 mii->mii_media_active |= IFM_10_T;
353 } else {
354 mii->mii_media_active |= IFM_NONE;
355 return;
356 }
357
358 if (bmsr & RE_GMEDIASTAT_FDX)
359 mii->mii_media_active |= IFM_FDX;
360}
361
362static int
46ad174e 363rgephy_mii_phy_auto(struct mii_softc *sc)
eb2ada2e 364{
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365 rgephy_loop(sc);
366 rgephy_reset(sc);
eb2ada2e 367
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368 PHY_WRITE(sc, RGEPHY_MII_ANAR,
369 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
eb2ada2e 370 DELAY(1000);
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371 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
372 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
eb2ada2e 373 DELAY(1000);
46ad174e 374 PHY_WRITE(sc, RGEPHY_MII_BMCR,
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375 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
376 DELAY(100);
377
378 return (EJUSTRETURN);
379}
380
381static void
382rgephy_loop(struct mii_softc *sc)
383{
46ad174e 384 uint32_t bmsr;
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385 int i;
386
387 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
388 DELAY(1000);
389
390 for (i = 0; i < 15000; i++) {
391 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
392 if (!(bmsr & RGEPHY_BMSR_LINK)) {
393#if 0
394 device_printf(sc->mii_dev, "looped %d\n", i);
395#endif
396 break;
397 }
398 DELAY(10);
399 }
400}
401
402#define PHY_SETBIT(x, y, z) \
403 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
404#define PHY_CLRBIT(x, y, z) \
405 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
406
407/*
408 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
409 * existing revisions of the 8169S/8110S chips need to be tuned in
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410 * order to reliably negotiate a 1000Mbps link. This is only needed
411 * for rev 0 and rev 1 of the PHY. Later versions work without
412 * any fixups.
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413 */
414static void
415rgephy_load_dspcode(struct mii_softc *sc)
416{
417 int val;
418
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419 if (sc->mii_rev > 1)
420 return;
421
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422 PHY_WRITE(sc, 31, 0x0001);
423 PHY_WRITE(sc, 21, 0x1000);
424 PHY_WRITE(sc, 24, 0x65C7);
425 PHY_CLRBIT(sc, 4, 0x0800);
426 val = PHY_READ(sc, 4) & 0xFFF;
427 PHY_WRITE(sc, 4, val);
428 PHY_WRITE(sc, 3, 0x00A1);
429 PHY_WRITE(sc, 2, 0x0008);
430 PHY_WRITE(sc, 1, 0x1020);
431 PHY_WRITE(sc, 0, 0x1000);
432 PHY_SETBIT(sc, 4, 0x0800);
433 PHY_CLRBIT(sc, 4, 0x0800);
434 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
435 PHY_WRITE(sc, 4, val);
436 PHY_WRITE(sc, 3, 0xFF41);
437 PHY_WRITE(sc, 2, 0xDE60);
438 PHY_WRITE(sc, 1, 0x0140);
439 PHY_WRITE(sc, 0, 0x0077);
440 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
441 PHY_WRITE(sc, 4, val);
442 PHY_WRITE(sc, 3, 0xDF01);
443 PHY_WRITE(sc, 2, 0xDF20);
444 PHY_WRITE(sc, 1, 0xFF95);
445 PHY_WRITE(sc, 0, 0xFA00);
446 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
447 PHY_WRITE(sc, 4, val);
448 PHY_WRITE(sc, 3, 0xFF41);
449 PHY_WRITE(sc, 2, 0xDE20);
450 PHY_WRITE(sc, 1, 0x0140);
451 PHY_WRITE(sc, 0, 0x00BB);
452 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
453 PHY_WRITE(sc, 4, val);
454 PHY_WRITE(sc, 3, 0xDF01);
455 PHY_WRITE(sc, 2, 0xDF20);
456 PHY_WRITE(sc, 1, 0xFF95);
457 PHY_WRITE(sc, 0, 0xBF00);
458 PHY_SETBIT(sc, 4, 0x0800);
459 PHY_CLRBIT(sc, 4, 0x0800);
460 PHY_WRITE(sc, 31, 0x0000);
461
462 DELAY(40);
463}
464
465static void
466rgephy_reset(struct mii_softc *sc)
467{
468 mii_phy_reset(sc);
469 DELAY(1000);
470 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN);
471 DELAY(1000);
472 rgephy_load_dspcode(sc);
473}