Do a major clean-up of the BUSDMA architecture. A large number of
[dragonfly.git] / sys / dev / netif / nv / if_nv.c
CommitLineData
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1/*-
2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>.
3 * Copyright (c) 2003,2004 by Quinton Dolan <q@onthenet.com.au>.
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4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
16 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
e5829d43 27 * $Id: if_nv.c,v 1.20 2005/03/12 01:11:00 q Exp $
5662379b 28 * $FreeBSD: src/sys/dev/nve/if_nve.c,v 1.20 2005/12/12 06:23:43 bz Exp $
1f7ab7c9 29 * $DragonFly: src/sys/dev/netif/nv/Attic/if_nv.c,v 1.28 2006/10/25 20:55:58 dillon Exp $
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30 */
31
32/*
33 * NVIDIA nForce MCP Networking Adapter driver
34 *
35 * This is a port of the NVIDIA MCP Linux ethernet driver distributed by NVIDIA
36 * through their web site.
37 *
38 * All mainstream nForce and nForce2 motherboards are supported. This module
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39 * is as stable, sometimes more stable, than the linux version. (Recent
40 * Linux stability issues seem to be related to some issues with newer
41 * distributions using GCC 3.x, however this don't appear to effect FreeBSD
42 * 5.x).
a072e131 43 *
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44 * In accordance with the NVIDIA distribution license it is necessary to
45 * link this module against the nvlibnet.o binary object included in the
46 * Linux driver source distribution. The binary component is not modified in
47 * any way and is simply linked against a FreeBSD equivalent of the nvnet.c
48 * linux kernel module "wrapper".
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49 *
50 * The Linux driver uses a common code API that is shared between Win32 and
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51 * i386 Linux. This abstracts the low level driver functions and uses
52 * callbacks and hooks to access the underlying hardware device. By using
53 * this same API in a FreeBSD kernel module it is possible to support the
54 * hardware without breaching the Linux source distributions licensing
55 * requirements, or obtaining the hardware programming specifications.
a072e131 56 *
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57 * Although not conventional, it works, and given the relatively small
58 * amount of hardware centric code, it's hopefully no more buggy than its
59 * linux counterpart.
60 *
5662379b 61 * NVIDIA now support the nForce3 AMD64 platform, however I have been
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62 * unable to access such a system to verify support. However, the code is
63 * reported to work with little modification when compiled with the AMD64
64 * version of the NVIDIA Linux library. All that should be necessary to make
65 * the driver work is to link it directly into the kernel, instead of as a
66 * module, and apply the docs/amd64.diff patch in this source distribution to
67 * the NVIDIA Linux driver source.
68 *
69 * This driver should work on all versions of FreeBSD since 4.9/5.1 as well
70 * as recent versions of DragonFly.
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71 *
72 * Written by Quinton Dolan <q@onthenet.com.au>
73 * Portions based on existing FreeBSD network drivers.
74 * NVIDIA API usage derived from distributed NVIDIA NVNET driver source files.
75 *
76 * $Id: if_nv.c,v 1.9 2003/12/13 15:27:40 q Exp $
77 */
78
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79#include "opt_polling.h"
80
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81#include <sys/param.h>
82#include <sys/systm.h>
83#include <sys/sockio.h>
84#include <sys/mbuf.h>
85#include <sys/malloc.h>
86#include <sys/kernel.h>
87#include <sys/socket.h>
88#include <sys/sysctl.h>
89#include <sys/queue.h>
90#include <sys/module.h>
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91#include <sys/bus.h>
92#include <sys/rman.h>
93#include <sys/serialize.h>
d28f25d7 94#include <sys/thread2.h>
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95
96#include <net/if.h>
c7f5b673 97#include <net/ifq_var.h>
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98#include <net/if_arp.h>
99#include <net/ethernet.h>
100#include <net/if_dl.h>
101#include <net/if_media.h>
102
103#include <net/bpf.h>
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104#include <net/vlan/if_vlan_var.h>
105
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106#include <vm/vm.h> /* for vtophys */
107#include <vm/pmap.h> /* for vtophys */
108#include <machine/clock.h> /* for DELAY */
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109
110#include <bus/pci/pcireg.h>
111#include <bus/pci/pcivar.h>
112
113#include <dev/netif/mii_layer/mii.h>
114#include <dev/netif/mii_layer/miivar.h>
115
116MODULE_DEPEND(nv, pci, 1, 1, 1);
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117MODULE_DEPEND(nv, miibus, 1, 1, 1);
118
119#include "if_nvreg.h"
120#include "miibus_if.h"
121
122static int nv_probe(device_t);
123static int nv_attach(device_t);
124static int nv_detach(device_t);
125static void nv_init(void *);
126static void nv_stop(struct nv_softc *);
127static void nv_shutdown(device_t);
128static int nv_init_rings(struct nv_softc *);
129static void nv_free_rings(struct nv_softc *);
130
131static void nv_ifstart(struct ifnet *);
132static int nv_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
133static void nv_intr(void *);
134static void nv_tick(void *);
135static void nv_setmulti(struct nv_softc *);
136static void nv_watchdog(struct ifnet *);
137static void nv_update_stats(struct nv_softc *);
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138#ifdef DEVICE_POLLING
139static void nv_poll(struct ifnet *, enum poll_cmd, int);
140#endif
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141
142static int nv_ifmedia_upd(struct ifnet *);
143static void nv_ifmedia_sts(struct ifnet *, struct ifmediareq *);
144static int nv_miibus_readreg(device_t, int, int);
145static void nv_miibus_writereg(device_t, int, int, int);
146
147static void nv_dmamap_cb(void *, bus_dma_segment_t *, int, int);
148static void nv_dmamap_tx_cb(void *, bus_dma_segment_t *, int, bus_size_t, int);
149
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150static NV_SINT32 nv_osalloc(PNV_VOID, PMEMORY_BLOCK);
151static NV_SINT32 nv_osfree(PNV_VOID, PMEMORY_BLOCK);
152static NV_SINT32 nv_osallocex(PNV_VOID, PMEMORY_BLOCKEX);
153static NV_SINT32 nv_osfreeex(PNV_VOID, PMEMORY_BLOCKEX);
154static NV_SINT32 nv_osclear(PNV_VOID, PNV_VOID, NV_SINT32);
155static NV_SINT32 nv_osdelay(PNV_VOID, NV_UINT32);
156static NV_SINT32 nv_osallocrxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID *);
157static NV_SINT32 nv_osfreerxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID);
158static NV_SINT32 nv_ospackettx(PNV_VOID, PNV_VOID, NV_UINT32);
159static NV_SINT32 nv_ospacketrx(PNV_VOID, PNV_VOID, NV_UINT32, NV_UINT8 *, NV_UINT8);
160static NV_SINT32 nv_oslinkchg(PNV_VOID, NV_SINT32);
161static NV_SINT32 nv_osalloctimer(PNV_VOID, PNV_VOID *);
162static NV_SINT32 nv_osfreetimer(PNV_VOID, PNV_VOID);
163static NV_SINT32 nv_osinittimer(PNV_VOID, PNV_VOID, PTIMER_FUNC, PNV_VOID);
164static NV_SINT32 nv_ossettimer(PNV_VOID, PNV_VOID, NV_UINT32);
165static NV_SINT32 nv_oscanceltimer(PNV_VOID, PNV_VOID);
166
167static NV_SINT32 nv_ospreprocpkt(PNV_VOID, PNV_VOID, PNV_VOID *, NV_UINT8 *, NV_UINT8);
168static PNV_VOID nv_ospreprocpktnopq(PNV_VOID, PNV_VOID);
169static NV_SINT32 nv_osindicatepkt(PNV_VOID, PNV_VOID *, NV_UINT32);
170static NV_SINT32 nv_oslockalloc(PNV_VOID, NV_SINT32, PNV_VOID *);
171static NV_SINT32 nv_oslockacquire(PNV_VOID, NV_SINT32, PNV_VOID);
172static NV_SINT32 nv_oslockrelease(PNV_VOID, NV_SINT32, PNV_VOID);
173static PNV_VOID nv_osreturnbufvirt(PNV_VOID, PNV_VOID);
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174
175static device_method_t nv_methods[] = {
176 /* Device interface */
177 DEVMETHOD(device_probe, nv_probe),
178 DEVMETHOD(device_attach, nv_attach),
179 DEVMETHOD(device_detach, nv_detach),
180 DEVMETHOD(device_shutdown, nv_shutdown),
181
182 /* Bus interface */
183 DEVMETHOD(bus_print_child, bus_generic_print_child),
184 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185
186 /* MII interface */
187 DEVMETHOD(miibus_readreg, nv_miibus_readreg),
188 DEVMETHOD(miibus_writereg, nv_miibus_writereg),
189
190 {0, 0}
191};
192
193static driver_t nv_driver = {
194 "nv",
195 nv_methods,
196 sizeof(struct nv_softc)
197};
198
199static devclass_t nv_devclass;
200
201static int nv_pollinterval = 0;
202SYSCTL_INT(_hw, OID_AUTO, nv_pollinterval, CTLFLAG_RW,
203 &nv_pollinterval, 0, "delay between interface polls");
204
205DRIVER_MODULE(nv, pci, nv_driver, nv_devclass, 0, 0);
206DRIVER_MODULE(miibus, nv, miibus_driver, miibus_devclass, 0, 0);
207
208static struct nv_type nv_devs[] = {
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209 {NVIDIA_VENDORID, NFORCE_MCPNET1_DEVICEID,
210 "NVIDIA nForce MCP Networking Adapter"},
211 {NVIDIA_VENDORID, NFORCE_MCPNET2_DEVICEID,
212 "NVIDIA nForce MCP2 Networking Adapter"},
213 {NVIDIA_VENDORID, NFORCE_MCPNET3_DEVICEID,
214 "NVIDIA nForce MCP3 Networking Adapter"},
215 {NVIDIA_VENDORID, NFORCE_MCPNET4_DEVICEID,
216 "NVIDIA nForce MCP4 Networking Adapter"},
217 {NVIDIA_VENDORID, NFORCE_MCPNET5_DEVICEID,
218 "NVIDIA nForce MCP5 Networking Adapter"},
219 {NVIDIA_VENDORID, NFORCE_MCPNET6_DEVICEID,
220 "NVIDIA nForce MCP6 Networking Adapter"},
221 {NVIDIA_VENDORID, NFORCE_MCPNET7_DEVICEID,
222 "NVIDIA nForce MCP7 Networking Adapter"},
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223 {NVIDIA_VENDORID, NFORCE_MCPNET8_DEVICEID,
224 "NVIDIA nForce MCP8 Networking Adapter"},
225 {NVIDIA_VENDORID, NFORCE_MCPNET9_DEVICEID,
226 "NVIDIA nForce MCP9 Networking Adapter"},
227 {NVIDIA_VENDORID, NFORCE_MCPNET10_DEVICEID,
228 "NVIDIA nForce MCP10 Networking Adapter"},
229 {NVIDIA_VENDORID, NFORCE_MCPNET11_DEVICEID,
230 "NVIDIA nForce MCP11 Networking Adapter"},
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231 {NVIDIA_VENDORID, NFORCE_MCPNET12_DEVICEID,
232 "NVIDIA nForce MCP12 Networking Adapter"},
233 {NVIDIA_VENDORID, NFORCE_MCPNET13_DEVICEID,
234 "NVIDIA nForce MCP13 Networking Adapter"},
2980fae4 235 {0, 0, NULL}
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236};
237
238/* DMA MEM map callback function to get data segment physical address */
239static void
240nv_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error)
241{
242 if (error)
243 return;
244
245 KASSERT(nsegs == 1,
246 ("Too many DMA segments returned when mapping DMA memory"));
247 *(bus_addr_t *)arg = segs->ds_addr;
248}
249
250/* DMA RX map callback function to get data segment physical address */
251static void
252nv_dmamap_rx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
253{
254 if (error)
255 return;
256 *(bus_addr_t *)arg = segs->ds_addr;
257}
258
259/*
260 * DMA TX buffer callback function to allocate fragment data segment
261 * addresses
262 */
263static void
264nv_dmamap_tx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
265{
266 struct nv_tx_desc *info = arg;
267
268 if (error)
269 return;
270 KASSERT(nsegs < NV_MAX_FRAGS,
271 ("Too many DMA segments returned when mapping mbuf"));
272 info->numfrags = nsegs;
273 bcopy(segs, info->frags, nsegs * sizeof(bus_dma_segment_t));
274}
275
276/* Probe for supported hardware ID's */
277static int
278nv_probe(device_t dev)
279{
280 struct nv_type *t = nv_devs;
281
282 /* Check for matching PCI DEVICE ID's */
283 while (t->name != NULL) {
284 if ((pci_get_vendor(dev) == t->vid_id) &&
285 (pci_get_device(dev) == t->dev_id)) {
286 device_set_desc(dev, t->name);
287 return (0);
288 }
289 t++;
290 }
291
292 return (ENXIO);
293}
294
295/* Attach driver and initialise hardware for use */
296static int
297nv_attach(device_t dev)
298{
299 u_char eaddr[ETHER_ADDR_LEN];
300 struct nv_softc *sc;
301 struct ifnet *ifp;
302 OS_API *osapi;
303 ADAPTER_OPEN_PARAMS OpenParams;
d0de58a2 304 int error = 0, i, rid;
9dda2746 305 u_int32_t unit;
a072e131 306
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307 if (bootverbose)
308 device_printf(dev, "nvenetlib.o version %s\n", DRIVER_VERSION);
309
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310 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_attach - entry\n");
311
312 sc = device_get_softc(dev);
9dda2746 313 unit = device_get_unit(dev);
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314
315 sc->dev = dev;
9dda2746 316 sc->unit = unit;
204b91ae 317 callout_init(&sc->nv_stat_timer);
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318
319 /* Preinitialize data structures */
320 bzero(&OpenParams, sizeof(ADAPTER_OPEN_PARAMS));
321
322 /* Enable bus mastering */
323 pci_enable_busmaster(dev);
324
325 /* Allocate memory mapped address space */
326 rid = NV_RID;
4e6d744d 327 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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328
329 if (sc->res == NULL) {
330 device_printf(dev, "couldn't map memory\n");
331 error = ENXIO;
332 goto fail;
333 }
334 sc->sc_st = rman_get_bustag(sc->res);
335 sc->sc_sh = rman_get_bushandle(sc->res);
336
337 /* Allocate interrupt */
338 rid = 0;
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339 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
340 RF_SHAREABLE | RF_ACTIVE);
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341
342 if (sc->irq == NULL) {
343 device_printf(dev, "couldn't map interrupt\n");
344 error = ENXIO;
345 goto fail;
346 }
347 /* Allocate DMA tags */
348 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
349 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * NV_MAX_FRAGS,
350 NV_MAX_FRAGS, MCLBYTES, 0,
351 &sc->mtag);
352 if (error) {
353 device_printf(dev, "couldn't allocate dma tag\n");
354 goto fail;
355 }
356 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
357 BUS_SPACE_MAXADDR, NULL, NULL,
358 sizeof(struct nv_rx_desc) * RX_RING_SIZE, 1,
359 sizeof(struct nv_rx_desc) * RX_RING_SIZE, 0,
360 &sc->rtag);
361 if (error) {
362 device_printf(dev, "couldn't allocate dma tag\n");
363 goto fail;
364 }
365 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
366 BUS_SPACE_MAXADDR, NULL, NULL,
367 sizeof(struct nv_tx_desc) * TX_RING_SIZE, 1,
368 sizeof(struct nv_tx_desc) * TX_RING_SIZE, 0,
369 &sc->ttag);
370 if (error) {
371 device_printf(dev, "couldn't allocate dma tag\n");
372 goto fail;
373 }
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374
375 error = bus_dmamap_create(sc->ttag, 0, &sc->tmap);
376 if (error) {
377 device_printf(dev, "couldn't create dma map\n");
378 goto fail;
379 }
380
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381 /* Allocate DMA safe memory and get the DMA addresses. */
382 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
4902425b 383 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tmap);
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384 if (error) {
385 device_printf(dev, "couldn't allocate dma memory\n");
386 goto fail;
387 }
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388 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
389 sizeof(struct nv_tx_desc) * TX_RING_SIZE, nv_dmamap_cb,
390 &sc->tx_addr, 0);
391 if (error) {
392 device_printf(dev, "couldn't map dma memory\n");
393 goto fail;
394 }
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395
396 error = bus_dmamap_create(sc->rtag, 0, &sc->rmap);
397 if (error) {
398 device_printf(dev, "couldn't create dma map\n");
399 goto fail;
400 }
401
a072e131 402 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
4902425b 403 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rmap);
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404 if (error) {
405 device_printf(dev, "couldn't allocate dma memory\n");
406 goto fail;
407 }
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408 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
409 sizeof(struct nv_rx_desc) * RX_RING_SIZE, nv_dmamap_cb,
410 &sc->rx_addr, 0);
411 if (error) {
412 device_printf(dev, "couldn't map dma memory\n");
413 goto fail;
414 }
415 /* Initialize rings. */
416 if (nv_init_rings(sc)) {
417 device_printf(dev, "failed to init rings\n");
418 error = ENXIO;
419 goto fail;
420 }
421 /* Setup NVIDIA API callback routines */
422 osapi = &sc->osapi;
423 osapi->pOSCX = sc;
424 osapi->pfnAllocMemory = nv_osalloc;
425 osapi->pfnFreeMemory = nv_osfree;
426 osapi->pfnAllocMemoryEx = nv_osallocex;
427 osapi->pfnFreeMemoryEx = nv_osfreeex;
428 osapi->pfnClearMemory = nv_osclear;
429 osapi->pfnStallExecution = nv_osdelay;
430 osapi->pfnAllocReceiveBuffer = nv_osallocrxbuf;
431 osapi->pfnFreeReceiveBuffer = nv_osfreerxbuf;
432 osapi->pfnPacketWasSent = nv_ospackettx;
433 osapi->pfnPacketWasReceived = nv_ospacketrx;
434 osapi->pfnLinkStateHasChanged = nv_oslinkchg;
435 osapi->pfnAllocTimer = nv_osalloctimer;
436 osapi->pfnFreeTimer = nv_osfreetimer;
437 osapi->pfnInitializeTimer = nv_osinittimer;
438 osapi->pfnSetTimer = nv_ossettimer;
439 osapi->pfnCancelTimer = nv_oscanceltimer;
440 osapi->pfnPreprocessPacket = nv_ospreprocpkt;
441 osapi->pfnPreprocessPacketNopq = nv_ospreprocpktnopq;
442 osapi->pfnIndicatePackets = nv_osindicatepkt;
443 osapi->pfnLockAlloc = nv_oslockalloc;
444 osapi->pfnLockAcquire = nv_oslockacquire;
445 osapi->pfnLockRelease = nv_oslockrelease;
446 osapi->pfnReturnBufferVirtual = nv_osreturnbufvirt;
447
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448 sc->linkup = FALSE;
449 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + FCS_LEN;
450
451 /* TODO - We don't support hardware offload yet */
452 sc->hwmode = 1;
453 sc->media = 0;
454
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455 /* Set NVIDIA API startup parameters */
456 OpenParams.MaxDpcLoop = 2;
457 OpenParams.MaxRxPkt = RX_RING_SIZE;
458 OpenParams.MaxTxPkt = TX_RING_SIZE;
459 OpenParams.SentPacketStatusSuccess = 1;
460 OpenParams.SentPacketStatusFailure = 0;
461 OpenParams.MaxRxPktToAccumulate = 6;
462 OpenParams.ulPollInterval = nv_pollinterval;
463 OpenParams.SetForcedModeEveryNthRxPacket = 0;
464 OpenParams.SetForcedModeEveryNthTxPacket = 0;
465 OpenParams.RxForcedInterrupt = 0;
466 OpenParams.TxForcedInterrupt = 0;
467 OpenParams.pOSApi = osapi;
468 OpenParams.pvHardwareBaseAddress = rman_get_virtual(sc->res);
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469 OpenParams.bASFEnabled = 0;
470 OpenParams.ulDescriptorVersion = sc->hwmode;
471 OpenParams.ulMaxPacketSize = sc->max_frame_size;
472 OpenParams.DeviceId = pci_get_device(dev);
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473
474 /* Open NVIDIA Hardware API */
475 error = ADAPTER_Open(&OpenParams, (void **)&(sc->hwapi), &sc->phyaddr);
476 if (error) {
477 device_printf(dev, "failed to open NVIDIA Hardware API: 0x%x\n", error);
478 goto fail;
479 }
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480
481 /* TODO - Add support for MODE2 hardware offload */
482
483 bzero(&sc->adapterdata, sizeof(sc->adapterdata));
484
485 sc->adapterdata.ulMediaIF = sc->media;
486 sc->adapterdata.ulModeRegTxReadCompleteEnable = 1;
487 sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata);
488
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489 sc->hwapi->pfnInit(sc->hwapi->pADCX,
490 0, /* force speed */
491 0, /* force full duplex */
492 0, /* force mode */
493 0, /* force async mode */
494 &sc->linkup);
495
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496 /* MAC is loaded backwards into h/w reg */
497 sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
498 for (i = 0; i < 6; i++) {
499 eaddr[i] = sc->original_mac_addr[5 - i];
500 }
501 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr);
502 bcopy(eaddr, (char *)&sc->sc_macaddr, ETHER_ADDR_LEN);
503
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504 DEBUGOUT(NV_DEBUG_INIT, "nv: do mii_phy_probe\n");
505
506 /* Probe device for MII interface to PHY */
59a5a75e 507 if (mii_phy_probe(dev, &sc->miibus, nv_ifmedia_upd, nv_ifmedia_sts)) {
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508 device_printf(dev, "MII without any phy!\n");
509 error = ENXIO;
510 goto fail;
511 }
512 /* Setup interface parameters */
513 ifp = &sc->sc_if;
514 ifp->if_softc = sc;
d0de58a2 515 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
517 ifp->if_ioctl = nv_ioctl;
518 ifp->if_start = nv_ifstart;
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519#ifdef DEVICE_POLLING
520 ifp->if_poll = nv_poll;
521#endif
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522 ifp->if_watchdog = nv_watchdog;
523 ifp->if_timer = 0;
524 ifp->if_init = nv_init;
525 ifp->if_mtu = ETHERMTU;
526 ifp->if_baudrate = IF_Mbps(100);
e5829d43
JS
527 ifp->if_capabilities |= IFCAP_VLAN_MTU;
528 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
ed0996d5 529 ifq_set_ready(&ifp->if_snd);
a072e131
JS
530
531 /* Attach to OS's managers. */
78195a76 532 ether_ifattach(ifp, sc->sc_macaddr, NULL);
a072e131
JS
533
534 /* Activate our interrupt handler. - attach last to avoid lock */
78195a76
MD
535 error = bus_setup_intr(sc->dev, sc->irq, INTR_NETSAFE,
536 nv_intr, sc, &sc->sc_ih, ifp->if_serializer);
a072e131 537 if (error) {
0dd4fceb 538 ether_ifdetach(ifp);
a072e131
JS
539 device_printf(sc->dev, "couldn't set up interrupt handler\n");
540 goto fail;
541 }
542 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_attach - exit\n");
543
544fail:
545 if (error)
546 nv_detach(dev);
547
548 return (error);
549}
550
551/* Detach interface for module unload */
552static int
553nv_detach(device_t dev)
554{
555 struct nv_softc *sc = device_get_softc(dev);
556 struct ifnet *ifp;
cdf89432 557 int is_attached;
a072e131 558
78195a76 559 ifp = &sc->arpcom.ac_if;
a072e131
JS
560
561 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_detach - entry\n");
562
cdf89432
SZ
563 lwkt_serialize_enter(ifp->if_serializer);
564
565 is_attached = device_is_attached(dev);
566 if (is_attached)
78195a76 567 nv_stop(sc);
a072e131
JS
568
569 if (sc->miibus)
570 device_delete_child(dev, sc->miibus);
571 bus_generic_detach(dev);
572
573 /* Reload unreversed address back into MAC in original state */
574 if (sc->original_mac_addr)
575 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
576
577 DEBUGOUT(NV_DEBUG_DEINIT, "nv: do pfnClose\n");
578 /* Detach from NVIDIA hardware API */
579 if (sc->hwapi->pfnClose)
e5829d43 580 sc->hwapi->pfnClose(sc->hwapi->pADCX, FALSE);
a072e131
JS
581 /* Release resources */
582 if (sc->sc_ih)
583 bus_teardown_intr(sc->dev, sc->irq, sc->sc_ih);
cdf89432
SZ
584
585 lwkt_serialize_exit(ifp->if_serializer);
586
587 if (is_attached)
588 ether_ifdetach(ifp);
589
a072e131
JS
590 if (sc->irq)
591 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
592 if (sc->res)
593 bus_release_resource(sc->dev, SYS_RES_MEMORY, NV_RID, sc->res);
594
595 nv_free_rings(sc);
596
597 if (sc->tx_desc) {
598 bus_dmamap_unload(sc->rtag, sc->rmap);
599 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
600 bus_dmamap_destroy(sc->rtag, sc->rmap);
601 }
602 if (sc->mtag)
603 bus_dma_tag_destroy(sc->mtag);
604 if (sc->ttag)
605 bus_dma_tag_destroy(sc->ttag);
606 if (sc->rtag)
607 bus_dma_tag_destroy(sc->rtag);
608
a072e131 609 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_detach - exit\n");
a072e131
JS
610 return (0);
611}
612
78195a76 613/* Initialise interface and start it "RUNNING" */
a072e131
JS
614static void
615nv_init(void *xsc)
616{
617 struct nv_softc *sc = xsc;
618 struct ifnet *ifp;
619 int error;
620
a072e131
JS
621 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init - entry (%d)\n", sc->linkup);
622
623 ifp = &sc->sc_if;
624
625 /* Do nothing if already running */
626 if (ifp->if_flags & IFF_RUNNING)
59a5a75e 627 return;
a072e131 628
78195a76 629 nv_stop(sc);
a072e131
JS
630
631 DEBUGOUT(NV_DEBUG_INIT, "nv: do pfnInit\n");
5662379b
SS
632
633 nv_ifmedia_upd(ifp);
634
a072e131 635 /* Setup Hardware interface and allocate memory structures */
e5829d43
JS
636 error = sc->hwapi->pfnInit(sc->hwapi->pADCX,
637 0, /* force speed */
638 0, /* force full duplex */
639 0, /* force mode */
640 0, /* force async mode */
641 &sc->linkup);
642
a072e131
JS
643 if (error) {
644 device_printf(sc->dev, "failed to start NVIDIA Hardware interface\n");
59a5a75e 645 return;
a072e131
JS
646 }
647 /* Set the MAC address */
648 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, sc->sc_macaddr);
59a5a75e 649
a072e131
JS
650 /* Setup multicast filter */
651 nv_setmulti(sc);
a072e131 652
d18fa9b5
MD
653 sc->hwapi->pfnStart(sc->hwapi->pADCX);
654
a072e131
JS
655 /* Update interface parameters */
656 ifp->if_flags |= IFF_RUNNING;
657 ifp->if_flags &= ~IFF_OACTIVE;
658
59a5a75e
MD
659 /*
660 * Enable the interrupt. Currently the nvidia API does not support
661 * polling, if we do not call pfnEnableInterrupts() we cannot
662 * issue the nvidia callback to process interrupts. Call the
663 * interrupt service routine in case the interrupt got stuck during
664 * a reset, renegotiation, or timeout.
665 */
666#if 1
78195a76 667 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
668 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
669#else
670 if ((ifp->if_flags & IFF_POLLING) == 0) {
78195a76 671 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
672 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
673 }
674#endif
675 nv_intr(sc);
676
9dda2746
MD
677 /*
678 * Reset watchdog and ring queue indexes. XXX if the interface
679 * is reset with pending tx packets queued to the actual device,
680 * the mbufs are currently lost.
681 */
682 ifp->if_timer = 0;
683 sc->pending_txs = 0;
684
204b91ae 685 callout_reset(&sc->nv_stat_timer, hz, nv_tick, sc);
a072e131
JS
686
687 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init - exit\n");
59a5a75e 688}
a072e131 689
59a5a75e
MD
690#ifdef DEVICE_POLLING
691
692static void
693nv_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
694{
695 struct nv_softc *sc = ifp->if_softc;
696
59a5a75e
MD
697 switch(cmd) {
698 case POLL_REGISTER:
699 /*
700 * We must disable the hardware interrupt on the device
701 * as well as ensure that any interrupt queued prior to
702 * this point does not execute the handler function.
703 *
704 * NOTE! The nvidia API does not support polling with
705 * interrupts disabled, so we have to leave them turned on
706 * unfortunately.
707 */
708#if 0
709 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
78195a76 710 lwkt_serialize_handler_disable(ifp->if_serializer);
59a5a75e
MD
711#endif
712 break;
713 case POLL_DEREGISTER:
714#if 0
78195a76 715 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
716 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
717#endif
718 break;
719 case POLL_AND_CHECK_STATUS:
720 /* fall through */
721 case POLL_ONLY:
722 if (ifp->if_flags & IFF_RUNNING) {
723 nv_intr(sc);
724 }
725 if (ifp->if_flags & IFF_RUNNING) {
726 if (!ifq_is_empty(&ifp->if_snd))
78195a76 727 nv_ifstart(ifp);
59a5a75e
MD
728 }
729 break;
730 }
59a5a75e 731}
a072e131 732
59a5a75e
MD
733#endif
734
a072e131
JS
735/* Stop interface activity ie. not "RUNNING" */
736static void
78195a76 737nv_stop(struct nv_softc *sc)
a072e131
JS
738{
739 struct ifnet *ifp;
740
a072e131
JS
741 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_stop - entry\n");
742
743 ifp = &sc->sc_if;
744 ifp->if_timer = 0;
745
746 /* Cancel tick timer */
204b91ae 747 callout_stop(&sc->nv_stat_timer);
a072e131 748
59a5a75e
MD
749 /*
750 * Stop hardware activity. The serializer handler disablement call
751 * prevents any interrupt scheduled prior to this call from calling
752 * the handler.
753 */
a072e131 754 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
78195a76 755 lwkt_serialize_handler_disable(ifp->if_serializer);
59a5a75e 756
d18fa9b5
MD
757 sc->hwapi->pfnStop(sc->hwapi->pADCX,
758 AFFECT_RECEIVER | AFFECT_TRANSMITTER);
59a5a75e 759 sc->hwapi->pfnClearTxDesc(sc->hwapi->pADCX);
a072e131
JS
760
761 DEBUGOUT(NV_DEBUG_DEINIT, "nv: do pfnDeinit\n");
762 /* Shutdown interface and deallocate memory buffers */
763 if (sc->hwapi->pfnDeinit)
764 sc->hwapi->pfnDeinit(sc->hwapi->pADCX, 0);
765
766 sc->linkup = 0;
767 sc->cur_rx = 0;
e5829d43 768 sc->pending_rxs = 0;
5662379b 769 sc->pending_txs = 0;
a072e131
JS
770
771 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
772
773 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_stop - exit\n");
a072e131
JS
774}
775
776/* Shutdown interface for unload/reboot */
777static void
778nv_shutdown(device_t dev)
779{
780 struct nv_softc *sc;
781
782 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_shutdown\n");
783
784 sc = device_get_softc(dev);
785
786 /* Stop hardware activity */
78195a76 787 lwkt_serialize_enter(sc->sc_if.if_serializer);
a072e131 788 nv_stop(sc);
78195a76 789 lwkt_serialize_exit(sc->sc_if.if_serializer);
a072e131
JS
790}
791
792/* Allocate TX ring buffers */
793static int
794nv_init_rings(struct nv_softc *sc)
795{
796 int error, i;
797
a072e131
JS
798 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init_rings - entry\n");
799
800 sc->cur_rx = sc->cur_tx = sc->pending_rxs = sc->pending_txs = 0;
801 /* Initialise RX ring */
802 for (i = 0; i < RX_RING_SIZE; i++) {
803 struct nv_rx_desc *desc = sc->rx_desc + i;
804 struct nv_map_buffer *buf = &desc->buf;
805
806 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
807 if (buf->mbuf == NULL) {
808 device_printf(sc->dev, "couldn't allocate mbuf\n");
809 nv_free_rings(sc);
810 error = ENOBUFS;
811 goto fail;
812 }
813 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
814 m_adj(buf->mbuf, ETHER_ALIGN);
815
816 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
817 if (error) {
818 device_printf(sc->dev, "couldn't create dma map\n");
819 nv_free_rings(sc);
820 goto fail;
821 }
822 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
823 nv_dmamap_rx_cb, &desc->paddr, 0);
824 if (error) {
825 device_printf(sc->dev, "couldn't dma map mbuf\n");
826 nv_free_rings(sc);
827 goto fail;
828 }
829 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
830
831 desc->buflength = buf->mbuf->m_len;
e5829d43 832 desc->vaddr = mtod(buf->mbuf, caddr_t);
a072e131
JS
833 }
834 bus_dmamap_sync(sc->rtag, sc->rmap,
835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
836
837 /* Initialize TX ring */
838 for (i = 0; i < TX_RING_SIZE; i++) {
839 struct nv_tx_desc *desc = sc->tx_desc + i;
840 struct nv_map_buffer *buf = &desc->buf;
841
842 buf->mbuf = NULL;
843
844 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
845 if (error) {
846 device_printf(sc->dev, "couldn't create dma map\n");
847 nv_free_rings(sc);
848 goto fail;
849 }
850 }
851 bus_dmamap_sync(sc->ttag, sc->tmap,
852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
853
854 DEBUGOUT(NV_DEBUG_INIT, "nv: nv_init_rings - exit\n");
855
856fail:
a072e131
JS
857 return (error);
858}
859
860/* Free the TX ring buffers */
861static void
862nv_free_rings(struct nv_softc *sc)
863{
864 int i;
865
a072e131
JS
866 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_free_rings - entry\n");
867
868 for (i = 0; i < RX_RING_SIZE; i++) {
869 struct nv_rx_desc *desc = sc->rx_desc + i;
870 struct nv_map_buffer *buf = &desc->buf;
871
872 if (buf->mbuf) {
873 bus_dmamap_unload(sc->mtag, buf->map);
874 bus_dmamap_destroy(sc->mtag, buf->map);
875 m_freem(buf->mbuf);
876 }
877 buf->mbuf = NULL;
878 }
879
880 for (i = 0; i < TX_RING_SIZE; i++) {
881 struct nv_tx_desc *desc = sc->tx_desc + i;
882 struct nv_map_buffer *buf = &desc->buf;
883
884 if (buf->mbuf) {
885 bus_dmamap_unload(sc->mtag, buf->map);
886 bus_dmamap_destroy(sc->mtag, buf->map);
887 m_freem(buf->mbuf);
888 }
889 buf->mbuf = NULL;
890 }
891
892 DEBUGOUT(NV_DEBUG_DEINIT, "nv: nv_free_rings - exit\n");
a072e131
JS
893}
894
895/* Main loop for sending packets from OS to interface */
59a5a75e 896
a072e131
JS
897static void
898nv_ifstart(struct ifnet *ifp)
899{
900 struct nv_softc *sc = ifp->if_softc;
901 struct nv_map_buffer *buf;
902 struct mbuf *m0, *m;
903 struct nv_tx_desc *desc;
904 ADAPTER_WRITE_DATA txdata;
905 int error, i;
906
907 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_ifstart - entry\n");
908
909 /* If link is down/busy or queue is empty do nothing */
59a5a75e 910 if ((ifp->if_flags & IFF_OACTIVE) || ifq_is_empty(&ifp->if_snd))
a072e131
JS
911 return;
912
913 /* Transmit queued packets until sent or TX ring is full */
914 while (sc->pending_txs < TX_RING_SIZE) {
915 desc = sc->tx_desc + sc->cur_tx;
916 buf = &desc->buf;
917
918 /* Get next packet to send. */
d2c71fa0 919 m0 = ifq_dequeue(&ifp->if_snd, NULL);
a072e131
JS
920
921 /* If nothing to send, return. */
922 if (m0 == NULL)
923 return;
924
925 /* Map MBUF for DMA access */
926 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
927 nv_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
928
929 if (error && error != EFBIG) {
930 m_freem(m0);
931 sc->tx_errors++;
932 continue;
933 }
934 /*
935 * Packet has too many fragments - defrag into new mbuf
936 * cluster
937 */
938 if (error) {
939 m = m_defrag(m0, MB_DONTWAIT);
940 if (m == NULL) {
941 m_freem(m0);
942 sc->tx_errors++;
943 continue;
944 }
a072e131
JS
945 m0 = m;
946
947 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
948 nv_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
949 if (error) {
950 m_freem(m);
951 sc->tx_errors++;
952 continue;
953 }
954 }
955 /* Do sync on DMA bounce buffer */
956 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
957
958 buf->mbuf = m0;
959 txdata.ulNumberOfElements = desc->numfrags;
960 txdata.pvID = (PVOID)desc;
961
962 /* Put fragments into API element list */
963 txdata.ulTotalLength = buf->mbuf->m_len;
964 for (i = 0; i < desc->numfrags; i++) {
965 txdata.sElement[i].ulLength = (ulong)desc->frags[i].ds_len;
966 txdata.sElement[i].pPhysical = (PVOID)desc->frags[i].ds_addr;
967 }
968
969 /* Send packet to Nvidia API for transmission */
970 error = sc->hwapi->pfnWrite(sc->hwapi->pADCX, &txdata);
971
972 switch (error) {
973 case ADAPTERERR_NONE:
974 /* Packet was queued in API TX queue successfully */
975 sc->pending_txs++;
976 sc->cur_tx = (sc->cur_tx + 1) % TX_RING_SIZE;
977 break;
978
979 case ADAPTERERR_TRANSMIT_QUEUE_FULL:
980 /* The API TX queue is full - requeue the packet */
981 device_printf(sc->dev, "nv_ifstart: transmit queue is full\n");
982 ifp->if_flags |= IFF_OACTIVE;
983 bus_dmamap_unload(sc->mtag, buf->map);
a072e131 984 buf->mbuf = NULL;
9dda2746 985 m_freem(m0); /* XXX requeue */
a072e131
JS
986 return;
987
988 default:
989 /* The API failed to queue/send the packet so dump it */
990 device_printf(sc->dev, "nv_ifstart: transmit error\n");
991 bus_dmamap_unload(sc->mtag, buf->map);
992 m_freem(buf->mbuf);
993 buf->mbuf = NULL;
994 sc->tx_errors++;
995 return;
996 }
997 /* Set watchdog timer. */
998 ifp->if_timer = 8;
999
1000 /* Copy packet to BPF tap */
1001 BPF_MTAP(ifp, m0);
1002 }
1003 ifp->if_flags |= IFF_OACTIVE;
1004
1005 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_ifstart - exit\n");
1006}
1007
1008/* Handle IOCTL events */
1009static int
1010nv_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1011{
1012 struct nv_softc *sc = ifp->if_softc;
1013 struct ifreq *ifr = (struct ifreq *) data;
1014 struct mii_data *mii;
1015 int error = 0;
1016
a072e131
JS
1017 DEBUGOUT(NV_DEBUG_IOCTL, "nv: nv_ioctl - entry\n");
1018
1019 switch (command) {
1020 case SIOCSIFMTU:
1021 /* Set MTU size */
1022 if (ifp->if_mtu == ifr->ifr_mtu)
1023 break;
e5829d43 1024 if (ifr->ifr_mtu + ifp->if_hdrlen <= MAX_PACKET_SIZE_1518) {
a072e131 1025 ifp->if_mtu = ifr->ifr_mtu;
78195a76
MD
1026 nv_stop(sc);
1027 nv_init(sc);
a072e131
JS
1028 } else
1029 error = EINVAL;
1030 break;
1031
1032 case SIOCSIFFLAGS:
1033 /* Setup interface flags */
1034 if (ifp->if_flags & IFF_UP) {
1035 if ((ifp->if_flags & IFF_RUNNING) == 0) {
78195a76 1036 nv_init(sc);
a072e131
JS
1037 break;
1038 }
1039 } else {
1040 if (ifp->if_flags & IFF_RUNNING) {
78195a76 1041 nv_stop(sc);
a072e131
JS
1042 break;
1043 }
1044 }
1045
1046 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
1047 nv_setmulti(sc);
1048 break;
1049
1050 case SIOCADDMULTI:
1051 case SIOCDELMULTI:
1052 /* Setup multicast filter */
1053 if (ifp->if_flags & IFF_RUNNING) {
1054 nv_setmulti(sc);
1055 }
1056 break;
1057 case SIOCGIFMEDIA:
1058 case SIOCSIFMEDIA:
1059 /* Get/Set interface media parameters */
1060 mii = device_get_softc(sc->miibus);
1061 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1062 break;
1063
1064 default:
1065 /* Everything else we forward to generic ether ioctl */
0b4a1d3a 1066 error = ether_ioctl(ifp, command, data);
a072e131
JS
1067 break;
1068 }
1069
1070 DEBUGOUT(NV_DEBUG_IOCTL, "nv: nv_ioctl - exit\n");
1071
a072e131
JS
1072 return (error);
1073}
1074
59a5a75e
MD
1075/*
1076 * Interrupt service routine. The serializer has already been entered
1077 * since we installed it in our bus_setup_intr() call.
1078 */
a072e131
JS
1079static void
1080nv_intr(void *arg)
1081{
1082 struct nv_softc *sc = arg;
1083 struct ifnet *ifp = &sc->sc_if;
1084
1085 DEBUGOUT(NV_DEBUG_INTERRUPT, "nv: nv_intr - entry\n");
1086
59a5a75e
MD
1087 /*
1088 * Handle an interrupt event. Unfortunately the nvidia API
1089 * does not support interrupt disablement when polling, so we
1090 * have to re-enable after the query masks them off.
1091 */
a072e131
JS
1092 if (sc->hwapi->pfnQueryInterrupt(sc->hwapi->pADCX)) {
1093 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
59a5a75e 1094#if 1
78195a76 1095 lwkt_serialize_handler_enable(ifp->if_serializer);
a072e131 1096 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
59a5a75e
MD
1097#else
1098 if ((ifp->if_flags & IFF_POLLING) == 0) {
78195a76 1099 lwkt_serialize_handler_enable(ifp->if_serializer);
59a5a75e
MD
1100 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1101 }
1102#endif
a072e131 1103 }
c7f5b673 1104 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1105 nv_ifstart(ifp);
a072e131
JS
1106
1107 /* If no pending packets we don't need a timeout */
1108 if (sc->pending_txs == 0)
1109 sc->sc_if.if_timer = 0;
1110
1111 DEBUGOUT(NV_DEBUG_INTERRUPT, "nv: nv_intr - exit\n");
a072e131
JS
1112}
1113
59a5a75e
MD
1114/*
1115 * Setup multicast filters
1116 *
1117 * Serialized on call
1118 */
a072e131
JS
1119static void
1120nv_setmulti(struct nv_softc *sc)
1121{
1122 struct ifnet *ifp;
1123 struct ifmultiaddr *ifma;
1124 PACKET_FILTER hwfilter;
1125 int i;
1126 u_int8_t oraddr[6];
1127 u_int8_t andaddr[6];
1128
a072e131
JS
1129 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_setmulti - entry\n");
1130
1131 ifp = &sc->sc_if;
1132
1133 /* Initialize filter */
1134 hwfilter.ulFilterFlags = 0;
1135 for (i = 0; i < 6; i++) {
1136 hwfilter.acMulticastAddress[i] = 0;
1137 hwfilter.acMulticastMask[i] = 0;
1138 }
1139
1140 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1141 /* Accept all packets */
1142 hwfilter.ulFilterFlags |= ACCEPT_ALL_PACKETS;
1143 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
a072e131
JS
1144 return;
1145 }
1146 /* Setup multicast filter */
1147 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1148 u_char *addrp;
1149
1150 if (ifma->ifma_addr->sa_family != AF_LINK)
1151 continue;
1152
1153 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1154 for (i = 0; i < 6; i++) {
1155 u_int8_t mcaddr = addrp[i];
1156 andaddr[i] &= mcaddr;
1157 oraddr[i] |= mcaddr;
1158 }
1159 }
1160 for (i = 0; i < 6; i++) {
1161 hwfilter.acMulticastAddress[i] = andaddr[i] & oraddr[i];
1162 hwfilter.acMulticastMask[i] = andaddr[i] | (~oraddr[i]);
1163 }
1164
1165 /* Send filter to NVIDIA API */
1166 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1167
a072e131 1168 DEBUGOUT(NV_DEBUG_RUNNING, "nv: nv_setmulti - exit\n");
a072e131
JS
1169}
1170
59a5a75e
MD
1171/*
1172 * Change the current media/mediaopts
1173 *
1174 * Serialized on call
1175 */
a072e131
JS
1176static int
1177nv_ifmedia_upd(struct ifnet *ifp)
1178{
1179 struct nv_softc *sc = ifp->if_softc;
1180 struct mii_data *mii;
1181
1182 DEBUGOUT(NV_DEBUG_MII, "nv: nv_ifmedia_upd\n");
1183
1184 mii = device_get_softc(sc->miibus);
1185
1186 if (mii->mii_instance) {
1187 struct mii_softc *miisc;
1188 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1189 miisc = LIST_NEXT(miisc, mii_list)) {
1190 mii_phy_reset(miisc);
1191 }
1192 }
1193 mii_mediachg(mii);
1194
1195 return (0);
1196}
1197
59a5a75e
MD
1198/*
1199 * Update current miibus PHY status of media
1200 *
1201 * Serialized on call
1202 */
a072e131
JS
1203static void
1204nv_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1205{
1206 struct nv_softc *sc;
1207 struct mii_data *mii;
1208
1209 DEBUGOUT(NV_DEBUG_MII, "nv: nv_ifmedia_sts\n");
1210
1211 sc = ifp->if_softc;
1212 mii = device_get_softc(sc->miibus);
1213 mii_pollstat(mii);
1214
1215 ifmr->ifm_active = mii->mii_media_active;
1216 ifmr->ifm_status = mii->mii_media_status;
a072e131
JS
1217}
1218
1219/* miibus tick timer - maintain link status */
1220static void
1221nv_tick(void *xsc)
1222{
1223 struct nv_softc *sc = xsc;
1224 struct mii_data *mii;
1225 struct ifnet *ifp;
1226
a072e131 1227 ifp = &sc->sc_if;
78195a76 1228 lwkt_serialize_enter(ifp->if_serializer);
a072e131
JS
1229 nv_update_stats(sc);
1230
1231 mii = device_get_softc(sc->miibus);
1232 mii_tick(mii);
1233
59a5a75e 1234 if ((mii->mii_media_status & IFM_ACTIVE) &&
a072e131 1235 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
c7f5b673 1236 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1237 nv_ifstart(ifp);
a072e131 1238 }
204b91ae 1239 callout_reset(&sc->nv_stat_timer, hz, nv_tick, sc);
78195a76 1240 lwkt_serialize_exit(ifp->if_serializer);
a072e131
JS
1241}
1242
1243/* Update ifnet data structure with collected interface stats from API */
1244static void
1245nv_update_stats(struct nv_softc *sc)
1246{
1247 struct ifnet *ifp = &sc->sc_if;
1248 ADAPTER_STATS stats;
1249
a072e131
JS
1250 if (sc->hwapi) {
1251 sc->hwapi->pfnGetStatistics(sc->hwapi->pADCX, &stats);
1252
1253 ifp->if_ipackets = stats.ulSuccessfulReceptions;
1254 ifp->if_ierrors = stats.ulMissedFrames +
1255 stats.ulFailedReceptions +
1256 stats.ulCRCErrors +
1257 stats.ulFramingErrors +
1258 stats.ulOverFlowErrors;
1259
1260 ifp->if_opackets = stats.ulSuccessfulTransmissions;
1261 ifp->if_oerrors = sc->tx_errors +
1262 stats.ulFailedTransmissions +
1263 stats.ulRetryErrors +
1264 stats.ulUnderflowErrors +
1265 stats.ulLossOfCarrierErrors +
1266 stats.ulLateCollisionErrors;
1267
1268 ifp->if_collisions = stats.ulLateCollisionErrors;
1269 }
a072e131
JS
1270}
1271
1272/* miibus Read PHY register wrapper - calls Nvidia API entry point */
1273static int
1274nv_miibus_readreg(device_t dev, int phy, int reg)
1275{
1276 struct nv_softc *sc = device_get_softc(dev);
e5829d43 1277 ULONG data;
a072e131
JS
1278
1279 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_readreg - entry\n");
1280
1281 ADAPTER_ReadPhy(sc->hwapi->pADCX, phy, reg, &data);
1282
1283 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_readreg - exit\n");
1284
1285 return (data);
1286}
1287
1288/* miibus Write PHY register wrapper - calls Nvidia API entry point */
1289static void
1290nv_miibus_writereg(device_t dev, int phy, int reg, int data)
1291{
1292 struct nv_softc *sc = device_get_softc(dev);
1293
1294 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_writereg - entry\n");
1295
1296 ADAPTER_WritePhy(sc->hwapi->pADCX, phy, reg, (ulong)data);
1297
1298 DEBUGOUT(NV_DEBUG_MII, "nv: nv_miibus_writereg - exit\n");
a072e131
JS
1299}
1300
1301/* Watchdog timer to prevent PHY lockups */
1302static void
1303nv_watchdog(struct ifnet *ifp)
1304{
1305 struct nv_softc *sc = ifp->if_softc;
1306
9dda2746
MD
1307 device_printf(sc->dev, "device timeout (%d) flags %d\n",
1308 sc->pending_txs, ifp->if_flags & IFF_OACTIVE);
a072e131
JS
1309
1310 sc->tx_errors++;
1311
78195a76 1312 nv_stop(sc);
a072e131 1313 ifp->if_flags &= ~IFF_RUNNING;
78195a76 1314 nv_init(sc);
a072e131 1315
c7f5b673 1316 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1317 nv_ifstart(ifp);
a072e131
JS
1318}
1319
1320/* --- Start of NVOSAPI interface --- */
1321
1322/* Allocate DMA enabled general use memory for API */
e5829d43
JS
1323static NV_SINT32
1324nv_osalloc(PNV_VOID ctx, PMEMORY_BLOCK mem)
a072e131
JS
1325{
1326 struct nv_softc *sc;
1327 bus_addr_t mem_physical;
1328
1329 DEBUGOUT(NV_DEBUG_API, "nv: nv_osalloc - %d\n", mem->uiLength);
1330
1331 sc = (struct nv_softc *)ctx;
1332
1333 mem->pLogical = (PVOID)contigmalloc(mem->uiLength, M_DEVBUF,
5662379b 1334 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
a072e131
JS
1335
1336 if (!mem->pLogical) {
1337 device_printf(sc->dev, "memory allocation failed\n");
1338 return (0);
1339 }
1340 memset(mem->pLogical, 0, (ulong)mem->uiLength);
1341 mem_physical = vtophys(mem->pLogical);
1342 mem->pPhysical = (PVOID)mem_physical;
1343
e5829d43
JS
1344 DEBUGOUT(NV_DEBUG_API, "nv: nv_osalloc %p/%p - %d\n",
1345 mem->pLogical, mem->pPhysical, mem->uiLength);
a072e131
JS
1346
1347 return (1);
1348}
1349
1350/* Free allocated memory */
e5829d43
JS
1351static NV_SINT32
1352nv_osfree(PNV_VOID ctx, PMEMORY_BLOCK mem)
a072e131 1353{
e5829d43
JS
1354 DEBUGOUT(NV_DEBUG_API, "nv: nv_osfree - %p - %d\n",
1355 mem->pLogical, mem->uiLength);
a072e131
JS
1356
1357 contigfree(mem->pLogical, PAGE_SIZE, M_DEVBUF);
1358 return (1);
1359}
1360
1361/* Copied directly from nvnet.c */
e5829d43
JS
1362static NV_SINT32
1363nv_osallocex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
a072e131
JS
1364{
1365 MEMORY_BLOCK mem_block;
1366
1367 DEBUGOUT(NV_DEBUG_API, "nv: nv_osallocex\n");
1368
1369 mem_block_ex->pLogical = NULL;
1370 mem_block_ex->uiLengthOrig = mem_block_ex->uiLength;
1371
1372 if ((mem_block_ex->AllocFlags & ALLOC_MEMORY_ALIGNED) &&
1373 (mem_block_ex->AlignmentSize > 1)) {
1374 DEBUGOUT(NV_DEBUG_API, " aligning on %d\n",
1375 mem_block_ex->AlignmentSize);
1376 mem_block_ex->uiLengthOrig += mem_block_ex->AlignmentSize;
1377 }
1378 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1379
1380 if (nv_osalloc(ctx, &mem_block) == 0) {
1381 return (0);
1382 }
1383 mem_block_ex->pLogicalOrig = mem_block.pLogical;
e5829d43 1384 mem_block_ex->pPhysicalOrigLow = (uintptr_t)mem_block.pPhysical;
a072e131
JS
1385 mem_block_ex->pPhysicalOrigHigh = 0;
1386
1387 mem_block_ex->pPhysical = mem_block.pPhysical;
1388 mem_block_ex->pLogical = mem_block.pLogical;
1389
1390 if (mem_block_ex->uiLength != mem_block_ex->uiLengthOrig) {
1391 unsigned int offset;
1392 offset = mem_block_ex->pPhysicalOrigLow & (mem_block_ex->AlignmentSize - 1);
1393
1394 if (offset) {
e5829d43 1395 mem_block_ex->pPhysical = (PVOID)((uintptr_t)mem_block_ex->pPhysical +
a072e131 1396 mem_block_ex->AlignmentSize - offset);
e5829d43 1397 mem_block_ex->pLogical = (PVOID)((uintptr_t)mem_block_ex->pLogical +
a072e131
JS
1398 mem_block_ex->AlignmentSize - offset);
1399 } /* if (offset) */
1400 } /* if (mem_block_ex->uiLength !=
1401 * mem_block_ex->uiLengthOrig) */
1402 return (1);
1403}
1404
1405/* Copied directly from nvnet.c */
e5829d43
JS
1406static NV_SINT32
1407nv_osfreeex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
a072e131
JS
1408{
1409 MEMORY_BLOCK mem_block;
1410
1411 DEBUGOUT(NV_DEBUG_API, "nv: nv_osfreeex\n");
1412
1413 mem_block.pLogical = mem_block_ex->pLogicalOrig;
e5829d43 1414 mem_block.pPhysical = (PVOID)((uintptr_t)mem_block_ex->pPhysicalOrigLow);
a072e131
JS
1415 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1416
1417 return (nv_osfree(ctx, &mem_block));
1418}
1419
1420/* Clear memory region */
e5829d43
JS
1421static NV_SINT32
1422nv_osclear(PNV_VOID ctx, PNV_VOID mem, NV_SINT32 length)
a072e131
JS
1423{
1424 DEBUGOUT(NV_DEBUG_API, "nv: nv_osclear\n");
1425 memset(mem, 0, length);
1426 return (1);
1427}
1428
1429/* Sleep for a tick */
e5829d43
JS
1430static NV_SINT32
1431nv_osdelay(PNV_VOID ctx, NV_UINT32 usec)
a072e131 1432{
59a5a75e
MD
1433 if (usec >= 1000000 / hz) {
1434 tsleep(nv_osdelay, 0, "nvdelay", (usec * hz / 1000000) + 1);
1435 } else {
1436 DELAY(usec);
1437 }
a072e131
JS
1438 return (1);
1439}
1440
1441/* Allocate memory for rx buffer */
e5829d43
JS
1442static NV_SINT32
1443nv_osallocrxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID *id)
a072e131
JS
1444{
1445 struct nv_softc *sc = ctx;
1446 struct nv_rx_desc *desc;
1447 struct nv_map_buffer *buf;
1448 int error;
1449
a072e131
JS
1450 DEBUGOUT(NV_DEBUG_API, "nv: nv_osallocrxbuf\n");
1451
1452 if (sc->pending_rxs == RX_RING_SIZE) {
1453 device_printf(sc->dev, "rx ring buffer is full\n");
1454 goto fail;
1455 }
1456 desc = sc->rx_desc + sc->cur_rx;
1457 buf = &desc->buf;
1458
1459 if (buf->mbuf == NULL) {
1460 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1461 if (buf->mbuf == NULL) {
1462 device_printf(sc->dev, "failed to allocate memory\n");
1463 goto fail;
1464 }
1465 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1466 m_adj(buf->mbuf, ETHER_ALIGN);
1467
1468 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1469 nv_dmamap_rx_cb, &desc->paddr, 0);
1470 if (error) {
1471 device_printf(sc->dev, "failed to dmamap mbuf\n");
1472 m_freem(buf->mbuf);
1473 buf->mbuf = NULL;
1474 goto fail;
1475 }
1476 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1477 desc->buflength = buf->mbuf->m_len;
1478 desc->vaddr = mtod(buf->mbuf, PVOID);
1479 }
1480 sc->pending_rxs++;
1481 sc->cur_rx = (sc->cur_rx + 1) % RX_RING_SIZE;
1482
1483 mem->pLogical = (void *)desc->vaddr;
1484 mem->pPhysical = (void *)desc->paddr;
1485 mem->uiLength = desc->buflength;
1486 *id = (void *)desc;
1487
a072e131 1488 return (1);
e5829d43 1489fail:
e5829d43 1490 return (0);
a072e131
JS
1491}
1492
1493
1494/* Free the rx buffer */
e5829d43
JS
1495static NV_SINT32
1496nv_osfreerxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID id)
a072e131
JS
1497{
1498 struct nv_softc *sc = ctx;
1499 struct nv_rx_desc *desc;
1500 struct nv_map_buffer *buf;
1501
a072e131
JS
1502 DEBUGOUT(NV_DEBUG_API, "nv: nv_osfreerxbuf\n");
1503
1504 desc = (struct nv_rx_desc *) id;
1505 buf = &desc->buf;
1506
1507 if (buf->mbuf) {
1508 bus_dmamap_unload(sc->mtag, buf->map);
1509 bus_dmamap_destroy(sc->mtag, buf->map);
1510 m_freem(buf->mbuf);
1511 }
1512 sc->pending_rxs--;
1513 buf->mbuf = NULL;
1514
a072e131
JS
1515 return (1);
1516}
1517
1518/* This gets called by the Nvidia API after our TX packet has been sent */
e5829d43
JS
1519static NV_SINT32
1520nv_ospackettx(PNV_VOID ctx, PNV_VOID id, NV_UINT32 success)
a072e131
JS
1521{
1522 struct nv_softc *sc = ctx;
1523 struct nv_map_buffer *buf;
1524 struct nv_tx_desc *desc = (struct nv_tx_desc *) id;
1525 struct ifnet *ifp;
1526
a072e131
JS
1527 DEBUGOUT(NV_DEBUG_API, "nv: nv_ospackettx\n");
1528
1529 ifp = &sc->sc_if;
a072e131 1530 buf = &desc->buf;
e5829d43 1531 sc->pending_txs--;
a072e131 1532
e5829d43 1533 /* Unload and free mbuf cluster */
a072e131
JS
1534 if (buf->mbuf == NULL)
1535 goto fail;
1536
1537 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
1538 bus_dmamap_unload(sc->mtag, buf->map);
1539 m_freem(buf->mbuf);
1540 buf->mbuf = NULL;
1541
9dda2746
MD
1542 /*
1543 * Make sure we are clear to go if we previously stalled due
1544 * to a full ring.
1545 */
1546 if (sc->pending_txs < TX_RING_SIZE) {
1547 ifp->if_flags &= ~IFF_OACTIVE;
1548 if (!ifq_is_empty(&ifp->if_snd))
78195a76 1549 nv_ifstart(ifp);
9dda2746 1550 }
a072e131 1551fail:
a072e131
JS
1552 return (1);
1553}
1554
1555/* This gets called by the Nvidia API when a new packet has been received */
1556/* XXX What is newbuf used for? XXX */
e5829d43
JS
1557static NV_SINT32
1558nv_ospacketrx(PNV_VOID ctx, PNV_VOID data, NV_UINT32 success,
1559 NV_UINT8 *newbuf, NV_UINT8 priority)
a072e131
JS
1560{
1561 struct nv_softc *sc = ctx;
1562 struct ifnet *ifp;
1563 struct nv_rx_desc *desc;
1564 struct nv_map_buffer *buf;
1565 ADAPTER_READ_DATA *readdata;
a072e131
JS
1566
1567 DEBUGOUT(NV_DEBUG_API, "nv: nv_ospacketrx\n");
1568
1569 ifp = &sc->sc_if;
1570
1571 readdata = (ADAPTER_READ_DATA *) data;
1572 desc = readdata->pvID;
1573 buf = &desc->buf;
1574 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1575
1576 if (success) {
1577 /* Sync DMA bounce buffer. */
1578 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1579
1580 /* First mbuf in packet holds the ethernet and packet headers */
1581 buf->mbuf->m_pkthdr.rcvif = ifp;
1582 buf->mbuf->m_pkthdr.len = buf->mbuf->m_len = readdata->ulTotalLength;
1583
1584 bus_dmamap_unload(sc->mtag, buf->map);
1585
1586 /* Give mbuf to OS. */
78195a76 1587 ifp->if_input(ifp, buf->mbuf);
a072e131
JS
1588 if (readdata->ulFilterMatch & ADREADFL_MULTICAST_MATCH)
1589 ifp->if_imcasts++;
1590
1591 /* Blat the mbuf pointer, kernel will free the mbuf cluster */
1592 buf->mbuf = NULL;
1593 } else {
1594 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1595 bus_dmamap_unload(sc->mtag, buf->map);
1596 m_freem(buf->mbuf);
1597 buf->mbuf = NULL;
1598 }
1599
1600 sc->cur_rx = desc - sc->rx_desc;
1601 sc->pending_rxs--;
1602
a072e131
JS
1603 return (1);
1604}
1605
1606/* This gets called by NVIDIA API when the PHY link state changes */
e5829d43
JS
1607static NV_SINT32
1608nv_oslinkchg(PNV_VOID ctx, NV_SINT32 enabled)
a072e131 1609{
a072e131
JS
1610 DEBUGOUT(NV_DEBUG_API, "nv: nv_oslinkchg\n");
1611
a072e131
JS
1612 return (1);
1613}
1614
1615
1616/* Setup a watchdog timer */
e5829d43
JS
1617static NV_SINT32
1618nv_osalloctimer(PNV_VOID ctx, PNV_VOID *timer)
a072e131
JS
1619{
1620 struct nv_softc *sc = (struct nv_softc *)ctx;
1621
1622 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osalloctimer\n");
1623
01a09a77 1624 callout_init(&sc->ostimer);
a072e131
JS
1625 *timer = &sc->ostimer;
1626
1627 return (1);
1628}
1629
1630/* Free the timer */
e5829d43
JS
1631static NV_SINT32
1632nv_osfreetimer(PNV_VOID ctx, PNV_VOID timer)
a072e131
JS
1633{
1634 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osfreetimer\n");
1635
1636 return (1);
1637}
1638
1639/* Setup timer parameters */
e5829d43
JS
1640static NV_SINT32
1641nv_osinittimer(PNV_VOID ctx, PNV_VOID timer, PTIMER_FUNC func, PNV_VOID parameters)
a072e131
JS
1642{
1643 struct nv_softc *sc = (struct nv_softc *)ctx;
1644
1645 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osinittimer\n");
1646
1647 sc->ostimer_func = func;
1648 sc->ostimer_params = parameters;
1649
1650 return (1);
1651}
1652
78195a76
MD
1653static void
1654nv_ostimer_callback(void *data)
1655{
1656 struct nv_softc *sc = data;
1657 struct ifnet *ifp = &sc->sc_if;
1658
1659 lwkt_serialize_enter(ifp->if_serializer);
1660 sc->ostimer_func(sc->ostimer_params);
1661 lwkt_serialize_exit(ifp->if_serializer);
1662}
1663
59a5a75e
MD
1664/*
1665 * Set the timer to go off
1666 *
1667 * XXX what the hell are the units for 'delay' ? They sure aren't ticks!
1668 */
e5829d43
JS
1669static NV_SINT32
1670nv_ossettimer(PNV_VOID ctx, PNV_VOID timer, NV_UINT32 delay)
a072e131
JS
1671{
1672 struct nv_softc *sc = ctx;
1673
1674 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_ossettimer\n");
59a5a75e 1675 printf("nv_ossettimer %d\n", (int)delay);
a072e131 1676
78195a76 1677 callout_reset(&sc->ostimer, delay, nv_ostimer_callback, sc);
a072e131
JS
1678
1679 return (1);
1680}
1681
1682/* Cancel the timer */
e5829d43
JS
1683static NV_SINT32
1684nv_oscanceltimer(PNV_VOID ctx, PNV_VOID timer)
a072e131
JS
1685{
1686 struct nv_softc *sc = ctx;
1687
1688 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_oscanceltimer\n");
1689
01a09a77 1690 callout_stop(&sc->ostimer);
a072e131
JS
1691
1692 return (1);
1693}
1694
e5829d43
JS
1695static NV_SINT32
1696nv_ospreprocpkt(PNV_VOID ctx, PNV_VOID readdata, PNV_VOID *id, NV_UINT8 *newbuffer,
1697 NV_UINT8 priority)
a072e131
JS
1698{
1699 /* Not implemented */
1700 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_ospreprocpkt\n");
1701
1702 return (1);
1703}
1704
e5829d43
JS
1705static PNV_VOID
1706nv_ospreprocpktnopq(PNV_VOID ctx, PNV_VOID readdata)
a072e131
JS
1707{
1708 /* Not implemented */
1709 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_ospreprocpkt\n");
1710
1711 return (NULL);
1712}
1713
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1714static NV_SINT32
1715nv_osindicatepkt(PNV_VOID ctx, PNV_VOID *id, NV_UINT32 pktno)
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1716{
1717 /* Not implemented */
1718 DEBUGOUT(NV_DEBUG_BROKEN, "nv: nv_osindicatepkt\n");
1719
1720 return (1);
1721}
1722
1723/* Allocate mutex context (already done in nv_attach) */
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1724static NV_SINT32
1725nv_oslockalloc(PNV_VOID ctx, NV_SINT32 type, PNV_VOID *pLock)
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1726{
1727 struct nv_softc *sc = (struct nv_softc *)ctx;
1728
1729 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_oslockalloc\n");
1730
1731 *pLock = (void **)sc;
1732
1733 return (1);
1734}
1735
1736/* Obtain a spin lock */
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1737static NV_SINT32
1738nv_oslockacquire(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
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1739{
1740 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_oslockacquire\n");
1741
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1742 return (1);
1743}
1744
1745/* Release lock */
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1746static NV_SINT32
1747nv_oslockrelease(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
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1748{
1749 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_oslockrelease\n");
1750
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1751 return (1);
1752}
1753
1754/* I have no idea what this is for */
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1755static PNV_VOID
1756nv_osreturnbufvirt(PNV_VOID ctx, PNV_VOID readdata)
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1757{
1758 /* Not implemented */
1759 DEBUGOUT(NV_DEBUG_LOCK, "nv: nv_osreturnbufvirt\n");
1760 panic("nv: nv_osreturnbufvirtual not implemented\n");
1761
1762 return (NULL);
1763}
1764
1765
1766/* --- End on NVOSAPI interface --- */