Do a major clean-up of the BUSDMA architecture. A large number of
[dragonfly.git] / sys / dev / netif / sr / if_sr.c
CommitLineData
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1/*
2 * Copyright (c) 1996 - 2001 John Hay.
3 * Copyright (c) 1996 SDL Communications, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
1f7ab7c9 31 * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.19 2006/10/25 20:55:59 dillon Exp $
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32 */
33
34/*
35 * Programming assumptions and other issues.
36 *
37 * Only a 16K window will be used.
38 *
39 * The descriptors of a DMA channel will fit in a 16K memory window.
40 *
41 * The buffers of a transmit DMA channel will fit in a 16K memory window.
42 *
43 * When interface is going up, handshaking is set and it is only cleared
44 * when the interface is down'ed.
45 *
46 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
47 * internal/external clock, etc.....
48 *
49 */
50
51#include "opt_netgraph.h"
52#ifdef NETGRAPH
1f2de5d4 53#include "if_sr.h"
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54#endif /* NETGRAPH */
55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/kernel.h>
59#include <sys/malloc.h>
60#include <sys/mbuf.h>
61#include <sys/sockio.h>
62#include <sys/socket.h>
7ff3b4d2 63#include <sys/thread2.h>
984263bc 64#include <sys/bus.h>
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65#include <sys/rman.h>
66
67#include <net/if.h>
68#ifdef NETGRAPH
69#include <sys/syslog.h>
70#else /* NETGRAPH */
53b3c2d0 71#include <net/sppp/if_sppp.h>
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72
73#include <net/bpf.h>
74#endif /* NETGRAPH */
75
76#include <machine/md_var.h>
77
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78#include "../ic_layer/hd64570.h"
79#include "if_srregs.h"
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80
81#ifdef NETGRAPH
82#include <netgraph/ng_message.h>
83#include <netgraph/netgraph.h>
84#endif /* NETGRAPH */
85/* #define USE_MODEMCK */
86
87#ifndef BUGGY
88#define BUGGY 0
89#endif
90
91#ifndef NETGRAPH
92#define PPP_HEADER_LEN 4
93#endif /* NETGRAPH */
94
95static int next_sc_unit = 0;
96#ifndef NETGRAPH
97#ifdef USE_MODEMCK
98static int sr_watcher = 0;
99#endif
100#endif /* NETGRAPH */
101
102/*
103 * Define the software interface for the card... There is one for
104 * every channel (port).
105 */
106struct sr_softc {
107#ifndef NETGRAPH
108 struct sppp ifsppp; /* PPP service w/in system */
109#endif /* NETGRAPH */
110 struct sr_hardc *hc; /* card-level information */
111
112 int unit; /* With regard to all sr devices */
113 int subunit; /* With regard to this card */
114
115 struct buf_block {
116 u_int txdesc; /* DPRAM offset */
117 u_int txstart;/* DPRAM offset */
118 u_int txend; /* DPRAM offset */
119 u_int txtail; /* # of 1st free gran */
120 u_int txmax; /* # of free grans */
121 u_int txeda; /* err descr addr */
122 } block[SR_TX_BLOCKS];
123
124 char xmit_busy; /* Transmitter is busy */
125 char txb_inuse; /* # of tx grans in use */
126 u_int txb_new; /* ndx to new buffer */
127 u_int txb_next_tx; /* ndx to next gran rdy tx */
128
129 u_int rxdesc; /* DPRAM offset */
130 u_int rxstart; /* DPRAM offset */
131 u_int rxend; /* DPRAM offset */
132 u_int rxhind; /* ndx to the hd of rx bufrs */
133 u_int rxmax; /* # of avail grans */
134
135 u_int clk_cfg; /* Clock configuration */
136
137 int scachan; /* channel # on card */
138#ifdef NETGRAPH
139 int running; /* something is attached so we are running */
140 int dcd; /* do we have dcd? */
141 /* ---netgraph bits --- */
142 char nodename[NG_NODELEN + 1]; /* store our node name */
143 int datahooks; /* number of data hooks attached */
144 node_p node; /* netgraph node */
145 hook_p hook; /* data hook */
146 hook_p debug_hook;
147 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
148 struct ifqueue xmitq; /* transmit queue */
149 int flags; /* state */
150#define SCF_RUNNING 0x01 /* board is active */
151#define SCF_OACTIVE 0x02 /* output is active */
152 int out_dog; /* watchdog cycles output count-down */
ce9980ee 153 struct callout sr_timer; /* timeout(9) handle */
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154 u_long inbytes, outbytes; /* stats */
155 u_long lastinbytes, lastoutbytes; /* a second ago */
156 u_long inrate, outrate; /* highest rate seen */
157 u_long inlast; /* last input N secs ago */
158 u_long out_deficit; /* output since last input */
159 u_long oerrors, ierrors[6];
160 u_long opackets, ipackets;
161#endif /* NETGRAPH */
162};
163
164#ifdef NETGRAPH
165#define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
166#define QUITE_A_WHILE 300 /* 5 MINUTES */
167#define LOTS_OF_PACKETS 100
168#endif /* NETGRAPH */
169
170/*
171 * Baud Rate table for Sync Mode.
172 * Each entry consists of 3 elements:
173 * Baud Rate (x100) , TMC, BR
174 *
175 * Baud Rate = FCLK / TMC / 2^BR
176 * Baud table for Crystal freq. of 9.8304 Mhz
177 */
178#ifdef N2_TEST_SPEED
179struct rate_line {
180 int target; /* target rate/100 */
181 int tmc_reg; /* TMC register value */
182 int br_reg; /* BR (BaudRateClk) selector */
183} n2_rates[] = {
184 /* Baudx100 TMC BR */
185 { 3, 128, 8 },
186 { 6, 128, 7 },
187 { 12, 128, 6 },
188 { 24, 128, 5 },
189 { 48, 128, 4 },
190 { 96, 128, 3 },
191 { 192, 128, 2 },
192 { 384, 128, 1 },
193 { 560, 88, 1 },
194 { 640, 77, 1 },
195 { 1280, 38, 1 },
196 { 2560, 19, 1 },
197 { 5120, 10, 1 },
198 { 10000, 5, 1 },
199 { 15000, 3, 1 },
200 { 25000, 2, 1 },
201 { 50000, 1, 1 },
202 { 0, 0, 0 }
203};
204
205int sr_test_speed[] = {
206 N2_TEST_SPEED,
207 N2_TEST_SPEED
208};
209
210int etc0vals[] = {
211 SR_MCR_ETC0, /* ISA channel 0 */
212 SR_MCR_ETC1, /* ISA channel 1 */
213 SR_FECR_ETC0, /* PCI channel 0 */
214 SR_FECR_ETC1 /* PCI channel 1 */
215};
216#endif
217
218devclass_t sr_devclass;
219#ifndef NETGRAPH
32832096 220DECLARE_DUMMY_MODULE(if_sr);
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221MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
222#else
223MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
224#endif
225
226static void srintr(void *arg);
227static void sr_xmit(struct sr_softc *sc);
228#ifndef NETGRAPH
229static void srstart(struct ifnet *ifp);
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230static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
231 struct ucred *);
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232static void srwatchdog(struct ifnet *ifp);
233#else
234static void srstart(struct sr_softc *sc);
235static void srwatchdog(struct sr_softc *sc);
236#endif /* NETGRAPH */
237static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
238static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
239static void sr_eat_packet(struct sr_softc *sc, int single);
240static void sr_get_packets(struct sr_softc *sc);
241
242static void sr_up(struct sr_softc *sc);
243static void sr_down(struct sr_softc *sc);
244static void src_init(struct sr_hardc *hc);
245static void sr_init_sca(struct sr_hardc *hc);
246static void sr_init_msci(struct sr_softc *sc);
247static void sr_init_rx_dmac(struct sr_softc *sc);
248static void sr_init_tx_dmac(struct sr_softc *sc);
249static void sr_dmac_intr(struct sr_hardc *hc, u_char isr);
250static void sr_msci_intr(struct sr_hardc *hc, u_char isr);
251static void sr_timer_intr(struct sr_hardc *hc, u_char isr);
252#ifndef NETGRAPH
253#ifdef USE_MODEMCK
254static void sr_modemck(void *x);
255#endif
256#else
257static void sr_modemck(struct sr_softc *x);
258#endif /* NETGRAPH */
259
260#ifdef NETGRAPH
261static void ngsr_watchdog_frame(void * arg);
262static void ngsr_init(void* ignored);
263
264static ng_constructor_t ngsr_constructor;
265static ng_rcvmsg_t ngsr_rcvmsg;
266static ng_shutdown_t ngsr_rmnode;
267static ng_newhook_t ngsr_newhook;
268/*static ng_findhook_t ngsr_findhook; */
269static ng_connect_t ngsr_connect;
270static ng_rcvdata_t ngsr_rcvdata;
271static ng_disconnect_t ngsr_disconnect;
272
273static struct ng_type typestruct = {
274 NG_VERSION,
275 NG_SR_NODE_TYPE,
276 NULL,
277 ngsr_constructor,
278 ngsr_rcvmsg,
279 ngsr_rmnode,
280 ngsr_newhook,
281 NULL,
282 ngsr_connect,
283 ngsr_rcvdata,
284 ngsr_rcvdata,
285 ngsr_disconnect,
286 NULL
287};
288
289static int ngsr_done_init = 0;
290#endif /* NETGRAPH */
291
292/*
293 * Register the ports on the adapter.
294 * Fill in the info for each port.
295#ifndef NETGRAPH
296 * Attach each port to sppp and bpf.
297#endif
298 */
299int
300sr_attach(device_t device)
301{
302 int intf_sw, pndx;
303 u_int32_t flags;
304 u_int fecr, *fecrp;
305 struct sr_hardc *hc;
306 struct sr_softc *sc;
307#ifndef NETGRAPH
308 struct ifnet *ifp;
309#endif /* NETGRAPH */
310 int unit; /* index: channel w/in card */
311
312 hc = (struct sr_hardc *)device_get_softc(device);
313 MALLOC(sc, struct sr_softc *,
314 hc->numports * sizeof(struct sr_softc),
315 M_DEVBUF, M_WAITOK | M_ZERO);
316 if (sc == NULL)
317 goto errexit;
318 hc->sc = sc;
319
320 /*
321 * Get the TX clock direction and configuration. The default is a
322 * single external clock which is used by RX and TX.
323 */
324 switch(hc->cardtype) {
325 case SR_CRD_N2:
326 flags = device_get_flags(device);
327#ifdef N2_TEST_SPEED
328 if (sr_test_speed[0] > 0)
329 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
330 else
331#endif
332 if (flags & SR_FLAGS_0_CLK_MSK)
333 hc->sc[0].clk_cfg =
334 (flags & SR_FLAGS_0_CLK_MSK)
335 >> SR_FLAGS_CLK_SHFT;
336
337 if (hc->numports == 2)
338#ifdef N2_TEST_SPEED
339 if (sr_test_speed[1] > 0)
340 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
341 else
342#endif
343 if (flags & SR_FLAGS_1_CLK_MSK)
344 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
345 >> (SR_FLAGS_CLK_SHFT +
346 SR_FLAGS_CLK_CHAN_SHFT);
347 break;
348 case SR_CRD_N2PCI:
349 fecrp = (u_int *)(hc->sca_base + SR_FECR);
350 fecr = *fecrp;
351 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
352 switch (pndx) {
353 case 1:
354 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
355 break;
356 case 0:
357 default:
358 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
359 }
360
361#ifdef N2_TEST_SPEED
362 if (sr_test_speed[pndx] > 0)
363 sc->clk_cfg = SR_FLAGS_INT_CLK;
364 else
365#endif
366 switch (intf_sw) {
367 default:
368 case SR_FE_ID_RS232:
369 case SR_FE_ID_HSSI:
370 case SR_FE_ID_RS422:
371 case SR_FE_ID_TEST:
372 break;
373
374 case SR_FE_ID_V35:
375 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
376 break;
377
378 case SR_FE_ID_X21:
379 sc->clk_cfg = SR_FLAGS_EXT_CLK;
380 break;
381 }
382 }
383 sc = hc->sc;
384 break;
385 }
386
387 /*
388 * Report Card configuration information before we start configuring
389 * each channel on the card...
390 */
391 printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
392 hc->cunit, hc->memsize / 1024, hc->mempages,
393 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
394
395 src_init(hc);
396 sr_init_sca(hc);
397
398 if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
ee61f228 399 0, srintr, hc,
e9cb6d99 400 &hc->intr_cookie, NULL) != 0)
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401 goto errexit;
402
403 /*
404 * Now configure each port on the card.
405 */
406 for (unit = 0; unit < hc->numports; sc++, unit++) {
407 sc->hc = hc;
408 sc->subunit = unit;
409 sc->unit = next_sc_unit;
410 next_sc_unit++;
411 sc->scachan = unit % NCHAN;
412
413 sr_init_rx_dmac(sc);
414 sr_init_tx_dmac(sc);
415 sr_init_msci(sc);
416
417 printf("sr%d: Adapter %d, port %d.\n",
418 sc->unit, hc->cunit, sc->subunit);
419
420#ifndef NETGRAPH
421 ifp = &sc->ifsppp.pp_if;
422 ifp->if_softc = sc;
cdb7d804 423 if_initname(ifp, "sr", sc->unit);
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424 ifp->if_mtu = PP_MTU;
425 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
426 ifp->if_ioctl = srioctl;
427 ifp->if_start = srstart;
428 ifp->if_watchdog = srwatchdog;
429
430 sc->ifsppp.pp_flags = PP_KEEPALIVE;
431 sppp_attach((struct ifnet *)&sc->ifsppp);
78195a76 432 if_attach(ifp, NULL);
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433
434 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
435#else /* NETGRAPH */
436 /*
437 * we have found a node, make sure our 'type' is availabe.
438 */
439 if (ngsr_done_init == 0) ngsr_init(NULL);
440 if (ng_make_node_common(&typestruct, &sc->node) != 0)
441 goto errexit;
442 sc->node->private = sc;
ce9980ee 443 callout_init(&sc->sr_timer);
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444 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
445 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
446 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
447 if (ng_name_node(sc->node, sc->nodename)) {
448 ng_rmnode(sc->node);
449 ng_unref(sc->node);
450 return (0);
451 }
452 sc->running = 0;
453#endif /* NETGRAPH */
454 }
455
456 if (hc->mempages)
457 SRC_SET_OFF(hc->iobase);
458
459 return (0);
460
461errexit:
462 sr_deallocate_resources(device);
463 return (ENXIO);
464}
465
466int
467sr_detach(device_t device)
468{
469 device_t parent = device_get_parent(device);
470 struct sr_hardc *hc = device_get_softc(device);
471
472 if (hc->intr_cookie != NULL) {
473 if (BUS_TEARDOWN_INTR(parent, device,
474 hc->res_irq, hc->intr_cookie) != 0) {
475 printf("intr teardown failed.. continuing\n");
476 }
477 hc->intr_cookie = NULL;
478 }
479
480 /* XXX Stop the DMA. */
481
482 /*
483 * deallocate any system resources we may have
484 * allocated on behalf of this driver.
485 */
486 FREE(hc->sc, M_DEVBUF);
487 hc->sc = NULL;
488 hc->mem_start = NULL;
489 return (sr_deallocate_resources(device));
490}
491
492int
493sr_allocate_ioport(device_t device, int rid, u_long size)
494{
495 struct sr_hardc *hc = device_get_softc(device);
496
497 hc->rid_ioport = rid;
498 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
499 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
500 if (hc->res_ioport == NULL) {
501 goto errexit;
502 }
503 return (0);
504
505errexit:
506 sr_deallocate_resources(device);
507 return (ENXIO);
508}
509
510int
511sr_allocate_irq(device_t device, int rid, u_long size)
512{
513 struct sr_hardc *hc = device_get_softc(device);
514
515 hc->rid_irq = rid;
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516 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
517 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
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518 if (hc->res_irq == NULL) {
519 goto errexit;
520 }
521 return (0);
522
523errexit:
524 sr_deallocate_resources(device);
525 return (ENXIO);
526}
527
528int
529sr_allocate_memory(device_t device, int rid, u_long size)
530{
531 struct sr_hardc *hc = device_get_softc(device);
532
533 hc->rid_memory = rid;
534 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
535 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
536 if (hc->res_memory == NULL) {
537 goto errexit;
538 }
539 return (0);
540
541errexit:
542 sr_deallocate_resources(device);
543 return (ENXIO);
544}
545
546int
547sr_allocate_plx_memory(device_t device, int rid, u_long size)
548{
549 struct sr_hardc *hc = device_get_softc(device);
550
551 hc->rid_plx_memory = rid;
552 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
553 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
554 if (hc->res_plx_memory == NULL) {
555 goto errexit;
556 }
557 return (0);
558
559errexit:
560 sr_deallocate_resources(device);
561 return (ENXIO);
562}
563
564int
565sr_deallocate_resources(device_t device)
566{
567 struct sr_hardc *hc = device_get_softc(device);
568
569 if (hc->res_irq != 0) {
570 bus_deactivate_resource(device, SYS_RES_IRQ,
571 hc->rid_irq, hc->res_irq);
572 bus_release_resource(device, SYS_RES_IRQ,
573 hc->rid_irq, hc->res_irq);
574 hc->res_irq = 0;
575 }
576 if (hc->res_ioport != 0) {
577 bus_deactivate_resource(device, SYS_RES_IOPORT,
578 hc->rid_ioport, hc->res_ioport);
579 bus_release_resource(device, SYS_RES_IOPORT,
580 hc->rid_ioport, hc->res_ioport);
581 hc->res_ioport = 0;
582 }
583 if (hc->res_memory != 0) {
584 bus_deactivate_resource(device, SYS_RES_MEMORY,
585 hc->rid_memory, hc->res_memory);
586 bus_release_resource(device, SYS_RES_MEMORY,
587 hc->rid_memory, hc->res_memory);
588 hc->res_memory = 0;
589 }
590 if (hc->res_plx_memory != 0) {
591 bus_deactivate_resource(device, SYS_RES_MEMORY,
592 hc->rid_plx_memory, hc->res_plx_memory);
593 bus_release_resource(device, SYS_RES_MEMORY,
594 hc->rid_plx_memory, hc->res_plx_memory);
595 hc->res_plx_memory = 0;
596 }
597 return (0);
598}
599
600/*
601 * N2 Interrupt Service Routine
602 *
603 * First figure out which SCA gave the interrupt.
604 * Process it.
605 * See if there is other interrupts pending.
606 * Repeat until there no interrupts remain.
607 */
608static void
609srintr(void *arg)
610{
611 struct sr_hardc *hc = (struct sr_hardc *)arg;
612 sca_regs *sca = hc->sca; /* MSCI register tree */
613 u_char isr0, isr1, isr2; /* interrupt statii captured */
614
615#if BUGGY > 1
616 printf("sr: srintr_hc(hc=%08x)\n", hc);
617#endif
618
619 /*
620 * Since multiple interfaces may share this interrupt, we must loop
621 * until no interrupts are still pending service.
622 */
623 while (1) {
624 /*
625 * Read all three interrupt status registers from the N2
626 * card...
627 */
628 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
629 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
630 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
631
632 /*
633 * If all three registers returned 0, we've finished
634 * processing interrupts from this device, so we can quit
635 * this loop...
636 */
637 if ((isr0 | isr1 | isr2) == 0)
638 break;
639
640#if BUGGY > 2
641 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
642#ifndef NETGRAPH
643 unit, isr0, isr1, isr2);
644#else
645 hc->cunit, isr0, isr1, isr2);
646#endif /* NETGRAPH */
647#endif
648
649 /*
650 * Now we can dispatch the interrupts. Since we don't expect
651 * either MSCI or timer interrupts, we'll test for DMA
652 * interrupts first...
653 */
654 if (isr1) /* DMA-initiated interrupt */
655 sr_dmac_intr(hc, isr1);
656
657 if (isr0) /* serial part IRQ? */
658 sr_msci_intr(hc, isr0);
659
660 if (isr2) /* timer-initiated interrupt */
661 sr_timer_intr(hc, isr2);
662 }
663}
664
665/*
666 * This will only start the transmitter. It is assumed that the data
667 * is already there.
668 * It is normally called from srstart() or sr_dmac_intr().
669 */
670static void
671sr_xmit(struct sr_softc *sc)
672{
673 u_short cda_value; /* starting descriptor */
674 u_short eda_value; /* ending descriptor */
675 struct sr_hardc *hc;
676#ifndef NETGRAPH
677 struct ifnet *ifp; /* O/S Network Services */
678#endif /* NETGRAPH */
679 dmac_channel *dmac; /* DMA channel registers */
680
681#if BUGGY > 0
682 printf("sr: sr_xmit( sc=%08x)\n", sc);
683#endif
684
685 hc = sc->hc;
686#ifndef NETGRAPH
687 ifp = &sc->ifsppp.pp_if;
688#endif /* NETGRAPH */
689 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
690
691 /*
692 * Get the starting and ending addresses of the chain to be
693 * transmitted and pass these on to the DMA engine on-chip.
694 */
695 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
696 cda_value &= 0x00ffff;
697 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
698 eda_value &= 0x00ffff;
699
700 SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
701 SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
702
703 /*
704 * Now we'll let the DMA status register know about this change
705 */
706 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
707
708 sc->xmit_busy = 1; /* mark transmitter busy */
709
710#if BUGGY > 2
711 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n",
712 sc->unit, cda_value, eda_value,
713 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
714#endif
715
716 sc->txb_next_tx++; /* update next transmit seq# */
717
718 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */
719 sc->txb_next_tx = 0;
720
721#ifndef NETGRAPH
722 /*
723 * Finally, we'll set a timout (which will start srwatchdog())
724 * within the O/S network services layer...
725 */
726 ifp->if_timer = 2; /* Value in seconds. */
727#else
728 /*
729 * Don't time out for a while.
730 */
731 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
732#endif /* NETGRAPH */
733}
734
735/*
736 * This function will be called from the upper level when a user add a
737 * packet to be send, and from the interrupt handler after a finished
738 * transmit.
739 *
984263bc
MD
740 * This function only place the data in the oncard buffers. It does not
741 * start the transmition. sr_xmit() does that.
742 *
743 * Transmitter idle state is indicated by the IFF_OACTIVE flag.
744 * The function that clears that should ensure that the transmitter
745 * and its DMA is in a "good" idle state.
746 */
747#ifndef NETGRAPH
748static void
749srstart(struct ifnet *ifp)
750{
751 struct sr_softc *sc; /* channel control structure */
752#else
753static void
754srstart(struct sr_softc *sc)
755{
756#endif /* NETGRAPH */
757 struct sr_hardc *hc; /* card control/config block */
758 int len; /* total length of a packet */
759 int pkts; /* packets placed in DPRAM */
760 int tlen; /* working length of pkt */
761 u_int i;
762 struct mbuf *mtx; /* message buffer from O/S */
763 u_char *txdata; /* buffer address in DPRAM */
764 sca_descriptor *txdesc; /* working descriptor pointr */
765 struct buf_block *blkp;
766
767#ifndef NETGRAPH
768#if BUGGY > 0
769 printf("sr: srstart( ifp=%08x)\n", ifp);
770#endif
771 sc = ifp->if_softc;
772 if ((ifp->if_flags & IFF_RUNNING) == 0)
773 return;
774#endif /* NETGRAPH */
775 hc = sc->hc;
776 /*
777 * It is OK to set the memory window outside the loop because all tx
778 * buffers and descriptors are assumed to be in the same 16K window.
779 */
780 if (hc->mempages) {
781 SRC_SET_ON(hc->iobase);
782 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
783 }
784
785 /*
786 * Loop to place packets into DPRAM.
787 *
788 * We stay in this loop until there is nothing in
789 * the TX queue left or the tx buffers are full.
790 */
791top_srstart:
792
793 /*
794 * See if we have space for more packets.
795 */
796 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */
797#ifndef NETGRAPH
798 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
799#else
800 /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
801#endif /* NETGRAPH */
802
803 if (hc->mempages)
804 SRC_SET_OFF(hc->iobase);
805
806#if BUGGY > 9
807 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
808 sc->unit, sc->txb_inuse);
809#endif
810 return;
811 }
812 /*
813 * OK, the card can take more traffic. Let's see if there's any
814 * pending from the system...
815 *
816 * NOTE:
817 * The architecture of the networking interface doesn't
818 * actually call us like 'write()', providing an address. We get
819 * started, a lot like a disk strategy routine, and we actually call
820 * back out to the system to get traffic to send...
821 *
822 * NOTE:
823 * If we were gonna run through another layer, we would use a
824 * dispatch table to select the service we're getting a packet
825 * from...
826 */
827#ifndef NETGRAPH
828 mtx = sppp_dequeue(ifp);
829#else /* NETGRAPH */
830 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
831 if (mtx == NULL) {
832 IF_DEQUEUE(&sc->xmitq, mtx);
833 }
834#endif /* NETGRAPH */
835 if (!mtx) {
836 if (hc->mempages)
837 SRC_SET_OFF(hc->iobase);
838 return;
839 }
840 /*
841 * OK, we got a packet from the network services of the O/S. Now we
842 * can move it into the DPRAM (under control of the descriptors) and
843 * fire it off...
844 */
845 pkts = 0;
846 i = 0; /* counts # of granules used */
847
848 blkp = &sc->block[sc->txb_new]; /* address of free granule */
849 txdesc = (sca_descriptor *)
850 (hc->mem_start + (blkp->txdesc & hc->winmsk));
851
852 txdata = (u_char *)(hc->mem_start
853 + (blkp->txstart & hc->winmsk));
854
855 /*
856 * Now we'll try to install as many packets as possible into the
857 * card's DP RAM buffers.
858 */
859 for (;;) { /* perform actual copy of packet */
860 len = mtx->m_pkthdr.len; /* length of message */
861
862#if BUGGY > 1
863 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
864 sc->unit, mtx, len);
865#endif
866
867#ifndef NETGRAPH
7600679e 868 BPF_MTAP(ifp, mtx);
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869#else /* NETGRAPH */
870 sc->outbytes += len;
871#endif /* NETGRAPH */
872
873 /*
874 * We can perform a straight copy because the tranmit
875 * buffers won't wrap.
876 */
877 m_copydata(mtx, 0, len, txdata);
878
879 /*
880 * Now we know how big the message is gonna be. We must now
881 * construct the descriptors to drive this message out...
882 */
883 tlen = len;
884 while (tlen > SR_BUF_SIZ) { /* loop for full granules */
885 txdesc->stat = 0; /* reset bits */
886 txdesc->len = SR_BUF_SIZ; /* size of granule */
887 tlen -= SR_BUF_SIZ;
888
889 txdesc++; /* move to next dscr */
890 txdata += SR_BUF_SIZ; /* adjust data addr */
891 i++;
892 }
893
894 /*
895 * This section handles the setting of the final piece of a
896 * message.
897 */
898 txdesc->stat = SCA_DESC_EOM;
899 txdesc->len = tlen;
900 pkts++;
901
902 /*
903 * prepare for subsequent packets (if any)
904 */
905 txdesc++;
906 txdata += SR_BUF_SIZ; /* next mem granule */
907 i++; /* count of granules */
908
909 /*
910 * OK, we've now placed the message into the DPRAM where it
911 * can be transmitted. We'll now release the message memory
912 * and update the statistics...
913 */
914 m_freem(mtx);
915#ifndef NETGRAPH
916 ++sc->ifsppp.pp_if.if_opackets;
917#else /* NETGRAPH */
918 sc->opackets++;
919#endif /* NETGRAPH */
920
921 /*
922 * Check if we have space for another packet. XXX This is
923 * hardcoded. A packet can't be larger than 3 buffers (3 x
924 * 512).
925 */
926 if ((i + 3) >= blkp->txmax) { /* enough remains? */
927#if BUGGY > 9
928 printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
929 sc->unit, i, pkts);
930#endif
931 break;
932 }
933 /*
934 * We'll pull the next message to be sent (if any)
935 */
936#ifndef NETGRAPH
937 mtx = sppp_dequeue(ifp);
938#else /* NETGRAPH */
939 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
940 if (mtx == NULL) {
941 IF_DEQUEUE(&sc->xmitq, mtx);
942 }
943#endif /* NETGRAPH */
944 if (!mtx) { /* no message? We're done! */
945#if BUGGY > 9
946 printf("sr%d.srstart: pending=0, pkts=%d\n",
947 sc->unit, pkts);
948#endif
949 break;
950 }
951 }
952
953 blkp->txtail = i; /* record next free granule */
954
955 /*
956 * Mark the last descriptor, so that the SCA know where to stop.
957 */
958 txdesc--; /* back up to last descriptor in list */
959 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */
960
961 /*
962 * Now we'll reset the transmit granule's descriptor address so we
963 * can record this in the structure and fire it off w/ the DMA
964 * processor of the serial chip...
965 */
966 txdesc = (sca_descriptor *)blkp->txdesc;
967 blkp->txeda = (u_short)((u_int)&txdesc[i]);
968
969 sc->txb_inuse++; /* update inuse status */
970 sc->txb_new++; /* new traffic wuz added */
971
972 if (sc->txb_new == SR_TX_BLOCKS)
973 sc->txb_new = 0;
974
975 /*
976 * If the tranmitter wasn't marked as "busy" we will force it to be
977 * started...
978 */
979 if (sc->xmit_busy == 0) {
980 sr_xmit(sc);
981#if BUGGY > 9
982 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
983#endif
984 }
985 goto top_srstart;
986}
987
988#ifndef NETGRAPH
989/*
990 * Handle ioctl's at the device level, though we *will* call up
991 * a layer...
992 */
993#if BUGGY > 2
994static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
995#endif
996
997static int
bd4539cc 998srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
984263bc 999{
7ff3b4d2 1000 int error, was_up, should_be_up;
984263bc
MD
1001 struct sr_softc *sc = ifp->if_softc;
1002
1003#if BUGGY > 0
cdb7d804
MD
1004 printf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1005 ifp->if_xname, ifp, cmd, data);
984263bc
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1006#endif
1007
1008 was_up = ifp->if_flags & IFF_RUNNING;
1009
1010 error = sppp_ioctl(ifp, cmd, data);
1011
1012#if BUGGY > 1
cdb7d804
MD
1013 printf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1014 ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
984263bc
MD
1015#endif
1016
1017 if (error)
1018 return error;
1019
1020 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1021#if BUGGY > 2
1022 if (bug_splats[sc->unit]++ < 2) {
1023 printf("sr(%d).if_addrlist = %08x\n",
1024 sc->unit, ifp->if_addrlist);
1025 printf("sr(%d).if_bpf = %08x\n",
1026 sc->unit, ifp->if_bpf);
1027 printf("sr(%d).if_init = %08x\n",
1028 sc->unit, ifp->if_init);
1029 printf("sr(%d).if_output = %08x\n",
1030 sc->unit, ifp->if_output);
1031 printf("sr(%d).if_start = %08x\n",
1032 sc->unit, ifp->if_start);
1033 printf("sr(%d).if_done = %08x\n",
1034 sc->unit, ifp->if_done);
1035 printf("sr(%d).if_ioctl = %08x\n",
1036 sc->unit, ifp->if_ioctl);
1037 printf("sr(%d).if_reset = %08x\n",
1038 sc->unit, ifp->if_reset);
1039 printf("sr(%d).if_watchdog = %08x\n",
1040 sc->unit, ifp->if_watchdog);
1041 }
1042#endif
1043 return 0;
1044 }
1045
7ff3b4d2
JS
1046 crit_enter();
1047
984263bc
MD
1048 should_be_up = ifp->if_flags & IFF_RUNNING;
1049
1050 if (!was_up && should_be_up) {
1051 /*
1052 * Interface should be up -- start it.
1053 */
1054 sr_up(sc);
1055 srstart(ifp);
1056
1057 /*
1058 * XXX Clear the IFF_UP flag so that the link will only go
1059 * up after sppp lcp and ipcp negotiation.
1060 */
1061 /* ifp->if_flags &= ~IFF_UP; */
1062 } else if (was_up && !should_be_up) {
1063 /*
1064 * Interface should be down -- stop it.
1065 */
1066 sr_down(sc);
1067 sppp_flush(ifp);
1068 }
7ff3b4d2
JS
1069
1070 crit_exit();
1071
984263bc
MD
1072 return 0;
1073}
1074#endif /* NETGRAPH */
1075
1076/*
1077 * This is to catch lost tx interrupts.
1078 */
1079static void
1080#ifndef NETGRAPH
1081srwatchdog(struct ifnet *ifp)
1082#else
1083srwatchdog(struct sr_softc *sc)
1084#endif /* NETGRAPH */
1085{
1086 int got_st0, got_st1, got_st3, got_dsr;
1087#ifndef NETGRAPH
1088 struct sr_softc *sc = ifp->if_softc;
1089#endif /* NETGRAPH */
1090 struct sr_hardc *hc = sc->hc;
1091 msci_channel *msci = &hc->sca->msci[sc->scachan];
1092 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1093
1094#if BUGGY > 0
1095#ifndef NETGRAPH
1096 printf("srwatchdog(unit=%d)\n", unit);
1097#else
1098 printf("srwatchdog(unit=%d)\n", sc->unit);
1099#endif /* NETGRAPH */
1100#endif
1101
1102#ifndef NETGRAPH
1103 if (!(ifp->if_flags & IFF_RUNNING))
1104 return;
1105
1106 ifp->if_oerrors++; /* update output error count */
1107#else /* NETGRAPH */
1108 sc->oerrors++; /* update output error count */
1109#endif /* NETGRAPH */
1110
1111 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1112 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1113 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1114 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1115
1116#ifndef NETGRAPH
1117#if 0
1118 if (ifp->if_flags & IFF_DEBUG)
1119#endif
1120 printf("sr%d: transmit failed, "
1121#else /* NETGRAPH */
1122 printf("sr%d: transmit failed, "
1123#endif /* NETGRAPH */
1124 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1125 sc->unit,
1126 got_st0, got_st1, got_st3, got_dsr);
1127
1128 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1129 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1130 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1131 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1132 }
1133 sc->xmit_busy = 0;
1134#ifndef NETGRAPH
1135 ifp->if_flags &= ~IFF_OACTIVE;
1136#else
1137 /*ifp->if_flags &= ~IFF_OACTIVE; */
1138#endif /* NETGRAPH */
1139
1140 if (sc->txb_inuse && --sc->txb_inuse)
1141 sr_xmit(sc);
1142
1143#ifndef NETGRAPH
1144 srstart(ifp); /* restart transmitter */
1145#else
1146 srstart(sc); /* restart transmitter */
1147#endif /* NETGRAPH */
1148}
1149
1150static void
1151sr_up(struct sr_softc *sc)
1152{
1153 u_int *fecrp;
1154 struct sr_hardc *hc = sc->hc;
1155 sca_regs *sca = hc->sca;
1156 msci_channel *msci = &sca->msci[sc->scachan];
1157
1158#if BUGGY > 0
1159 printf("sr_up(sc=%08x)\n", sc);
1160#endif
1161
1162 /*
1163 * Enable transmitter and receiver. Raise DTR and RTS. Enable
1164 * interrupts.
1165 *
1166 * XXX What about using AUTO mode in msci->md0 ???
1167 */
1168 SRC_PUT8(hc->sca_base, msci->ctl,
1169 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1170
1171 if (sc->scachan == 0)
1172 switch (hc->cardtype) {
1173 case SR_CRD_N2:
1174 outb(hc->iobase + SR_MCR,
1175 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1176 break;
1177 case SR_CRD_N2PCI:
1178 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1179 *fecrp &= ~SR_FECR_DTR0;
1180 break;
1181 }
1182 else
1183 switch (hc->cardtype) {
1184 case SR_CRD_N2:
1185 outb(hc->iobase + SR_MCR,
1186 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1187 break;
1188 case SR_CRD_N2PCI:
1189 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1190 *fecrp &= ~SR_FECR_DTR1;
1191 break;
1192 }
1193
1194 if (sc->scachan == 0) {
1195 SRC_PUT8(hc->sca_base, sca->ier0,
1196 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1197 SRC_PUT8(hc->sca_base, sca->ier1,
1198 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1199 } else {
1200 SRC_PUT8(hc->sca_base, sca->ier0,
1201 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1202 SRC_PUT8(hc->sca_base, sca->ier1,
1203 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1204 }
1205
1206 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1207 inb(hc->iobase); /* XXX slow it down a bit. */
1208 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1209
1210#ifndef NETGRAPH
1211#ifdef USE_MODEMCK
1212 if (sr_watcher == 0)
1213 sr_modemck(NULL);
1214#endif
1215#else /* NETGRAPH */
ce9980ee 1216 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
984263bc
MD
1217 sc->running = 1;
1218#endif /* NETGRAPH */
1219}
1220
1221static void
1222sr_down(struct sr_softc *sc)
1223{
1224 u_int *fecrp;
1225 struct sr_hardc *hc = sc->hc;
1226 sca_regs *sca = hc->sca;
1227 msci_channel *msci = &sca->msci[sc->scachan];
1228
1229#if BUGGY > 0
1230 printf("sr_down(sc=%08x)\n", sc);
1231#endif
1232#ifdef NETGRAPH
ce9980ee 1233 callout_stop(&sc->sr_timer);
984263bc
MD
1234 sc->running = 0;
1235#endif /* NETGRAPH */
1236
1237 /*
1238 * Disable transmitter and receiver. Lower DTR and RTS. Disable
1239 * interrupts.
1240 */
1241 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1242 inb(hc->iobase); /* XXX slow it down a bit. */
1243 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1244
1245 SRC_PUT8(hc->sca_base, msci->ctl,
1246 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1247
1248 if (sc->scachan == 0)
1249 switch (hc->cardtype) {
1250 case SR_CRD_N2:
1251 outb(hc->iobase + SR_MCR,
1252 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1253 break;
1254 case SR_CRD_N2PCI:
1255 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1256 *fecrp |= SR_FECR_DTR0;
1257 break;
1258 }
1259 else
1260 switch (hc->cardtype) {
1261 case SR_CRD_N2:
1262 outb(hc->iobase + SR_MCR,
1263 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1264 break;
1265 case SR_CRD_N2PCI:
1266 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1267 *fecrp |= SR_FECR_DTR1;
1268 break;
1269 }
1270
1271 if (sc->scachan == 0) {
1272 SRC_PUT8(hc->sca_base, sca->ier0,
1273 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1274 SRC_PUT8(hc->sca_base, sca->ier1,
1275 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1276 } else {
1277 SRC_PUT8(hc->sca_base, sca->ier0,
1278 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1279 SRC_PUT8(hc->sca_base, sca->ier1,
1280 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1281 }
1282}
1283
1284/*
1285 * Initialize the card, allocate memory for the sr_softc structures
1286 * and fill in the pointers.
1287 */
1288static void
1289src_init(struct sr_hardc *hc)
1290{
1291 struct sr_softc *sc = hc->sc;
1292 int x;
1293 u_int chanmem;
1294 u_int bufmem;
1295 u_int next;
1296 u_int descneeded;
1297
1298#if BUGGY > 0
1299 printf("src_init(hc=%08x)\n", hc);
1300#endif
1301
1302 chanmem = hc->memsize / hc->numports;
1303 next = 0;
1304
1305 for (x = 0; x < hc->numports; x++, sc++) {
1306 int blk;
1307
1308 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1309 sc->block[blk].txdesc = next;
1310 bufmem = (16 * 1024) / SR_TX_BLOCKS;
1311 descneeded = bufmem / SR_BUF_SIZ;
1312
1313 sc->block[blk].txstart = sc->block[blk].txdesc
1314 + ((((descneeded * sizeof(sca_descriptor))
1315 / SR_BUF_SIZ) + 1)
1316 * SR_BUF_SIZ);
1317
1318 sc->block[blk].txend = next + bufmem;
1319 sc->block[blk].txmax =
1320 (sc->block[blk].txend - sc->block[blk].txstart)
1321 / SR_BUF_SIZ;
1322 next += bufmem;
1323
1324#if BUGGY > 2
1325 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1326 sc->unit, blk,
1327 sc->block[blk].txdesc, sc->block[blk].txstart);
1328#endif
1329 }
1330
1331 sc->rxdesc = next;
1332 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1333 descneeded = bufmem / SR_BUF_SIZ;
1334 sc->rxstart = sc->rxdesc +
1335 ((((descneeded * sizeof(sca_descriptor)) /
1336 SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1337 sc->rxend = next + bufmem;
1338 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1339 next += bufmem;
1340 }
1341}
1342
1343/*
1344 * The things done here are channel independent.
1345 *
1346 * Configure the sca waitstates.
1347 * Configure the global interrupt registers.
1348 * Enable master dma enable.
1349 */
1350static void
1351sr_init_sca(struct sr_hardc *hc)
1352{
1353 sca_regs *sca = hc->sca;
1354
1355#if BUGGY > 0
1356 printf("sr_init_sca(hc=%08x)\n", hc);
1357#endif
1358
1359 /*
1360 * Do the wait registers. Set everything to 0 wait states.
1361 */
1362 SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1363 SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1364 SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1365 SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1366 SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1367
1368 /*
1369 * Configure the interrupt registers. Most are cleared until the
1370 * interface is configured.
1371 */
1372 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */
1373 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */
1374 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */
1375 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr
1376 * ack */
1377 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1378 SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1379
1380 /*
1381 * Configure the timers. XXX Later
1382 */
1383
1384 /*
1385 * Set the DMA channel priority to rotate between all four channels.
1386 *
1387 * Enable all dma channels.
1388 */
1389 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1390 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1391}
1392
1393/*
1394 * Configure the msci
1395 *
1396 * NOTE: The serial port configuration is hardcoded at the moment.
1397 */
1398static void
1399sr_init_msci(struct sr_softc *sc)
1400{
1401 int portndx; /* on-board port number */
1402 u_int mcr_v; /* contents of modem control */
1403 u_int *fecrp; /* pointer for PCI's MCR i/o */
1404 struct sr_hardc *hc = sc->hc;
1405 msci_channel *msci = &hc->sca->msci[sc->scachan];
1406#ifdef N2_TEST_SPEED
1407 int br_v; /* contents for BR divisor */
1408 int etcndx; /* index into ETC table */
1409 int fifo_v, gotspeed; /* final tabled speed found */
1410 int tmc_v; /* timer control register */
1411 int wanted; /* speed (bitrate) wanted... */
1412 struct rate_line *rtp;
1413#endif
1414
1415 portndx = sc->scachan;
1416
1417#if BUGGY > 0
1418 printf("sr: sr_init_msci( sc=%08x)\n", sc);
1419#endif
1420
1421 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1422 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1423 SCA_MD0_CRC_CCITT |
1424 SCA_MD0_CRC_ENABLE |
1425 SCA_MD0_MODE_HDLC);
1426 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1427 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1428
1429 /*
1430 * According to the manual I should give a reset after changing the
1431 * mode registers.
1432 */
1433 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1434 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1435 SCA_CTL_UDRNC |
1436 SCA_CTL_RTS);
1437
1438 /*
1439 * XXX Later we will have to support different clock settings.
1440 */
1441 switch (sc->clk_cfg) {
1442 default:
1443#if BUGGY > 0
1444 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1445 portndx, sc->clk_cfg);
1446#endif
1447 /* FALLTHROUGH */
1448 case SR_FLAGS_EXT_CLK:
1449 /*
1450 * For now all interfaces are programmed to use the RX clock
1451 * for the TX clock.
1452 */
1453
1454#if BUGGY > 0
1455 printf("sr%d: External Clock Selected.\n", portndx);
1456#endif
1457
1458 SRC_PUT8(hc->sca_base, msci->rxs,
1459 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1460 SRC_PUT8(hc->sca_base, msci->txs,
1461 SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1462 break;
1463
1464 case SR_FLAGS_EXT_SEP_CLK:
1465#if BUGGY > 0
1466 printf("sr%d: Split Clocking Selected.\n", portndx);
1467#endif
1468
1469 SRC_PUT8(hc->sca_base, msci->rxs,
1470 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1471 SRC_PUT8(hc->sca_base, msci->txs,
1472 SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1473 break;
1474
1475 case SR_FLAGS_INT_CLK:
1476#if BUGGY > 0
1477 printf("sr%d: Internal Clocking selected.\n", portndx);
1478#endif
1479
1480 /*
1481 * XXX I do need some code to set the baud rate here!
1482 */
1483#ifdef N2_TEST_SPEED
1484 switch (hc->cardtype) {
1485 case SR_CRD_N2PCI:
1486 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1487 mcr_v = *fecrp;
1488 etcndx = 2;
1489 break;
1490 case SR_CRD_N2:
1491 default:
1492 mcr_v = inb(hc->iobase + SR_MCR);
1493 etcndx = 0;
1494 }
1495
1496 fifo_v = 0x10; /* stolen from Linux version */
1497
1498 /*
1499 * search for appropriate speed in table, don't calc it:
1500 */
1501 wanted = sr_test_speed[portndx];
1502 rtp = &n2_rates[0]; /* point to first table item */
1503
1504 while ((rtp->target > 0) /* search table for speed */
1505 &&(rtp->target != wanted))
1506 rtp++;
1507
1508 /*
1509 * We've searched the table for a matching speed. If we've
1510 * found the correct rate line, we'll get the pre-calc'd
1511 * values for the TMC and baud rate divisor for subsequent
1512 * use...
1513 */
1514 if (rtp->target > 0) { /* use table-provided values */
1515 gotspeed = wanted;
1516 tmc_v = rtp->tmc_reg;
1517 br_v = rtp->br_reg;
1518 } else { /* otherwise assume 1MBit comm rate */
1519 gotspeed = 10000;
1520 tmc_v = 5;
1521 br_v = 1;
1522 }
1523
1524 /*
1525 * Now we mask in the enable clock output for the MCR:
1526 */
1527 mcr_v |= etc0vals[etcndx + portndx];
1528
1529 /*
1530 * Now we'll program the registers with these speed- related
1531 * contents...
1532 */
1533 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1534 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1535 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1536 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1537
1538 switch (hc->cardtype) {
1539 case SR_CRD_N2PCI:
1540 *fecrp = mcr_v;
1541 break;
1542 case SR_CRD_N2:
1543 default:
1544 outb(hc->iobase + SR_MCR, mcr_v);
1545 }
1546
1547#if BUGGY > 0
1548 if (wanted != gotspeed)
1549 printf("sr%d: Speed wanted=%d, found=%d\n",
1550 wanted, gotspeed);
1551
1552 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1553 portndx, gotspeed, tmc_v, br_v);
1554#endif
1555#else
1556 SRC_PUT8(hc->sca_base, msci->rxs,
1557 SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1558 SRC_PUT8(hc->sca_base, msci->txs,
1559 SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1560
1561 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1562
1563 if (portndx == 0)
1564 switch (hc->cardtype) {
1565 case SR_CRD_N2PCI:
1566 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1567 *fecrp |= SR_FECR_ETC0;
1568 break;
1569 case SR_CRD_N2:
1570 default:
1571 mcr_v = inb(hc->iobase + SR_MCR);
1572 mcr_v |= SR_MCR_ETC0;
1573 outb(hc->iobase + SR_MCR, mcr_v);
1574 }
1575 else
1576 switch (hc->cardtype) {
1577 case SR_CRD_N2:
1578 mcr_v = inb(hc->iobase + SR_MCR);
1579 mcr_v |= SR_MCR_ETC1;
1580 outb(hc->iobase + SR_MCR, mcr_v);
1581 break;
1582 case SR_CRD_N2PCI:
1583 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1584 *fecrp |= SR_FECR_ETC1;
1585 break;
1586 }
1587#endif
1588 }
1589
1590 /*
1591 * XXX Disable all interrupts for now. I think if you are using the
1592 * dmac you don't use these interrupts.
1593 */
1594 SRC_PUT8(hc->sca_base, msci->ie0, 0);
1595 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1596 SRC_PUT8(hc->sca_base, msci->ie2, 0);
1597 SRC_PUT8(hc->sca_base, msci->fie, 0);
1598
1599 SRC_PUT8(hc->sca_base, msci->sa0, 0);
1600 SRC_PUT8(hc->sca_base, msci->sa1, 0);
1601
1602 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */
1603
1604 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1605 SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1606 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1607}
1608
1609/*
1610 * Configure the rx dma controller.
1611 */
1612static void
1613sr_init_rx_dmac(struct sr_softc *sc)
1614{
1615 struct sr_hardc *hc;
1616 dmac_channel *dmac;
1617 sca_descriptor *rxd;
1618 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1619
1620#if BUGGY > 0
1621 printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1622#endif
1623
1624 hc = sc->hc;
1625 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1626
1627 if (hc->mempages)
1628 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1629
1630 /*
1631 * This phase initializes the contents of the descriptor table
1632 * needed to construct a circular buffer...
1633 */
1634 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1635 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1636
1637 for (rxbuf = sc->rxstart;
1638 rxbuf < sc->rxend;
1639 rxbuf += SR_BUF_SIZ, rxd++) {
1640 /*
1641 * construct the circular chain...
1642 */
1643 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1644 rxd->cp = (u_short)(rxda & 0xffff);
1645
1646 /*
1647 * set the on-card buffer address...
1648 */
1649 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1650 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1651
1652 rxd->len = 0; /* bytes resident w/in granule */
1653 rxd->stat = 0xff; /* The sca write here when finished */
1654 }
1655
1656 /*
1657 * heal the chain so that the last entry points to the first...
1658 */
1659 rxd--;
1660 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1661
1662 /*
1663 * reset the reception handler's index...
1664 */
1665 sc->rxhind = 0;
1666
1667 /*
1668 * We'll now configure the receiver's DMA logic...
1669 */
1670 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */
1671 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1672
1673 /* XXX maybe also SCA_DMR_CNTE */
1674 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1675 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1676
1677 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1678 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1679
1680 SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1681 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1682
1683 rxd = (sca_descriptor *)sc->rxstart;
1684
1685 SRC_PUT16(hc->sca_base, dmac->eda,
1686 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1687
1688 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1689
1690
1691 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */
1692}
1693
1694/*
1695 * Configure the TX DMA descriptors.
1696 * Initialize the needed values and chain the descriptors.
1697 */
1698static void
1699sr_init_tx_dmac(struct sr_softc *sc)
1700{
1701 int blk;
1702 u_int txbuf, txda, txda_d;
1703 struct sr_hardc *hc;
1704 sca_descriptor *txd;
1705 dmac_channel *dmac;
1706 struct buf_block *blkp;
1707 u_int x;
1708 u_int sarb_v;
1709
1710#if BUGGY > 0
1711 printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1712#endif
1713
1714 hc = sc->hc;
1715 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1716
1717 if (hc->mempages)
1718 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1719
1720 /*
1721 * Initialize the array of descriptors for transmission
1722 */
1723 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1724 blkp = &sc->block[blk];
1725 txd = (sca_descriptor *)(hc->mem_start
1726 + (blkp->txdesc & hc->winmsk));
1727 txda_d = (u_int) hc->mem_start
1728 - (blkp->txdesc & ~hc->winmsk);
1729
1730 x = 0;
1731 txbuf = blkp->txstart;
1732 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1733 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1734 txd->cp = (u_short)(txda & 0xffff);
1735
1736 txd->bp = (u_short)((txbuf + hc->mem_pstart)
1737 & 0xffff);
1738 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1739 & 0xff);
1740 txd->len = 0;
1741 txd->stat = 0;
1742 x++;
1743 }
1744
1745 txd--;
1746 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1747 & 0xffff);
1748
1749 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1750 }
1751
1752 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */
1753 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1754 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1755 SRC_PUT8(hc->sca_base, dmac->dir,
1756 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1757
1758 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1759 sarb_v &= 0x00ff;
1760
1761 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1762}
1763
1764/*
1765 * Look through the descriptors to see if there is a complete packet
1766 * available. Stop if we get to where the sca is busy.
1767 *
1768 * Return the length and status of the packet.
1769 * Return nonzero if there is a packet available.
1770 *
1771 * NOTE:
1772 * It seems that we get the interrupt a bit early. The updateing of
1773 * descriptor values is not always completed when this is called.
1774 */
1775static int
1776sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1777{
1778 int granules; /* count of granules in pkt */
1779 int wki, wko;
1780 struct sr_hardc *hc;
1781 sca_descriptor *rxdesc; /* current descriptor */
1782 sca_descriptor *endp; /* ending descriptor */
1783 sca_descriptor *cda; /* starting descriptor */
1784
1785 hc = sc->hc; /* get card's information */
1786
1787 /*
1788 * set up starting descriptor by pulling that info from the DMA half
1789 * of the HD chip...
1790 */
1791 wki = DMAC_RXCH(sc->scachan);
1792 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1793
1794 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1795
1796#if BUGGY > 1
1797 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1798 wki, wko, cda);
1799#endif
1800
1801 /*
1802 * open the appropriate memory window and set our expectations...
1803 */
1804 if (hc->mempages) {
1805 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1806 SRC_SET_ON(hc->iobase);
1807 }
1808 rxdesc = (sca_descriptor *)
1809 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1810 endp = rxdesc;
1811 rxdesc = &rxdesc[sc->rxhind];
1812 endp = &endp[sc->rxmax];
1813
1814 *len = 0; /* reset result total length */
1815 granules = 0; /* reset count of granules */
1816
1817 /*
1818 * This loop will scan descriptors, but it *will* puke up if we wrap
1819 * around to our starting point...
1820 */
1821 while (rxdesc != cda) {
1822 *len += rxdesc->len; /* increment result length */
1823 granules++;
1824
1825 /*
1826 * If we hit a valid packet's completion we'll know we've
1827 * got a live one, and that we can deliver the packet.
1828 * Since we're only allowed to report a packet available,
1829 * somebody else does that...
1830 */
1831 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */
1832 *rxstat = rxdesc->stat; /* return closing */
1833#if BUGGY > 0
1834 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1835 sc->unit, *len, *rxstat, granules);
1836#endif
1837 return 1; /* indicate success */
1838 }
1839 /*
1840 * OK, this packet take up multiple granules. Move on to
1841 * the next descriptor so we can consider it...
1842 */
1843 rxdesc++;
1844
1845 if (rxdesc == endp) /* recognize & act on wrap point */
1846 rxdesc = (sca_descriptor *)
1847 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1848 }
1849
1850 /*
1851 * Nothing found in the DPRAM. Let the caller know...
1852 */
1853 *len = 0;
1854 *rxstat = 0;
1855
1856 return 0;
1857}
1858
1859/*
1860 * Copy a packet from the on card memory into a provided mbuf.
1861 * Take into account that buffers wrap and that a packet may
1862 * be larger than a buffer.
1863 */
1864static void
1865sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1866{
1867 struct sr_hardc *hc;
1868 sca_descriptor *rxdesc;
1869 u_int rxdata;
1870 u_int rxmax;
1871 u_int off = 0;
1872 u_int tlen;
1873
1874#if BUGGY > 0
1875 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1876 m, sc, len);
1877#endif
1878
1879 hc = sc->hc;
1880
1881 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1882 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1883
1884 rxdesc = (sca_descriptor *)
1885 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1886 rxdesc = &rxdesc[sc->rxhind];
1887
1888 /*
1889 * Using the count of bytes in the received packet, we decrement it
1890 * for each granule (controller by an SCA descriptor) to control the
1891 * looping...
1892 */
1893 while (len) {
1894 /*
1895 * tlen gets the length of *this* granule... ...which is
1896 * then copied to the target buffer.
1897 */
1898 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1899
1900 if (hc->mempages)
1901 SRC_SET_MEM(hc->iobase, rxdata);
1902
1903 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1904 mtod(m, caddr_t) +off,
1905 tlen);
1906
1907 off += tlen;
1908 len -= tlen;
1909
1910 /*
1911 * now, return to the descriptor's window in DPRAM and reset
1912 * the descriptor we've just suctioned...
1913 */
1914 if (hc->mempages)
1915 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1916
1917 rxdesc->len = 0;
1918 rxdesc->stat = 0xff;
1919
1920 /*
1921 * Move on to the next granule. If we've any remaining
1922 * bytes to process we'll just continue in our loop...
1923 */
1924 rxdata += SR_BUF_SIZ;
1925 rxdesc++;
1926
1927 if (rxdata == rxmax) { /* handle the wrap point */
1928 rxdata = sc->rxstart;
1929 rxdesc = (sca_descriptor *)
1930 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1931 }
1932 }
1933}
1934
1935/*
1936 * If single is set, just eat a packet. Otherwise eat everything up to
1937 * where cda points. Update pointers to point to the next packet.
1938 *
1939 * This handles "flushing" of a packet as received...
1940 *
1941 * If the "single" parameter is zero, all pending reeceive traffic will
1942 * be flushed out of existence. A non-zero value will only drop the
1943 * *next* (currently) pending packet...
1944 */
1945static void
1946sr_eat_packet(struct sr_softc *sc, int single)
1947{
1948 struct sr_hardc *hc;
1949 sca_descriptor *rxdesc; /* current descriptor being eval'd */
1950 sca_descriptor *endp; /* last descriptor in chain */
1951 sca_descriptor *cda; /* current start point */
1952 u_int loopcnt = 0; /* count of packets flushed ??? */
1953 u_char stat; /* captured status byte from descr */
1954
1955 hc = sc->hc;
1956 cda = (sca_descriptor *)(hc->mem_start +
1957 (SRC_GET16(hc->sca_base,
1958 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1959 hc->winmsk));
1960
1961 /*
1962 * loop until desc->stat == (0xff || EOM) Clear the status and
1963 * length in the descriptor. Increment the descriptor.
1964 */
1965 if (hc->mempages)
1966 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1967
1968 rxdesc = (sca_descriptor *)
1969 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1970 endp = rxdesc;
1971 rxdesc = &rxdesc[sc->rxhind];
1972 endp = &endp[sc->rxmax];
1973
1974 /*
1975 * allow loop, but abort it if we wrap completely...
1976 */
1977 while (rxdesc != cda) {
1978 loopcnt++;
1979
1980 if (loopcnt > sc->rxmax) {
1981 printf("sr%d: eat pkt %d loop, cda %x, "
1982 "rxdesc %x, stat %x.\n",
1983 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1984 rxdesc->stat);
1985 break;
1986 }
1987 stat = rxdesc->stat;
1988
1989 rxdesc->len = 0;
1990 rxdesc->stat = 0xff;
1991
1992 rxdesc++;
1993 sc->rxhind++;
1994
1995 if (rxdesc == endp) {
1996 rxdesc = (sca_descriptor *)
1997 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1998 sc->rxhind = 0;
1999 }
2000 if (single && (stat == SCA_DESC_EOM))
2001 break;
2002 }
2003
2004 /*
2005 * Update the eda to the previous descriptor.
2006 */
2007 rxdesc = (sca_descriptor *)sc->rxdesc;
2008 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2009
2010 SRC_PUT16(hc->sca_base,
2011 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2012 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2013}
2014
2015/*
2016 * While there is packets available in the rx buffer, read them out
2017 * into mbufs and ship them off.
2018 */
2019static void
2020sr_get_packets(struct sr_softc *sc)
2021{
2022 u_char rxstat; /* acquired status byte */
2023 int i;
2024 int pkts; /* count of packets found */
2025 int rxndx; /* rcv buffer index */
2026 int tries; /* settling time counter */
2027 u_int len; /* length of pending packet */
2028 struct sr_hardc *hc; /* card-level information */
2029 sca_descriptor *rxdesc; /* descriptor in memory */
2030#ifndef NETGRAPH
2031 struct ifnet *ifp; /* network intf ctl table */
2032#endif /* NETGRAPH */
2033 struct mbuf *m = NULL; /* message buffer */
2034
2035#if BUGGY > 0
2036 printf("sr_get_packets(sc=%08x)\n", sc);
2037#endif
2038
2039 hc = sc->hc;
2040#ifndef NETGRAPH
2041 ifp = &sc->ifsppp.pp_if;
2042#endif /* NETGRAPH */
2043
2044 if (hc->mempages) {
2045 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2046 SRC_SET_ON(hc->iobase); /* enable shared memory */
2047 }
2048 pkts = 0; /* reset count of found packets */
2049
2050 /*
2051 * for each complete packet in the receiving pool, process each
2052 * packet...
2053 */
2054 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */
2055 /*
2056 * I have seen situations where we got the interrupt but the
2057 * status value wasn't deposited. This code should allow
2058 * the status byte's value to settle...
2059 */
2060
2061 tries = 5;
2062
2063 while ((rxstat == 0x00ff)
2064 && --tries)
2065 sr_packet_avail(sc, &len, &rxstat);
2066
2067#if BUGGY > 1
2068 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2069 len, rxstat);
2070#endif
2071
2072 pkts++;
2073#ifdef NETGRAPH
2074 sc->inbytes += len;
2075 sc->inlast = 0;
2076#endif /* NETGRAPH */
2077
2078 /*
2079 * OK, we've settled the incoming message status. We can now
2080 * process it...
2081 */
2082 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2083#if BUGGY > 1
2084 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2085 sc->unit, rxstat, len);
2086#endif
2087
74f1caca 2088 MGETHDR(m, MB_DONTWAIT, MT_DATA);
984263bc
MD
2089 if (m == NULL) {
2090 /*
2091 * eat (flush) packet if get mbuf fail!!
2092 */
2093 sr_eat_packet(sc, 1);
2094 continue;
2095 }
2096 /*
2097 * construct control information for pass-off
2098 */
2099#ifndef NETGRAPH
2100 m->m_pkthdr.rcvif = ifp;
2101#else
2102 m->m_pkthdr.rcvif = NULL;
2103#endif /* NETGRAPH */
2104 m->m_pkthdr.len = m->m_len = len;
2105 if (len > MHLEN) {
74f1caca 2106 MCLGET(m, MB_DONTWAIT);
984263bc
MD
2107 if ((m->m_flags & M_EXT) == 0) {
2108 /*
2109 * We couldn't get a big enough
2110 * message packet, so we'll send the
2111 * packet to /dev/null...
2112 */
2113 m_freem(m);
2114 sr_eat_packet(sc, 1);
2115 continue;
2116 }
2117 }
2118 /*
2119 * OK, we've got a good message buffer. Now we can
2120 * copy the received message into it
2121 */
2122 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */
2123
2124#ifndef NETGRAPH
7600679e 2125 BPF_MTAP(ifp, m);
984263bc
MD
2126
2127#if BUGGY > 3
2128 {
2129 u_char *bp;
2130
2131 bp = (u_char *)m;
2132 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2133 sc->unit,
2134 bp[0], bp[1], bp[2],
2135 bp[4], bp[5], bp[6]);
2136 }
2137#endif
2138 sppp_input(ifp, m);
2139 ifp->if_ipackets++;
2140
2141#else /* NETGRAPH */
2142#if BUGGY > 3
2143 {
2144 u_char *bp;
2145
2146 bp = mtod(m,u_char *);
2147 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2148 sc->unit,
2149 bp[0], bp[1], bp[2],
2150 bp[4], bp[5], bp[6]);
2151 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2152 bp[6], bp[7], bp[8],
2153 bp[9], bp[10], bp[11]);
2154 }
2155#endif
2156 ng_queue_data(sc->hook, m, NULL);
2157 sc->ipackets++;
2158#endif /* NETGRAPH */
2159 /*
2160 * Update the eda to the previous descriptor.
2161 */
2162 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2163 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2164
2165 rxdesc = (sca_descriptor *)sc->rxdesc;
2166 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2167 rxdesc = &rxdesc[rxndx];
2168
2169 SRC_PUT16(hc->sca_base,
2170 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2171 (u_short)((u_int)(rxdesc + hc->mem_pstart)
2172 & 0xffff));
2173
2174 } else {
2175 int got_st3, got_cda, got_eda;
2176 int tries = 5;
2177
2178 while ((rxstat == 0xff) && --tries)
2179 sr_packet_avail(sc, &len, &rxstat);
2180
2181 /*
2182 * It look like we get an interrupt early
2183 * sometimes and then the status is not
2184 * filled in yet.
2185 */
2186 if (tries && (tries != 5))
2187 continue;
2188
2189 /*
2190 * This chunk of code handles the error packets.
2191 * We'll log them for posterity...
2192 */
2193 sr_eat_packet(sc, 1);
2194
2195#ifndef NETGRAPH
2196 ifp->if_ierrors++;
2197#else
2198 sc->ierrors[0]++;
2199#endif /* NETGRAPH */
2200
2201 got_st3 = SRC_GET8(hc->sca_base,
2202 hc->sca->msci[sc->scachan].st3);
2203 got_cda = SRC_GET16(hc->sca_base,
2204 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2205 got_eda = SRC_GET16(hc->sca_base,
2206 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2207
2208#if BUGGY > 0
2209 printf("sr%d: Receive error chan %d, "
2210 "stat %02x, msci st3 %02x,"
2211 "rxhind %d, cda %04x, eda %04x.\n",
2212 sc->unit, sc->scachan, rxstat,
2213 got_st3, sc->rxhind, got_cda, got_eda);
2214#endif
2215 }
2216 }
2217
2218#if BUGGY > 0
2219 printf("sr%d: sr_get_packets() found %d packet(s)\n",
2220 sc->unit, pkts);
2221#endif
2222
2223 if (hc->mempages)
2224 SRC_SET_OFF(hc->iobase);
2225}
2226
2227/*
2228 * All DMA interrupts come here.
2229 *
2230 * Each channel has two interrupts.
2231 * Interrupt A for errors and Interrupt B for normal stuff like end
2232 * of transmit or receive dmas.
2233 */
2234static void
2235sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2236{
2237 u_char dsr; /* contents of DMA Stat Reg */
2238 u_char dotxstart; /* enables for tranmit part */
2239 int mch; /* channel being processed */
2240 struct sr_softc *sc; /* channel's softc structure */
2241 sca_regs *sca = hc->sca;
2242 dmac_channel *dmac; /* dma structure of chip */
2243
2244#if BUGGY > 0
2245 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2246#endif
2247
2248 mch = 0; /* assume chan0 on card */
2249 dotxstart = isr1; /* copy for xmitter starts */
2250
2251 /*
2252 * Shortcut if there is no interrupts for dma channel 0 or 1.
2253 * Skip processing for channel 0 if no incoming hit
2254 */
2255 if ((isr1 & 0x0F) == 0) {
2256 mch = 1;
2257 isr1 >>= 4;
2258 }
2259 do {
2260 sc = &hc->sc[mch];
2261
2262 /*
2263 * Transmit channel - DMA Status Register Evaluation
2264 */
2265 if (isr1 & 0x0C) {
2266 dmac = &sca->dmac[DMAC_TXCH(mch)];
2267
2268 /*
2269 * get the DMA Status Register contents and write
2270 * back to reset interrupt...
2271 */
2272 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2273 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2274
2275 /*
2276 * Check for (& process) a Counter overflow
2277 */
2278 if (dsr & SCA_DSR_COF) {
2279 printf("sr%d: TX DMA Counter overflow, "
2280 "txpacket no %lu.\n",
2281#ifndef NETGRAPH
2282 sc->unit, sc->ifsppp.pp_if.if_opackets);
2283 sc->ifsppp.pp_if.if_oerrors++;
2284#else
2285 sc->unit, sc->opackets);
2286 sc->oerrors++;
2287#endif /* NETGRAPH */
2288 }
2289 /*
2290 * Check for (& process) a Buffer overflow
2291 */
2292 if (dsr & SCA_DSR_BOF) {
2293 printf("sr%d: TX DMA Buffer overflow, "
2294 "txpacket no %lu, dsr %02x, "
2295 "cda %04x, eda %04x.\n",
2296#ifndef NETGRAPH
2297 sc->unit, sc->ifsppp.pp_if.if_opackets,
2298#else
2299 sc->unit, sc->opackets,
2300#endif /* NETGRAPH */
2301 dsr,
2302 SRC_GET16(hc->sca_base, dmac->cda),
2303 SRC_GET16(hc->sca_base, dmac->eda));
2304#ifndef NETGRAPH
2305 sc->ifsppp.pp_if.if_oerrors++;
2306#else
2307 sc->oerrors++;
2308#endif /* NETGRAPH */
2309 }
2310 /*
2311 * Check for (& process) an End of Transfer (OK)
2312 */
2313 if (dsr & SCA_DSR_EOT) {
2314 /*
2315 * This should be the most common case.
2316 *
2317 * Clear the IFF_OACTIVE flag.
2318 *
2319 * Call srstart to start a new transmit if
2320 * there is data to transmit.
2321 */
2322#if BUGGY > 0
2323 printf("sr%d: TX Completed OK\n", sc->unit);
2324#endif
2325 sc->xmit_busy = 0;
2326#ifndef NETGRAPH
2327 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2328 sc->ifsppp.pp_if.if_timer = 0;
2329#else
2330 /* XXX may need to mark tx inactive? */
2331 sc->out_deficit++;
2332 sc->out_dog = DOG_HOLDOFF;
2333#endif /* NETGRAPH */
2334
2335 if (sc->txb_inuse && --sc->txb_inuse)
2336 sr_xmit(sc);
2337 }
2338 }
2339 /*
2340 * Receive channel processing of DMA Status Register
2341 */
2342 if (isr1 & 0x03) {
2343 dmac = &sca->dmac[DMAC_RXCH(mch)];
2344
2345 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2346 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2347
2348 /*
2349 * End of frame processing (MSG OK?)
2350 */
2351 if (dsr & SCA_DSR_EOM) {
2352#if BUGGY > 0
2353 int tt, ind;
2354
2355#ifndef NETGRAPH
2356 tt = sc->ifsppp.pp_if.if_ipackets;
2357#else /* NETGRAPH */
2358 tt = sc->ipackets;
2359#endif /* NETGRAPH */
2360 ind = sc->rxhind;
2361#endif
2362
2363 sr_get_packets(sc);
2364#if BUGGY > 0
2365#ifndef NETGRAPH
2366 if (tt == sc->ifsppp.pp_if.if_ipackets)
2367#else /* NETGRAPH */
2368 if (tt == sc->ipackets)
2369#endif /* NETGRAPH */
2370 {
2371 sca_descriptor *rxdesc;
2372 int i;
2373
2374 printf("SR: RXINTR isr1 %x, dsr %x, "
2375 "no data %d pkts, orxind %d.\n",
2376 dotxstart, dsr, tt, ind);
2377 printf("SR: rxdesc %x, rxstart %x, "
2378 "rxend %x, rxhind %d, "
2379 "rxmax %d.\n",
2380 sc->rxdesc, sc->rxstart,
2381 sc->rxend, sc->rxhind,
2382 sc->rxmax);
2383 printf("SR: cda %x, eda %x.\n",
2384 SRC_GET16(hc->sca_base, dmac->cda),
2385 SRC_GET16(hc->sca_base, dmac->eda));
2386
2387 if (hc->mempages) {
2388 SRC_SET_ON(hc->iobase);
2389 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2390 }
2391 rxdesc = (sca_descriptor *)
2392 (hc->mem_start +
2393 (sc->rxdesc & hc->winmsk));
2394 rxdesc = &rxdesc[sc->rxhind];
2395
2396 for (i = 0; i < 3; i++, rxdesc++)
2397 printf("SR: rxdesc->stat %x, "
2398 "len %d.\n",
2399 rxdesc->stat,
2400 rxdesc->len);
2401
2402 if (hc->mempages)
2403 SRC_SET_OFF(hc->iobase);
2404 }
2405#endif /* BUGGY */
2406 }
2407 /*
2408 * Check for Counter overflow
2409 */
2410 if (dsr & SCA_DSR_COF) {
2411 printf("sr%d: RX DMA Counter overflow, "
2412 "rxpkts %lu.\n",
2413#ifndef NETGRAPH
2414 sc->unit, sc->ifsppp.pp_if.if_ipackets);
2415 sc->ifsppp.pp_if.if_ierrors++;
2416#else /* NETGRAPH */
2417 sc->unit, sc->ipackets);
2418 sc->ierrors[1]++;
2419#endif /* NETGRAPH */
2420 }
2421 /*
2422 * Check for Buffer overflow
2423 */
2424 if (dsr & SCA_DSR_BOF) {
2425 printf("sr%d: RX DMA Buffer overflow, "
2426 "rxpkts %lu, rxind %d, "
2427 "cda %x, eda %x, dsr %x.\n",
2428#ifndef NETGRAPH
2429 sc->unit, sc->ifsppp.pp_if.if_ipackets,
2430#else /* NETGRAPH */
2431 sc->unit, sc->ipackets,
2432#endif /* NETGRAPH */
2433 sc->rxhind,
2434 SRC_GET16(hc->sca_base, dmac->cda),
2435 SRC_GET16(hc->sca_base, dmac->eda),
2436 dsr);
2437
2438 /*
2439 * Make sure we eat as many as possible.
2440 * Then get the system running again.
2441 */
2442 if (hc->mempages)
2443 SRC_SET_ON(hc->iobase);
2444
2445 sr_eat_packet(sc, 0);
2446#ifndef NETGRAPH
2447 sc->ifsppp.pp_if.if_ierrors++;
2448#else /* NETGRAPH */
2449 sc->ierrors[2]++;
2450#endif /* NETGRAPH */
2451
2452 SRC_PUT8(hc->sca_base,
2453 sca->msci[mch].cmd,
2454 SCA_CMD_RXMSGREJ);
2455
2456 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2457
2458#if BUGGY > 0
2459 printf("sr%d: RX DMA Buffer overflow, "
2460 "rxpkts %lu, rxind %d, "
2461 "cda %x, eda %x, dsr %x. After\n",
2462 sc->unit,
2463#ifndef NETGRAPH
2464 sc->ipackets,
2465#else /* NETGRAPH */
2466 sc->ifsppp.pp_if.if_ipackets,
2467#endif /* NETGRAPH */
2468 sc->rxhind,
2469 SRC_GET16(hc->sca_base, dmac->cda),
2470 SRC_GET16(hc->sca_base, dmac->eda),
2471 SRC_GET8(hc->sca_base, dmac->dsr));
2472#endif
2473
2474 if (hc->mempages)
2475 SRC_SET_OFF(hc->iobase);
2476 }
2477 /*
2478 * End of Transfer
2479 */
2480 if (dsr & SCA_DSR_EOT) {
2481 /*
2482 * If this happen, it means that we are
2483 * receiving faster than what the processor
2484 * can handle.
2485 *
2486 * XXX We should enable the dma again.
2487 */
2488 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2489 sc->unit,
2490#ifndef NETGRAPH
2491 sc->ifsppp.pp_if.if_ipackets);
2492 sc->ifsppp.pp_if.if_ierrors++;
2493#else
2494 sc->ipackets);
2495 sc->ierrors[3]++;
2496#endif /* NETGRAPH */
2497 }
2498 }
2499 isr1 >>= 4; /* process next half of ISR */
2500 mch++; /* and move to next channel */
2501 } while ((mch < NCHAN) && isr1); /* loop for each chn */
2502
2503 /*
2504 * Now that we have done all the urgent things, see if we can fill
2505 * the transmit buffers.
2506 */
2507 for (mch = 0; mch < NCHAN; mch++) {
2508 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2509 sc = &hc->sc[mch];
2510#ifndef NETGRAPH
2511 srstart(&sc->ifsppp.pp_if);
2512#else
2513 srstart(sc);
2514#endif /* NETGRAPH */
2515 }
2516 dotxstart >>= 4;/* shift for next channel */
2517 }
2518}
2519#ifndef NETGRAPH
2520#ifdef USE_MODEMCK
2521/*
2522 * Perform timeout on an FR channel
2523 *
2524 * Establish a periodic check of open N2 ports; If
2525 * a port is open/active, its DCD state is checked
2526 * and a loss of DCD is recognized (and eventually
2527 * processed).
2528 */
2529static void
2530sr_modemck(void *arg)
2531{
984263bc
MD
2532 int card; /* card index in table */
2533 int cards; /* card list index */
2534 int mch; /* channel on card */
2535 u_char dcd_v; /* Data Carrier Detect */
2536 u_char got_st0; /* contents of ST0 */
2537 u_char got_st1; /* contents of ST1 */
2538 u_char got_st2; /* contents of ST2 */
2539 u_char got_st3; /* contents of ST3 */
2540 struct sr_hardc *hc; /* card's configuration */
2541 struct sr_hardc *Card[16];/* up to 16 cards in system */
2542 struct sr_softc *sc; /* channel's softc structure */
2543 struct ifnet *ifp; /* interface control table */
2544 msci_channel *msci; /* regs specific to channel */
2545
7ff3b4d2 2546 crit_enter();
984263bc
MD
2547
2548#if 0
2549 if (sr_opens == 0) { /* count of "up" channels */
2550 sr_watcher = 0; /* indicate no watcher */
7ff3b4d2
JS
2551
2552 crit_exit();
2553
984263bc
MD
2554 return;
2555 }
2556#endif
2557
2558 sr_watcher = 1; /* mark that we're online */
2559
2560 /*
2561 * Now we'll need a list of cards to process. Since we can handle
2562 * both ISA and PCI cards (and I didn't think of making this logic
2563 * global YET) we'll generate a single table of card table
2564 * addresses.
2565 */
2566 cards = 0;
2567
2568 for (card = 0; card < NSR; card++) {
2569 hc = &sr_hardc[card];
2570
2571 if (hc->sc == (void *)0)
2572 continue;
2573
2574 Card[cards++] = hc;
2575 }
2576
2577 hc = sr_hardc_pci;
2578
2579 while (hc) {
2580 Card[cards++] = hc;
2581 hc = hc->next;
2582 }
2583
2584 /*
2585 * OK, we've got work we can do. Let's do it... (Please note that
2586 * this code _only_ deals w/ ISA cards)
2587 */
2588 for (card = 0; card < cards; card++) {
2589 hc = Card[card];/* get card table */
2590
2591 for (mch = 0; mch < hc->numports; mch++) {
2592 sc = &hc->sc[mch];
2593
2594 ifp = &sc->ifsppp.pp_if;
2595
2596 /*
2597 * if this channel isn't "up", skip it
2598 */
2599 if ((ifp->if_flags & IFF_UP) == 0)
2600 continue;
2601
2602 /*
2603 * OK, now we can go looking at this channel's
2604 * actual register contents...
2605 */
2606 msci = &hc->sca->msci[sc->scachan];
2607
2608 /*
2609 * OK, now we'll look into the actual status of this
2610 * channel...
2611 *
2612 * I suck in more registers than strictly needed
2613 */
2614 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2615 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2616 got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2617 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2618
2619 /*
2620 * We want to see if the DCD signal is up (DCD is
2621 * true if zero)
2622 */
2623 dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2624
2625 if (dcd_v == 0)
2626 printf("sr%d: DCD lost\n", sc->unit);
2627 }
2628 }
2629
2630 /*
2631 * OK, now set up for the next modem signal checking pass...
2632 */
2633 timeout(sr_modemck, NULL, hz);
2634
7ff3b4d2 2635 crit_exit();
984263bc
MD
2636}
2637#endif
2638#else /* NETGRAPH */
2639/*
2640 * If a port is open/active, it's DCD state is checked
2641 * and a loss of DCD is recognized (and eventually processed?).
2642 */
2643static void
2644sr_modemck(struct sr_softc *sc )
2645{
984263bc
MD
2646 u_char got_st3; /* contents of ST3 */
2647 struct sr_hardc *hc = sc->hc; /* card's configuration */
2648 msci_channel *msci; /* regs specific to channel */
2649
7ff3b4d2 2650 crit_enter();
984263bc 2651
7ff3b4d2
JS
2652 if (sc->running == 0) {
2653 crit_exit();
984263bc 2654 return;
7ff3b4d2
JS
2655 }
2656
984263bc
MD
2657 /*
2658 * OK, now we can go looking at this channel's register contents...
2659 */
2660 msci = &hc->sca->msci[sc->scachan];
2661 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2662
2663 /*
2664 * We want to see if the DCD signal is up (DCD is true if zero)
2665 */
2666 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
7ff3b4d2
JS
2667
2668 crit_exit();
984263bc
MD
2669}
2670
2671#endif /* NETGRAPH */
2672static void
2673sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2674{
2675 printf("src%d: SRINTR: MSCI\n", hc->cunit);
2676}
2677
2678static void
2679sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2680{
2681 printf("src%d: SRINTR: TIMER\n", hc->cunit);
2682}
2683
2684#ifdef NETGRAPH
2685/*****************************************
2686 * Device timeout/watchdog routine.
2687 * called once per second.
2688 * checks to see that if activity was expected, that it hapenned.
2689 * At present we only look to see if expected output was completed.
2690 */
2691static void
2692ngsr_watchdog_frame(void * arg)
2693{
2694 struct sr_softc * sc = arg;
984263bc
MD
2695 int speed;
2696
7ff3b4d2
JS
2697 crit_enter();
2698
2699 if (sc->running == 0) {
2700 crit_enter();
984263bc 2701 return; /* if we are not running let timeouts die */
7ff3b4d2 2702 }
984263bc
MD
2703 /*
2704 * calculate the apparent throughputs
2705 * XXX a real hack
2706 */
7ff3b4d2 2707
984263bc
MD
2708 speed = sc->inbytes - sc->lastinbytes;
2709 sc->lastinbytes = sc->inbytes;
2710 if ( sc->inrate < speed )
2711 sc->inrate = speed;
2712 speed = sc->outbytes - sc->lastoutbytes;
2713 sc->lastoutbytes = sc->outbytes;
2714 if ( sc->outrate < speed )
2715 sc->outrate = speed;
2716 sc->inlast++;
7ff3b4d2
JS
2717
2718 crit_exit();
984263bc
MD
2719
2720 if ((sc->inlast > QUITE_A_WHILE)
2721 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2722 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
7ff3b4d2
JS
2723
2724 crit_enter();
2725
984263bc
MD
2726 sr_down(sc);
2727 sr_up(sc);
2728 sc->inlast = sc->out_deficit = 0;
7ff3b4d2
JS
2729
2730 crit_exit();
984263bc
MD
2731 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2732 if (sc->out_dog == 0) {
2733 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2734 sc->unit);
7ff3b4d2
JS
2735
2736 crit_enter();
2737
984263bc
MD
2738 srwatchdog(sc);
2739#if 0
2740 sr_down(sc);
2741 sr_up(sc);
2742#endif
7ff3b4d2
JS
2743
2744 crit_exit();
2745
984263bc
MD
2746 sc->inlast = sc->out_deficit = 0;
2747 } else {
2748 sc->out_dog--;
2749 }
2750 }
2751 sr_modemck(sc); /* update the DCD status */
ce9980ee 2752 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
984263bc
MD
2753}
2754
2755/***********************************************************************
2756 * This section contains the methods for the Netgraph interface
2757 ***********************************************************************/
2758/*
2759 * It is not possible or allowable to create a node of this type.
2760 * If the hardware exists, it will already have created it.
2761 */
2762static int
2763ngsr_constructor(node_p *nodep)
2764{
2765 return (EINVAL);
2766}
2767
2768/*
2769 * give our ok for a hook to be added...
2770 * If we are not running this should kick the device into life.
2771 * The hook's private info points to our stash of info about that
2772 * channel.
2773 */
2774static int
2775ngsr_newhook(node_p node, hook_p hook, const char *name)
2776{
2777 struct sr_softc * sc = node->private;
2778
2779 /*
2780 * check if it's our friend the debug hook
2781 */
2782 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2783 hook->private = NULL; /* paranoid */
2784 sc->debug_hook = hook;
2785 return (0);
2786 }
2787
2788 /*
2789 * Check for raw mode hook.
2790 */
2791 if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2792 return (EINVAL);
2793 }
2794 hook->private = sc;
2795 sc->hook = hook;
2796 sc->datahooks++;
2797 sr_up(sc);
2798 return (0);
2799}
2800
2801/*
2802 * incoming messages.
2803 * Just respond to the generic TEXT_STATUS message
2804 */
2805static int
2806ngsr_rcvmsg(node_p node,
2807 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2808{
2809 struct sr_softc * sc;
2810 int error = 0;
2811
2812 sc = node->private;
2813 switch (msg->header.typecookie) {
2814 case NG_SR_COOKIE:
2815 error = EINVAL;
2816 break;
2817 case NGM_GENERIC_COOKIE:
2818 switch(msg->header.cmd) {
2819 case NGM_TEXT_STATUS: {
2820 char *arg;
2821 int pos = 0;
2822 int resplen = sizeof(struct ng_mesg) + 512;
2823 MALLOC(*resp, struct ng_mesg *, resplen,
c5541aee 2824 M_NETGRAPH, M_INTWAIT | M_ZERO);
984263bc
MD
2825 if (*resp == NULL) {
2826 error = ENOMEM;
2827 break;
2828 }
2829 arg = (*resp)->data;
2830
2831 /*
2832 * Put in the throughput information.
2833 */
2834 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2835 "highest rate seen: %ld B/S in, %ld B/S out\n",
2836 sc->inbytes, sc->outbytes,
2837 sc->inrate, sc->outrate);
2838 pos += sprintf(arg + pos,
2839 "%ld output errors\n",
2840 sc->oerrors);
2841 pos += sprintf(arg + pos,
2842 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2843 sc->ierrors[0],
2844 sc->ierrors[1],
2845 sc->ierrors[2],
2846 sc->ierrors[3],
2847 sc->ierrors[4],
2848 sc->ierrors[5]);
2849
2850 (*resp)->header.version = NG_VERSION;
2851 (*resp)->header.arglen = strlen(arg) + 1;
2852 (*resp)->header.token = msg->header.token;
2853 (*resp)->header.typecookie = NG_SR_COOKIE;
2854 (*resp)->header.cmd = msg->header.cmd;
2855 strncpy((*resp)->header.cmdstr, "status",
2856 NG_CMDSTRLEN);
2857 }
2858 break;
2859 default:
2860 error = EINVAL;
2861 break;
2862 }
2863 break;
2864 default:
2865 error = EINVAL;
2866 break;
2867 }
efda3bd0 2868 kfree(msg, M_NETGRAPH);
984263bc
MD
2869 return (error);
2870}
2871
2872/*
2873 * get data from another node and transmit it to the correct channel
2874 */
2875static int
2876ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2877{
984263bc
MD
2878 int error = 0;
2879 struct sr_softc * sc = hook->node->private;
2880 struct ifqueue *xmitq_p;
2881
2882 /*
2883 * data doesn't come in from just anywhere (e.g control hook)
2884 */
2885 if ( hook->private == NULL) {
2886 error = ENETDOWN;
2887 goto bad;
2888 }
2889
2890 /*
2891 * Now queue the data for when it can be sent
2892 */
2893 if (meta && meta->priority > 0) {
2894 xmitq_p = (&sc->xmitq_hipri);
2895 } else {
2896 xmitq_p = (&sc->xmitq);
2897 }
7ff3b4d2
JS
2898
2899 crit_enter();
2900
984263bc
MD
2901 if (IF_QFULL(xmitq_p)) {
2902 IF_DROP(xmitq_p);
7ff3b4d2
JS
2903
2904 crit_exit();
2905
984263bc
MD
2906 error = ENOBUFS;
2907 goto bad;
2908 }
2909 IF_ENQUEUE(xmitq_p, m);
2910 srstart(sc);
7ff3b4d2
JS
2911
2912 crit_exit();
2913
984263bc
MD
2914 return (0);
2915
2916bad:
2917 /*
2918 * It was an error case.
2919 * check if we need to free the mbuf, and then return the error
2920 */
2921 NG_FREE_DATA(m, meta);
2922 return (error);
2923}
2924
2925/*
2926 * do local shutdown processing..
2927 * this node will refuse to go away, unless the hardware says to..
2928 * don't unref the node, or remove our name. just clear our links up.
2929 */
2930static int
2931ngsr_rmnode(node_p node)
2932{
2933 struct sr_softc * sc = node->private;
2934
2935 sr_down(sc);
2936 ng_cutlinks(node);
2937 node->flags &= ~NG_INVALID; /* bounce back to life */
2938 return (0);
2939}
2940
2941/* already linked */
2942static int
2943ngsr_connect(hook_p hook)
2944{
2945 /* be really amiable and just say "YUP that's OK by me! " */
2946 return (0);
2947}
2948
2949/*
2950 * notify on hook disconnection (destruction)
2951 *
2952 * Invalidate the private data associated with this dlci.
2953 * For this type, removal of the last link resets tries to destroy the node.
2954 * As the device still exists, the shutdown method will not actually
2955 * destroy the node, but reset the device and leave it 'fresh' :)
2956 *
2957 * The node removal code will remove all references except that owned by the
2958 * driver.
2959 */
2960static int
2961ngsr_disconnect(hook_p hook)
2962{
2963 struct sr_softc * sc = hook->node->private;
984263bc
MD
2964 /*
2965 * If it's the data hook, then free resources etc.
2966 */
2967 if (hook->private) {
7ff3b4d2
JS
2968 crit_enter();
2969
984263bc
MD
2970 sc->datahooks--;
2971 if (sc->datahooks == 0)
2972 sr_down(sc);
7ff3b4d2
JS
2973
2974 crit_exit();
984263bc
MD
2975 } else {
2976 sc->debug_hook = NULL;
2977 }
2978 return (0);
2979}
2980
2981/*
2982 * called during bootup
2983 * or LKM loading to put this type into the list of known modules
2984 */
2985static void
2986ngsr_init(void *ignored)
2987{
2988 if (ng_newtype(&typestruct))
2989 printf("ngsr install failed\n");
2990 ngsr_done_init = 1;
2991}
2992#endif /* NETGRAPH */
2993
2994/*
2995 ********************************* END ************************************
2996 */