Do a major clean-up of the BUSDMA architecture. A large number of
[dragonfly.git] / sys / dev / netif / ste / if_ste.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
1f7ab7c9 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.35 2006/10/25 20:55:59 dillon Exp $
984263bc
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34 */
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/sockio.h>
39#include <sys/mbuf.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/socket.h>
78195a76 43#include <sys/serialize.h>
1f7ab7c9
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44#include <sys/bus.h>
45#include <sys/rman.h>
9228feed 46#include <sys/thread2.h>
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47
48#include <net/if.h>
2f2e6d88 49#include <net/ifq_var.h>
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50#include <net/if_arp.h>
51#include <net/ethernet.h>
52#include <net/if_dl.h>
53#include <net/if_media.h>
1f2de5d4 54#include <net/vlan/if_vlan_var.h>
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55
56#include <net/bpf.h>
57
58#include <vm/vm.h> /* for vtophys */
59#include <vm/pmap.h> /* for vtophys */
984263bc 60
1f2de5d4
MD
61#include "../mii_layer/mii.h"
62#include "../mii_layer/miivar.h"
984263bc 63
0bc504d2 64#include <bus/pci/pcidevs.h>
1f2de5d4
MD
65#include <bus/pci/pcireg.h>
66#include <bus/pci/pcivar.h>
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67
68/* "controller miibus0" required. See GENERIC if you get errors here. */
69#include "miibus_if.h"
70
71#define STE_USEIOSPACE
72
1f2de5d4 73#include "if_stereg.h"
984263bc 74
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75/*
76 * Various supported device vendors/types and their names.
77 */
78static struct ste_type ste_devs[] = {
0bc504d2
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79 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201,
80 "Sundance ST201 10/100BaseTX" },
81 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002,
82 "D-Link DFE-550TX 10/100BaseTX" },
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83 { 0, 0, NULL }
84};
85
b5101a88
RG
86static int ste_probe (device_t);
87static int ste_attach (device_t);
88static int ste_detach (device_t);
89static void ste_init (void *);
90static void ste_intr (void *);
91static void ste_rxeof (struct ste_softc *);
92static void ste_txeoc (struct ste_softc *);
93static void ste_txeof (struct ste_softc *);
94static void ste_stats_update (void *);
95static void ste_stop (struct ste_softc *);
96static void ste_reset (struct ste_softc *);
bd4539cc
JH
97static int ste_ioctl (struct ifnet *, u_long, caddr_t,
98 struct ucred *);
b5101a88
RG
99static int ste_encap (struct ste_softc *, struct ste_chain *,
100 struct mbuf *);
101static void ste_start (struct ifnet *);
102static void ste_watchdog (struct ifnet *);
103static void ste_shutdown (device_t);
104static int ste_newbuf (struct ste_softc *,
984263bc 105 struct ste_chain_onefrag *,
b5101a88
RG
106 struct mbuf *);
107static int ste_ifmedia_upd (struct ifnet *);
108static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
109
110static void ste_mii_sync (struct ste_softc *);
111static void ste_mii_send (struct ste_softc *, u_int32_t, int);
112static int ste_mii_readreg (struct ste_softc *,
113 struct ste_mii_frame *);
114static int ste_mii_writereg (struct ste_softc *,
115 struct ste_mii_frame *);
116static int ste_miibus_readreg (device_t, int, int);
117static int ste_miibus_writereg (device_t, int, int, int);
118static void ste_miibus_statchg (device_t);
119
120static int ste_eeprom_wait (struct ste_softc *);
121static int ste_read_eeprom (struct ste_softc *, caddr_t, int,
122 int, int);
123static void ste_wait (struct ste_softc *);
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RG
124static void ste_setmulti (struct ste_softc *);
125static int ste_init_rx_list (struct ste_softc *);
126static void ste_init_tx_list (struct ste_softc *);
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127
128#ifdef STE_USEIOSPACE
129#define STE_RES SYS_RES_IOPORT
130#define STE_RID STE_PCI_LOIO
131#else
132#define STE_RES SYS_RES_MEMORY
133#define STE_RID STE_PCI_LOMEM
134#endif
135
136static device_method_t ste_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, ste_probe),
139 DEVMETHOD(device_attach, ste_attach),
140 DEVMETHOD(device_detach, ste_detach),
141 DEVMETHOD(device_shutdown, ste_shutdown),
142
143 /* bus interface */
144 DEVMETHOD(bus_print_child, bus_generic_print_child),
145 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
146
147 /* MII interface */
148 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
149 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
150 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
151
152 { 0, 0 }
153};
154
155static driver_t ste_driver = {
156 "ste",
157 ste_methods,
158 sizeof(struct ste_softc)
159};
160
161static devclass_t ste_devclass;
162
32832096 163DECLARE_DUMMY_MODULE(if_ste);
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164DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
166
167#define STE_SETBIT4(sc, reg, x) \
168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
169
170#define STE_CLRBIT4(sc, reg, x) \
171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
172
173#define STE_SETBIT2(sc, reg, x) \
174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
175
176#define STE_CLRBIT2(sc, reg, x) \
177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
178
179#define STE_SETBIT1(sc, reg, x) \
180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
181
182#define STE_CLRBIT1(sc, reg, x) \
183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
184
185
186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
188
189/*
190 * Sync the PHYs by setting data bit and strobing the clock 32 times.
191 */
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SW
192static void
193ste_mii_sync(struct ste_softc *sc)
984263bc 194{
3d0f5f54 195 int i;
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196
197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
198
199 for (i = 0; i < 32; i++) {
200 MII_SET(STE_PHYCTL_MCLK);
201 DELAY(1);
202 MII_CLR(STE_PHYCTL_MCLK);
203 DELAY(1);
204 }
205
206 return;
207}
208
209/*
210 * Clock a series of bits through the MII.
211 */
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212static void
213ste_mii_send(struct ste_softc *sc, u_int32_t bits, int cnt)
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214{
215 int i;
216
217 MII_CLR(STE_PHYCTL_MCLK);
218
219 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
220 if (bits & i) {
221 MII_SET(STE_PHYCTL_MDATA);
222 } else {
223 MII_CLR(STE_PHYCTL_MDATA);
224 }
225 DELAY(1);
226 MII_CLR(STE_PHYCTL_MCLK);
227 DELAY(1);
228 MII_SET(STE_PHYCTL_MCLK);
229 }
230}
231
232/*
233 * Read an PHY register through the MII.
234 */
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SW
235static int
236ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame)
984263bc 237{
9228feed 238 int i, ack;
984263bc 239
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MD
240 /*
241 * Set up frame for RX.
242 */
243 frame->mii_stdelim = STE_MII_STARTDELIM;
244 frame->mii_opcode = STE_MII_READOP;
245 frame->mii_turnaround = 0;
246 frame->mii_data = 0;
247
248 CSR_WRITE_2(sc, STE_PHYCTL, 0);
249 /*
250 * Turn on data xmit.
251 */
252 MII_SET(STE_PHYCTL_MDIR);
253
254 ste_mii_sync(sc);
255
256 /*
257 * Send command/address info.
258 */
259 ste_mii_send(sc, frame->mii_stdelim, 2);
260 ste_mii_send(sc, frame->mii_opcode, 2);
261 ste_mii_send(sc, frame->mii_phyaddr, 5);
262 ste_mii_send(sc, frame->mii_regaddr, 5);
263
264 /* Turn off xmit. */
265 MII_CLR(STE_PHYCTL_MDIR);
266
267 /* Idle bit */
268 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
269 DELAY(1);
270 MII_SET(STE_PHYCTL_MCLK);
271 DELAY(1);
272
273 /* Check for ack */
274 MII_CLR(STE_PHYCTL_MCLK);
275 DELAY(1);
276 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
277 MII_SET(STE_PHYCTL_MCLK);
278 DELAY(1);
279
280 /*
281 * Now try reading data bits. If the ack failed, we still
282 * need to clock through 16 cycles to keep the PHY(s) in sync.
283 */
284 if (ack) {
285 for(i = 0; i < 16; i++) {
286 MII_CLR(STE_PHYCTL_MCLK);
287 DELAY(1);
288 MII_SET(STE_PHYCTL_MCLK);
289 DELAY(1);
290 }
291 goto fail;
292 }
293
294 for (i = 0x8000; i; i >>= 1) {
295 MII_CLR(STE_PHYCTL_MCLK);
296 DELAY(1);
297 if (!ack) {
298 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
299 frame->mii_data |= i;
300 DELAY(1);
301 }
302 MII_SET(STE_PHYCTL_MCLK);
303 DELAY(1);
304 }
305
306fail:
307
308 MII_CLR(STE_PHYCTL_MCLK);
309 DELAY(1);
310 MII_SET(STE_PHYCTL_MCLK);
311 DELAY(1);
312
984263bc
MD
313 if (ack)
314 return(1);
315 return(0);
316}
317
318/*
319 * Write to a PHY register through the MII.
320 */
c436375a
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321static int
322ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame)
984263bc 323{
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MD
324 /*
325 * Set up frame for TX.
326 */
327
328 frame->mii_stdelim = STE_MII_STARTDELIM;
329 frame->mii_opcode = STE_MII_WRITEOP;
330 frame->mii_turnaround = STE_MII_TURNAROUND;
331
332 /*
333 * Turn on data output.
334 */
335 MII_SET(STE_PHYCTL_MDIR);
336
337 ste_mii_sync(sc);
338
339 ste_mii_send(sc, frame->mii_stdelim, 2);
340 ste_mii_send(sc, frame->mii_opcode, 2);
341 ste_mii_send(sc, frame->mii_phyaddr, 5);
342 ste_mii_send(sc, frame->mii_regaddr, 5);
343 ste_mii_send(sc, frame->mii_turnaround, 2);
344 ste_mii_send(sc, frame->mii_data, 16);
345
346 /* Idle bit. */
347 MII_SET(STE_PHYCTL_MCLK);
348 DELAY(1);
349 MII_CLR(STE_PHYCTL_MCLK);
350 DELAY(1);
351
352 /*
353 * Turn off xmit.
354 */
355 MII_CLR(STE_PHYCTL_MDIR);
356
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MD
357 return(0);
358}
359
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360static int
361ste_miibus_readreg(device_t dev, int phy, int reg)
984263bc
MD
362{
363 struct ste_softc *sc;
364 struct ste_mii_frame frame;
365
366 sc = device_get_softc(dev);
367
368 if ( sc->ste_one_phy && phy != 0 )
369 return (0);
370
371 bzero((char *)&frame, sizeof(frame));
372
373 frame.mii_phyaddr = phy;
374 frame.mii_regaddr = reg;
375 ste_mii_readreg(sc, &frame);
376
377 return(frame.mii_data);
378}
379
c436375a
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380static int
381ste_miibus_writereg(device_t dev, int phy, int reg, int data)
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382{
383 struct ste_softc *sc;
384 struct ste_mii_frame frame;
385
386 sc = device_get_softc(dev);
387 bzero((char *)&frame, sizeof(frame));
388
389 frame.mii_phyaddr = phy;
390 frame.mii_regaddr = reg;
391 frame.mii_data = data;
392
393 ste_mii_writereg(sc, &frame);
394
395 return(0);
396}
397
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398static void
399ste_miibus_statchg(device_t dev)
984263bc
MD
400{
401 struct ste_softc *sc;
402 struct mii_data *mii;
403 int i;
404
405 sc = device_get_softc(dev);
406 mii = device_get_softc(sc->ste_miibus);
407
408 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
409 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
410 } else {
411 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
412 }
413
414 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
415 STE_ASICCTL_TX_RESET);
416 for (i = 0; i < STE_TIMEOUT; i++) {
417 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
418 break;
419 }
420 if (i == STE_TIMEOUT)
98b2fe08 421 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n");
984263bc
MD
422
423 return;
424}
425
c436375a
SW
426static int
427ste_ifmedia_upd(struct ifnet *ifp)
984263bc
MD
428{
429 struct ste_softc *sc;
430 struct mii_data *mii;
431
432 sc = ifp->if_softc;
433 mii = device_get_softc(sc->ste_miibus);
434 sc->ste_link = 0;
435 if (mii->mii_instance) {
436 struct mii_softc *miisc;
437 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
438 miisc = LIST_NEXT(miisc, mii_list))
439 mii_phy_reset(miisc);
440 }
441 mii_mediachg(mii);
442
443 return(0);
444}
445
c436375a
SW
446static void
447ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc
MD
448{
449 struct ste_softc *sc;
450 struct mii_data *mii;
451
452 sc = ifp->if_softc;
453 mii = device_get_softc(sc->ste_miibus);
454
455 mii_pollstat(mii);
456 ifmr->ifm_active = mii->mii_media_active;
457 ifmr->ifm_status = mii->mii_media_status;
458
459 return;
460}
461
c436375a
SW
462static void
463ste_wait(struct ste_softc *sc)
984263bc 464{
3d0f5f54 465 int i;
984263bc
MD
466
467 for (i = 0; i < STE_TIMEOUT; i++) {
468 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
469 break;
470 }
471
472 if (i == STE_TIMEOUT)
98b2fe08 473 if_printf(&sc->arpcom.ac_if, "command never completed!\n");
984263bc
MD
474
475 return;
476}
477
478/*
479 * The EEPROM is slow: give it time to come ready after issuing
480 * it a command.
481 */
c436375a
SW
482static int
483ste_eeprom_wait(struct ste_softc *sc)
984263bc
MD
484{
485 int i;
486
487 DELAY(1000);
488
489 for (i = 0; i < 100; i++) {
490 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
491 DELAY(1000);
492 else
493 break;
494 }
495
496 if (i == 100) {
98b2fe08 497 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
984263bc
MD
498 return(1);
499 }
500
501 return(0);
502}
503
504/*
505 * Read a sequence of words from the EEPROM. Note that ethernet address
506 * data is stored in the EEPROM in network byte order.
507 */
c436375a
SW
508static int
509ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc
MD
510{
511 int err = 0, i;
512 u_int16_t word = 0, *ptr;
513
514 if (ste_eeprom_wait(sc))
515 return(1);
516
517 for (i = 0; i < cnt; i++) {
518 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
519 err = ste_eeprom_wait(sc);
520 if (err)
521 break;
522 word = CSR_READ_2(sc, STE_EEPROM_DATA);
523 ptr = (u_int16_t *)(dest + (i * 2));
524 if (swap)
525 *ptr = ntohs(word);
526 else
527 *ptr = word;
528 }
529
530 return(err ? 1 : 0);
531}
532
c436375a
SW
533static void
534ste_setmulti(struct ste_softc *sc)
984263bc
MD
535{
536 struct ifnet *ifp;
537 int h = 0;
538 u_int32_t hashes[2] = { 0, 0 };
539 struct ifmultiaddr *ifma;
540
541 ifp = &sc->arpcom.ac_if;
542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
543 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
544 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
545 return;
546 }
547
548 /* first, zot all the existing hash bits */
549 CSR_WRITE_2(sc, STE_MAR0, 0);
550 CSR_WRITE_2(sc, STE_MAR1, 0);
551 CSR_WRITE_2(sc, STE_MAR2, 0);
552 CSR_WRITE_2(sc, STE_MAR3, 0);
553
554 /* now program new ones */
03df8a20 555 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
556 if (ifma->ifma_addr->sa_family != AF_LINK)
557 continue;
d1c520bc
JS
558 h = ether_crc32_be(
559 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
560 ETHER_ADDR_LEN) & 0x3f;
984263bc
MD
561 if (h < 32)
562 hashes[0] |= (1 << h);
563 else
564 hashes[1] |= (1 << (h - 32));
565 }
566
567 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
568 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
569 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
570 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
571 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
572 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
573
574 return;
575}
576
c436375a
SW
577static void
578ste_intr(void *xsc)
984263bc
MD
579{
580 struct ste_softc *sc;
581 struct ifnet *ifp;
582 u_int16_t status;
583
584 sc = xsc;
585 ifp = &sc->arpcom.ac_if;
586
587 /* See if this is really our interrupt. */
588 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
589 return;
590
591 for (;;) {
592 status = CSR_READ_2(sc, STE_ISR_ACK);
593
594 if (!(status & STE_INTRS))
595 break;
596
597 if (status & STE_ISR_RX_DMADONE)
598 ste_rxeof(sc);
599
600 if (status & STE_ISR_TX_DMADONE)
601 ste_txeof(sc);
602
603 if (status & STE_ISR_TX_DONE)
604 ste_txeoc(sc);
605
606 if (status & STE_ISR_STATS_OFLOW) {
5abe9a2d 607 callout_stop(&sc->ste_stat_timer);
984263bc
MD
608 ste_stats_update(sc);
609 }
610
611 if (status & STE_ISR_LINKEVENT)
612 mii_pollstat(device_get_softc(sc->ste_miibus));
613
614 if (status & STE_ISR_HOSTERR) {
615 ste_reset(sc);
616 ste_init(sc);
617 }
618 }
619
620 /* Re-enable interrupts */
621 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
622
2f2e6d88 623 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
624 ste_start(ifp);
625
626 return;
627}
628
629/*
630 * A frame has been uploaded: pass the resulting mbuf chain up to
631 * the higher level protocols.
632 */
c436375a
SW
633static void
634ste_rxeof(struct ste_softc *sc)
984263bc 635{
984263bc
MD
636 struct mbuf *m;
637 struct ifnet *ifp;
638 struct ste_chain_onefrag *cur_rx;
639 int total_len = 0, count=0;
640 u_int32_t rxstat;
641
642 ifp = &sc->arpcom.ac_if;
643
644 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
645 & STE_RXSTAT_DMADONE) {
646 if ((STE_RX_LIST_CNT - count) < 3) {
647 break;
648 }
649
650 cur_rx = sc->ste_cdata.ste_rx_head;
651 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
652
653 /*
654 * If an error occurs, update stats, clear the
655 * status word and leave the mbuf cluster in place:
656 * it should simply get re-used next time this descriptor
657 * comes up in the ring.
658 */
659 if (rxstat & STE_RXSTAT_FRAME_ERR) {
660 ifp->if_ierrors++;
661 cur_rx->ste_ptr->ste_status = 0;
662 continue;
663 }
664
665 /*
666 * If there error bit was not set, the upload complete
667 * bit should be set which means we have a valid packet.
668 * If not, something truly strange has happened.
669 */
670 if (!(rxstat & STE_RXSTAT_DMADONE)) {
98b2fe08 671 if_printf(ifp, "bad receive status -- packet dropped");
984263bc
MD
672 ifp->if_ierrors++;
673 cur_rx->ste_ptr->ste_status = 0;
674 continue;
675 }
676
677 /* No errors; receive the packet. */
678 m = cur_rx->ste_mbuf;
679 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
680
681 /*
682 * Try to conjure up a new mbuf cluster. If that
683 * fails, it means we have an out of memory condition and
684 * should leave the buffer in place and continue. This will
685 * result in a lost packet, but there's little else we
686 * can do in this situation.
687 */
688 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
689 ifp->if_ierrors++;
690 cur_rx->ste_ptr->ste_status = 0;
691 continue;
692 }
693
694 ifp->if_ipackets++;
984263bc
MD
695 m->m_pkthdr.rcvif = ifp;
696 m->m_pkthdr.len = m->m_len = total_len;
697
78195a76 698 ifp->if_input(ifp, m);
984263bc
MD
699
700 cur_rx->ste_ptr->ste_status = 0;
701 count++;
702 }
703
704 return;
705}
706
c436375a
SW
707static void
708ste_txeoc(struct ste_softc *sc)
984263bc
MD
709{
710 u_int8_t txstat;
711 struct ifnet *ifp;
712
713 ifp = &sc->arpcom.ac_if;
714
715 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
716 STE_TXSTATUS_TXDONE) {
717 if (txstat & STE_TXSTATUS_UNDERRUN ||
718 txstat & STE_TXSTATUS_EXCESSCOLLS ||
719 txstat & STE_TXSTATUS_RECLAIMERR) {
720 ifp->if_oerrors++;
98b2fe08 721 if_printf(ifp, "transmission error: %x\n", txstat);
984263bc
MD
722
723 ste_reset(sc);
724 ste_init(sc);
725
726 if (txstat & STE_TXSTATUS_UNDERRUN &&
727 sc->ste_tx_thresh < STE_PACKET_SIZE) {
728 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
98b2fe08 729 if_printf(ifp, "tx underrun, increasing tx"
984263bc 730 " start threshold to %d bytes\n",
98b2fe08 731 sc->ste_tx_thresh);
984263bc
MD
732 }
733 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
734 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
735 (STE_PACKET_SIZE >> 4));
736 }
737 ste_init(sc);
738 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
739 }
740
741 return;
742}
743
c436375a
SW
744static void
745ste_txeof(struct ste_softc *sc)
984263bc
MD
746{
747 struct ste_chain *cur_tx = NULL;
748 struct ifnet *ifp;
749 int idx;
750
751 ifp = &sc->arpcom.ac_if;
752
753 idx = sc->ste_cdata.ste_tx_cons;
754 while(idx != sc->ste_cdata.ste_tx_prod) {
755 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
756
757 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
758 break;
759
760 if (cur_tx->ste_mbuf != NULL) {
761 m_freem(cur_tx->ste_mbuf);
762 cur_tx->ste_mbuf = NULL;
763 }
764
765 ifp->if_opackets++;
766
767 sc->ste_cdata.ste_tx_cnt--;
768 STE_INC(idx, STE_TX_LIST_CNT);
769 ifp->if_timer = 0;
770 }
771
772 sc->ste_cdata.ste_tx_cons = idx;
773
774 if (cur_tx != NULL)
775 ifp->if_flags &= ~IFF_OACTIVE;
776
777 return;
778}
779
c436375a
SW
780static void
781ste_stats_update(void *xsc)
984263bc
MD
782{
783 struct ste_softc *sc;
784 struct ifnet *ifp;
785 struct mii_data *mii;
984263bc 786
984263bc
MD
787 sc = xsc;
788 ifp = &sc->arpcom.ac_if;
789 mii = device_get_softc(sc->ste_miibus);
790
78195a76
MD
791 lwkt_serialize_enter(ifp->if_serializer);
792
984263bc
MD
793 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
794 + CSR_READ_1(sc, STE_MULTI_COLLS)
795 + CSR_READ_1(sc, STE_SINGLE_COLLS);
796
797 if (!sc->ste_link) {
798 mii_pollstat(mii);
799 if (mii->mii_media_status & IFM_ACTIVE &&
800 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
801 sc->ste_link++;
802 /*
803 * we don't get a call-back on re-init so do it
804 * otherwise we get stuck in the wrong link state
805 */
806 ste_miibus_statchg(sc->ste_dev);
2f2e6d88 807 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
808 ste_start(ifp);
809 }
810 }
811
5abe9a2d 812 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
78195a76 813 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
814}
815
816
817/*
818 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
819 * IDs against our list and return a device name if we find a match.
820 */
c436375a
SW
821static int
822ste_probe(device_t dev)
984263bc
MD
823{
824 struct ste_type *t;
825
826 t = ste_devs;
827
828 while(t->ste_name != NULL) {
829 if ((pci_get_vendor(dev) == t->ste_vid) &&
830 (pci_get_device(dev) == t->ste_did)) {
831 device_set_desc(dev, t->ste_name);
832 return(0);
833 }
834 t++;
835 }
836
837 return(ENXIO);
838}
839
840/*
841 * Attach the interface. Allocate softc structures, do ifmedia
842 * setup and ethernet/BPF attach.
843 */
c436375a
SW
844static int
845ste_attach(device_t dev)
984263bc 846{
984263bc
MD
847 struct ste_softc *sc;
848 struct ifnet *ifp;
98b2fe08 849 int error = 0, rid;
aff62688 850 uint8_t eaddr[ETHER_ADDR_LEN];
984263bc 851
984263bc 852 sc = device_get_softc(dev);
984263bc
MD
853 sc->ste_dev = dev;
854
855 /*
856 * Only use one PHY since this chip reports multiple
857 * Note on the DFE-550 the PHY is at 1 on the DFE-580
858 * it is at 0 & 1. It is rev 0x12.
859 */
0bc504d2
SW
860 if (pci_get_vendor(dev) == PCI_VENDOR_DLINK &&
861 pci_get_device(dev) == PCI_PRODUCT_DLINK_DL1002 &&
984263bc
MD
862 pci_get_revid(dev) == 0x12 )
863 sc->ste_one_phy = 1;
864
865 /*
866 * Handle power management nonsense.
867 */
38d17198
JS
868 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
869 u_int32_t iobase, membase, irq;
870
871 /* Save important PCI config data. */
872 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
873 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
874 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
875
876 /* Reset the power state. */
877 device_printf(dev, "chip is in D%d power mode "
878 "-- setting to D0\n", pci_get_powerstate(dev));
879 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
880
881 /* Restore PCI config data. */
882 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
883 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
884 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
984263bc
MD
885 }
886
887 /*
888 * Map control/status registers.
889 */
38d17198 890 pci_enable_busmaster(dev);
984263bc
MD
891
892 rid = STE_RID;
4e6d744d 893 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
984263bc
MD
894
895 if (sc->ste_res == NULL) {
98b2fe08 896 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
897 error = ENXIO;
898 goto fail;
899 }
900
901 sc->ste_btag = rman_get_bustag(sc->ste_res);
902 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
903
904 rid = 0;
4e6d744d 905 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
906 RF_SHAREABLE | RF_ACTIVE);
907
908 if (sc->ste_irq == NULL) {
98b2fe08 909 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
910 error = ENXIO;
911 goto fail;
912 }
913
5abe9a2d 914 callout_init(&sc->ste_stat_timer);
984263bc 915
98b2fe08
JS
916 ifp = &sc->arpcom.ac_if;
917 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
918
984263bc
MD
919 /* Reset the adapter. */
920 ste_reset(sc);
921
922 /*
923 * Get station address from the EEPROM.
924 */
aff62688 925 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) {
98b2fe08 926 device_printf(dev, "failed to read station address\n");
aff62688 927 error = ENXIO;
984263bc
MD
928 goto fail;
929 }
930
984263bc
MD
931 /* Allocate the descriptor queues. */
932 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
35d0dcfc 933 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
934
935 if (sc->ste_ldata == NULL) {
98b2fe08 936 device_printf(dev, "no memory for list buffers!\n");
984263bc
MD
937 error = ENXIO;
938 goto fail;
939 }
940
941 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
942
943 /* Do MII setup. */
944 if (mii_phy_probe(dev, &sc->ste_miibus,
945 ste_ifmedia_upd, ste_ifmedia_sts)) {
98b2fe08 946 device_printf(dev, "MII without any phy!\n");
984263bc
MD
947 error = ENXIO;
948 goto fail;
949 }
950
984263bc 951 ifp->if_softc = sc;
984263bc
MD
952 ifp->if_mtu = ETHERMTU;
953 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
954 ifp->if_ioctl = ste_ioctl;
984263bc
MD
955 ifp->if_start = ste_start;
956 ifp->if_watchdog = ste_watchdog;
957 ifp->if_init = ste_init;
958 ifp->if_baudrate = 10000000;
2f2e6d88
JS
959 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1);
960 ifq_set_ready(&ifp->if_snd);
984263bc
MD
961
962 sc->ste_tx_thresh = STE_TXSTART_THRESH;
963
964 /*
965 * Call MI attach routine.
966 */
78195a76 967 ether_ifattach(ifp, eaddr, NULL);
984263bc
MD
968
969 /*
970 * Tell the upper layer(s) we support long frames.
971 */
972 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
973
78195a76
MD
974 error = bus_setup_intr(dev, sc->ste_irq, INTR_NETSAFE,
975 ste_intr, sc, &sc->ste_intrhand,
976 ifp->if_serializer);
2e89e2bd
JS
977 if (error) {
978 device_printf(dev, "couldn't set up irq\n");
979 ether_ifdetach(ifp);
980 goto fail;
981 }
982
983 return 0;
984
984263bc 985fail:
2e89e2bd 986 ste_detach(dev);
984263bc
MD
987 return(error);
988}
989
c436375a
SW
990static int
991ste_detach(device_t dev)
984263bc 992{
cdf89432
SZ
993 struct ste_softc *sc = device_get_softc(dev);
994 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 995
2e89e2bd 996 if (device_is_attached(dev)) {
cdf89432
SZ
997 lwkt_serialize_enter(ifp->if_serializer);
998 ste_stop(sc);
999 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1000 lwkt_serialize_exit(ifp->if_serializer);
1001
2e89e2bd
JS
1002 ether_ifdetach(ifp);
1003 }
1004 if (sc->ste_miibus != NULL)
1005 device_delete_child(dev, sc->ste_miibus);
984263bc 1006 bus_generic_detach(dev);
984263bc 1007
2e89e2bd
JS
1008 if (sc->ste_irq != NULL)
1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1010 if (sc->ste_res != NULL)
1011 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1012 if (sc->ste_ldata != NULL) {
1013 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1014 M_DEVBUF);
1015 }
1016
984263bc
MD
1017 return(0);
1018}
1019
c436375a
SW
1020static int
1021ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *c,
1022 struct mbuf *m)
984263bc
MD
1023{
1024 struct mbuf *m_new = NULL;
1025
1026 if (m == NULL) {
74f1caca 1027 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1028 if (m_new == NULL)
1029 return(ENOBUFS);
74f1caca 1030 MCLGET(m_new, MB_DONTWAIT);
984263bc
MD
1031 if (!(m_new->m_flags & M_EXT)) {
1032 m_freem(m_new);
1033 return(ENOBUFS);
1034 }
1035 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1036 } else {
1037 m_new = m;
1038 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1039 m_new->m_data = m_new->m_ext.ext_buf;
1040 }
1041
1042 m_adj(m_new, ETHER_ALIGN);
1043
1044 c->ste_mbuf = m_new;
1045 c->ste_ptr->ste_status = 0;
1046 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1047 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
1048
1049 return(0);
1050}
1051
c436375a
SW
1052static int
1053ste_init_rx_list(struct ste_softc *sc)
984263bc
MD
1054{
1055 struct ste_chain_data *cd;
1056 struct ste_list_data *ld;
1057 int i;
1058
1059 cd = &sc->ste_cdata;
1060 ld = sc->ste_ldata;
1061
1062 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1063 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1064 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1065 return(ENOBUFS);
1066 if (i == (STE_RX_LIST_CNT - 1)) {
1067 cd->ste_rx_chain[i].ste_next =
1068 &cd->ste_rx_chain[0];
1069 ld->ste_rx_list[i].ste_next =
1070 vtophys(&ld->ste_rx_list[0]);
1071 } else {
1072 cd->ste_rx_chain[i].ste_next =
1073 &cd->ste_rx_chain[i + 1];
1074 ld->ste_rx_list[i].ste_next =
1075 vtophys(&ld->ste_rx_list[i + 1]);
1076 }
1077 ld->ste_rx_list[i].ste_status = 0;
1078 }
1079
1080 cd->ste_rx_head = &cd->ste_rx_chain[0];
1081
1082 return(0);
1083}
1084
c436375a
SW
1085static void
1086ste_init_tx_list(struct ste_softc *sc)
984263bc
MD
1087{
1088 struct ste_chain_data *cd;
1089 struct ste_list_data *ld;
1090 int i;
1091
1092 cd = &sc->ste_cdata;
1093 ld = sc->ste_ldata;
1094 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1095 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1096 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1097 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1098 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1099 if (i == (STE_TX_LIST_CNT - 1))
1100 cd->ste_tx_chain[i].ste_next =
1101 &cd->ste_tx_chain[0];
1102 else
1103 cd->ste_tx_chain[i].ste_next =
1104 &cd->ste_tx_chain[i + 1];
1105 if (i == 0)
1106 cd->ste_tx_chain[i].ste_prev =
1107 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1108 else
1109 cd->ste_tx_chain[i].ste_prev =
1110 &cd->ste_tx_chain[i - 1];
1111 }
1112
1113 cd->ste_tx_prod = 0;
1114 cd->ste_tx_cons = 0;
1115 cd->ste_tx_cnt = 0;
1116
1117 return;
1118}
1119
c436375a
SW
1120static void
1121ste_init(void *xsc)
984263bc
MD
1122{
1123 struct ste_softc *sc;
9228feed 1124 int i;
984263bc
MD
1125 struct ifnet *ifp;
1126 struct mii_data *mii;
1127
984263bc
MD
1128 sc = xsc;
1129 ifp = &sc->arpcom.ac_if;
1130 mii = device_get_softc(sc->ste_miibus);
1131
1132 ste_stop(sc);
1133
1134 /* Init our MAC address */
1135 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1136 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1137 }
1138
1139 /* Init RX list */
1140 if (ste_init_rx_list(sc) == ENOBUFS) {
98b2fe08
JS
1141 if_printf(ifp, "initialization failed: no "
1142 "memory for RX buffers\n");
984263bc 1143 ste_stop(sc);
984263bc
MD
1144 return;
1145 }
1146
1147 /* Set RX polling interval */
1148 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
1149
1150 /* Init TX descriptors */
1151 ste_init_tx_list(sc);
1152
1153 /* Set the TX freethresh value */
1154 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1155
1156 /* Set the TX start threshold for best performance. */
1157 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1158
1159 /* Set the TX reclaim threshold. */
1160 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1161
1162 /* Set up the RX filter. */
1163 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1164
1165 /* If we want promiscuous mode, set the allframes bit. */
1166 if (ifp->if_flags & IFF_PROMISC) {
1167 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1168 } else {
1169 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1170 }
1171
1172 /* Set capture broadcast bit to accept broadcast frames. */
1173 if (ifp->if_flags & IFF_BROADCAST) {
1174 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1175 } else {
1176 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1177 }
1178
1179 ste_setmulti(sc);
1180
1181 /* Load the address of the RX list. */
1182 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1183 ste_wait(sc);
1184 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1185 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1186 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1187 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1188
1189 /* Set TX polling interval (defer until we TX first packet */
1190 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1191
1192 /* Load address of the TX list */
1193 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1194 ste_wait(sc);
1195 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1196 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1197 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1198 ste_wait(sc);
1199 sc->ste_tx_prev_idx=-1;
1200
1201 /* Enable receiver and transmitter */
1202 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1203 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1204 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1205 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1206
1207 /* Enable stats counters. */
1208 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1209
1210 /* Enable interrupts. */
1211 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1212 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1213
1214 /* Accept VLAN length packets */
1215 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
1216
1217 ste_ifmedia_upd(ifp);
1218
1219 ifp->if_flags |= IFF_RUNNING;
1220 ifp->if_flags &= ~IFF_OACTIVE;
1221
5abe9a2d 1222 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
984263bc
MD
1223}
1224
c436375a
SW
1225static void
1226ste_stop(struct ste_softc *sc)
984263bc
MD
1227{
1228 int i;
1229 struct ifnet *ifp;
1230
1231 ifp = &sc->arpcom.ac_if;
1232
5abe9a2d 1233 callout_stop(&sc->ste_stat_timer);
984263bc
MD
1234
1235 CSR_WRITE_2(sc, STE_IMR, 0);
1236 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1237 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1238 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1239 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1240 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1241 ste_wait(sc);
1242 /*
1243 * Try really hard to stop the RX engine or under heavy RX
1244 * data chip will write into de-allocated memory.
1245 */
1246 ste_reset(sc);
1247
1248 sc->ste_link = 0;
1249
1250 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1251 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1252 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1253 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1254 }
1255 }
1256
1257 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1258 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1259 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1260 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1261 }
1262 }
1263
1264 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1265
1266 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1267
1268 return;
1269}
1270
c436375a
SW
1271static void
1272ste_reset(struct ste_softc *sc)
984263bc
MD
1273{
1274 int i;
1275
1276 STE_SETBIT4(sc, STE_ASICCTL,
1277 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1278 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1279 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1280 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1281 STE_ASICCTL_EXTRESET_RESET);
1282
1283 DELAY(100000);
1284
1285 for (i = 0; i < STE_TIMEOUT; i++) {
1286 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1287 break;
1288 }
1289
1290 if (i == STE_TIMEOUT)
98b2fe08 1291 if_printf(&sc->arpcom.ac_if, "global reset never completed\n");
984263bc
MD
1292
1293 return;
1294}
1295
c436375a
SW
1296static int
1297ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
1298{
1299 struct ste_softc *sc;
1300 struct ifreq *ifr;
1301 struct mii_data *mii;
9228feed 1302 int error = 0;
984263bc 1303
984263bc
MD
1304 sc = ifp->if_softc;
1305 ifr = (struct ifreq *)data;
1306
1307 switch(command) {
984263bc
MD
1308 case SIOCSIFFLAGS:
1309 if (ifp->if_flags & IFF_UP) {
1310 if (ifp->if_flags & IFF_RUNNING &&
1311 ifp->if_flags & IFF_PROMISC &&
1312 !(sc->ste_if_flags & IFF_PROMISC)) {
1313 STE_SETBIT1(sc, STE_RX_MODE,
1314 STE_RXMODE_PROMISC);
1315 } else if (ifp->if_flags & IFF_RUNNING &&
1316 !(ifp->if_flags & IFF_PROMISC) &&
1317 sc->ste_if_flags & IFF_PROMISC) {
1318 STE_CLRBIT1(sc, STE_RX_MODE,
1319 STE_RXMODE_PROMISC);
1320 }
1321 if (!(ifp->if_flags & IFF_RUNNING)) {
1322 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1323 ste_init(sc);
1324 }
1325 } else {
1326 if (ifp->if_flags & IFF_RUNNING)
1327 ste_stop(sc);
1328 }
1329 sc->ste_if_flags = ifp->if_flags;
1330 error = 0;
1331 break;
1332 case SIOCADDMULTI:
1333 case SIOCDELMULTI:
1334 ste_setmulti(sc);
1335 error = 0;
1336 break;
1337 case SIOCGIFMEDIA:
1338 case SIOCSIFMEDIA:
1339 mii = device_get_softc(sc->ste_miibus);
1340 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1341 break;
1342 default:
4cde4dd5 1343 error = ether_ioctl(ifp, command, data);
984263bc
MD
1344 break;
1345 }
984263bc
MD
1346 return(error);
1347}
1348
c436375a
SW
1349static int
1350ste_encap(struct ste_softc *sc, struct ste_chain *c, struct mbuf *m_head)
984263bc
MD
1351{
1352 int frag = 0;
1353 struct ste_frag *f = NULL;
1354 struct mbuf *m;
1355 struct ste_desc *d;
1356 int total_len = 0;
1357
1358 d = c->ste_ptr;
1359 d->ste_ctl = 0;
1360
1361encap_retry:
1362 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1363 if (m->m_len != 0) {
1364 if (frag == STE_MAXFRAGS)
1365 break;
1366 total_len += m->m_len;
1367 f = &d->ste_frags[frag];
1368 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1369 f->ste_len = m->m_len;
1370 frag++;
1371 }
1372 }
1373
1374 if (m != NULL) {
1375 struct mbuf *mn;
1376
1377 /*
1378 * We ran out of segments. We have to recopy this
1379 * mbuf chain first. Bail out if we can't get the
1380 * new buffers. Code borrowed from if_fxp.c.
1381 */
74f1caca 1382 MGETHDR(mn, MB_DONTWAIT, MT_DATA);
984263bc
MD
1383 if (mn == NULL) {
1384 m_freem(m_head);
1385 return ENOMEM;
1386 }
1387 if (m_head->m_pkthdr.len > MHLEN) {
74f1caca 1388 MCLGET(mn, MB_DONTWAIT);
984263bc
MD
1389 if ((mn->m_flags & M_EXT) == 0) {
1390 m_freem(mn);
1391 m_freem(m_head);
1392 return ENOMEM;
1393 }
1394 }
1395 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1396 mtod(mn, caddr_t));
1397 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len;
1398 m_freem(m_head);
1399 m_head = mn;
1400 goto encap_retry;
1401 }
1402
1403 c->ste_mbuf = m_head;
1404 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1405 d->ste_ctl = 1;
1406
1407 return(0);
1408}
1409
c436375a
SW
1410static void
1411ste_start(struct ifnet *ifp)
984263bc
MD
1412{
1413 struct ste_softc *sc;
1414 struct mbuf *m_head = NULL;
1415 struct ste_chain *cur_tx = NULL;
1416 int idx;
1417
1418 sc = ifp->if_softc;
1419
1420 if (!sc->ste_link)
1421 return;
1422
1423 if (ifp->if_flags & IFF_OACTIVE)
1424 return;
1425
1426 idx = sc->ste_cdata.ste_tx_prod;
1427
1428 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1429
1430 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1431 ifp->if_flags |= IFF_OACTIVE;
1432 break;
1433 }
1434
d2c71fa0 1435 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1436 if (m_head == NULL)
1437 break;
1438
1439 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1440
1441 if (ste_encap(sc, cur_tx, m_head) != 0)
1442 break;
1443
1444 cur_tx->ste_ptr->ste_next = 0;
1445
1446 if(sc->ste_tx_prev_idx < 0){
1447 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1448 /* Load address of the TX list */
1449 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1450 ste_wait(sc);
1451
1452 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1453 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1454
1455 /* Set TX polling interval to start TX engine */
1456 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1457
1458 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1459 ste_wait(sc);
1460 }else{
1461 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1462 sc->ste_cdata.ste_tx_chain[
1463 sc->ste_tx_prev_idx].ste_ptr->ste_next
1464 = cur_tx->ste_phys;
1465 }
1466
1467 sc->ste_tx_prev_idx=idx;
1468
7600679e 1469 BPF_MTAP(ifp, cur_tx->ste_mbuf);
984263bc
MD
1470
1471 STE_INC(idx, STE_TX_LIST_CNT);
1472 sc->ste_cdata.ste_tx_cnt++;
1473 ifp->if_timer = 5;
1474 sc->ste_cdata.ste_tx_prod = idx;
1475 }
1476
1477 return;
1478}
1479
c436375a
SW
1480static void
1481ste_watchdog(struct ifnet *ifp)
984263bc
MD
1482{
1483 struct ste_softc *sc;
1484
1485 sc = ifp->if_softc;
1486
1487 ifp->if_oerrors++;
98b2fe08 1488 if_printf(ifp, "watchdog timeout\n");
984263bc
MD
1489
1490 ste_txeoc(sc);
1491 ste_txeof(sc);
1492 ste_rxeof(sc);
1493 ste_reset(sc);
1494 ste_init(sc);
1495
2f2e6d88 1496 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1497 ste_start(ifp);
1498
1499 return;
1500}
1501
c436375a
SW
1502static void
1503ste_shutdown(device_t dev)
984263bc
MD
1504{
1505 struct ste_softc *sc;
1506
1507 sc = device_get_softc(dev);
1508
1509 ste_stop(sc);
1510
1511 return;
1512}