Announce MAC address in ether_ifattach, not in each NIC indepently.
[dragonfly.git] / sys / dev / netif / rl / if_rl.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
267caeeb 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.12 2004/07/02 17:42:18 joerg Exp $
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34 *
35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
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36 */
37
38/*
39 * RealTek 8129/8139 PCI NIC driver
40 *
41 * Supports several extremely cheap PCI 10/100 adapters based on
42 * the RealTek chipset. Datasheets can be obtained from
43 * www.realtek.com.tw.
44 *
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
48 */
49
50/*
51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
52 * probably the worst PCI ethernet controller ever made, with the possible
53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
54 * DMA, but it has a terrible interface that nullifies any performance
55 * gains that bus-master DMA usually offers.
56 *
57 * For transmission, the chip offers a series of four TX descriptor
58 * registers. Each transmit frame must be in a contiguous buffer, aligned
59 * on a longword (32-bit) boundary. This means we almost always have to
60 * do mbuf copies in order to transmit a frame, except in the unlikely
61 * case where a) the packet fits into a single mbuf, and b) the packet
62 * is 32-bit aligned within the mbuf's data area. The presence of only
63 * four descriptor registers means that we can never have more than four
64 * packets queued for transmission at any one time.
65 *
66 * Reception is not much better. The driver has to allocate a single large
67 * buffer area (up to 64K in size) into which the chip will DMA received
68 * frames. Because we don't know where within this region received packets
69 * will begin or end, we have no choice but to copy data from the buffer
70 * area into mbufs in order to pass the packets up to the higher protocol
71 * levels.
72 *
73 * It's impossible given this rotten design to really achieve decent
74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
75 * some equally overmuscled CPU to drive it.
76 *
77 * On the bright side, the 8139 does have a built-in PHY, although
78 * rather than using an MDIO serial interface like most other NICs, the
79 * PHY registers are directly accessible through the 8139's register
80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
81 * filter.
82 *
83 * The 8129 chip is an older version of the 8139 that uses an external PHY
84 * chip. The 8129 has a serial MDIO interface for accessing the MII where
85 * the 8139 lets you directly access the on-board PHY registers. We need
86 * to select which interface to use depending on the chip type.
87 */
88
89#include <sys/param.h>
90#include <sys/systm.h>
91#include <sys/sockio.h>
92#include <sys/mbuf.h>
93#include <sys/malloc.h>
94#include <sys/kernel.h>
95#include <sys/socket.h>
96
97#include <net/if.h>
98#include <net/if_arp.h>
99#include <net/ethernet.h>
100#include <net/if_dl.h>
101#include <net/if_media.h>
102
103#include <net/bpf.h>
104
105#include <vm/vm.h> /* for vtophys */
106#include <vm/pmap.h> /* for vtophys */
107#include <machine/clock.h> /* for DELAY */
108#include <machine/bus_pio.h>
109#include <machine/bus_memio.h>
110#include <machine/bus.h>
111#include <machine/resource.h>
112#include <sys/bus.h>
113#include <sys/rman.h>
114
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115#include "../mii_layer/mii.h"
116#include "../mii_layer/miivar.h"
984263bc 117
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118#include <bus/pci/pcireg.h>
119#include <bus/pci/pcivar.h>
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120
121/* "controller miibus0" required. See GENERIC if you get errors here. */
122#include "miibus_if.h"
123
124/*
125 * Default to using PIO access for this driver. On SMP systems,
126 * there appear to be problems with memory mapped mode: it looks like
127 * doing too many memory mapped access back to back in rapid succession
128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
131 */
132#define RL_USEIOSPACE
133
1f2de5d4 134#include "if_rlreg.h"
984263bc 135
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136/*
137 * Various supported device vendors/types and their names.
138 */
139static struct rl_type rl_devs[] = {
140 { RT_VENDORID, RT_DEVICEID_8129,
141 "RealTek 8129 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8139,
143 "RealTek 8139 10/100BaseTX" },
144 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
145 "Accton MPX 5030/5038 10/100BaseTX" },
146 { DELTA_VENDORID, DELTA_DEVICEID_8139,
147 "Delta Electronics 8139 10/100BaseTX" },
148 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
149 "Addtron Technolgy 8139 10/100BaseTX" },
150 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
151 "D-Link DFE-530TX+ 10/100BaseTX" },
152 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
153 "Nortel Networks 10/100BaseTX" },
154 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
155 "Peppercon AG ROL/F" },
156 { 0, 0, NULL }
157};
158
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159static int rl_probe (device_t);
160static int rl_attach (device_t);
161static int rl_detach (device_t);
162
163static int rl_encap (struct rl_softc *, struct mbuf * );
164
165static void rl_rxeof (struct rl_softc *);
166static void rl_txeof (struct rl_softc *);
167static void rl_intr (void *);
168static void rl_tick (void *);
169static void rl_start (struct ifnet *);
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170static int rl_ioctl (struct ifnet *, u_long, caddr_t,
171 struct ucred *);
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172static void rl_init (void *);
173static void rl_stop (struct rl_softc *);
174static void rl_watchdog (struct ifnet *);
175static int rl_suspend (device_t);
176static int rl_resume (device_t);
177static void rl_shutdown (device_t);
178static int rl_ifmedia_upd (struct ifnet *);
179static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
180
181static void rl_eeprom_putbyte (struct rl_softc *, int);
182static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
183static void rl_read_eeprom (struct rl_softc *, caddr_t,
184 int, int, int);
185static void rl_mii_sync (struct rl_softc *);
186static void rl_mii_send (struct rl_softc *, u_int32_t, int);
187static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
188static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
189
190static int rl_miibus_readreg (device_t, int, int);
191static int rl_miibus_writereg (device_t, int, int, int);
192static void rl_miibus_statchg (device_t);
193
194static u_int8_t rl_calchash (caddr_t);
195static void rl_setmulti (struct rl_softc *);
196static void rl_reset (struct rl_softc *);
197static int rl_list_tx_init (struct rl_softc *);
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198
199#ifdef RL_USEIOSPACE
200#define RL_RES SYS_RES_IOPORT
201#define RL_RID RL_PCI_LOIO
202#else
203#define RL_RES SYS_RES_MEMORY
204#define RL_RID RL_PCI_LOMEM
205#endif
206
207static device_method_t rl_methods[] = {
208 /* Device interface */
209 DEVMETHOD(device_probe, rl_probe),
210 DEVMETHOD(device_attach, rl_attach),
211 DEVMETHOD(device_detach, rl_detach),
212 DEVMETHOD(device_suspend, rl_suspend),
213 DEVMETHOD(device_resume, rl_resume),
214 DEVMETHOD(device_shutdown, rl_shutdown),
215
216 /* bus interface */
217 DEVMETHOD(bus_print_child, bus_generic_print_child),
218 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
219
220 /* MII interface */
221 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
222 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
223 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
224
225 { 0, 0 }
226};
227
228static driver_t rl_driver = {
229 "rl",
230 rl_methods,
231 sizeof(struct rl_softc)
232};
233
234static devclass_t rl_devclass;
235
32832096 236DECLARE_DUMMY_MODULE(if_rl);
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237DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
238DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
239
240#define EE_SET(x) \
241 CSR_WRITE_1(sc, RL_EECMD, \
242 CSR_READ_1(sc, RL_EECMD) | x)
243
244#define EE_CLR(x) \
245 CSR_WRITE_1(sc, RL_EECMD, \
246 CSR_READ_1(sc, RL_EECMD) & ~x)
247
248/*
249 * Send a read command and address to the EEPROM, check for ACK.
250 */
251static void rl_eeprom_putbyte(sc, addr)
252 struct rl_softc *sc;
253 int addr;
254{
3d0f5f54 255 int d, i;
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256
257 d = addr | RL_EECMD_READ;
258
259 /*
260 * Feed in each bit and strobe the clock.
261 */
262 for (i = 0x400; i; i >>= 1) {
263 if (d & i) {
264 EE_SET(RL_EE_DATAIN);
265 } else {
266 EE_CLR(RL_EE_DATAIN);
267 }
268 DELAY(100);
269 EE_SET(RL_EE_CLK);
270 DELAY(150);
271 EE_CLR(RL_EE_CLK);
272 DELAY(100);
273 }
274
275 return;
276}
277
278/*
279 * Read a word of data stored in the EEPROM at address 'addr.'
280 */
281static void rl_eeprom_getword(sc, addr, dest)
282 struct rl_softc *sc;
283 int addr;
284 u_int16_t *dest;
285{
3d0f5f54 286 int i;
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287 u_int16_t word = 0;
288
289 /* Enter EEPROM access mode. */
290 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
291
292 /*
293 * Send address of word we want to read.
294 */
295 rl_eeprom_putbyte(sc, addr);
296
297 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
298
299 /*
300 * Start reading bits from EEPROM.
301 */
302 for (i = 0x8000; i; i >>= 1) {
303 EE_SET(RL_EE_CLK);
304 DELAY(100);
305 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
306 word |= i;
307 EE_CLR(RL_EE_CLK);
308 DELAY(100);
309 }
310
311 /* Turn off EEPROM access mode. */
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
313
314 *dest = word;
315
316 return;
317}
318
319/*
320 * Read a sequence of words from the EEPROM.
321 */
322static void rl_read_eeprom(sc, dest, off, cnt, swap)
323 struct rl_softc *sc;
324 caddr_t dest;
325 int off;
326 int cnt;
327 int swap;
328{
329 int i;
330 u_int16_t word = 0, *ptr;
331
332 for (i = 0; i < cnt; i++) {
333 rl_eeprom_getword(sc, off + i, &word);
334 ptr = (u_int16_t *)(dest + (i * 2));
335 if (swap)
336 *ptr = ntohs(word);
337 else
338 *ptr = word;
339 }
340
341 return;
342}
343
344
345/*
346 * MII access routines are provided for the 8129, which
347 * doesn't have a built-in PHY. For the 8139, we fake things
348 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
349 * direct access PHY registers.
350 */
351#define MII_SET(x) \
352 CSR_WRITE_1(sc, RL_MII, \
353 CSR_READ_1(sc, RL_MII) | x)
354
355#define MII_CLR(x) \
356 CSR_WRITE_1(sc, RL_MII, \
357 CSR_READ_1(sc, RL_MII) & ~x)
358
359/*
360 * Sync the PHYs by setting data bit and strobing the clock 32 times.
361 */
362static void rl_mii_sync(sc)
363 struct rl_softc *sc;
364{
3d0f5f54 365 int i;
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366
367 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
368
369 for (i = 0; i < 32; i++) {
370 MII_SET(RL_MII_CLK);
371 DELAY(1);
372 MII_CLR(RL_MII_CLK);
373 DELAY(1);
374 }
375
376 return;
377}
378
379/*
380 * Clock a series of bits through the MII.
381 */
382static void rl_mii_send(sc, bits, cnt)
383 struct rl_softc *sc;
384 u_int32_t bits;
385 int cnt;
386{
387 int i;
388
389 MII_CLR(RL_MII_CLK);
390
391 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
392 if (bits & i) {
393 MII_SET(RL_MII_DATAOUT);
394 } else {
395 MII_CLR(RL_MII_DATAOUT);
396 }
397 DELAY(1);
398 MII_CLR(RL_MII_CLK);
399 DELAY(1);
400 MII_SET(RL_MII_CLK);
401 }
402}
403
404/*
405 * Read an PHY register through the MII.
406 */
407static int rl_mii_readreg(sc, frame)
408 struct rl_softc *sc;
409 struct rl_mii_frame *frame;
410
411{
412 int i, ack, s;
413
414 s = splimp();
415
416 /*
417 * Set up frame for RX.
418 */
419 frame->mii_stdelim = RL_MII_STARTDELIM;
420 frame->mii_opcode = RL_MII_READOP;
421 frame->mii_turnaround = 0;
422 frame->mii_data = 0;
423
424 CSR_WRITE_2(sc, RL_MII, 0);
425
426 /*
427 * Turn on data xmit.
428 */
429 MII_SET(RL_MII_DIR);
430
431 rl_mii_sync(sc);
432
433 /*
434 * Send command/address info.
435 */
436 rl_mii_send(sc, frame->mii_stdelim, 2);
437 rl_mii_send(sc, frame->mii_opcode, 2);
438 rl_mii_send(sc, frame->mii_phyaddr, 5);
439 rl_mii_send(sc, frame->mii_regaddr, 5);
440
441 /* Idle bit */
442 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
443 DELAY(1);
444 MII_SET(RL_MII_CLK);
445 DELAY(1);
446
447 /* Turn off xmit. */
448 MII_CLR(RL_MII_DIR);
449
450 /* Check for ack */
451 MII_CLR(RL_MII_CLK);
452 DELAY(1);
453 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
454 MII_SET(RL_MII_CLK);
455 DELAY(1);
456
457 /*
458 * Now try reading data bits. If the ack failed, we still
459 * need to clock through 16 cycles to keep the PHY(s) in sync.
460 */
461 if (ack) {
462 for(i = 0; i < 16; i++) {
463 MII_CLR(RL_MII_CLK);
464 DELAY(1);
465 MII_SET(RL_MII_CLK);
466 DELAY(1);
467 }
468 goto fail;
469 }
470
471 for (i = 0x8000; i; i >>= 1) {
472 MII_CLR(RL_MII_CLK);
473 DELAY(1);
474 if (!ack) {
475 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
476 frame->mii_data |= i;
477 DELAY(1);
478 }
479 MII_SET(RL_MII_CLK);
480 DELAY(1);
481 }
482
483fail:
484
485 MII_CLR(RL_MII_CLK);
486 DELAY(1);
487 MII_SET(RL_MII_CLK);
488 DELAY(1);
489
490 splx(s);
491
492 if (ack)
493 return(1);
494 return(0);
495}
496
497/*
498 * Write to a PHY register through the MII.
499 */
500static int rl_mii_writereg(sc, frame)
501 struct rl_softc *sc;
502 struct rl_mii_frame *frame;
503
504{
505 int s;
506
507 s = splimp();
508 /*
509 * Set up frame for TX.
510 */
511
512 frame->mii_stdelim = RL_MII_STARTDELIM;
513 frame->mii_opcode = RL_MII_WRITEOP;
514 frame->mii_turnaround = RL_MII_TURNAROUND;
515
516 /*
517 * Turn on data output.
518 */
519 MII_SET(RL_MII_DIR);
520
521 rl_mii_sync(sc);
522
523 rl_mii_send(sc, frame->mii_stdelim, 2);
524 rl_mii_send(sc, frame->mii_opcode, 2);
525 rl_mii_send(sc, frame->mii_phyaddr, 5);
526 rl_mii_send(sc, frame->mii_regaddr, 5);
527 rl_mii_send(sc, frame->mii_turnaround, 2);
528 rl_mii_send(sc, frame->mii_data, 16);
529
530 /* Idle bit. */
531 MII_SET(RL_MII_CLK);
532 DELAY(1);
533 MII_CLR(RL_MII_CLK);
534 DELAY(1);
535
536 /*
537 * Turn off xmit.
538 */
539 MII_CLR(RL_MII_DIR);
540
541 splx(s);
542
543 return(0);
544}
545
546static int rl_miibus_readreg(dev, phy, reg)
547 device_t dev;
548 int phy, reg;
549{
550 struct rl_softc *sc;
551 struct rl_mii_frame frame;
552 u_int16_t rval = 0;
553 u_int16_t rl8139_reg = 0;
554
555 sc = device_get_softc(dev);
556
557 if (sc->rl_type == RL_8139) {
558 /* Pretend the internal PHY is only at address 0 */
559 if (phy)
560 return(0);
561 switch(reg) {
562 case MII_BMCR:
563 rl8139_reg = RL_BMCR;
564 break;
565 case MII_BMSR:
566 rl8139_reg = RL_BMSR;
567 break;
568 case MII_ANAR:
569 rl8139_reg = RL_ANAR;
570 break;
571 case MII_ANER:
572 rl8139_reg = RL_ANER;
573 break;
574 case MII_ANLPAR:
575 rl8139_reg = RL_LPAR;
576 break;
577 case MII_PHYIDR1:
578 case MII_PHYIDR2:
579 return(0);
580 break;
581 /*
582 * Allow the rlphy driver to read the media status
583 * register. If we have a link partner which does not
584 * support NWAY, this is the register which will tell
585 * us the results of parallel detection.
586 */
587 case RL_MEDIASTAT:
588 rval = CSR_READ_1(sc, RL_MEDIASTAT);
589 return(rval);
590 break;
591 default:
592 printf("rl%d: bad phy register\n", sc->rl_unit);
593 return(0);
594 }
595 rval = CSR_READ_2(sc, rl8139_reg);
596 return(rval);
597 }
598
599 bzero((char *)&frame, sizeof(frame));
600
601 frame.mii_phyaddr = phy;
602 frame.mii_regaddr = reg;
603 rl_mii_readreg(sc, &frame);
604
605 return(frame.mii_data);
606}
607
608static int rl_miibus_writereg(dev, phy, reg, data)
609 device_t dev;
610 int phy, reg, data;
611{
612 struct rl_softc *sc;
613 struct rl_mii_frame frame;
614 u_int16_t rl8139_reg = 0;
615
616 sc = device_get_softc(dev);
617
618 if (sc->rl_type == RL_8139) {
619 /* Pretend the internal PHY is only at address 0 */
620 if (phy)
621 return(0);
622 switch(reg) {
623 case MII_BMCR:
624 rl8139_reg = RL_BMCR;
625 break;
626 case MII_BMSR:
627 rl8139_reg = RL_BMSR;
628 break;
629 case MII_ANAR:
630 rl8139_reg = RL_ANAR;
631 break;
632 case MII_ANER:
633 rl8139_reg = RL_ANER;
634 break;
635 case MII_ANLPAR:
636 rl8139_reg = RL_LPAR;
637 break;
638 case MII_PHYIDR1:
639 case MII_PHYIDR2:
640 return(0);
641 break;
642 default:
643 printf("rl%d: bad phy register\n", sc->rl_unit);
644 return(0);
645 }
646 CSR_WRITE_2(sc, rl8139_reg, data);
647 return(0);
648 }
649
650 bzero((char *)&frame, sizeof(frame));
651
652 frame.mii_phyaddr = phy;
653 frame.mii_regaddr = reg;
654 frame.mii_data = data;
655
656 rl_mii_writereg(sc, &frame);
657
658 return(0);
659}
660
661static void rl_miibus_statchg(dev)
662 device_t dev;
663{
664 return;
665}
666
667/*
668 * Calculate CRC of a multicast group address, return the upper 6 bits.
669 */
670static u_int8_t rl_calchash(addr)
671 caddr_t addr;
672{
673 u_int32_t crc, carry;
674 int i, j;
675 u_int8_t c;
676
677 /* Compute CRC for the address value. */
678 crc = 0xFFFFFFFF; /* initial value */
679
680 for (i = 0; i < 6; i++) {
681 c = *(addr + i);
682 for (j = 0; j < 8; j++) {
683 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
684 crc <<= 1;
685 c >>= 1;
686 if (carry)
687 crc = (crc ^ 0x04c11db6) | carry;
688 }
689 }
690
691 /* return the filter bit position */
692 return(crc >> 26);
693}
694
695/*
696 * Program the 64-bit multicast hash filter.
697 */
698static void rl_setmulti(sc)
699 struct rl_softc *sc;
700{
701 struct ifnet *ifp;
702 int h = 0;
703 u_int32_t hashes[2] = { 0, 0 };
704 struct ifmultiaddr *ifma;
705 u_int32_t rxfilt;
706 int mcnt = 0;
707
708 ifp = &sc->arpcom.ac_if;
709
710 rxfilt = CSR_READ_4(sc, RL_RXCFG);
711
712 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
713 rxfilt |= RL_RXCFG_RX_MULTI;
714 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
715 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
716 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
717 return;
718 }
719
720 /* first, zot all the existing hash bits */
721 CSR_WRITE_4(sc, RL_MAR0, 0);
722 CSR_WRITE_4(sc, RL_MAR4, 0);
723
724 /* now program new ones */
725 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
726 ifma = ifma->ifma_link.le_next) {
727 if (ifma->ifma_addr->sa_family != AF_LINK)
728 continue;
729 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
730 if (h < 32)
731 hashes[0] |= (1 << h);
732 else
733 hashes[1] |= (1 << (h - 32));
734 mcnt++;
735 }
736
737 if (mcnt)
738 rxfilt |= RL_RXCFG_RX_MULTI;
739 else
740 rxfilt &= ~RL_RXCFG_RX_MULTI;
741
742 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
743 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
744 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
745
746 return;
747}
748
749static void rl_reset(sc)
750 struct rl_softc *sc;
751{
3d0f5f54 752 int i;
984263bc
MD
753
754 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
755
756 for (i = 0; i < RL_TIMEOUT; i++) {
757 DELAY(10);
758 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
759 break;
760 }
761 if (i == RL_TIMEOUT)
762 printf("rl%d: reset never completed!\n", sc->rl_unit);
763
764 return;
765}
766
767/*
768 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
769 * IDs against our list and return a device name if we find a match.
770 */
771static int rl_probe(dev)
772 device_t dev;
773{
774 struct rl_type *t;
775
776 t = rl_devs;
777
778 while(t->rl_name != NULL) {
779 if ((pci_get_vendor(dev) == t->rl_vid) &&
780 (pci_get_device(dev) == t->rl_did)) {
781 device_set_desc(dev, t->rl_name);
782 return(0);
783 }
784 t++;
785 }
786
787 return(ENXIO);
788}
789
790/*
791 * Attach the interface. Allocate softc structures, do ifmedia
792 * setup and ethernet/BPF attach.
793 */
794static int rl_attach(dev)
795 device_t dev;
796{
797 int s;
798 u_char eaddr[ETHER_ADDR_LEN];
799 u_int32_t command;
800 struct rl_softc *sc;
801 struct ifnet *ifp;
802 u_int16_t rl_did = 0;
803 int unit, error = 0, rid;
804
805 s = splimp();
806
807 sc = device_get_softc(dev);
808 unit = device_get_unit(dev);
809 bzero(sc, sizeof(struct rl_softc));
810
811 /*
812 * Handle power management nonsense.
813 */
814
815 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF;
816 if (command == 0x01) {
817
818 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4);
819 if (command & RL_PSTATE_MASK) {
820 u_int32_t iobase, membase, irq;
821
822 /* Save important PCI config data. */
823 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
824 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
825 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
826
827 /* Reset the power state. */
828 printf("rl%d: chip is is in D%d power mode "
829 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
830 command &= 0xFFFFFFFC;
831 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4);
832
833 /* Restore PCI config data. */
834 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
835 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
836 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
837 }
838 }
839
840 /*
841 * Map control/status registers.
842 */
843 command = pci_read_config(dev, PCIR_COMMAND, 4);
844 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
845 pci_write_config(dev, PCIR_COMMAND, command, 4);
846 command = pci_read_config(dev, PCIR_COMMAND, 4);
847
848#ifdef RL_USEIOSPACE
849 if (!(command & PCIM_CMD_PORTEN)) {
850 printf("rl%d: failed to enable I/O ports!\n", unit);
851 error = ENXIO;
852 goto fail;
853 }
854#else
855 if (!(command & PCIM_CMD_MEMEN)) {
856 printf("rl%d: failed to enable memory mapping!\n", unit);
857 error = ENXIO;
858 goto fail;
859 }
860#endif
861
862 rid = RL_RID;
863 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
864 0, ~0, 1, RF_ACTIVE);
865
866 if (sc->rl_res == NULL) {
867 printf ("rl%d: couldn't map ports/memory\n", unit);
868 error = ENXIO;
869 goto fail;
870 }
871
872 sc->rl_btag = rman_get_bustag(sc->rl_res);
873 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
874
875 rid = 0;
876 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
877 RF_SHAREABLE | RF_ACTIVE);
878
879 if (sc->rl_irq == NULL) {
880 printf("rl%d: couldn't map interrupt\n", unit);
881 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
882 error = ENXIO;
883 goto fail;
884 }
885
886 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
887 rl_intr, sc, &sc->rl_intrhand);
888
889 if (error) {
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
891 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
892 printf("rl%d: couldn't set up irq\n", unit);
893 goto fail;
894 }
895
896 callout_handle_init(&sc->rl_stat_ch);
897
898 /* Reset the adapter. */
899 rl_reset(sc);
900
901 /*
902 * Get station address from the EEPROM.
903 */
904 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
905
984263bc 906 sc->rl_unit = unit;
984263bc
MD
907
908 /*
909 * Now read the exact device type from the EEPROM to find
910 * out if it's an 8129 or 8139.
911 */
912 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
913
914 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
915 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
916 rl_did == DLINK_DEVICEID_530TXPLUS)
917 sc->rl_type = RL_8139;
918 else if (rl_did == RT_DEVICEID_8129)
919 sc->rl_type = RL_8129;
920 else {
921 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
922 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
923 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
924 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
925 error = ENXIO;
926 goto fail;
927 }
928
929 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF,
930 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
931
932 if (sc->rl_cdata.rl_rx_buf == NULL) {
933 printf("rl%d: no memory for list buffers!\n", unit);
934 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
936 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
937 error = ENXIO;
938 goto fail;
939 }
940
941 /* Leave a few bytes before the start of the RX ring buffer. */
942 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
943 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
944
945 /* Do MII setup */
946 if (mii_phy_probe(dev, &sc->rl_miibus,
947 rl_ifmedia_upd, rl_ifmedia_sts)) {
948 printf("rl%d: MII without any phy!\n", sc->rl_unit);
949 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518,
950 M_DEVBUF);
951 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
952 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
953 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
954 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF);
955 error = ENXIO;
956 goto fail;
957 }
958
959 ifp = &sc->arpcom.ac_if;
960 ifp->if_softc = sc;
cdb7d804 961 if_initname(ifp, "rl", unit);
984263bc
MD
962 ifp->if_mtu = ETHERMTU;
963 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
964 ifp->if_ioctl = rl_ioctl;
965 ifp->if_output = ether_output;
966 ifp->if_start = rl_start;
967 ifp->if_watchdog = rl_watchdog;
968 ifp->if_init = rl_init;
969 ifp->if_baudrate = 10000000;
970 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
971
972 /*
973 * Call MI attach routine.
974 */
0a8b5977 975 ether_ifattach(ifp, eaddr);
984263bc
MD
976
977fail:
978 splx(s);
979 return(error);
980}
981
982static int rl_detach(dev)
983 device_t dev;
984{
985 struct rl_softc *sc;
986 struct ifnet *ifp;
987 int s;
988
989 s = splimp();
990
991 sc = device_get_softc(dev);
992 ifp = &sc->arpcom.ac_if;
993
0a8b5977 994 ether_ifdetach(ifp);
984263bc
MD
995 rl_stop(sc);
996
997 bus_generic_detach(dev);
998 device_delete_child(dev, sc->rl_miibus);
999
1000 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1002 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1003
1004 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, M_DEVBUF);
1005
1006 splx(s);
1007
1008 return(0);
1009}
1010
1011/*
1012 * Initialize the transmit descriptors.
1013 */
1014static int rl_list_tx_init(sc)
1015 struct rl_softc *sc;
1016{
1017 struct rl_chain_data *cd;
1018 int i;
1019
1020 cd = &sc->rl_cdata;
1021 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1022 cd->rl_tx_chain[i] = NULL;
1023 CSR_WRITE_4(sc,
1024 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1025 }
1026
1027 sc->rl_cdata.cur_tx = 0;
1028 sc->rl_cdata.last_tx = 0;
1029
1030 return(0);
1031}
1032
1033/*
1034 * A frame has been uploaded: pass the resulting mbuf chain up to
1035 * the higher level protocols.
1036 *
1037 * You know there's something wrong with a PCI bus-master chip design
1038 * when you have to use m_devget().
1039 *
1040 * The receive operation is badly documented in the datasheet, so I'll
1041 * attempt to document it here. The driver provides a buffer area and
1042 * places its base address in the RX buffer start address register.
1043 * The chip then begins copying frames into the RX buffer. Each frame
1044 * is preceeded by a 32-bit RX status word which specifies the length
1045 * of the frame and certain other status bits. Each frame (starting with
1046 * the status word) is also 32-bit aligned. The frame length is in the
1047 * first 16 bits of the status word; the lower 15 bits correspond with
1048 * the 'rx status register' mentioned in the datasheet.
1049 *
1050 * Note: to make the Alpha happy, the frame payload needs to be aligned
1051 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1052 * the ring buffer starting at an address two bytes before the actual
1053 * data location. We can then shave off the first two bytes using m_adj().
1054 * The reason we do this is because m_devget() doesn't let us specify an
1055 * offset into the mbuf storage space, so we have to artificially create
1056 * one. The ring is allocated in such a way that there are a few unused
1057 * bytes of space preceecing it so that it will be safe for us to do the
1058 * 2-byte backstep even if reading from the ring at offset 0.
1059 */
1060static void rl_rxeof(sc)
1061 struct rl_softc *sc;
1062{
1063 struct ether_header *eh;
1064 struct mbuf *m;
1065 struct ifnet *ifp;
1066 int total_len = 0;
1067 u_int32_t rxstat;
1068 caddr_t rxbufpos;
1069 int wrap = 0;
1070 u_int16_t cur_rx;
1071 u_int16_t limit;
1072 u_int16_t rx_bytes = 0, max_bytes;
1073
1074 ifp = &sc->arpcom.ac_if;
1075
1076 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1077
1078 /* Do not try to read past this point. */
1079 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1080
1081 if (limit < cur_rx)
1082 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1083 else
1084 max_bytes = limit - cur_rx;
1085
1086 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1087#ifdef DEVICE_POLLING
46f25451 1088 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1089 if (sc->rxcycles <= 0)
1090 break;
1091 sc->rxcycles--;
1092 }
1093#endif /* DEVICE_POLLING */
1094 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1095 rxstat = *(u_int32_t *)rxbufpos;
1096
1097 /*
1098 * Here's a totally undocumented fact for you. When the
1099 * RealTek chip is in the process of copying a packet into
1100 * RAM for you, the length will be 0xfff0. If you spot a
1101 * packet header with this value, you need to stop. The
1102 * datasheet makes absolutely no mention of this and
1103 * RealTek should be shot for this.
1104 */
1105 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1106 break;
1107
1108 if (!(rxstat & RL_RXSTAT_RXOK)) {
1109 ifp->if_ierrors++;
1110 rl_init(sc);
1111 return;
1112 }
1113
1114 /* No errors; receive the packet. */
1115 total_len = rxstat >> 16;
1116 rx_bytes += total_len + 4;
1117
1118 /*
1119 * XXX The RealTek chip includes the CRC with every
1120 * received frame, and there's no way to turn this
1121 * behavior off (at least, I can't find anything in
1122 * the manual that explains how to do it) so we have
1123 * to trim off the CRC manually.
1124 */
1125 total_len -= ETHER_CRC_LEN;
1126
1127 /*
1128 * Avoid trying to read more bytes than we know
1129 * the chip has prepared for us.
1130 */
1131 if (rx_bytes > max_bytes)
1132 break;
1133
1134 rxbufpos = sc->rl_cdata.rl_rx_buf +
1135 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1136
1137 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1138 rxbufpos = sc->rl_cdata.rl_rx_buf;
1139
1140 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1141
1142 if (total_len > wrap) {
1143 /*
1144 * Fool m_devget() into thinking we want to copy
1145 * the whole buffer so we don't end up fragmenting
1146 * the data.
1147 */
1148 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1149 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1150 if (m == NULL) {
1151 ifp->if_ierrors++;
1152 } else {
1153 m_adj(m, RL_ETHER_ALIGN);
1154 m_copyback(m, wrap, total_len - wrap,
1155 sc->rl_cdata.rl_rx_buf);
1156 }
1157 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1158 } else {
1159 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1160 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1161 if (m == NULL) {
1162 ifp->if_ierrors++;
1163 } else
1164 m_adj(m, RL_ETHER_ALIGN);
1165 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1166 }
1167
1168 /*
1169 * Round up to 32-bit boundary.
1170 */
1171 cur_rx = (cur_rx + 3) & ~3;
1172 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1173
1174 if (m == NULL)
1175 continue;
1176
1177 eh = mtod(m, struct ether_header *);
1178 ifp->if_ipackets++;
1179
1180 /* Remove header from mbuf and pass it on. */
1181 m_adj(m, sizeof(struct ether_header));
1182 ether_input(ifp, eh, m);
1183 }
1184
1185 return;
1186}
1187
1188/*
1189 * A frame was downloaded to the chip. It's safe for us to clean up
1190 * the list buffers.
1191 */
1192static void rl_txeof(sc)
1193 struct rl_softc *sc;
1194{
1195 struct ifnet *ifp;
1196 u_int32_t txstat;
1197
1198 ifp = &sc->arpcom.ac_if;
1199
1200 /*
1201 * Go through our tx list and free mbufs for those
1202 * frames that have been uploaded.
1203 */
1204 do {
1205 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1206 if (!(txstat & (RL_TXSTAT_TX_OK|
1207 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1208 break;
1209
1210 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1211
1212 if (RL_LAST_TXMBUF(sc) != NULL) {
1213 m_freem(RL_LAST_TXMBUF(sc));
1214 RL_LAST_TXMBUF(sc) = NULL;
1215 }
1216 if (txstat & RL_TXSTAT_TX_OK)
1217 ifp->if_opackets++;
1218 else {
1219 int oldthresh;
1220 ifp->if_oerrors++;
1221 if ((txstat & RL_TXSTAT_TXABRT) ||
1222 (txstat & RL_TXSTAT_OUTOFWIN))
1223 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1224 oldthresh = sc->rl_txthresh;
1225 /* error recovery */
1226 rl_reset(sc);
1227 rl_init(sc);
1228 /*
1229 * If there was a transmit underrun,
1230 * bump the TX threshold.
1231 */
1232 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1233 sc->rl_txthresh = oldthresh + 32;
1234 return;
1235 }
1236 RL_INC(sc->rl_cdata.last_tx);
1237 ifp->if_flags &= ~IFF_OACTIVE;
1238 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1239
1240 ifp->if_timer =
1241 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5;
1242
1243 return;
1244}
1245
1246static void rl_tick(xsc)
1247 void *xsc;
1248{
1249 struct rl_softc *sc;
1250 struct mii_data *mii;
1251 int s;
1252
1253 s = splimp();
1254
1255 sc = xsc;
1256 mii = device_get_softc(sc->rl_miibus);
1257
1258 mii_tick(mii);
1259
1260 splx(s);
1261
1262 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1263
1264 return;
1265}
1266
1267#ifdef DEVICE_POLLING
1268static poll_handler_t rl_poll;
1269
1270static void
1271rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1272{
1273 struct rl_softc *sc = ifp->if_softc;
1274
1275 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1276 CSR_WRITE_4(sc, RL_IMR, RL_INTRS);
1277 return;
1278 }
1279
1280 sc->rxcycles = count;
1281 rl_rxeof(sc);
1282 rl_txeof(sc);
1283 if (ifp->if_snd.ifq_head != NULL)
1284 rl_start(ifp);
1285
1286 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1287 u_int16_t status;
1288
1289 status = CSR_READ_2(sc, RL_ISR);
1290 if (status)
1291 CSR_WRITE_2(sc, RL_ISR, status);
1292
1293 /*
1294 * XXX check behaviour on receiver stalls.
1295 */
1296
1297 if (status & RL_ISR_SYSTEM_ERR) {
1298 rl_reset(sc);
1299 rl_init(sc);
1300 }
1301 }
1302}
1303#endif /* DEVICE_POLLING */
1304
1305static void rl_intr(arg)
1306 void *arg;
1307{
1308 struct rl_softc *sc;
1309 struct ifnet *ifp;
1310 u_int16_t status;
1311
1312 sc = arg;
1313
1314 if (sc->suspended) {
1315 return;
1316 }
1317
1318 ifp = &sc->arpcom.ac_if;
1319#ifdef DEVICE_POLLING
46f25451 1320 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
1321 return;
1322 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1323 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1324 rl_poll(ifp, 0, 1);
1325 return;
1326 }
1327#endif /* DEVICE_POLLING */
1328
1329 for (;;) {
1330
1331 status = CSR_READ_2(sc, RL_ISR);
1332 if (status)
1333 CSR_WRITE_2(sc, RL_ISR, status);
1334
1335 if ((status & RL_INTRS) == 0)
1336 break;
1337
1338 if (status & RL_ISR_RX_OK)
1339 rl_rxeof(sc);
1340
1341 if (status & RL_ISR_RX_ERR)
1342 rl_rxeof(sc);
1343
1344 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1345 rl_txeof(sc);
1346
1347 if (status & RL_ISR_SYSTEM_ERR) {
1348 rl_reset(sc);
1349 rl_init(sc);
1350 }
1351
1352 }
1353 if (ifp->if_snd.ifq_head != NULL)
1354 rl_start(ifp);
1355
1356 return;
1357}
1358
1359/*
1360 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1361 * pointers to the fragment pointers.
1362 */
1363static int rl_encap(sc, m_head)
1364 struct rl_softc *sc;
1365 struct mbuf *m_head;
1366{
1367 struct mbuf *m_new = NULL;
1368
1369 /*
1370 * The RealTek is brain damaged and wants longword-aligned
1371 * TX buffers, plus we can only have one fragment buffer
1372 * per packet. We have to copy pretty much all the time.
1373 */
1374
74f1caca 1375 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
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1376 if (m_new == NULL)
1377 return(1);
1378 if (m_head->m_pkthdr.len > MHLEN) {
74f1caca 1379 MCLGET(m_new, MB_DONTWAIT);
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1380 if (!(m_new->m_flags & M_EXT)) {
1381 m_freem(m_new);
1382 return(1);
1383 }
1384 }
1385 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1386 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1387 m_freem(m_head);
1388 m_head = m_new;
1389
1390 /* Pad frames to at least 60 bytes. */
1391 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1392 /*
1393 * Make security concious people happy: zero out the
1394 * bytes in the pad area, since we don't know what
1395 * this mbuf cluster buffer's previous user might
1396 * have left in it.
1397 */
1398 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1399 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1400 m_head->m_pkthdr.len +=
1401 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1402 m_head->m_len = m_head->m_pkthdr.len;
1403 }
1404
1405 RL_CUR_TXMBUF(sc) = m_head;
1406
1407 return(0);
1408}
1409
1410/*
1411 * Main transmit routine.
1412 */
1413
1414static void rl_start(ifp)
1415 struct ifnet *ifp;
1416{
1417 struct rl_softc *sc;
1418 struct mbuf *m_head = NULL;
1419
1420 sc = ifp->if_softc;
1421
1422 while(RL_CUR_TXMBUF(sc) == NULL) {
1423 IF_DEQUEUE(&ifp->if_snd, m_head);
1424 if (m_head == NULL)
1425 break;
1426
1427 if (rl_encap(sc, m_head)) {
1428 IF_PREPEND(&ifp->if_snd, m_head);
1429 ifp->if_flags |= IFF_OACTIVE;
1430 break;
1431 }
1432
1433 /*
1434 * If there's a BPF listener, bounce a copy of this frame
1435 * to him.
1436 */
1437 if (ifp->if_bpf)
1438 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1439
1440 /*
1441 * Transmit the frame.
1442 */
1443 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1444 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1445 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1446 RL_TXTHRESH(sc->rl_txthresh) |
1447 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1448
1449 RL_INC(sc->rl_cdata.cur_tx);
1450 }
1451
1452 /*
1453 * We broke out of the loop because all our TX slots are
1454 * full. Mark the NIC as busy until it drains some of the
1455 * packets from the queue.
1456 */
1457 if (RL_CUR_TXMBUF(sc) != NULL)
1458 ifp->if_flags |= IFF_OACTIVE;
1459
1460 /*
1461 * Set a timeout in case the chip goes out to lunch.
1462 */
1463 ifp->if_timer = 5;
1464
1465 return;
1466}
1467
1468static void rl_init(xsc)
1469 void *xsc;
1470{
1471 struct rl_softc *sc = xsc;
1472 struct ifnet *ifp = &sc->arpcom.ac_if;
1473 struct mii_data *mii;
1474 int s, i;
1475 u_int32_t rxcfg = 0;
1476
1477 s = splimp();
1478
1479 mii = device_get_softc(sc->rl_miibus);
1480
1481 /*
1482 * Cancel pending I/O and free all RX/TX buffers.
1483 */
1484 rl_stop(sc);
1485
1486 /* Init our MAC address */
1487 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1488 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1489 }
1490
1491 /* Init the RX buffer pointer register. */
1492 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1493
1494 /* Init TX descriptors. */
1495 rl_list_tx_init(sc);
1496
1497 /*
1498 * Enable transmit and receive.
1499 */
1500 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1501
1502 /*
1503 * Set the initial TX and RX configuration.
1504 */
1505 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1506 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1507
1508 /* Set the individual bit to receive frames for this host only. */
1509 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1510 rxcfg |= RL_RXCFG_RX_INDIV;
1511
1512 /* If we want promiscuous mode, set the allframes bit. */
1513 if (ifp->if_flags & IFF_PROMISC) {
1514 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1515 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1516 } else {
1517 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1518 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1519 }
1520
1521 /*
1522 * Set capture broadcast bit to capture broadcast frames.
1523 */
1524 if (ifp->if_flags & IFF_BROADCAST) {
1525 rxcfg |= RL_RXCFG_RX_BROAD;
1526 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1527 } else {
1528 rxcfg &= ~RL_RXCFG_RX_BROAD;
1529 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1530 }
1531
1532 /*
1533 * Program the multicast filter, if necessary.
1534 */
1535 rl_setmulti(sc);
1536
1537#ifdef DEVICE_POLLING
1538 /*
1539 * Only enable interrupts if we are polling, keep them off otherwise.
1540 */
46f25451 1541 if (ifp->if_flags & IFF_POLLING)
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1542 CSR_WRITE_2(sc, RL_IMR, 0);
1543 else
1544#endif /* DEVICE_POLLING */
1545 /*
1546 * Enable interrupts.
1547 */
1548 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1549
1550 /* Set initial TX threshold */
1551 sc->rl_txthresh = RL_TX_THRESH_INIT;
1552
1553 /* Start RX/TX process. */
1554 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1555
1556 /* Enable receiver and transmitter. */
1557 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1558
1559 mii_mediachg(mii);
1560
1561 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1562
1563 ifp->if_flags |= IFF_RUNNING;
1564 ifp->if_flags &= ~IFF_OACTIVE;
1565
1566 (void)splx(s);
1567
1568 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1569
1570 return;
1571}
1572
1573/*
1574 * Set media options.
1575 */
1576static int rl_ifmedia_upd(ifp)
1577 struct ifnet *ifp;
1578{
1579 struct rl_softc *sc;
1580 struct mii_data *mii;
1581
1582 sc = ifp->if_softc;
1583 mii = device_get_softc(sc->rl_miibus);
1584 mii_mediachg(mii);
1585
1586 return(0);
1587}
1588
1589/*
1590 * Report current media status.
1591 */
1592static void rl_ifmedia_sts(ifp, ifmr)
1593 struct ifnet *ifp;
1594 struct ifmediareq *ifmr;
1595{
1596 struct rl_softc *sc;
1597 struct mii_data *mii;
1598
1599 sc = ifp->if_softc;
1600 mii = device_get_softc(sc->rl_miibus);
1601
1602 mii_pollstat(mii);
1603 ifmr->ifm_active = mii->mii_media_active;
1604 ifmr->ifm_status = mii->mii_media_status;
1605
1606 return;
1607}
1608
bd4539cc 1609static int rl_ioctl(ifp, command, data, cr)
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1610 struct ifnet *ifp;
1611 u_long command;
1612 caddr_t data;
bd4539cc 1613 struct ucred *cr;
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1614{
1615 struct rl_softc *sc = ifp->if_softc;
1616 struct ifreq *ifr = (struct ifreq *) data;
1617 struct mii_data *mii;
1618 int s, error = 0;
1619
1620 s = splimp();
1621
1622 switch(command) {
1623 case SIOCSIFADDR:
1624 case SIOCGIFADDR:
1625 case SIOCSIFMTU:
1626 error = ether_ioctl(ifp, command, data);
1627 break;
1628 case SIOCSIFFLAGS:
1629 if (ifp->if_flags & IFF_UP) {
1630 rl_init(sc);
1631 } else {
1632 if (ifp->if_flags & IFF_RUNNING)
1633 rl_stop(sc);
1634 }
1635 error = 0;
1636 break;
1637 case SIOCADDMULTI:
1638 case SIOCDELMULTI:
1639 rl_setmulti(sc);
1640 error = 0;
1641 break;
1642 case SIOCGIFMEDIA:
1643 case SIOCSIFMEDIA:
1644 mii = device_get_softc(sc->rl_miibus);
1645 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1646 break;
1647 default:
1648 error = EINVAL;
1649 break;
1650 }
1651
1652 (void)splx(s);
1653
1654 return(error);
1655}
1656
1657static void rl_watchdog(ifp)
1658 struct ifnet *ifp;
1659{
1660 struct rl_softc *sc;
1661
1662 sc = ifp->if_softc;
1663
1664 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1665 ifp->if_oerrors++;
1666
1667 rl_txeof(sc);
1668 rl_rxeof(sc);
1669 rl_init(sc);
1670
1671 return;
1672}
1673
1674/*
1675 * Stop the adapter and free any mbufs allocated to the
1676 * RX and TX lists.
1677 */
1678static void rl_stop(sc)
1679 struct rl_softc *sc;
1680{
3d0f5f54 1681 int i;
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1682 struct ifnet *ifp;
1683
1684 ifp = &sc->arpcom.ac_if;
1685 ifp->if_timer = 0;
1686
1687 untimeout(rl_tick, sc, sc->rl_stat_ch);
1688 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1689#ifdef DEVICE_POLLING
1690 ether_poll_deregister(ifp);
1691#endif /* DEVICE_POLLING */
1692
1693 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1694 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1695
1696 /*
1697 * Free the TX list buffers.
1698 */
1699 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1700 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1701 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1702 sc->rl_cdata.rl_tx_chain[i] = NULL;
1703 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1704 }
1705 }
1706
1707
1708 return;
1709}
1710
1711/*
1712 * Stop all chip I/O so that the kernel's probe routines don't
1713 * get confused by errant DMAs when rebooting.
1714 */
1715static void rl_shutdown(dev)
1716 device_t dev;
1717{
1718 struct rl_softc *sc;
1719
1720 sc = device_get_softc(dev);
1721
1722 rl_stop(sc);
1723
1724 return;
1725}
1726
1727/*
1728 * Device suspend routine. Stop the interface and save some PCI
1729 * settings in case the BIOS doesn't restore them properly on
1730 * resume.
1731 */
1732static int rl_suspend(dev)
1733 device_t dev;
1734{
3d0f5f54 1735 int i;
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MD
1736 struct rl_softc *sc;
1737
1738 sc = device_get_softc(dev);
1739
1740 rl_stop(sc);
1741
1742 for (i = 0; i < 5; i++)
1743 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1744 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1745 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1746 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1747 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1748
1749 sc->suspended = 1;
1750
1751 return (0);
1752}
1753
1754/*
1755 * Device resume routine. Restore some PCI settings in case the BIOS
1756 * doesn't, re-enable busmastering, and restart the interface if
1757 * appropriate.
1758 */
1759static int rl_resume(dev)
1760 device_t dev;
1761{
3d0f5f54 1762 int i;
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MD
1763 struct rl_softc *sc;
1764 struct ifnet *ifp;
1765
1766 sc = device_get_softc(dev);
1767 ifp = &sc->arpcom.ac_if;
1768
1769 /* better way to do this? */
1770 for (i = 0; i < 5; i++)
1771 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1772 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1773 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1774 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1775 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1776
1777 /* reenable busmastering */
1778 pci_enable_busmaster(dev);
1779 pci_enable_io(dev, RL_RES);
1780
1781 /* reinitialize interface if necessary */
1782 if (ifp->if_flags & IFF_UP)
1783 rl_init(sc);
1784
1785 sc->suspended = 0;
1786
1787 return (0);
1788}