Announce MAC address in ether_ifattach, not in each NIC indepently.
[dragonfly.git] / sys / dev / netif / rl / if_rlreg.h
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14.2.5 2003/03/02 20:58:54 dan Exp $
1de703da 33 * $DragonFly: src/sys/dev/netif/rl/if_rlreg.h,v 1.2 2003/06/17 04:28:57 dillon Exp $
984263bc
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34 */
35
36/*
37 * RealTek 8129/8139 register offsets
38 */
39#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
40#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
41#define RL_IDR2 0x0002
42#define RL_IDR3 0x0003
43#define RL_IDR4 0x0004
44#define RL_IDR5 0x0005
45 /* 0006-0007 reserved */
46#define RL_MAR0 0x0008 /* Multicast hash table */
47#define RL_MAR1 0x0009
48#define RL_MAR2 0x000A
49#define RL_MAR3 0x000B
50#define RL_MAR4 0x000C
51#define RL_MAR5 0x000D
52#define RL_MAR6 0x000E
53#define RL_MAR7 0x000F
54
55#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
56#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
57#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
58#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
59
60#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
61#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
62#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
63#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
64
65#define RL_RXADDR 0x0030 /* RX ring start address */
66#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
67#define RL_RX_EARLY_STAT 0x0036 /* RX early status */
68#define RL_COMMAND 0x0037 /* command register */
69#define RL_CURRXADDR 0x0038 /* current address of packet read */
70#define RL_CURRXBUF 0x003A /* current RX buffer address */
71#define RL_IMR 0x003C /* interrupt mask register */
72#define RL_ISR 0x003E /* interrupt status register */
73#define RL_TXCFG 0x0040 /* transmit config */
74#define RL_RXCFG 0x0044 /* receive config */
75#define RL_TIMERCNT 0x0048 /* timer count register */
76#define RL_MISSEDPKT 0x004C /* missed packet counter */
77#define RL_EECMD 0x0050 /* EEPROM command register */
78#define RL_CFG0 0x0051 /* config register #0 */
79#define RL_CFG1 0x0052 /* config register #1 */
80 /* 0053-0057 reserved */
81#define RL_MEDIASTAT 0x0058 /* media status register (8139) */
82 /* 0059-005A reserved */
83#define RL_MII 0x005A /* 8129 chip only */
84#define RL_HALTCLK 0x005B
85#define RL_MULTIINTR 0x005C /* multiple interrupt */
86#define RL_PCIREV 0x005E /* PCI revision value */
87 /* 005F reserved */
88#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
89
90/* Direct PHY access registers only available on 8139 */
91#define RL_BMCR 0x0062 /* PHY basic mode control */
92#define RL_BMSR 0x0064 /* PHY basic mode status */
93#define RL_ANAR 0x0066 /* PHY autoneg advert */
94#define RL_LPAR 0x0068 /* PHY link partner ability */
95#define RL_ANER 0x006A /* PHY autoneg expansion */
96
97#define RL_DISCCNT 0x006C /* disconnect counter */
98#define RL_FALSECAR 0x006E /* false carrier counter */
99#define RL_NWAYTST 0x0070 /* NWAY test register */
100#define RL_RX_ER 0x0072 /* RX_ER counter */
101#define RL_CSCFG 0x0074 /* CS configuration register */
102
103
104/*
105 * TX config register bits
106 */
107#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
108#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
109#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
110#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
111#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
112
113#define RL_TXDMA_16BYTES 0x00000000
114#define RL_TXDMA_32BYTES 0x00000100
115#define RL_TXDMA_64BYTES 0x00000200
116#define RL_TXDMA_128BYTES 0x00000300
117#define RL_TXDMA_256BYTES 0x00000400
118#define RL_TXDMA_512BYTES 0x00000500
119#define RL_TXDMA_1024BYTES 0x00000600
120#define RL_TXDMA_2048BYTES 0x00000700
121
122/*
123 * Transmit descriptor status register bits.
124 */
125#define RL_TXSTAT_LENMASK 0x00001FFF
126#define RL_TXSTAT_OWN 0x00002000
127#define RL_TXSTAT_TX_UNDERRUN 0x00004000
128#define RL_TXSTAT_TX_OK 0x00008000
129#define RL_TXSTAT_EARLY_THRESH 0x003F0000
130#define RL_TXSTAT_COLLCNT 0x0F000000
131#define RL_TXSTAT_CARR_HBEAT 0x10000000
132#define RL_TXSTAT_OUTOFWIN 0x20000000
133#define RL_TXSTAT_TXABRT 0x40000000
134#define RL_TXSTAT_CARRLOSS 0x80000000
135
136/*
137 * Interrupt status register bits.
138 */
139#define RL_ISR_RX_OK 0x0001
140#define RL_ISR_RX_ERR 0x0002
141#define RL_ISR_TX_OK 0x0004
142#define RL_ISR_TX_ERR 0x0008
143#define RL_ISR_RX_OVERRUN 0x0010
144#define RL_ISR_PKT_UNDERRUN 0x0020
145#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
146#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
147#define RL_ISR_SYSTEM_ERR 0x8000
148
149#define RL_INTRS \
150 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
151 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
152 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
153
154/*
155 * Media status register. (8139 only)
156 */
157#define RL_MEDIASTAT_RXPAUSE 0x01
158#define RL_MEDIASTAT_TXPAUSE 0x02
159#define RL_MEDIASTAT_LINK 0x04
160#define RL_MEDIASTAT_SPEED10 0x08
161#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
162#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
163
164/*
165 * Receive config register.
166 */
167#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
168#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
169#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
170#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
171#define RL_RXCFG_RX_RUNT 0x00000010
172#define RL_RXCFG_RX_ERRPKT 0x00000020
173#define RL_RXCFG_WRAP 0x00000080
174#define RL_RXCFG_MAXDMA 0x00000700
175#define RL_RXCFG_BUFSZ 0x00001800
176#define RL_RXCFG_FIFOTHRESH 0x0000E000
177#define RL_RXCFG_EARLYTHRESH 0x07000000
178
179#define RL_RXDMA_16BYTES 0x00000000
180#define RL_RXDMA_32BYTES 0x00000100
181#define RL_RXDMA_64BYTES 0x00000200
182#define RL_RXDMA_128BYTES 0x00000300
183#define RL_RXDMA_256BYTES 0x00000400
184#define RL_RXDMA_512BYTES 0x00000500
185#define RL_RXDMA_1024BYTES 0x00000600
186#define RL_RXDMA_UNLIMITED 0x00000700
187
188#define RL_RXBUF_8 0x00000000
189#define RL_RXBUF_16 0x00000800
190#define RL_RXBUF_32 0x00001000
191#define RL_RXBUF_64 0x00001800
192
193#define RL_RXFIFO_16BYTES 0x00000000
194#define RL_RXFIFO_32BYTES 0x00002000
195#define RL_RXFIFO_64BYTES 0x00004000
196#define RL_RXFIFO_128BYTES 0x00006000
197#define RL_RXFIFO_256BYTES 0x00008000
198#define RL_RXFIFO_512BYTES 0x0000A000
199#define RL_RXFIFO_1024BYTES 0x0000C000
200#define RL_RXFIFO_NOTHRESH 0x0000E000
201
202/*
203 * Bits in RX status header (included with RX'ed packet
204 * in ring buffer).
205 */
206#define RL_RXSTAT_RXOK 0x00000001
207#define RL_RXSTAT_ALIGNERR 0x00000002
208#define RL_RXSTAT_CRCERR 0x00000004
209#define RL_RXSTAT_GIANT 0x00000008
210#define RL_RXSTAT_RUNT 0x00000010
211#define RL_RXSTAT_BADSYM 0x00000020
212#define RL_RXSTAT_BROAD 0x00002000
213#define RL_RXSTAT_INDIV 0x00004000
214#define RL_RXSTAT_MULTI 0x00008000
215#define RL_RXSTAT_LENMASK 0xFFFF0000
216
217#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
218/*
219 * Command register.
220 */
221#define RL_CMD_EMPTY_RXBUF 0x0001
222#define RL_CMD_TX_ENB 0x0004
223#define RL_CMD_RX_ENB 0x0008
224#define RL_CMD_RESET 0x0010
225
226/*
227 * EEPROM control register
228 */
229#define RL_EE_DATAOUT 0x01 /* Data out */
230#define RL_EE_DATAIN 0x02 /* Data in */
231#define RL_EE_CLK 0x04 /* clock */
232#define RL_EE_SEL 0x08 /* chip select */
233#define RL_EE_MODE (0x40|0x80)
234
235#define RL_EEMODE_OFF 0x00
236#define RL_EEMODE_AUTOLOAD 0x40
237#define RL_EEMODE_PROGRAM 0x80
238#define RL_EEMODE_WRITECFG (0x80|0x40)
239
240/* 9346 EEPROM commands */
241#define RL_EECMD_WRITE 0x140
242#define RL_EECMD_READ 0x180
243#define RL_EECMD_ERASE 0x1c0
244
245#define RL_EE_ID 0x00
246#define RL_EE_PCI_VID 0x01
247#define RL_EE_PCI_DID 0x02
248/* Location of station address inside EEPROM */
249#define RL_EE_EADDR 0x07
250
251/*
252 * MII register (8129 only)
253 */
254#define RL_MII_CLK 0x01
255#define RL_MII_DATAIN 0x02
256#define RL_MII_DATAOUT 0x04
257#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
258
259/*
260 * Config 0 register
261 */
262#define RL_CFG0_ROM0 0x01
263#define RL_CFG0_ROM1 0x02
264#define RL_CFG0_ROM2 0x04
265#define RL_CFG0_PL0 0x08
266#define RL_CFG0_PL1 0x10
267#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
268#define RL_CFG0_PCS 0x40
269#define RL_CFG0_SCR 0x80
270
271/*
272 * Config 1 register
273 */
274#define RL_CFG1_PWRDWN 0x01
275#define RL_CFG1_SLEEP 0x02
276#define RL_CFG1_IOMAP 0x04
277#define RL_CFG1_MEMMAP 0x08
278#define RL_CFG1_RSVD 0x10
279#define RL_CFG1_DRVLOAD 0x20
280#define RL_CFG1_LED0 0x40
281#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
282#define RL_CFG1_LED1 0x80
283
284/*
285 * The RealTek doesn't use a fragment-based descriptor mechanism.
286 * Instead, there are only four register sets, each or which represents
287 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
288 * packet buffer (32-bit aligned!) and we place the buffer addresses in
289 * the registers so the chip knows where they are.
290 *
291 * We can sort of kludge together the same kind of buffer management
292 * used in previous drivers, but we have to do buffer copies almost all
293 * the time, so it doesn't really buy us much.
294 *
295 * For reception, there's just one large buffer where the chip stores
296 * all received packets.
297 */
298
299#define RL_RX_BUF_SZ RL_RXBUF_64
300#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
301#define RL_TX_LIST_CNT 4
302#define RL_MIN_FRAMELEN 60
303#define RL_TXTHRESH(x) ((x) << 11)
304#define RL_TX_THRESH_INIT 96
305#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES
306#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
307#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
308
309#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
310#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
311
312#define RL_ETHER_ALIGN 2
313
314struct rl_chain_data {
315 u_int16_t cur_rx;
316 caddr_t rl_rx_buf;
317 caddr_t rl_rx_buf_ptr;
318
319 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
320 u_int8_t last_tx;
321 u_int8_t cur_tx;
322};
323
324#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
325#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
326#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
327#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
328#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
329#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
330#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
331
332struct rl_type {
333 u_int16_t rl_vid;
334 u_int16_t rl_did;
335 char *rl_name;
336};
337
338struct rl_mii_frame {
339 u_int8_t mii_stdelim;
340 u_int8_t mii_opcode;
341 u_int8_t mii_phyaddr;
342 u_int8_t mii_regaddr;
343 u_int8_t mii_turnaround;
344 u_int16_t mii_data;
345};
346
347/*
348 * MII constants
349 */
350#define RL_MII_STARTDELIM 0x01
351#define RL_MII_READOP 0x02
352#define RL_MII_WRITEOP 0x01
353#define RL_MII_TURNAROUND 0x02
354
355#define RL_8129 1
356#define RL_8139 2
357
358struct rl_softc {
359 struct arpcom arpcom; /* interface info */
360 bus_space_handle_t rl_bhandle; /* bus space handle */
361 bus_space_tag_t rl_btag; /* bus space tag */
362 struct resource *rl_res;
363 struct resource *rl_irq;
364 void *rl_intrhand;
365 device_t rl_miibus;
366 u_int8_t rl_unit; /* interface number */
367 u_int8_t rl_type;
368 u_int8_t rl_stats_no_timeout;
369 int rl_txthresh;
370 struct rl_chain_data rl_cdata;
371 struct callout_handle rl_stat_ch;
372 int suspended; /* 0 = normal 1 = suspended */
373#ifdef DEVICE_POLLING
374 int rxcycles;
375#endif /* DEVICE_POLLING */
376
377 u_int32_t saved_maps[5]; /* pci data */
378 u_int32_t saved_biosaddr;
379 u_int8_t saved_intline;
380 u_int8_t saved_cachelnsz;
381 u_int8_t saved_lattimer;
382};
383
384/*
385 * register space access macros
386 */
387#define CSR_WRITE_4(sc, reg, val) \
388 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
389#define CSR_WRITE_2(sc, reg, val) \
390 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
391#define CSR_WRITE_1(sc, reg, val) \
392 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
393
394#define CSR_READ_4(sc, reg) \
395 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
396#define CSR_READ_2(sc, reg) \
397 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
398#define CSR_READ_1(sc, reg) \
399 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
400
401#define RL_TIMEOUT 1000
402
403/*
404 * General constants that are fun to know.
405 *
406 * RealTek PCI vendor ID
407 */
408#define RT_VENDORID 0x10EC
409
410/*
411 * RealTek chip device IDs.
412 */
413#define RT_DEVICEID_8129 0x8129
414#define RT_DEVICEID_8139 0x8139
415
416/*
417 * Accton PCI vendor ID
418 */
419#define ACCTON_VENDORID 0x1113
420
421/*
422 * Accton MPX 5030/5038 device ID.
423 */
424#define ACCTON_DEVICEID_5030 0x1211
425
426/*
427 * Nortel PCI vendor ID
428 */
429#define NORTEL_VENDORID 0x126C
430
431/*
432 * Delta Electronics Vendor ID.
433 */
434#define DELTA_VENDORID 0x1500
435
436/*
437 * Delta device IDs.
438 */
439#define DELTA_DEVICEID_8139 0x1360
440
441/*
442 * Addtron vendor ID.
443 */
444#define ADDTRON_VENDORID 0x4033
445
446/*
447 * Addtron device IDs.
448 */
449#define ADDTRON_DEVICEID_8139 0x1360
450
451/*
452 * D-Link vendor ID.
453 */
454#define DLINK_VENDORID 0x1186
455
456/*
457 * D-Link DFE-530TX+ device ID
458 */
459#define DLINK_DEVICEID_530TXPLUS 0x1300
460
461/*
462 * Peppercon vendor ID.
463 */
464#define PEPPERCON_VENDORID 0x1743
465
466/*
467 * Peppercon AG ROL/F device ID.
468 */
469#define PEPPERCON_DEVICEID_ROLF 0x8139
470
471/*
472 * PCI low memory base and low I/O base register, and
473 * other PCI registers.
474 */
475
476#define RL_PCI_VENDOR_ID 0x00
477#define RL_PCI_DEVICE_ID 0x02
478#define RL_PCI_COMMAND 0x04
479#define RL_PCI_STATUS 0x06
480#define RL_PCI_CLASSCODE 0x09
481#define RL_PCI_LATENCY_TIMER 0x0D
482#define RL_PCI_HEADER_TYPE 0x0E
483#define RL_PCI_LOIO 0x10
484#define RL_PCI_LOMEM 0x14
485#define RL_PCI_BIOSROM 0x30
486#define RL_PCI_INTLINE 0x3C
487#define RL_PCI_INTPIN 0x3D
488#define RL_PCI_MINGNT 0x3E
489#define RL_PCI_MINLAT 0x0F
490#define RL_PCI_RESETOPT 0x48
491#define RL_PCI_EEPROM_DATA 0x4C
492
493#define RL_PCI_CAPID 0x50 /* 8 bits */
494#define RL_PCI_NEXTPTR 0x51 /* 8 bits */
495#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */
496#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
497
498#define RL_PSTATE_MASK 0x0003
499#define RL_PSTATE_D0 0x0000
500#define RL_PSTATE_D1 0x0002
501#define RL_PSTATE_D2 0x0002
502#define RL_PSTATE_D3 0x0003
503#define RL_PME_EN 0x0010
504#define RL_PME_STATUS 0x8000
505
506#ifdef __alpha__
507#undef vtophys
508#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
509#endif