bce: Rework MSI checkout for 5706 and 5708
[dragonfly.git] / sys / dev / netif / bce / if_bcereg.h
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1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written consent.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.13 2007/05/16 23:34:11 davidch Exp $
7b5b8bce 30 * $DragonFly: src/sys/dev/netif/bce/if_bcereg.h,v 1.3 2008/06/15 05:14:41 sephe Exp $
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31 */
32
33#ifndef _BCE_H_DEFINED
34#define _BCE_H_DEFINED
35
36/****************************************************************************/
37/* Debugging macros and definitions. */
38/****************************************************************************/
39#ifdef BCE_DEBUG
40
41#define BCE_CP_LOAD 0x00000001
42#define BCE_CP_SEND 0x00000002
43#define BCE_CP_RECV 0x00000004
44#define BCE_CP_INTR 0x00000008
45#define BCE_CP_UNLOAD 0x00000010
46#define BCE_CP_RESET 0x00000020
47#define BCE_CP_ALL 0x00FFFFFF
48
49#define BCE_CP_MASK 0x00FFFFFF
50
51#define BCE_LEVEL_FATAL 0x00000000
52#define BCE_LEVEL_WARN 0x01000000
53#define BCE_LEVEL_INFO 0x02000000
54#define BCE_LEVEL_VERBOSE 0x03000000
55#define BCE_LEVEL_EXCESSIVE 0x04000000
56
57#define BCE_LEVEL_MASK 0xFF000000
58
59#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN)
60#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO)
61#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
62#define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE)
63
64#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN)
65#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO)
66#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE)
67#define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE)
68
69#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN)
70#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO)
71#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE)
72#define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE)
73
74#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN)
75#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO)
76#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE)
77#define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE)
78
79#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN)
80#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO)
81#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
82#define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE)
83
84#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN)
85#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO)
86#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE)
87#define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE)
88
89#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL)
90#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN)
91#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO)
92#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE)
93#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
94
95#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug)
96#define BCE_MSG_LEVEL(lv) \
97 ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
98#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
99
100/* Print a message based on the logging level and code path. */
101#define DBPRINT(sc, level, format, args...) \
102do { \
103 if (BCE_LOG_MSG(level)) \
104 if_printf(&sc->arpcom.ac_if, format, ## args); \
105} while (0)
106
107/* Runs a particular command based on the logging level and code path. */
108#define DBRUN(m, args...) \
109do { \
110 if (BCE_LOG_MSG(m)) { \
111 args; \
112 } \
113} while (0)
114
115/* Runs a particular command based on the logging level. */
116#define DBRUNLV(level, args...) \
117do { \
118 if (BCE_MSG_LEVEL(level)) { \
119 args; \
120 } \
121} while (0)
122
123/* Runs a particular command based on the code path. */
124#define DBRUNCP(cp, args...) \
125do { \
126 if (BCE_CODE_PATH(cp)) { \
127 args; \
128 } \
129} while (0)
130
131/* Runs a particular command based on a condition. */
132#define DBRUNIF(cond, args...) \
133do { \
134 if (cond) { \
135 args; \
136 } \
137} while (0)
138
139/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
140#define DB_RANDOMFALSE(defects) (krandom() > defects)
141#define DB_OR_RANDOMFALSE(defects) || (krandom() > defects)
142#define DB_AND_RANDOMFALSE(defects) && (krandom() > ddfects)
143
144/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
145#define DB_RANDOMTRUE(defects) (krandom() < defects)
146#define DB_OR_RANDOMTRUE(defects) || (krandom() < defects)
147#define DB_AND_RANDOMTRUE(defects) && (krandom() < defects)
148
149#else /* !BCE_DEBUG */
150
151#define DBPRINT(level, format, args...)
152#define DBRUN(m, args...)
153#define DBRUNLV(level, args...)
154#define DBRUNCP(cp, args...)
155#define DBRUNIF(cond, args...)
156#define DB_RANDOMFALSE(defects)
157#define DB_OR_RANDOMFALSE(percent)
158#define DB_AND_RANDOMFALSE(percent)
159#define DB_RANDOMTRUE(defects)
160#define DB_OR_RANDOMTRUE(percent)
161#define DB_AND_RANDOMTRUE(percent)
162
163#endif /* BCE_DEBUG */
164
165
166/****************************************************************************/
167/* Device identification definitions. */
168/****************************************************************************/
169#define BRCM_VENDORID 0x14E4
170#define BRCM_DEVICEID_BCM5706 0x164A
171#define BRCM_DEVICEID_BCM5706S 0x16AA
172#define BRCM_DEVICEID_BCM5708 0x164C
173#define BRCM_DEVICEID_BCM5708S 0x16AC
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174#define BRCM_DEVICEID_BCM5709 0x1639
175#define BRCM_DEVICEID_BCM5709S 0x163A
176#define BRCM_DEVICEID_BCM5716 0x163B
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177
178#define HP_VENDORID 0x103C
179
180#define PCI_ANY_ID (uint16_t) (~0U)
181
182/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
183
184#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000)
185#define BCE_CHIP_NUM_5706 0x57060000
186#define BCE_CHIP_NUM_5708 0x57080000
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187#define BCE_CHIP_NUM_5709 0x57090000
188#define BCE_CHIP_NUM_5716 0x57160000
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189
190#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000)
191#define BCE_CHIP_REV_Ax 0x00000000
192#define BCE_CHIP_REV_Bx 0x00001000
193#define BCE_CHIP_REV_Cx 0x00002000
194
195#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0)
196#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f)
197
198#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0)
199#define BCE_CHIP_ID_5706_A0 0x57060000
200#define BCE_CHIP_ID_5706_A1 0x57060010
201#define BCE_CHIP_ID_5706_A2 0x57060020
202#define BCE_CHIP_ID_5706_A3 0x57060030
203#define BCE_CHIP_ID_5708_A0 0x57080000
204#define BCE_CHIP_ID_5708_B0 0x57081000
205#define BCE_CHIP_ID_5708_B1 0x57081010
206#define BCE_CHIP_ID_5708_B2 0x57081020
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207#define BCE_CHIP_ID_5709_A0 0x57090000
208#define BCE_CHIP_ID_5709_A1 0x57090010
209#define BCE_CHIP_ID_5709_B0 0x57091000
210#define BCE_CHIP_ID_5709_B1 0x57091010
211#define BCE_CHIP_ID_5709_B2 0x57091020
212#define BCE_CHIP_ID_5709_C0 0x57092000
213#define BCE_CHIP_ID_5716_C0 0x57162000
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214
215#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf)
216
217/* A serdes chip will have the first bit of the bond id set. */
218#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01
219
220
221/* shorthand one */
222#define BCE_ASICREV(x) ((x) >> 28)
223#define BCE_ASICREV_BCM5700 0x06
224
225/* chip revisions */
226#define BCE_CHIPREV(x) ((x) >> 24)
227#define BCE_CHIPREV_5700_AX 0x70
228#define BCE_CHIPREV_5700_BX 0x71
229#define BCE_CHIPREV_5700_CX 0x72
230#define BCE_CHIPREV_5701_AX 0x00
231
232struct bce_type {
233 uint16_t bce_vid;
234 uint16_t bce_did;
235 uint16_t bce_svid;
236 uint16_t bce_sdid;
237 const char *bce_name;
238};
239
240/****************************************************************************/
241/* NVRAM Access */
242/****************************************************************************/
243
244/* Buffered flash (Atmel: AT45DB011B) specific information */
245#define SEEPROM_PAGE_BITS 2
246#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
247#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
248#define SEEPROM_PAGE_SIZE 4
249#define SEEPROM_TOTAL_SIZE 65536
250
251#define BUFFERED_FLASH_PAGE_BITS 9
252#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
253#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
254#define BUFFERED_FLASH_PAGE_SIZE 264
255#define BUFFERED_FLASH_TOTAL_SIZE 0x21000
256
257#define SAIFUN_FLASH_PAGE_BITS 8
258#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
259#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
260#define SAIFUN_FLASH_PAGE_SIZE 256
261#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
262
263#define ST_MICRO_FLASH_PAGE_BITS 8
264#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
265#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
266#define ST_MICRO_FLASH_PAGE_SIZE 256
267#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
268
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269#define BCM5709_FLASH_PAGE_BITS 8
270#define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS)
271#define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1)
272#define BCM5709_FLASH_PAGE_SIZE 256
273
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274#define NVRAM_TIMEOUT_COUNT 30000
275#define BCE_FLASHDESC_MAX 64
276
277#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \
278 BCE_NVM_CFG1_BUFFER_MODE | \
279 BCE_NVM_CFG1_PROTECT_MODE | \
280 BCE_NVM_CFG1_FLASH_SIZE)
281
282#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
283
284struct flash_spec {
285 uint32_t strapping;
286 uint32_t config1;
287 uint32_t config2;
288 uint32_t config3;
289 uint32_t write1;
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290#define BCE_NV_BUFFERED 0x00000001
291#define BCE_NV_TRANSLATE 0x00000002
292#define BCE_NV_WREN 0x00000004
293 uint32_t flags;
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294 uint32_t page_bits;
295 uint32_t page_size;
296 uint32_t addr_mask;
297 uint32_t total_size;
298 uint8_t *name;
299};
300
301
302/****************************************************************************/
303/* Shared Memory layout */
304/* The BCE bootcode will initialize this data area with port configurtion */
305/* information which can be accessed by the driver. */
306/****************************************************************************/
307
308/*
309 * This value (in milliseconds) determines the frequency of the driver
310 * issuing the PULSE message code. The firmware monitors this periodic
311 * pulse to determine when to switch to an OS-absent mode.
312 */
313#define DRV_PULSE_PERIOD_MS 250
314
315/*
316 * This value (in milliseconds) determines how long the driver should
317 * wait for an acknowledgement from the firmware before timing out. Once
318 * the firmware has timed out, the driver will assume there is no firmware
319 * running and there won't be any firmware-driver synchronization during a
320 * driver reset.
321 */
046d6b48 322#define FW_ACK_TIME_OUT_MS 1000
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323
324
325#define BCE_DRV_RESET_SIGNATURE 0x00000000
326#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
327
328#define BCE_DRV_MB 0x00000004
329#define BCE_DRV_MSG_CODE 0xff000000
330#define BCE_DRV_MSG_CODE_RESET 0x01000000
331#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000
332#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000
333#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
334#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
335#define BCE_DRV_MSG_CODE_PULSE 0x06000000
336#define BCE_DRV_MSG_CODE_DIAG 0x07000000
337#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
d0092544 338#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
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339
340#define BCE_DRV_MSG_DATA 0x00ff0000
341#define BCE_DRV_MSG_DATA_WAIT0 0x00010000
342#define BCE_DRV_MSG_DATA_WAIT1 0x00020000
343#define BCE_DRV_MSG_DATA_WAIT2 0x00030000
344#define BCE_DRV_MSG_DATA_WAIT3 0x00040000
345
346#define BCE_DRV_MSG_SEQ 0x0000ffff
347
348#define BCE_FW_MB 0x00000008
349#define BCE_FW_MSG_ACK 0x0000ffff
350#define BCE_FW_MSG_STATUS_MASK 0x00ff0000
351#define BCE_FW_MSG_STATUS_OK 0x00000000
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352#define BCE_FW_MSG_STATUS_INVALID_ARGS 0x00010000
353#define BCE_FW_MSG_STATUS_DRV_PRSNT 0x00020000
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354#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000
355
356#define BCE_LINK_STATUS 0x0000000c
357#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff
358#define BCE_LINK_STATUS_LINK_UP 0x1
359#define BCE_LINK_STATUS_LINK_DOWN 0x0
360#define BCE_LINK_STATUS_SPEED_MASK 0x1e
361#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1)
362#define BCE_LINK_STATUS_10HALF (1<<1)
363#define BCE_LINK_STATUS_10FULL (2<<1)
364#define BCE_LINK_STATUS_100HALF (3<<1)
365#define BCE_LINK_STATUS_100BASE_T4 (4<<1)
366#define BCE_LINK_STATUS_100FULL (5<<1)
367#define BCE_LINK_STATUS_1000HALF (6<<1)
368#define BCE_LINK_STATUS_1000FULL (7<<1)
369#define BCE_LINK_STATUS_2500HALF (8<<1)
370#define BCE_LINK_STATUS_2500FULL (9<<1)
371#define BCE_LINK_STATUS_AN_ENABLED (1<<5)
372#define BCE_LINK_STATUS_AN_COMPLETE (1<<6)
373#define BCE_LINK_STATUS_PARALLEL_DET (1<<7)
374#define BCE_LINK_STATUS_RESERVED (1<<8)
375#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
376#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
377#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
378#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
379#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
380#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
381#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
382#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16)
383#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17)
384#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
385#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
386#define BCE_LINK_STATUS_SERDES_LINK (1<<20)
387#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
388#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
389
390#define BCE_DRV_PULSE_MB 0x00000010
391#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff
392
393/* Indicate to the firmware not to go into the
394 * OS absent when it is not getting driver pulse.
395 * This is used for debugging. */
396#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
397
398#define BCE_DEV_INFO_SIGNATURE 0x00000020
399#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900
400#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
401#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01
402#define BCE_DEV_INFO_SECONDARY_PORT 0x80
403#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
404
405#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024
406
407#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
408#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
409#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
410#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
411#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
412
413#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038
414#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c
415#define BCE_SHARED_HW_CFG_DESIGN_NIC 0
416#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1
417#define BCE_SHARED_HW_CFG_PHY_COPPER 0
418#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2
419#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20
420#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40
421#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
422#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300
423#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0
424#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
425#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
426
427#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040
428#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
429
430#define BCE_DEV_INFO_BC_REV 0x0000004c
431
432#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050
433#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff
434
435#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054
436#define BCE_PORT_HW_CFG_CONFIG 0x00000058
437#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
438#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
439#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
440#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
441#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
442
443#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
444#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
445#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
446#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
447#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
448#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
449
450#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
451
452#define BCE_DEV_INFO_FORMAT_REV 0x000000c4
453#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000
454#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24)
455
456#define BCE_SHARED_FEATURE 0x000000c8
457#define BCE_SHARED_FEATURE_MASK 0xffffffff
458
459#define BCE_PORT_FEATURE 0x000000d8
460#define BCE_PORT2_FEATURE 0x00000014c
461#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000
462#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000
463#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000
464#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000
465#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf
466#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
467#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1
468#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2
469#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3
470#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4
471#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5
472#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6
473#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7
474#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8
475#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9
476#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa
477#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb
478#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc
479#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd
480#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe
481#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf
482
483#define BCE_PORT_FEATURE_WOL 0xdc
484#define BCE_PORT2_FEATURE_WOL 0x150
485#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
486#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
487#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
488#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
489#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
490#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
491#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
492#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
493#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
494#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
495#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
496#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
497#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
498#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
499#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
500#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
501#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
502
503#define BCE_PORT_FEATURE_MBA 0xe0
504#define BCE_PORT2_FEATURE_MBA 0x154
505#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
506#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
507#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
508#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
509#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
510#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
511#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
512#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
513#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
514#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
515#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
516#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
517#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
518#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
519#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
520#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
521#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
522#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
523#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
524#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
525#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
526#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
527#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
528#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
529#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
530#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
531#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
532#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
533#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
534#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
535#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
536#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
537#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
538#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
539#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
540#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
541#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
542#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
543#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
544#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
545#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
546#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
547#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
548
549#define BCE_PORT_FEATURE_IMD 0xe4
550#define BCE_PORT2_FEATURE_IMD 0x158
551#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
552#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
553
554#define BCE_PORT_FEATURE_VLAN 0xe8
555#define BCE_PORT2_FEATURE_VLAN 0x15c
556#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
557#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
558
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559#define BCE_MFW_VER_PTR 0x00000014c
560
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561#define BCE_BC_STATE_RESET_TYPE 0x000001c0
562#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254
563#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
564#define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \
565 0x00010000)
566#define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \
567 0x00020000)
568#define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \
569 0x00030000)
570#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
571#define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \
572 DRV_MSG_CODE_RESET)
573#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \
574 DRV_MSG_CODE_UNLOAD)
575#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \
576 DRV_MSG_CODE_SHUTDOWN)
577#define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \
578 DRV_MSG_CODE_WOL)
579#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \
580 DRV_MSG_CODE_DIAG)
581#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \
582 (msg))
583
584#define BCE_BC_STATE 0x000001c4
585#define BCE_BC_STATE_ERR_MASK 0x0000ff00
586#define BCE_BC_STATE_SIGN 0x42530000
587#define BCE_BC_STATE_SIGN_MASK 0xffff0000
588#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1)
589#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2)
590#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3)
591#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4)
592#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5)
593#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6)
594#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7)
595#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8)
596#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9)
597#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81)
598#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82)
599#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83)
600#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84)
601#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85)
602#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86)
603#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87)
604#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88)
605#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89)
606#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100)
607#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200)
608#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300)
609#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400)
610#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500)
611#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600)
612#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700)
613
bc30d40d 614#define BCE_BC_STATE_CONDITION 0x000001c8
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615#define BCE_CONDITION_INIT_POR 0x00000001
616#define BCE_CONDITION_INIT_VAUX_AVAIL 0x00000002
617#define BCE_CONDITION_INIT_PCI_AVAIL 0x00000004
618#define BCE_CONDITION_INIT_PCI_RESET 0x00000008
619#define BCE_CONDITION_INIT_HD_RESET 0x00000010 /* 5709/16 only */
620#define BCE_CONDITION_DRV_PRESENT 0x00000100
621#define BCE_CONDITION_LOW_POWER_LINK 0x00000200
622#define BCE_CONDITION_CORE_RST_OCCURRED 0x00000400 /* 5709/16 only */
623#define BCE_CONDITION_UNUSED 0x00000800
624#define BCE_CONDITION_BUSY_EXPROM 0x00001000 /* 5706/08 only */
625
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626#define BCE_CONDITION_MFW_RUN_UNKNOWN 0x00000000
627#define BCE_CONDITION_MFW_RUN_IPMI 0x00002000
628#define BCE_CONDITION_MFW_RUN_UMP 0x00004000
629#define BCE_CONDITION_MFW_RUN_NCSI 0x00006000
630#define BCE_CONDITION_MFW_RUN_NONE 0x0000e000
631#define BCE_CONDITION_MFW_RUN_MASK 0x0000e000
632
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633/* 5709/16 only */
634#define BCE_CONDITION_PM_STATE_MASK 0x00030000
635#define BCE_CONDITION_PM_STATE_FULL 0x00030000
636#define BCE_CONDITION_PM_STATE_PREP 0x00020000
637#define BCE_CONDITION_PM_STATE_UNPREP 0x00010000
638#define BCE_CONDITION_PM_RESERVED 0x00000000
639
640/* 5709/16 only */
641#define BCE_CONDITION_RXMODE_KEEP_VLAN 0x00040000
642#define BCE_CONDITION_DRV_WOL_ENABLED 0x00080000
643#define BCE_CONDITION_PORT_DISABLED 0x00100000
644#define BCE_CONDITION_DRV_MAYBE_OUT 0x00200000
645#define BCE_CONDITION_DPFW_DEAD 0x00400000
646
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647#define BCE_BC_STATE_DEBUG_CMD 0x1dc
648#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
649#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
650#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
651#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
652
653#define HOST_VIEW_SHMEM_BASE 0x167c00
654
655/*
656 * PCI registers defined in the PCI 2.2 spec.
657 */
658#define BCE_PCI_PCIX_CMD 0x42
659
660
661/****************************************************************************/
662/* Convenience definitions. */
663/****************************************************************************/
664#define REG_WR(sc, reg, val) \
665 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
666#define REG_WR16(sc, reg, val) \
667 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
668#define REG_RD(sc, reg) \
669 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
670
671#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset)
672#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val)
673
674#define CTX_WR(sc, cid_addr, offset, val) \
675 bce_ctx_wr(sc, cid_addr, offset, val)
676
677#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
678#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
679
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680#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo
681#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
682#define BCE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
683#define BCE_ADDR_HI(y) ((uint64_t) (y) >> 32)
684#else
685#define BCE_ADDR_LO(y) ((uint32_t)y)
686#define BCE_ADDR_HI(y) (0)
687#endif
688
689
690/*
691 * The following data structures are generated from RTL code.
692 * Do not modify any values below this line.
693 */
694
695/****************************************************************************/
696/* Do not modify any of the following data structures, they are generated */
697/* from RTL code. */
698/* */
699/* Begin machine generated definitions. */
700/****************************************************************************/
701
702/*
703 * tx_bd definition
704 */
705struct tx_bd {
706 uint32_t tx_bd_haddr_hi;
707 uint32_t tx_bd_haddr_lo;
708 uint32_t tx_bd_mss_nbytes;
709 uint16_t tx_bd_flags;
710 uint16_t tx_bd_vlan_tag;
711#define TX_BD_FLAGS_CONN_FAULT (1<<0)
712#define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
713#define TX_BD_FLAGS_IP_CKSUM (1<<2)
714#define TX_BD_FLAGS_VLAN_TAG (1<<3)
715#define TX_BD_FLAGS_COAL_NOW (1<<4)
716#define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
717#define TX_BD_FLAGS_END (1<<6)
718#define TX_BD_FLAGS_START (1<<7)
719#define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
720#define TX_BD_FLAGS_SW_FLAGS (1<<13)
721#define TX_BD_FLAGS_SW_SNAP (1<<14)
722#define TX_BD_FLAGS_SW_LSO (1<<15)
723};
724
725
726/*
727 * rx_bd definition
728 */
729struct rx_bd {
730 uint32_t rx_bd_haddr_hi;
731 uint32_t rx_bd_haddr_lo;
732 uint32_t rx_bd_len;
733 uint32_t rx_bd_flags;
734#define RX_BD_FLAGS_NOPUSH (1<<0)
735#define RX_BD_FLAGS_DUMMY (1<<1)
736#define RX_BD_FLAGS_END (1<<2)
737#define RX_BD_FLAGS_START (1<<3)
738};
739
740
741/*
742 * status_block definition
743 */
744struct status_block {
745 uint32_t status_attn_bits;
746#define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
747#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
748#define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
749#define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
750#define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
751#define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
752#define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
753#define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
754#define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
755#define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
756#define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
757#define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
758#define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
759#define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
760#define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
761#define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
762#define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
763#define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
764#define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
765#define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
766#define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
767#define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
768#define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
769#define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
770#define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
771#define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
772#define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
773#define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
774#define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
775
776 uint32_t status_attn_bits_ack;
777#if BYTE_ORDER == BIG_ENDIAN
778 uint16_t status_tx_quick_consumer_index0;
779 uint16_t status_tx_quick_consumer_index1;
780 uint16_t status_tx_quick_consumer_index2;
781 uint16_t status_tx_quick_consumer_index3;
782 uint16_t status_rx_quick_consumer_index0;
783 uint16_t status_rx_quick_consumer_index1;
784 uint16_t status_rx_quick_consumer_index2;
785 uint16_t status_rx_quick_consumer_index3;
786 uint16_t status_rx_quick_consumer_index4;
787 uint16_t status_rx_quick_consumer_index5;
788 uint16_t status_rx_quick_consumer_index6;
789 uint16_t status_rx_quick_consumer_index7;
790 uint16_t status_rx_quick_consumer_index8;
791 uint16_t status_rx_quick_consumer_index9;
792 uint16_t status_rx_quick_consumer_index10;
793 uint16_t status_rx_quick_consumer_index11;
794 uint16_t status_rx_quick_consumer_index12;
795 uint16_t status_rx_quick_consumer_index13;
796 uint16_t status_rx_quick_consumer_index14;
797 uint16_t status_rx_quick_consumer_index15;
798 uint16_t status_completion_producer_index;
799 uint16_t status_cmd_consumer_index;
800 uint16_t status_idx;
801 uint16_t status_unused;
802#else
803 uint16_t status_tx_quick_consumer_index1;
804 uint16_t status_tx_quick_consumer_index0;
805 uint16_t status_tx_quick_consumer_index3;
806 uint16_t status_tx_quick_consumer_index2;
807 uint16_t status_rx_quick_consumer_index1;
808 uint16_t status_rx_quick_consumer_index0;
809 uint16_t status_rx_quick_consumer_index3;
810 uint16_t status_rx_quick_consumer_index2;
811 uint16_t status_rx_quick_consumer_index5;
812 uint16_t status_rx_quick_consumer_index4;
813 uint16_t status_rx_quick_consumer_index7;
814 uint16_t status_rx_quick_consumer_index6;
815 uint16_t status_rx_quick_consumer_index9;
816 uint16_t status_rx_quick_consumer_index8;
817 uint16_t status_rx_quick_consumer_index11;
818 uint16_t status_rx_quick_consumer_index10;
819 uint16_t status_rx_quick_consumer_index13;
820 uint16_t status_rx_quick_consumer_index12;
821 uint16_t status_rx_quick_consumer_index15;
822 uint16_t status_rx_quick_consumer_index14;
823 uint16_t status_cmd_consumer_index;
824 uint16_t status_completion_producer_index;
825 uint16_t status_unused;
826 uint16_t status_idx;
827#endif
828};
829
830
831/*
832 * statistics_block definition
833 */
834struct statistics_block {
835 uint32_t stat_IfHCInOctets_hi;
836 uint32_t stat_IfHCInOctets_lo;
837 uint32_t stat_IfHCInBadOctets_hi;
838 uint32_t stat_IfHCInBadOctets_lo;
839 uint32_t stat_IfHCOutOctets_hi;
840 uint32_t stat_IfHCOutOctets_lo;
841 uint32_t stat_IfHCOutBadOctets_hi;
842 uint32_t stat_IfHCOutBadOctets_lo;
843 uint32_t stat_IfHCInUcastPkts_hi;
844 uint32_t stat_IfHCInUcastPkts_lo;
845 uint32_t stat_IfHCInMulticastPkts_hi;
846 uint32_t stat_IfHCInMulticastPkts_lo;
847 uint32_t stat_IfHCInBroadcastPkts_hi;
848 uint32_t stat_IfHCInBroadcastPkts_lo;
849 uint32_t stat_IfHCOutUcastPkts_hi;
850 uint32_t stat_IfHCOutUcastPkts_lo;
851 uint32_t stat_IfHCOutMulticastPkts_hi;
852 uint32_t stat_IfHCOutMulticastPkts_lo;
853 uint32_t stat_IfHCOutBroadcastPkts_hi;
854 uint32_t stat_IfHCOutBroadcastPkts_lo;
855 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
856 uint32_t stat_Dot3StatsCarrierSenseErrors;
857 uint32_t stat_Dot3StatsFCSErrors;
858 uint32_t stat_Dot3StatsAlignmentErrors;
859 uint32_t stat_Dot3StatsSingleCollisionFrames;
860 uint32_t stat_Dot3StatsMultipleCollisionFrames;
861 uint32_t stat_Dot3StatsDeferredTransmissions;
862 uint32_t stat_Dot3StatsExcessiveCollisions;
863 uint32_t stat_Dot3StatsLateCollisions;
864 uint32_t stat_EtherStatsCollisions;
865 uint32_t stat_EtherStatsFragments;
866 uint32_t stat_EtherStatsJabbers;
867 uint32_t stat_EtherStatsUndersizePkts;
868 uint32_t stat_EtherStatsOverrsizePkts;
869 uint32_t stat_EtherStatsPktsRx64Octets;
870 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets;
871 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets;
872 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets;
873 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
874 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
875 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
876 uint32_t stat_EtherStatsPktsTx64Octets;
877 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets;
878 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets;
879 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets;
880 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
881 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
882 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
883 uint32_t stat_XonPauseFramesReceived;
884 uint32_t stat_XoffPauseFramesReceived;
885 uint32_t stat_OutXonSent;
886 uint32_t stat_OutXoffSent;
887 uint32_t stat_FlowControlDone;
888 uint32_t stat_MacControlFramesReceived;
889 uint32_t stat_XoffStateEntered;
890 uint32_t stat_IfInFramesL2FilterDiscards;
891 uint32_t stat_IfInRuleCheckerDiscards;
892 uint32_t stat_IfInFTQDiscards;
893 uint32_t stat_IfInMBUFDiscards;
894 uint32_t stat_IfInRuleCheckerP4Hit;
895 uint32_t stat_CatchupInRuleCheckerDiscards;
896 uint32_t stat_CatchupInFTQDiscards;
897 uint32_t stat_CatchupInMBUFDiscards;
898 uint32_t stat_CatchupInRuleCheckerP4Hit;
899 uint32_t stat_GenStat00;
900 uint32_t stat_GenStat01;
901 uint32_t stat_GenStat02;
902 uint32_t stat_GenStat03;
903 uint32_t stat_GenStat04;
904 uint32_t stat_GenStat05;
905 uint32_t stat_GenStat06;
906 uint32_t stat_GenStat07;
907 uint32_t stat_GenStat08;
908 uint32_t stat_GenStat09;
909 uint32_t stat_GenStat10;
910 uint32_t stat_GenStat11;
911 uint32_t stat_GenStat12;
912 uint32_t stat_GenStat13;
913 uint32_t stat_GenStat14;
914 uint32_t stat_GenStat15;
915};
916
917
918/*
919 * l2_fhdr definition
920 */
921struct l2_fhdr {
922 uint32_t l2_fhdr_status;
923#define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
924#define L2_FHDR_STATUS_RULE_P2 (1<<3)
925#define L2_FHDR_STATUS_RULE_P3 (1<<4)
926#define L2_FHDR_STATUS_RULE_P4 (1<<5)
927#define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
928#define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
929#define L2_FHDR_STATUS_RSS_HASH (1<<8)
930#define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
931#define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
932#define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
933
934#define L2_FHDR_ERRORS_BAD_CRC (1<<17)
935#define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
936#define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
937#define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
938#define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
f5f45da0 939#define L2_FHDR_ERRORS_IPV4_BAD_LEN (1<<22)
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940#define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
941#define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
942
943 uint32_t l2_fhdr_hash;
944#if BYTE_ORDER == BIG_ENDIAN
945 uint16_t l2_fhdr_pkt_len;
946 uint16_t l2_fhdr_vlan_tag;
947 uint16_t l2_fhdr_ip_xsum;
948 uint16_t l2_fhdr_tcp_udp_xsum;
949#else
950 uint16_t l2_fhdr_vlan_tag;
951 uint16_t l2_fhdr_pkt_len;
952 uint16_t l2_fhdr_tcp_udp_xsum;
953 uint16_t l2_fhdr_ip_xsum;
954#endif
955};
956
957
958/*
d0092544 959 * l2_tx_context definition (5706 and 5708)
43c2aeb0 960 */
d0092544
SZ
961#define BCE_L2CTX_TX_TYPE 0x00000000
962#define BCE_L2CTX_TX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
963#define BCE_L2CTX_TX_TYPE_TYPE (0xf<<28)
964#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY (0<<28)
965#define BCE_L2CTX_TX_TYPE_TYPE_L2 (1<<28)
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966
967#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
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968#define BCE_L2CTX_TX_EST_NBD 0x00000088
969#define BCE_L2CTX_TX_CMD_TYPE 0x00000088
970#define BCE_L2CTX_TX_CMD_TYPE_TYPE (0xf<<24)
971#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 (0<<24)
972#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP (1<<24)
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973
974#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
d0092544
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975#define BCE_L2CTX_TX_TSCH_BSEQ 0x00000094
976#define BCE_L2CTX_TX_TBDR_BSEQ 0x00000098
977#define BCE_L2CTX_TX_TBDR_BOFF 0x0000009c
978#define BCE_L2CTX_TX_TBDR_BIDX 0x0000009c
979#define BCE_L2CTX_TX_TBDR_BHADDR_HI 0x000000a0
980#define BCE_L2CTX_TX_TBDR_BHADDR_LO 0x000000a4
981#define BCE_L2CTX_TX_TXP_BOFF 0x000000a8
982#define BCE_L2CTX_TX_TXP_BIDX 0x000000a8
983#define BCE_L2CTX_TX_TXP_BSEQ 0x000000ac
984
985/*
986 * l2_tx_context definition (5709 and 5716)
987 */
988#define BCE_L2CTX_TX_TYPE_XI 0x00000080
989#define BCE_L2CTX_TX_TYPE_SIZE_L2_XI ((0xc0/0x20)<<16)
990#define BCE_L2CTX_TX_TYPE_TYPE_XI (0xf<<28)
991#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI (0<<28)
992#define BCE_L2CTX_TX_TYPE_TYPE_L2_XI (1<<28)
993
994#define BCE_L2CTX_TX_CMD_TYPE_XI 0x00000240
995#define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI (0xf<<24)
996#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI (0<<24)
997#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI (1<<24)
998
999#define BCE_L2CTX_TX_HOST_BIDX_XI 0x00000240
1000#define BCE_L2CTX_TX_HOST_BSEQ_XI 0x00000248
1001#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258
1002#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c
1003
1004
1005/*
1006 * l2_rx_context definition (5706, 5708, 5709, and 5716)
1007 */
1008#define BCE_L2CTX_RX_WATER_MARK 0x00000000
1009#define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT 0
1010#define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT 32
1011#define BCE_L2CTX_RX_LO_WATER_MARK_SCALE 4
1012#define BCE_L2CTX_RX_LO_WATER_MARK_DIS 0
1013#define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT 4
1014#define BCE_L2CTX_RX_HI_WATER_MARK_SCALE 16
1015#define BCE_L2CTX_RX_WATER_MARKS_MSK 0x000000ff
1016
1017#define BCE_L2CTX_RX_BD_PRE_READ 0x00000000
1018#define BCE_L2CTX_RX_BD_PRE_READ_SHIFT 8
1019
1020#define BCE_L2CTX_RX_CTX_SIZE 0x00000000
1021#define BCE_L2CTX_RX_CTX_SIZE_SHIFT 16
1022#define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT)
1023
1024#define BCE_L2CTX_RX_CTX_TYPE 0x00000000
1025#define BCE_L2CTX_RX_CTX_TYPE_SHIFT 24
1026
1027#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
1028#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
1029#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
1030
1031#define BCE_L2CTX_RX_HOST_BDIDX 0x00000004
1032#define BCE_L2CTX_RX_HOST_BSEQ 0x00000008
1033#define BCE_L2CTX_RX_NX_BSEQ 0x0000000c
1034#define BCE_L2CTX_RX_NX_BDHADDR_HI 0x00000010
1035#define BCE_L2CTX_RX_NX_BDHADDR_LO 0x00000014
1036#define BCE_L2CTX_RX_NX_BDIDX 0x00000018
1037
1038#define BCE_L2CTX_RX_HOST_PG_BDIDX 0x00000044
1039#define BCE_L2CTX_RX_PG_BUF_SIZE 0x00000048
1040#define BCE_L2CTX_RX_RBDC_KEY 0x0000004c
1041#define BCE_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe
1042#define BCE_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050
1043#define BCE_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054
1044#define BCE_L2CTX_RX_NX_PG_BDIDX 0x00000058
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1045
1046
1047/*
d0092544 1048 * l2_mq definitions (5706, 5708, 5709, and 5716)
43c2aeb0 1049 */
d0092544
SZ
1050#define BCE_L2MQ_RX_HOST_BDIDX 0x00000004
1051#define BCE_L2MQ_RX_HOST_BSEQ 0x00000008
1052#define BCE_L2MQ_RX_HOST_PG_BDIDX 0x00000044
1053
1054#define BCE_L2MQ_TX_HOST_BIDX 0x00000088
1055#define BCE_L2MQ_TX_HOST_BSEQ 0x00000090
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SZ
1056
1057
1058/*
1059 * pci_config_l definition
1060 * offset: 0000
1061 */
733403d6
SZ
1062#define BCE_PCICFG_MSI_CONTROL 0x00000058
1063#define BCE_PCICFG_MSI_CONTROL_ENABLE (1L<<16)
1064
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1065#define BCE_PCICFG_MISC_CONFIG 0x00000068
1066#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
1067#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
1068#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
1069#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
1070#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
1071#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
1072#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
1073#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
1074#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
1075#define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
1076#define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16)
1077
1078#define BCE_PCICFG_MISC_STATUS 0x0000006c
1079#define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
1080#define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
1081#define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2)
1082#define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
1083#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
1084#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
1085#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
1086#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
1087#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
1088
1089#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
1090#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1091#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1092#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1093#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1094#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1095#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1096#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1097#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1098#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1099#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1100#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1101#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1102#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1103#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1104#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1105#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1106#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1107#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1108#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1109#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1110#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1111#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1112#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1113#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1114#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1115#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1116#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1117#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1118#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1119
1120#define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078
1121#define BCE_PCICFG_REG_WINDOW 0x00000080
1122#define BCE_PCICFG_INT_ACK_CMD 0x00000084
1123#define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
1124#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
1125#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
1126#define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
1127
1128#define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088
1129#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
1130#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
1131#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
1132
1133
1134/*
1135 * pci_reg definition
1136 * offset: 0x400
1137 */
1138#define BCE_PCI_GRC_WINDOW_ADDR 0x00000400
1139#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
1140
1141#define BCE_PCI_CONFIG_1 0x00000404
1142#define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
1143#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
1144#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
1145#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
1146#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
1147#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
1148#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
1149#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
1150#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
1151#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
1152#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
1153#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
1154#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
1155#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
1156#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
1157#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
1158#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
1159#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
1160
1161#define BCE_PCI_CONFIG_2 0x00000408
1162#define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
1163#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
1164#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
1165#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
1166#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
1167#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
1168#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
1169#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
1170#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
1171#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
1172#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
1173#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
1174#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
1175#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
1176#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
1177#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
1178#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
1179#define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
1180#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
1181#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
1182#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
1183#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
1184#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
1185#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
1186#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
1187#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
1188#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
1189#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
1190#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
1191#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
1192#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
1193#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
1194#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
1195#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
1196#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
1197#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
1198#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
1199#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
1200#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
1201#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
1202#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
1203#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
1204#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
1205#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
1206#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
1207#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
1208#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
1209
1210#define BCE_PCI_CONFIG_3 0x0000040c
1211#define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
1212#define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24)
1213#define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25)
1214#define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26)
1215#define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27)
1216#define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
1217#define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31)
1218
1219#define BCE_PCI_PM_DATA_A 0x00000410
1220#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
1221#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
1222#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
1223#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
1224
1225#define BCE_PCI_PM_DATA_B 0x00000414
1226#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
1227#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
1228#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
1229#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
1230
1231#define BCE_PCI_SWAP_DIAG0 0x00000418
1232#define BCE_PCI_SWAP_DIAG1 0x0000041c
1233#define BCE_PCI_EXP_ROM_ADDR 0x00000420
1234#define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
1235#define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31)
1236
1237#define BCE_PCI_EXP_ROM_DATA 0x00000424
1238#define BCE_PCI_VPD_INTF 0x00000428
1239#define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0)
1240
1241#define BCE_PCI_VPD_ADDR_FLAG 0x0000042c
1242#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
1243#define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15)
1244
1245#define BCE_PCI_VPD_DATA 0x00000430
1246#define BCE_PCI_ID_VAL1 0x00000434
1247#define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
1248#define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
1249
1250#define BCE_PCI_ID_VAL2 0x00000438
1251#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
1252#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
1253
1254#define BCE_PCI_ID_VAL3 0x0000043c
1255#define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
1256#define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
1257
1258#define BCE_PCI_ID_VAL4 0x00000440
1259#define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
1260#define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
1261#define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
1262#define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
1263#define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
1264#define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
1265#define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
1266#define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
1267#define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
1268#define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
1269#define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
1270#define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
1271#define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
1272#define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
1273#define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
1274#define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
1275#define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
1276#define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
1277#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
1278#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
1279#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
1280#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
1281#define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
1282#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
1283#define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
1284#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
1285#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
1286#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
1287#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
1288#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
1289
1290#define BCE_PCI_ID_VAL5 0x00000444
1291#define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
1292#define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
1293#define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
1294#define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
1295#define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
1296#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
1297
1298#define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448
1299#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
1300#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
1301#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
1302#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
1303
1304#define BCE_PCI_ID_VAL6 0x0000044c
1305#define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
1306#define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
1307#define BCE_PCI_ID_VAL6_BIST (0xffL<<16)
1308
1309#define BCE_PCI_MSI_DATA 0x00000450
1310#define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
1311
1312#define BCE_PCI_MSI_ADDR_H 0x00000454
1313#define BCE_PCI_MSI_ADDR_L 0x00000458
1314
1315
1316/*
1317 * misc_reg definition
1318 * offset: 0x800
1319 */
1320#define BCE_MISC_COMMAND 0x00000800
1321#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0)
1322#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1)
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1323#define BCE_MISC_COMMAND_SW_RESET (1L<<4)
1324#define BCE_MISC_COMMAND_POR_RESET (1L<<5)
1325#define BCE_MISC_COMMAND_HD_RESET (1L<<6)
1326#define BCE_MISC_COMMAND_CMN_SW_RESET (1L<<7)
43c2aeb0 1327#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8)
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1328#define BCE_MISC_COMMAND_CS16_ERR (1L<<9)
1329#define BCE_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
43c2aeb0 1330#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
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1331#define BCE_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
1332#define BCE_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
1333#define BCE_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
1334#define BCE_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
1335#define BCE_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
1336#define BCE_MISC_COMMAND_PCIE_DIS (1L<<28)
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1337
1338#define BCE_MISC_CFG 0x00000804
d0092544 1339#define BCE_MISC_CFG_GRC_TMOUT (1L<<0)
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1340#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1)
1341#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1342#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1343#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1344#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1345#define BCE_MISC_CFG_BIST_EN (1L<<3)
1346#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
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1347#define BCE_MISC_CFG_RESERVED5_TE (1L<<5)
1348#define BCE_MISC_CFG_RESERVED6_TE (1L<<6)
43c2aeb0 1349#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
d0092544 1350#define BCE_MISC_CFG_LEDMODE (0x7L<<8)
43c2aeb0 1351#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8)
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1352#define BCE_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
1353#define BCE_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
1354#define BCE_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
1355#define BCE_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
1356#define BCE_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
1357#define BCE_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
1358#define BCE_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
1359#define BCE_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
1360#define BCE_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
1361#define BCE_MISC_CFG_LEDMODE_XI (0xfL<<8)
1362#define BCE_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
1363#define BCE_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
1364#define BCE_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
1365#define BCE_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
1366#define BCE_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
1367#define BCE_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
1368#define BCE_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
1369#define BCE_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
1370#define BCE_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
1371#define BCE_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
1372#define BCE_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
1373#define BCE_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
1374#define BCE_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
1375#define BCE_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
1376#define BCE_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
1377#define BCE_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
1378#define BCE_MISC_CFG_PORT_SELECT_XI (1L<<13)
1379#define BCE_MISC_CFG_PARITY_MODE_XI (1L<<14)
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1380
1381#define BCE_MISC_ID 0x00000808
1382#define BCE_MISC_ID_BOND_ID (0xfL<<0)
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1383#define BCE_MISC_ID_BOND_ID_X (0L<<0)
1384#define BCE_MISC_ID_BOND_ID_C (3L<<0)
1385#define BCE_MISC_ID_BOND_ID_S (12L<<0)
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1386#define BCE_MISC_ID_CHIP_METAL (0xffL<<4)
1387#define BCE_MISC_ID_CHIP_REV (0xfL<<12)
1388#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16)
1389
1390#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c
1391#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1392#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1393#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1394#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1395#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1396#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1397#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1398#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1399#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1400#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1401#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1402#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1403#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1404#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1405#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1406#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1407#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1408#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1409#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1410#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1411#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1412#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1413#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1414#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1415#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1416#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1417#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1418#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
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1419#define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1420#define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
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1421
1422#define BCE_MISC_ENABLE_SET_BITS 0x00000810
1423#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1424#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1425#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1426#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1427#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1428#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1429#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1430#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1431#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1432#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1433#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1434#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1435#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1436#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1437#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1438#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1439#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1440#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1441#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1442#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1443#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1444#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1445#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1446#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1447#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1448#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1449#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1450#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
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1451#define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1452#define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1453
1454#define BCE_MISC_ENABLE_DEFAULT 0x05ffffff
1455#define BCE_MISC_ENABLE_DEFAULT_XI 0x17ffffff
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1456
1457#define BCE_MISC_ENABLE_CLR_BITS 0x00000814
1458#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1459#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1460#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1461#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1462#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1463#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1464#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1465#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1466#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1467#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1468#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1469#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1470#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1471#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1472#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1473#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1474#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1475#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1476#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1477#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1478#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1479#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1480#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1481#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1482#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1483#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1484#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1485#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
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1486#define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1487#define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1488
1489#define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff
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1490
1491#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818
1492#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1493#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1494#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1495#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1496#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1497#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1498#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1499#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1500#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1501#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1502#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1503#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1504#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1505#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1506#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1507#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1508#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
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1509#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8)
1510#define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
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1511#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1512#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1513#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1514#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1515#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1516#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
d0092544 1517#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12)
43c2aeb0 1518#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
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1519#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
1520#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
1521#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
1522#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20)
1523#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
1524#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18)
1525#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24)
1526#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
1527#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28)
1528
1529#define BCE_MISC_SPIO 0x0000081c
1530#define BCE_MISC_SPIO_VALUE (0xffL<<0)
1531#define BCE_MISC_SPIO_SET (0xffL<<8)
1532#define BCE_MISC_SPIO_CLR (0xffL<<16)
1533#define BCE_MISC_SPIO_FLOAT (0xffL<<24)
1534
1535#define BCE_MISC_SPIO_INT 0x00000820
1536#define BCE_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0)
1537#define BCE_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8)
1538#define BCE_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16)
1539#define BCE_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24)
1540#define BCE_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0)
1541#define BCE_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8)
1542#define BCE_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16)
1543#define BCE_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24)
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1544
1545#define BCE_MISC_CONFIG_LFSR 0x00000824
1546#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
1547
1548#define BCE_MISC_LFSR_MASK_BITS 0x00000828
1549#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1550#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1551#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1552#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1553#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
1554#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
1555#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1556#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1557#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1558#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
1559#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1560#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1561#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
1562#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
1563#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1564#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
1565#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1566#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
1567#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
1568#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
1569#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1570#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1571#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1572#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1573#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1574#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1575#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1576#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
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1577#define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1578#define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
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1579
1580#define BCE_MISC_ARB_REQ0 0x0000082c
1581#define BCE_MISC_ARB_REQ1 0x00000830
1582#define BCE_MISC_ARB_REQ2 0x00000834
1583#define BCE_MISC_ARB_REQ3 0x00000838
1584#define BCE_MISC_ARB_REQ4 0x0000083c
1585#define BCE_MISC_ARB_FREE0 0x00000840
1586#define BCE_MISC_ARB_FREE1 0x00000844
1587#define BCE_MISC_ARB_FREE2 0x00000848
1588#define BCE_MISC_ARB_FREE3 0x0000084c
1589#define BCE_MISC_ARB_FREE4 0x00000850
1590#define BCE_MISC_ARB_REQ_STATUS0 0x00000854
1591#define BCE_MISC_ARB_REQ_STATUS1 0x00000858
1592#define BCE_MISC_ARB_REQ_STATUS2 0x0000085c
1593#define BCE_MISC_ARB_REQ_STATUS3 0x00000860
1594#define BCE_MISC_ARB_REQ_STATUS4 0x00000864
1595#define BCE_MISC_ARB_GNT0 0x00000868
1596#define BCE_MISC_ARB_GNT0_0 (0x7L<<0)
1597#define BCE_MISC_ARB_GNT0_1 (0x7L<<4)
1598#define BCE_MISC_ARB_GNT0_2 (0x7L<<8)
1599#define BCE_MISC_ARB_GNT0_3 (0x7L<<12)
1600#define BCE_MISC_ARB_GNT0_4 (0x7L<<16)
1601#define BCE_MISC_ARB_GNT0_5 (0x7L<<20)
1602#define BCE_MISC_ARB_GNT0_6 (0x7L<<24)
1603#define BCE_MISC_ARB_GNT0_7 (0x7L<<28)
1604
1605#define BCE_MISC_ARB_GNT1 0x0000086c
1606#define BCE_MISC_ARB_GNT1_8 (0x7L<<0)
1607#define BCE_MISC_ARB_GNT1_9 (0x7L<<4)
1608#define BCE_MISC_ARB_GNT1_10 (0x7L<<8)
1609#define BCE_MISC_ARB_GNT1_11 (0x7L<<12)
1610#define BCE_MISC_ARB_GNT1_12 (0x7L<<16)
1611#define BCE_MISC_ARB_GNT1_13 (0x7L<<20)
1612#define BCE_MISC_ARB_GNT1_14 (0x7L<<24)
1613#define BCE_MISC_ARB_GNT1_15 (0x7L<<28)
1614
1615#define BCE_MISC_ARB_GNT2 0x00000870
1616#define BCE_MISC_ARB_GNT2_16 (0x7L<<0)
1617#define BCE_MISC_ARB_GNT2_17 (0x7L<<4)
1618#define BCE_MISC_ARB_GNT2_18 (0x7L<<8)
1619#define BCE_MISC_ARB_GNT2_19 (0x7L<<12)
1620#define BCE_MISC_ARB_GNT2_20 (0x7L<<16)
1621#define BCE_MISC_ARB_GNT2_21 (0x7L<<20)
1622#define BCE_MISC_ARB_GNT2_22 (0x7L<<24)
1623#define BCE_MISC_ARB_GNT2_23 (0x7L<<28)
1624
1625#define BCE_MISC_ARB_GNT3 0x00000874
1626#define BCE_MISC_ARB_GNT3_24 (0x7L<<0)
1627#define BCE_MISC_ARB_GNT3_25 (0x7L<<4)
1628#define BCE_MISC_ARB_GNT3_26 (0x7L<<8)
1629#define BCE_MISC_ARB_GNT3_27 (0x7L<<12)
1630#define BCE_MISC_ARB_GNT3_28 (0x7L<<16)
1631#define BCE_MISC_ARB_GNT3_29 (0x7L<<20)
1632#define BCE_MISC_ARB_GNT3_30 (0x7L<<24)
1633#define BCE_MISC_ARB_GNT3_31 (0x7L<<28)
1634
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1635#define BCE_MISC_RESERVED1 0x00000878
1636#define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0)
1637
1638#define BCE_MISC_RESERVED2 0x0000087c
1639#define BCE_MISC_RESERVED2_PCIE_DIS (1L<<0)
1640#define BCE_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
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1641
1642#define BCE_MISC_SM_ASF_CONTROL 0x00000880
1643#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1644#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
1645#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
1646#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
1647#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
1648#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
1649#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
1650#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
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1651#define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
1652#define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
1653#define BCE_MISC_SM_ASF_CONTROL_RES (0x3L<<10)
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SZ
1654#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
1655#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
1656#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
1657#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
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1658#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16)
1659#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23)
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1660#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
1661#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
1662
1663#define BCE_MISC_SMB_IN 0x00000884
1664#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0)
1665#define BCE_MISC_SMB_IN_RDY (1L<<8)
1666#define BCE_MISC_SMB_IN_DONE (1L<<9)
1667#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10)
1668#define BCE_MISC_SMB_IN_STATUS (0x7L<<11)
1669#define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11)
1670#define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
1671#define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
1672#define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
1673#define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
1674
1675#define BCE_MISC_SMB_OUT 0x00000888
1676#define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
1677#define BCE_MISC_SMB_OUT_RDY (1L<<8)
1678#define BCE_MISC_SMB_OUT_START (1L<<9)
1679#define BCE_MISC_SMB_OUT_LAST (1L<<10)
1680#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1681#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12)
1682#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1683#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1684#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1685#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1686#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
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1687#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1688#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1689#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1690#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
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1691#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
1692#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
43c2aeb0 1693#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
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1694#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1695#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1696#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1697#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1698#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1699
1700#define BCE_MISC_SMB_WATCHDOG 0x0000088c
1701#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
1702
1703#define BCE_MISC_SMB_HEARTBEAT 0x00000890
1704#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
1705
1706#define BCE_MISC_SMB_POLL_ASF 0x00000894
1707#define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
1708
1709#define BCE_MISC_SMB_POLL_LEGACY 0x00000898
1710#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
1711
1712#define BCE_MISC_SMB_RETRAN 0x0000089c
1713#define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
1714
1715#define BCE_MISC_SMB_TIMESTAMP 0x000008a0
1716#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
1717
1718#define BCE_MISC_PERR_ENA0 0x000008a4
1719#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1720#define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
1721#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
1722#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
1723#define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
1724#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
1725#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
1726#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
1727#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
1728#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
1729#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
1730#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
1731#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
1732#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
1733#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
1734#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
1735#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
1736#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
1737#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
1738#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
1739#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
1740#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
1741#define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
1742#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
1743#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1744#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1745#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1746#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1747#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1748#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1749#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1750#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
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1751#define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
1752#define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
1753#define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
1754#define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
1755#define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
1756#define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
1757#define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
1758#define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
1759#define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
1760#define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
1761#define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
1762#define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
1763#define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
1764#define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
1765#define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
1766#define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
1767#define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
1768#define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
1769#define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
1770#define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
1771#define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
1772#define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
1773#define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
1774#define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
1775#define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
1776#define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
1777#define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
1778#define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
1779#define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
1780#define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
1781#define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
1782#define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
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1783
1784#define BCE_MISC_PERR_ENA1 0x000008a8
1785#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1786#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1787#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1788#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1789#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1790#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1791#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1792#define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1793#define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1794#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1795#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1796#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1797#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1798#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1799#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1800#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1801#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1802#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1803#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1804#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1805#define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1806#define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1807#define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1808#define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1809#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1810#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1811#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1812#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1813#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1814#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1815#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1816#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
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1817#define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
1818#define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
1819#define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
1820#define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
1821#define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
1822#define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
1823#define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
1824#define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
1825#define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
1826#define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
1827#define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
1828#define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
1829#define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
1830#define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
1831#define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
1832#define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
1833#define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
1834#define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
1835#define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
1836#define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
1837#define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
1838#define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
1839#define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
1840#define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
1841#define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
1842#define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
1843#define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
1844#define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
1845#define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
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1846
1847#define BCE_MISC_PERR_ENA2 0x000008ac
1848#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1849#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1850#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1851#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1852#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1853#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1854#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1855#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1856#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
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1857#define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
1858#define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
1859#define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
1860#define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
1861#define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
1862#define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
1863#define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
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1864
1865#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0
1866#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1867#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
d0092544 1868#define BCE_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15)
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1869
1870#define BCE_MISC_VREG_CONTROL 0x000008b4
1871#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0)
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1872#define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0)
1873#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
1874#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
1875#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
1876#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
1877#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
1878#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
1879#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
1880#define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
1881#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
1882#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
1883#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
1884#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
1885#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
1886#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
1887#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
1888#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
43c2aeb0 1889#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4)
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1890#define BCE_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
1891#define BCE_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
1892#define BCE_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
1893#define BCE_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
1894#define BCE_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
1895#define BCE_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
1896#define BCE_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
1897#define BCE_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
1898#define BCE_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
1899#define BCE_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
1900#define BCE_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
1901#define BCE_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
1902#define BCE_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
1903#define BCE_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
1904#define BCE_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
1905#define BCE_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
1906#define BCE_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8)
1907#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
1908#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
1909#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
1910#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
1911#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
1912#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
1913#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
1914#define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
1915#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
1916#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
1917#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
1918#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
1919#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
1920#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
1921#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
1922#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
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1923
1924#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1925#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1926
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1927#define BCE_MISC_GP_HW_CTL0 0x000008bc
1928#define BCE_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
1929#define BCE_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
1930#define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
1931#define BCE_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
1932#define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
1933#define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
1934#define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
1935#define BCE_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4)
1936#define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
1937#define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
1938#define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
1939#define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
1940#define BCE_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8)
1941#define BCE_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
1942#define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
1943#define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
1944#define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
1945#define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
1946#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16)
1947#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
1948#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
1949#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
1950#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
1951#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
1952#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
1953#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
1954#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
1955#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22)
1956#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
1957#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
1958#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
1959#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
1960#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24)
1961#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
1962#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
1963#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
1964#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
1965#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26)
1966#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
1967#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
1968#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
1969#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
1970#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28)
1971#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
1972#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
1973#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
1974#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
1975#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30)
1976#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
1977#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
1978#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
1979#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
1980
1981#define BCE_MISC_GP_HW_CTL1 0x000008c0
1982#define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
1983#define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
1984#define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
1985#define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
1986#define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0)
1987#define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16)
1988
1989#define BCE_MISC_NEW_HW_CTL 0x000008c4
1990#define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
1991#define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
1992#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
1993#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
1994#define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4)
1995#define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16)
1996
1997#define BCE_MISC_NEW_CORE_CTL 0x000008c8
1998#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
1999#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
2000#define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
2001#define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
2002#define BCE_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
2003
2004#define BCE_MISC_ECO_HW_CTL 0x000008cc
2005#define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
2006#define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1)
2007#define BCE_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16)
2008
2009#define BCE_MISC_ECO_CORE_CTL 0x000008d0
2010#define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0)
2011#define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16)
2012
2013#define BCE_MISC_PPIO 0x000008d4
2014#define BCE_MISC_PPIO_VALUE (0xfL<<0)
2015#define BCE_MISC_PPIO_SET (0xfL<<8)
2016#define BCE_MISC_PPIO_CLR (0xfL<<16)
2017#define BCE_MISC_PPIO_FLOAT (0xfL<<24)
2018
2019#define BCE_MISC_PPIO_INT 0x000008d8
2020#define BCE_MISC_PPIO_INT_INT_STATE (0xfL<<0)
2021#define BCE_MISC_PPIO_INT_OLD_VALUE (0xfL<<8)
2022#define BCE_MISC_PPIO_INT_OLD_SET (0xfL<<16)
2023#define BCE_MISC_PPIO_INT_OLD_CLR (0xfL<<24)
2024
2025#define BCE_MISC_RESET_NUMS 0x000008dc
2026#define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0)
2027#define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4)
2028#define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8)
2029#define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12)
2030#define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16)
2031
2032#define BCE_MISC_CS16_ERR 0x000008e0
2033#define BCE_MISC_CS16_ERR_ENA_PCI (1L<<0)
2034#define BCE_MISC_CS16_ERR_ENA_RDMA (1L<<1)
2035#define BCE_MISC_CS16_ERR_ENA_TDMA (1L<<2)
2036#define BCE_MISC_CS16_ERR_ENA_EMAC (1L<<3)
2037#define BCE_MISC_CS16_ERR_ENA_CTX (1L<<4)
2038#define BCE_MISC_CS16_ERR_ENA_TBDR (1L<<5)
2039#define BCE_MISC_CS16_ERR_ENA_RBDC (1L<<6)
2040#define BCE_MISC_CS16_ERR_ENA_COM (1L<<7)
2041#define BCE_MISC_CS16_ERR_ENA_CP (1L<<8)
2042#define BCE_MISC_CS16_ERR_STA_PCI (1L<<16)
2043#define BCE_MISC_CS16_ERR_STA_RDMA (1L<<17)
2044#define BCE_MISC_CS16_ERR_STA_TDMA (1L<<18)
2045#define BCE_MISC_CS16_ERR_STA_EMAC (1L<<19)
2046#define BCE_MISC_CS16_ERR_STA_CTX (1L<<20)
2047#define BCE_MISC_CS16_ERR_STA_TBDR (1L<<21)
2048#define BCE_MISC_CS16_ERR_STA_RBDC (1L<<22)
2049#define BCE_MISC_CS16_ERR_STA_COM (1L<<23)
2050#define BCE_MISC_CS16_ERR_STA_CP (1L<<24)
2051
2052#define BCE_MISC_SPIO_EVENT 0x000008e4
2053#define BCE_MISC_SPIO_EVENT_ENABLE (0xffL<<0)
2054
2055#define BCE_MISC_PPIO_EVENT 0x000008e8
2056#define BCE_MISC_PPIO_EVENT_ENABLE (0xfL<<0)
2057
2058#define BCE_MISC_DUAL_MEDIA_CTRL 0x000008ec
2059#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
2060#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
2061#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
2062#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
2063#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
2064#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
2065#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
2066#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
2067#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
2068#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
2069#define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
2070#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
2071#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
2072#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
2073#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
2074#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
2075#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
2076#define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
2077#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
2078#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
2079#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
2080#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
2081#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
2082
2083#define BCE_MISC_OTP_CMD1 0x000008f0
2084#define BCE_MISC_OTP_CMD1_FMODE (0x7L<<0)
2085#define BCE_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
2086#define BCE_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
2087#define BCE_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
2088#define BCE_MISC_OTP_CMD1_FMODE_SET (3L<<0)
2089#define BCE_MISC_OTP_CMD1_FMODE_RST (4L<<0)
2090#define BCE_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
2091#define BCE_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
2092#define BCE_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
2093#define BCE_MISC_OTP_CMD1_USEPINS (1L<<8)
2094#define BCE_MISC_OTP_CMD1_PROGSEL (1L<<9)
2095#define BCE_MISC_OTP_CMD1_PROGSTART (1L<<10)
2096#define BCE_MISC_OTP_CMD1_PCOUNT (0x7L<<16)
2097#define BCE_MISC_OTP_CMD1_PBYP (1L<<19)
2098#define BCE_MISC_OTP_CMD1_VSEL (0xfL<<20)
2099#define BCE_MISC_OTP_CMD1_TM (0x7L<<27)
2100#define BCE_MISC_OTP_CMD1_SADBYP (1L<<30)
2101#define BCE_MISC_OTP_CMD1_DEBUG (1L<<31)
2102
2103#define BCE_MISC_OTP_CMD2 0x000008f4
2104#define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0)
2105#define BCE_MISC_OTP_CMD2_DOSEL (0x7fL<<16)
2106#define BCE_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
2107#define BCE_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
2108#define BCE_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
2109
2110#define BCE_MISC_OTP_STATUS 0x000008f8
2111#define BCE_MISC_OTP_STATUS_DATA (0xffL<<0)
2112#define BCE_MISC_OTP_STATUS_VALID (1L<<8)
2113#define BCE_MISC_OTP_STATUS_BUSY (1L<<9)
2114#define BCE_MISC_OTP_STATUS_BUSYSM (1L<<10)
2115#define BCE_MISC_OTP_STATUS_DONE (1L<<11)
2116
2117#define BCE_MISC_OTP_SHIFT1_CMD 0x000008fc
2118#define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
2119#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
2120#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
2121#define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
2122#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8)
2123
2124#define BCE_MISC_OTP_SHIFT1_DATA 0x00000900
2125#define BCE_MISC_OTP_SHIFT2_CMD 0x00000904
2126#define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
2127#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
2128#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
2129#define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
2130#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8)
2131
2132#define BCE_MISC_OTP_SHIFT2_DATA 0x00000908
2133#define BCE_MISC_BIST_CS0 0x0000090c
2134#define BCE_MISC_BIST_CS0_MBIST_EN (1L<<0)
2135#define BCE_MISC_BIST_CS0_BIST_SETUP (0x3L<<1)
2136#define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
2137#define BCE_MISC_BIST_CS0_MBIST_DONE (1L<<8)
2138#define BCE_MISC_BIST_CS0_MBIST_GO (1L<<9)
2139#define BCE_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
2140
2141#define BCE_MISC_BIST_MEMSTATUS0 0x00000910
2142#define BCE_MISC_BIST_CS1 0x00000914
2143#define BCE_MISC_BIST_CS1_MBIST_EN (1L<<0)
2144#define BCE_MISC_BIST_CS1_BIST_SETUP (0x3L<<1)
2145#define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
2146#define BCE_MISC_BIST_CS1_MBIST_DONE (1L<<8)
2147#define BCE_MISC_BIST_CS1_MBIST_GO (1L<<9)
2148
2149#define BCE_MISC_BIST_MEMSTATUS1 0x00000918
2150#define BCE_MISC_BIST_CS2 0x0000091c
2151#define BCE_MISC_BIST_CS2_MBIST_EN (1L<<0)
2152#define BCE_MISC_BIST_CS2_BIST_SETUP (0x3L<<1)
2153#define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
2154#define BCE_MISC_BIST_CS2_MBIST_DONE (1L<<8)
2155#define BCE_MISC_BIST_CS2_MBIST_GO (1L<<9)
2156
2157#define BCE_MISC_BIST_MEMSTATUS2 0x00000920
2158#define BCE_MISC_BIST_CS3 0x00000924
2159#define BCE_MISC_BIST_CS3_MBIST_EN (1L<<0)
2160#define BCE_MISC_BIST_CS3_BIST_SETUP (0x3L<<1)
2161#define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
2162#define BCE_MISC_BIST_CS3_MBIST_DONE (1L<<8)
2163#define BCE_MISC_BIST_CS3_MBIST_GO (1L<<9)
2164
2165#define BCE_MISC_BIST_MEMSTATUS3 0x00000928
2166#define BCE_MISC_BIST_CS4 0x0000092c
2167#define BCE_MISC_BIST_CS4_MBIST_EN (1L<<0)
2168#define BCE_MISC_BIST_CS4_BIST_SETUP (0x3L<<1)
2169#define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
2170#define BCE_MISC_BIST_CS4_MBIST_DONE (1L<<8)
2171#define BCE_MISC_BIST_CS4_MBIST_GO (1L<<9)
2172
2173#define BCE_MISC_BIST_MEMSTATUS4 0x00000930
2174#define BCE_MISC_BIST_CS5 0x00000934
2175#define BCE_MISC_BIST_CS5_MBIST_EN (1L<<0)
2176#define BCE_MISC_BIST_CS5_BIST_SETUP (0x3L<<1)
2177#define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
2178#define BCE_MISC_BIST_CS5_MBIST_DONE (1L<<8)
2179#define BCE_MISC_BIST_CS5_MBIST_GO (1L<<9)
2180
2181#define BCE_MISC_BIST_MEMSTATUS5 0x00000938
2182#define BCE_MISC_MEM_TM0 0x0000093c
2183#define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0)
2184#define BCE_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8)
2185#define BCE_MISC_MEM_TM0_UMP_TM (0xffL<<16)
2186#define BCE_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24)
2187
2188#define BCE_MISC_USPLL_CTRL 0x00000940
2189#define BCE_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
2190#define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
2191#define BCE_MISC_USPLL_CTRL_LCPX (0x3fL<<2)
2192#define BCE_MISC_USPLL_CTRL_RX (0x3L<<8)
2193#define BCE_MISC_USPLL_CTRL_VC_EN (1L<<10)
2194#define BCE_MISC_USPLL_CTRL_VCO_MG (0x3L<<11)
2195#define BCE_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13)
2196#define BCE_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16)
2197#define BCE_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
2198#define BCE_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20)
2199#define BCE_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
2200#define BCE_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24)
2201#define BCE_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
2202#define BCE_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
2203#define BCE_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
2204#define BCE_MISC_USPLL_CTRL_LOCK (1L<<29)
2205
2206#define BCE_MISC_PERR_STATUS0 0x00000944
2207#define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
2208#define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
2209#define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
2210#define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
2211#define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
2212#define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
2213#define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
2214#define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
2215#define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
2216#define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
2217#define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
2218#define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
2219#define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
2220#define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
2221#define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
2222#define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
2223#define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
2224#define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
2225#define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
2226#define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
2227#define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
2228#define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
2229#define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
2230#define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
2231#define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
2232#define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
2233#define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
2234#define BCE_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
2235#define BCE_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
2236#define BCE_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
2237#define BCE_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
2238#define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
2239
2240#define BCE_MISC_PERR_STATUS1 0x00000948
2241#define BCE_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
2242#define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
2243#define BCE_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
2244#define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
2245#define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
2246#define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
2247#define BCE_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
2248#define BCE_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
2249#define BCE_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
2250#define BCE_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
2251#define BCE_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
2252#define BCE_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
2253#define BCE_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
2254#define BCE_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
2255#define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
2256#define BCE_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
2257#define BCE_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
2258#define BCE_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
2259#define BCE_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
2260#define BCE_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
2261#define BCE_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
2262#define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
2263#define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
2264#define BCE_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
2265#define BCE_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
2266#define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
2267#define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
2268#define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
2269#define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
2270
2271#define BCE_MISC_PERR_STATUS2 0x0000094c
2272#define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
2273#define BCE_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
2274#define BCE_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
2275#define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
2276#define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
2277#define BCE_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
2278#define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
2279
2280#define BCE_MISC_LCPLL_CTRL0 0x00000950
2281#define BCE_MISC_LCPLL_CTRL0_OAC (0x7L<<0)
2282#define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
2283#define BCE_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
2284#define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
2285#define BCE_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
2286#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3)
2287#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
2288#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
2289#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
2290#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
2291#define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6)
2292#define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8)
2293#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11)
2294#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
2295#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
2296#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
2297#define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
2298#define BCE_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
2299#define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
2300#define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
2301#define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
2302#define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
2303#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
2304#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
2305#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
2306#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
2307#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
2308#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
2309#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
2310#define BCE_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
2311#define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
2312
2313#define BCE_MISC_LCPLL_CTRL1 0x00000954
2314#define BCE_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0)
2315#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
2316#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
2317#define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
2318
2319#define BCE_MISC_LCPLL_STATUS 0x00000958
2320#define BCE_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
2321#define BCE_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
2322#define BCE_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
2323#define BCE_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
2324#define BCE_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4)
2325#define BCE_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7)
2326#define BCE_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10)
2327#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
2328#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
2329#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
2330
2331#define BCE_MISC_OSCFUNDS_CTRL 0x0000095c
2332#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
2333#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
2334#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
2335#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6)
2336#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
2337#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
2338#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
2339#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
2340#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8)
2341#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
2342#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
2343#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
2344#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
2345#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10)
2346#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
2347#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
2348#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
2349#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
43c2aeb0
SZ
2350
2351
2352/*
2353 * dma_reg definition
2354 * offset: 0xc00
2355 */
2356#define BCE_DMA_COMMAND 0x00000c00
2357#define BCE_DMA_COMMAND_ENABLE (1L<<0)
2358
2359#define BCE_DMA_STATUS 0x00000c04
2360#define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
2361#define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
2362#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
2363#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
2364#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
2365#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
2366#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
2367#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
2368#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
2369#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
2370#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
2371
2372#define BCE_DMA_CONFIG 0x00000c08
2373#define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
2374#define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
2375#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
2376#define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
2377#define BCE_DMA_CONFIG_ONE_DMA (1L<<6)
2378#define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
2379#define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
2380#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
2381#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
2382#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
2383#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
2384#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
2385#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
2386#define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24)
2387#define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
2388#define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
2389#define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
2390#define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
2391#define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
2392
2393#define BCE_DMA_BLACKOUT 0x00000c0c
2394#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
2395#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
2396#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
2397
2398#define BCE_DMA_RCHAN_STAT 0x00000c30
2399#define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
2400#define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
2401#define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
2402#define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
2403#define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
2404#define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
2405#define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
2406#define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
2407#define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
2408#define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
2409#define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
2410#define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
2411#define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
2412#define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
2413#define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
2414#define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
2415
2416#define BCE_DMA_WCHAN_STAT 0x00000c34
2417#define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
2418#define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
2419#define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
2420#define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
2421#define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
2422#define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
2423#define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
2424#define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
2425#define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
2426#define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
2427#define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
2428#define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
2429#define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
2430#define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
2431#define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
2432#define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
2433
2434#define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38
2435#define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
2436#define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
2437#define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
2438#define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
2439#define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
2440#define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
2441#define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
2442#define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
2443
2444#define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c
2445#define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
2446#define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
2447#define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
2448#define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
2449#define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
2450#define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
2451#define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
2452#define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
2453
2454#define BCE_DMA_RCHAN_STAT_00 0x00000c40
2455#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
2456
2457#define BCE_DMA_RCHAN_STAT_01 0x00000c44
2458#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
2459
2460#define BCE_DMA_RCHAN_STAT_02 0x00000c48
2461#define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
2462#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
2463#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
2464#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
2465
2466#define BCE_DMA_RCHAN_STAT_10 0x00000c4c
2467#define BCE_DMA_RCHAN_STAT_11 0x00000c50
2468#define BCE_DMA_RCHAN_STAT_12 0x00000c54
2469#define BCE_DMA_RCHAN_STAT_20 0x00000c58
2470#define BCE_DMA_RCHAN_STAT_21 0x00000c5c
2471#define BCE_DMA_RCHAN_STAT_22 0x00000c60
2472#define BCE_DMA_RCHAN_STAT_30 0x00000c64
2473#define BCE_DMA_RCHAN_STAT_31 0x00000c68
2474#define BCE_DMA_RCHAN_STAT_32 0x00000c6c
2475#define BCE_DMA_RCHAN_STAT_40 0x00000c70
2476#define BCE_DMA_RCHAN_STAT_41 0x00000c74
2477#define BCE_DMA_RCHAN_STAT_42 0x00000c78
2478#define BCE_DMA_RCHAN_STAT_50 0x00000c7c
2479#define BCE_DMA_RCHAN_STAT_51 0x00000c80
2480#define BCE_DMA_RCHAN_STAT_52 0x00000c84
2481#define BCE_DMA_RCHAN_STAT_60 0x00000c88
2482#define BCE_DMA_RCHAN_STAT_61 0x00000c8c
2483#define BCE_DMA_RCHAN_STAT_62 0x00000c90
2484#define BCE_DMA_RCHAN_STAT_70 0x00000c94
2485#define BCE_DMA_RCHAN_STAT_71 0x00000c98
2486#define BCE_DMA_RCHAN_STAT_72 0x00000c9c
2487#define BCE_DMA_WCHAN_STAT_00 0x00000ca0
2488#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
2489
2490#define BCE_DMA_WCHAN_STAT_01 0x00000ca4
2491#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
2492
2493#define BCE_DMA_WCHAN_STAT_02 0x00000ca8
2494#define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
2495#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
2496#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
2497#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
2498
2499#define BCE_DMA_WCHAN_STAT_10 0x00000cac
2500#define BCE_DMA_WCHAN_STAT_11 0x00000cb0
2501#define BCE_DMA_WCHAN_STAT_12 0x00000cb4
2502#define BCE_DMA_WCHAN_STAT_20 0x00000cb8
2503#define BCE_DMA_WCHAN_STAT_21 0x00000cbc
2504#define BCE_DMA_WCHAN_STAT_22 0x00000cc0
2505#define BCE_DMA_WCHAN_STAT_30 0x00000cc4
2506#define BCE_DMA_WCHAN_STAT_31 0x00000cc8
2507#define BCE_DMA_WCHAN_STAT_32 0x00000ccc
2508#define BCE_DMA_WCHAN_STAT_40 0x00000cd0
2509#define BCE_DMA_WCHAN_STAT_41 0x00000cd4
2510#define BCE_DMA_WCHAN_STAT_42 0x00000cd8
2511#define BCE_DMA_WCHAN_STAT_50 0x00000cdc
2512#define BCE_DMA_WCHAN_STAT_51 0x00000ce0
2513#define BCE_DMA_WCHAN_STAT_52 0x00000ce4
2514#define BCE_DMA_WCHAN_STAT_60 0x00000ce8
2515#define BCE_DMA_WCHAN_STAT_61 0x00000cec
2516#define BCE_DMA_WCHAN_STAT_62 0x00000cf0
2517#define BCE_DMA_WCHAN_STAT_70 0x00000cf4
2518#define BCE_DMA_WCHAN_STAT_71 0x00000cf8
2519#define BCE_DMA_WCHAN_STAT_72 0x00000cfc
2520#define BCE_DMA_ARB_STAT_00 0x00000d00
2521#define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
2522#define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
2523#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
2524
2525#define BCE_DMA_ARB_STAT_01 0x00000d04
2526#define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
2527#define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
2528#define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
2529#define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
2530#define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
2531#define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
2532#define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
2533#define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
2534
2535#define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00
2536#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
2537#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
2538#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
2539#define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
2540#define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
2541
2542#define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04
2543#define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08
2544#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
2545#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
2546#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
2547#define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
2548#define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
2549
2550#define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c
2551#define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10
2552#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
2553#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
2554#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
2555#define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
2556#define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
2557
2558#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14
2559
2560
2561/*
2562 * context_reg definition
2563 * offset: 0x1000
2564 */
2565#define BCE_CTX_COMMAND 0x00001000
2566#define BCE_CTX_COMMAND_ENABLED (1L<<0)
d0092544
SZ
2567#define BCE_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
2568#define BCE_CTX_COMMAND_DISABLE_PLRU (1L<<2)
2569#define BCE_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
2570#define BCE_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
2571#define BCE_CTX_COMMAND_MEM_INIT (1L<<13)
2572#define BCE_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
2573#define BCE_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2574#define BCE_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
2575#define BCE_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
2576#define BCE_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
2577#define BCE_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
2578#define BCE_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
2579#define BCE_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
2580#define BCE_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
2581#define BCE_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
2582#define BCE_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
2583#define BCE_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
2584#define BCE_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
2585#define BCE_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
43c2aeb0
SZ
2586
2587#define BCE_CTX_STATUS 0x00001004
2588#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0)
2589#define BCE_CTX_STATUS_READ_STAT (1L<<16)
2590#define BCE_CTX_STATUS_WRITE_STAT (1L<<17)
2591#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18)
2592#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
d0092544
SZ
2593#define BCE_CTX_STATUS_EXT_READ_STAT (1L<<20)
2594#define BCE_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
2595#define BCE_CTX_STATUS_MISS_STAT (1L<<22)
2596#define BCE_CTX_STATUS_HIT_STAT (1L<<23)
2597#define BCE_CTX_STATUS_DEAD_LOCK (1L<<24)
2598#define BCE_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
2599#define BCE_CTX_STATUS_INVALID_PAGE (1L<<26)
43c2aeb0
SZ
2600
2601#define BCE_CTX_VIRT_ADDR 0x00001008
2602#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
2603
2604#define BCE_CTX_PAGE_TBL 0x0000100c
2605#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
2606
2607#define BCE_CTX_DATA_ADR 0x00001010
2608#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
2609
2610#define BCE_CTX_DATA 0x00001014
2611#define BCE_CTX_LOCK 0x00001018
2612#define BCE_CTX_LOCK_TYPE (0x7L<<0)
2613#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
43c2aeb0
SZ
2614#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
2615#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
2616#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
d0092544
SZ
2617#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
2618#define BCE_CTX_LOCK_TYPE_VOID_XI (0L<<0)
2619#define BCE_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
2620#define BCE_CTX_LOCK_TYPE_TX_XI (2L<<0)
2621#define BCE_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
2622#define BCE_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
43c2aeb0
SZ
2623#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7)
2624#define BCE_CTX_LOCK_GRANTED (1L<<26)
2625#define BCE_CTX_LOCK_MODE (0x7L<<27)
2626#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
2627#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
2628#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27)
2629#define BCE_CTX_LOCK_STATUS (1L<<30)
2630#define BCE_CTX_LOCK_REQ (1L<<31)
2631
d0092544
SZ
2632#define BCE_CTX_CTX_CTRL 0x0000101c
2633#define BCE_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
2634#define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
2635#define BCE_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
2636#define BCE_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
2637#define BCE_CTX_CTX_CTRL_ATTR (1L<<26)
2638#define BCE_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
2639#define BCE_CTX_CTX_CTRL_READ_REQ (1L<<31)
2640
2641#define BCE_CTX_CTX_DATA 0x00001020
43c2aeb0
SZ
2642#define BCE_CTX_ACCESS_STATUS 0x00001040
2643#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
2644#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
2645#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
2646#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
2647#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
d0092544
SZ
2648#define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
2649#define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
2650#define BCE_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
43c2aeb0
SZ
2651
2652#define BCE_CTX_DBG_LOCK_STATUS 0x00001044
2653#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
2654#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
2655
d0092544
SZ
2656#define BCE_CTX_CACHE_CTRL_STATUS 0x00001048
2657#define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
2658#define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
2659#define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
2660#define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7)
2661#define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13)
2662#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
2663#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
2664#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
2665#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
2666#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
2667#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
2668#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
2669#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
2670#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
2671#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
2672#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
2673
2674#define BCE_CTX_CACHE_CTRL_SM_STATUS 0x0000104c
2675#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0)
2676#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3)
2677#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6)
2678#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9)
2679#define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16)
2680
2681#define BCE_CTX_CACHE_STATUS 0x00001050
2682#define BCE_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0)
2683#define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16)
2684
2685#define BCE_CTX_DMA_STATUS 0x00001054
2686#define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0)
2687#define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2)
2688#define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4)
2689#define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6)
2690#define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8)
2691#define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10)
2692#define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12)
2693#define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14)
2694#define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16)
2695#define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18)
2696#define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20)
2697
2698#define BCE_CTX_REP_STATUS 0x00001058
2699#define BCE_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0)
2700#define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10)
2701#define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
2702#define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
2703#define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
2704
2705#define BCE_CTX_CKSUM_ERROR_STATUS 0x0000105c
2706#define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
2707#define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
2708
43c2aeb0
SZ
2709#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080
2710#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
2711#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
2712#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
d0092544
SZ
2713#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
2714#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15)
43c2aeb0
SZ
2715
2716#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084
2717#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088
2718#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c
2719#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090
2720#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094
2721#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098
2722#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c
2723#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0
d0092544
SZ
2724#define BCE_CTX_CHNL_LOCK_STATUS_9 0x000010a4
2725
2726#define BCE_CTX_CACHE_DATA 0x000010c4
2727#define BCE_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
2728#define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
2729#define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
2730#define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
2731
2732#define BCE_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
2733#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
2734#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
2735
2736#define BCE_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
2737#define BCE_CTX_CAM_CTRL 0x000010d4
2738#define BCE_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0)
2739#define BCE_CTX_CAM_CTRL_RESET (1L<<27)
2740#define BCE_CTX_CAM_CTRL_INVALIDATE (1L<<28)
2741#define BCE_CTX_CAM_CTRL_SEARCH (1L<<29)
2742#define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
2743#define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31)
43c2aeb0
SZ
2744
2745
2746/*
2747 * emac_reg definition
2748 * offset: 0x1400
2749 */
2750#define BCE_EMAC_MODE 0x00001400
2751#define BCE_EMAC_MODE_RESET (1L<<0)
2752#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1)
2753#define BCE_EMAC_MODE_PORT (0x3L<<2)
2754#define BCE_EMAC_MODE_PORT_NONE (0L<<2)
2755#define BCE_EMAC_MODE_PORT_MII (1L<<2)
2756#define BCE_EMAC_MODE_PORT_GMII (2L<<2)
2757#define BCE_EMAC_MODE_PORT_MII_10 (3L<<2)
2758#define BCE_EMAC_MODE_MAC_LOOP (1L<<4)
2759#define BCE_EMAC_MODE_25G (1L<<5)
2760#define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
2761#define BCE_EMAC_MODE_TX_BURST (1L<<8)
2762#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
2763#define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10)
2764#define BCE_EMAC_MODE_FORCE_LINK (1L<<11)
2765#define BCE_EMAC_MODE_MPKT (1L<<18)
2766#define BCE_EMAC_MODE_MPKT_RCVD (1L<<19)
2767#define BCE_EMAC_MODE_ACPI_RCVD (1L<<20)
2768
2769#define BCE_EMAC_STATUS 0x00001404
2770#define BCE_EMAC_STATUS_LINK (1L<<11)
2771#define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12)
2772#define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22)
2773#define BCE_EMAC_STATUS_MI_INT (1L<<23)
2774#define BCE_EMAC_STATUS_AP_ERROR (1L<<24)
2775#define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
2776
2777#define BCE_EMAC_ATTENTION_ENA 0x00001408
2778#define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11)
2779#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
2780#define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
2781#define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
2782
2783#define BCE_EMAC_LED 0x0000140c
2784#define BCE_EMAC_LED_OVERRIDE (1L<<0)
2785#define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1)
2786#define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2)
2787#define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3)
2788#define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
2789#define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5)
2790#define BCE_EMAC_LED_TRAFFIC (1L<<6)
2791#define BCE_EMAC_LED_1000MB (1L<<7)
2792#define BCE_EMAC_LED_100MB (1L<<8)
2793#define BCE_EMAC_LED_10MB (1L<<9)
2794#define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10)
2795#define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19)
2796#define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31)
2797
2798#define BCE_EMAC_MAC_MATCH0 0x00001410
2799#define BCE_EMAC_MAC_MATCH1 0x00001414
2800#define BCE_EMAC_MAC_MATCH2 0x00001418
2801#define BCE_EMAC_MAC_MATCH3 0x0000141c
2802#define BCE_EMAC_MAC_MATCH4 0x00001420
2803#define BCE_EMAC_MAC_MATCH5 0x00001424
2804#define BCE_EMAC_MAC_MATCH6 0x00001428
2805#define BCE_EMAC_MAC_MATCH7 0x0000142c
2806#define BCE_EMAC_MAC_MATCH8 0x00001430
2807#define BCE_EMAC_MAC_MATCH9 0x00001434
2808#define BCE_EMAC_MAC_MATCH10 0x00001438
2809#define BCE_EMAC_MAC_MATCH11 0x0000143c
2810#define BCE_EMAC_MAC_MATCH12 0x00001440
2811#define BCE_EMAC_MAC_MATCH13 0x00001444
2812#define BCE_EMAC_MAC_MATCH14 0x00001448
2813#define BCE_EMAC_MAC_MATCH15 0x0000144c
2814#define BCE_EMAC_MAC_MATCH16 0x00001450
2815#define BCE_EMAC_MAC_MATCH17 0x00001454
2816#define BCE_EMAC_MAC_MATCH18 0x00001458
2817#define BCE_EMAC_MAC_MATCH19 0x0000145c
2818#define BCE_EMAC_MAC_MATCH20 0x00001460
2819#define BCE_EMAC_MAC_MATCH21 0x00001464
2820#define BCE_EMAC_MAC_MATCH22 0x00001468
2821#define BCE_EMAC_MAC_MATCH23 0x0000146c
2822#define BCE_EMAC_MAC_MATCH24 0x00001470
2823#define BCE_EMAC_MAC_MATCH25 0x00001474
2824#define BCE_EMAC_MAC_MATCH26 0x00001478
2825#define BCE_EMAC_MAC_MATCH27 0x0000147c
2826#define BCE_EMAC_MAC_MATCH28 0x00001480
2827#define BCE_EMAC_MAC_MATCH29 0x00001484
2828#define BCE_EMAC_MAC_MATCH30 0x00001488
2829#define BCE_EMAC_MAC_MATCH31 0x0000148c
2830#define BCE_EMAC_BACKOFF_SEED 0x00001498
2831#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
2832
2833#define BCE_EMAC_RX_MTU_SIZE 0x0000149c
2834#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
2835#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
2836
2837#define BCE_EMAC_SERDES_CNTL 0x000014a4
2838#define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0)
2839#define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3)
2840#define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
2841#define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
2842#define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10)
2843#define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11)
2844#define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12)
2845#define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
2846#define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
2847#define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
2848#define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
2849#define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
2850#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
2851#define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
2852#define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
2853#define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
2854
2855#define BCE_EMAC_SERDES_STATUS 0x000014a8
2856#define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
2857#define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
2858
2859#define BCE_EMAC_MDIO_COMM 0x000014ac
2860#define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0)
2861#define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
2862#define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
2863#define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
2864#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2865#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
2866#define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
2867#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
2868#define BCE_EMAC_MDIO_COMM_FAIL (1L<<28)
2869#define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29)
2870#define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30)
2871
2872#define BCE_EMAC_MDIO_STATUS 0x000014b0
2873#define BCE_EMAC_MDIO_STATUS_LINK (1L<<0)
2874#define BCE_EMAC_MDIO_STATUS_10MB (1L<<1)
2875
2876#define BCE_EMAC_MDIO_MODE 0x000014b4
2877#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
2878#define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
2879#define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
2880#define BCE_EMAC_MDIO_MODE_MDIO (1L<<9)
2881#define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
2882#define BCE_EMAC_MDIO_MODE_MDC (1L<<11)
2883#define BCE_EMAC_MDIO_MODE_MDINT (1L<<12)
2884#define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
2885
2886#define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8
2887#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
2888
2889#define BCE_EMAC_TX_MODE 0x000014bc
2890#define BCE_EMAC_TX_MODE_RESET (1L<<0)
2891#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
2892#define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4)
2893#define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
2894#define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
2895#define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7)
2896
2897#define BCE_EMAC_TX_STATUS 0x000014c0
2898#define BCE_EMAC_TX_STATUS_XOFFED (1L<<0)
2899#define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
2900#define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2)
2901#define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3)
2902#define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4)
2903
2904#define BCE_EMAC_TX_LENGTHS 0x000014c4
2905#define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
2906#define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8)
2907#define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
2908
2909#define BCE_EMAC_RX_MODE 0x000014c8
2910#define BCE_EMAC_RX_MODE_RESET (1L<<0)
2911#define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2)
2912#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
2913#define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
2914#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
2915#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
2916#define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7)
2917#define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
2918#define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
2919#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
2920#define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
2921#define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12)
2922
2923#define BCE_EMAC_RX_STATUS 0x000014cc
2924#define BCE_EMAC_RX_STATUS_FFED (1L<<0)
2925#define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
2926#define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
2927
2928#define BCE_EMAC_MULTICAST_HASH0 0x000014d0
2929#define BCE_EMAC_MULTICAST_HASH1 0x000014d4
2930#define BCE_EMAC_MULTICAST_HASH2 0x000014d8
2931#define BCE_EMAC_MULTICAST_HASH3 0x000014dc
2932#define BCE_EMAC_MULTICAST_HASH4 0x000014e0
2933#define BCE_EMAC_MULTICAST_HASH5 0x000014e4
2934#define BCE_EMAC_MULTICAST_HASH6 0x000014e8
2935#define BCE_EMAC_MULTICAST_HASH7 0x000014ec
2936#define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
2937#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
2938#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
2939#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
2940#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
2941#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
2942#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
2943#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
2944#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
2945#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
2946#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
2947#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
2948#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
2949#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
2950#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
2951#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
2952#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
2953#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
2954#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
2955#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
2956#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
2957#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
2958#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
2959#define BCE_EMAC_RXMAC_DEBUG0 0x0000155c
2960#define BCE_EMAC_RXMAC_DEBUG1 0x00001560
2961#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
2962#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
2963#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
2964#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
2965#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
2966#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
2967#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
2968#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
2969#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
2970
2971#define BCE_EMAC_RXMAC_DEBUG2 0x00001564
2972#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
2973#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
2974#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
2975#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
2976#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
2977#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
2978#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
2979#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
2980#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
2981#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
2982#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
2983#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
2984#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
2985#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
2986#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
2987#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
2988#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
2989#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
2990#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
2991#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
2992#define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
2993#define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
2994#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
2995#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2996#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
2997#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
2998#define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
2999
3000#define BCE_EMAC_RXMAC_DEBUG3 0x00001568
3001#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
3002#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
3003
3004#define BCE_EMAC_RXMAC_DEBUG4 0x0000156c
3005#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
3006#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
3007#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
3008#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
3009#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
3010#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
3011#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
3012#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
3013#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
3014#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
3015#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
3016#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
3017#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
3018#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
3019#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
3020#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
3021#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
3022#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
3023#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
3024#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
3025#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
3026#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
3027#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
3028#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
3029#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
3030#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
3031#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
3032#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
3033#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
3034#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
3035#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
3036#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
3037#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
3038#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
3039#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
3040#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
3041#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
3042#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
3043#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
3044#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
3045#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
3046#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
3047#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
3048#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
3049#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
3050#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
3051#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
3052#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
3053#define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28)
3054
3055#define BCE_EMAC_RXMAC_DEBUG5 0x00001570
3056#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
3057#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
3058#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
3059#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
3060#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
3061#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
3062#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
3063#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
3064#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
3065#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
3066#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
3067#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
3068#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
3069#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
3070#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
3071#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
3072#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
3073#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
3074#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
3075#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
3076#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
3077#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
3078#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
3079#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
3080#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
3081#define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
3082
3083#define BCE_EMAC_RX_STAT_AC0 0x00001580
3084#define BCE_EMAC_RX_STAT_AC1 0x00001584
3085#define BCE_EMAC_RX_STAT_AC2 0x00001588
3086#define BCE_EMAC_RX_STAT_AC3 0x0000158c
3087#define BCE_EMAC_RX_STAT_AC4 0x00001590
3088#define BCE_EMAC_RX_STAT_AC5 0x00001594
3089#define BCE_EMAC_RX_STAT_AC6 0x00001598
3090#define BCE_EMAC_RX_STAT_AC7 0x0000159c
3091#define BCE_EMAC_RX_STAT_AC8 0x000015a0
3092#define BCE_EMAC_RX_STAT_AC9 0x000015a4
3093#define BCE_EMAC_RX_STAT_AC10 0x000015a8
3094#define BCE_EMAC_RX_STAT_AC11 0x000015ac
3095#define BCE_EMAC_RX_STAT_AC12 0x000015b0
3096#define BCE_EMAC_RX_STAT_AC13 0x000015b4
3097#define BCE_EMAC_RX_STAT_AC14 0x000015b8
3098#define BCE_EMAC_RX_STAT_AC15 0x000015bc
3099#define BCE_EMAC_RX_STAT_AC16 0x000015c0
3100#define BCE_EMAC_RX_STAT_AC17 0x000015c4
3101#define BCE_EMAC_RX_STAT_AC18 0x000015c8
3102#define BCE_EMAC_RX_STAT_AC19 0x000015cc
3103#define BCE_EMAC_RX_STAT_AC20 0x000015d0
3104#define BCE_EMAC_RX_STAT_AC21 0x000015d4
3105#define BCE_EMAC_RX_STAT_AC22 0x000015d8
3106#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
3107#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
3108#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
3109#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
3110#define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c
3111#define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
3112#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
3113#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
3114#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
3115#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
3116#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
3117#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
3118#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
3119#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
3120#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
3121#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
3122#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
3123#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
3124#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
3125#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
3126#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
3127#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
3128#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
3129#define BCE_EMAC_TXMAC_DEBUG0 0x00001658
3130#define BCE_EMAC_TXMAC_DEBUG1 0x0000165c
3131#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
3132#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
3133#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
3134#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
3135#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
3136#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
3137#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
3138#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
3139#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
3140#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
3141#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
3142#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
3143#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
3144#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
3145#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
3146#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
3147#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
3148#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
3149#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
3150
3151#define BCE_EMAC_TXMAC_DEBUG2 0x00001660
3152#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
3153#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
3154#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
3155#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
3156
3157#define BCE_EMAC_TXMAC_DEBUG3 0x00001664
3158#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
3159#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
3160#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
3161#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
3162#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
3163#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
3164#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
3165#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
3166#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
3167#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
3168#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
3169#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
3170#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
3171#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
3172#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
3173#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
3174#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
3175#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
3176#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
3177#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
3178#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
3179#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
3180#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
3181#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
3182#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
3183#define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
3184#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
3185#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
3186
3187#define BCE_EMAC_TXMAC_DEBUG4 0x00001668
3188#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
3189#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
3190#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
3191#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
3192#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
3193#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
3194#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
3195#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
3196#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
3197#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
3198#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
3199#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
3200#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
3201#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
3202#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
3203#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
3204#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
3205#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
3206#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
3207#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
3208#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
3209#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
3210#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
3211#define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
3212#define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
3213#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
3214#define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31)
3215
3216#define BCE_EMAC_TX_STAT_AC0 0x00001680
3217#define BCE_EMAC_TX_STAT_AC1 0x00001684
3218#define BCE_EMAC_TX_STAT_AC2 0x00001688
3219#define BCE_EMAC_TX_STAT_AC3 0x0000168c
3220#define BCE_EMAC_TX_STAT_AC4 0x00001690
3221#define BCE_EMAC_TX_STAT_AC5 0x00001694
3222#define BCE_EMAC_TX_STAT_AC6 0x00001698
3223#define BCE_EMAC_TX_STAT_AC7 0x0000169c
3224#define BCE_EMAC_TX_STAT_AC8 0x000016a0
3225#define BCE_EMAC_TX_STAT_AC9 0x000016a4
3226#define BCE_EMAC_TX_STAT_AC10 0x000016a8
3227#define BCE_EMAC_TX_STAT_AC11 0x000016ac
3228#define BCE_EMAC_TX_STAT_AC12 0x000016b0
3229#define BCE_EMAC_TX_STAT_AC13 0x000016b4
3230#define BCE_EMAC_TX_STAT_AC14 0x000016b8
3231#define BCE_EMAC_TX_STAT_AC15 0x000016bc
3232#define BCE_EMAC_TX_STAT_AC16 0x000016c0
3233#define BCE_EMAC_TX_STAT_AC17 0x000016c4
3234#define BCE_EMAC_TX_STAT_AC18 0x000016c8
3235#define BCE_EMAC_TX_STAT_AC19 0x000016cc
3236#define BCE_EMAC_TX_STAT_AC20 0x000016d0
3237#define BCE_EMAC_TX_STAT_AC21 0x000016d4
3238#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
3239
3240
3241/*
3242 * rpm_reg definition
3243 * offset: 0x1800
3244 */
3245#define BCE_RPM_COMMAND 0x00001800
3246#define BCE_RPM_COMMAND_ENABLED (1L<<0)
3247#define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
3248
3249#define BCE_RPM_STATUS 0x00001804
3250#define BCE_RPM_STATUS_MBUF_WAIT (1L<<0)
3251#define BCE_RPM_STATUS_FREE_WAIT (1L<<1)
3252
3253#define BCE_RPM_CONFIG 0x00001808
3254#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
3255#define BCE_RPM_CONFIG_ACPI_ENA (1L<<1)
3256#define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2)
3257#define BCE_RPM_CONFIG_MP_KEEP (1L<<3)
3258#define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
3259#define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31)
3260
5d05a208
SZ
3261#define BCE_RPM_MGMT_PKT_CTRL 0x0000180c
3262#define BCE_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30)
3263#define BCE_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31)
3264
43c2aeb0
SZ
3265#define BCE_RPM_VLAN_MATCH0 0x00001810
3266#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
3267
3268#define BCE_RPM_VLAN_MATCH1 0x00001814
3269#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
3270
3271#define BCE_RPM_VLAN_MATCH2 0x00001818
3272#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
3273
3274#define BCE_RPM_VLAN_MATCH3 0x0000181c
3275#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
3276
3277#define BCE_RPM_SORT_USER0 0x00001820
3278#define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0)
3279#define BCE_RPM_SORT_USER0_BC_EN (1L<<16)
3280#define BCE_RPM_SORT_USER0_MC_EN (1L<<17)
3281#define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
3282#define BCE_RPM_SORT_USER0_PROM_EN (1L<<19)
3283#define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
3284#define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24)
3285#define BCE_RPM_SORT_USER0_ENA (1L<<31)
3286
3287#define BCE_RPM_SORT_USER1 0x00001824
3288#define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0)
3289#define BCE_RPM_SORT_USER1_BC_EN (1L<<16)
3290#define BCE_RPM_SORT_USER1_MC_EN (1L<<17)
3291#define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
3292#define BCE_RPM_SORT_USER1_PROM_EN (1L<<19)
3293#define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
3294#define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24)
3295#define BCE_RPM_SORT_USER1_ENA (1L<<31)
3296
3297#define BCE_RPM_SORT_USER2 0x00001828
3298#define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0)
3299#define BCE_RPM_SORT_USER2_BC_EN (1L<<16)
3300#define BCE_RPM_SORT_USER2_MC_EN (1L<<17)
3301#define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
3302#define BCE_RPM_SORT_USER2_PROM_EN (1L<<19)
3303#define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
3304#define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24)
3305#define BCE_RPM_SORT_USER2_ENA (1L<<31)
3306
3307#define BCE_RPM_SORT_USER3 0x0000182c
3308#define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0)
3309#define BCE_RPM_SORT_USER3_BC_EN (1L<<16)
3310#define BCE_RPM_SORT_USER3_MC_EN (1L<<17)
3311#define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
3312#define BCE_RPM_SORT_USER3_PROM_EN (1L<<19)
3313#define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
3314#define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24)
3315#define BCE_RPM_SORT_USER3_ENA (1L<<31)
3316
3317#define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
3318#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
3319#define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848
3320#define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c
3321#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
3322#define BCE_RPM_STAT_AC0 0x00001880
3323#define BCE_RPM_STAT_AC1 0x00001884
3324#define BCE_RPM_STAT_AC2 0x00001888
3325#define BCE_RPM_STAT_AC3 0x0000188c
3326#define BCE_RPM_STAT_AC4 0x00001890
3327#define BCE_RPM_RC_CNTL_0 0x00001900
3328#define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
3329#define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8)
3330#define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11)
3331#define BCE_RPM_RC_CNTL_0_P4 (1L<<12)
3332#define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
3333#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
3334#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
3335#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
3336#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
3337#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
3338#define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16)
3339#define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
3340#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
3341#define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
3342#define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
3343#define BCE_RPM_RC_CNTL_0_SBIT (1L<<19)
3344#define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
3345#define BCE_RPM_RC_CNTL_0_MAP (1L<<24)
3346#define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25)
3347#define BCE_RPM_RC_CNTL_0_MASK (1L<<26)
3348#define BCE_RPM_RC_CNTL_0_P1 (1L<<27)
3349#define BCE_RPM_RC_CNTL_0_P2 (1L<<28)
3350#define BCE_RPM_RC_CNTL_0_P3 (1L<<29)
3351#define BCE_RPM_RC_CNTL_0_NBIT (1L<<30)
3352
3353#define BCE_RPM_RC_VALUE_MASK_0 0x00001904
3354#define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
3355#define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
3356
3357#define BCE_RPM_RC_CNTL_1 0x00001908
3358#define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0)
3359#define BCE_RPM_RC_CNTL_1_B (0xfffL<<19)
3360
3361#define BCE_RPM_RC_VALUE_MASK_1 0x0000190c
3362#define BCE_RPM_RC_CNTL_2 0x00001910
3363#define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0)
3364#define BCE_RPM_RC_CNTL_2_B (0xfffL<<19)
3365
3366#define BCE_RPM_RC_VALUE_MASK_2 0x00001914
3367#define BCE_RPM_RC_CNTL_3 0x00001918
3368#define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0)
3369#define BCE_RPM_RC_CNTL_3_B (0xfffL<<19)
3370
3371#define BCE_RPM_RC_VALUE_MASK_3 0x0000191c
3372#define BCE_RPM_RC_CNTL_4 0x00001920
3373#define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0)
3374#define BCE_RPM_RC_CNTL_4_B (0xfffL<<19)
3375
3376#define BCE_RPM_RC_VALUE_MASK_4 0x00001924
3377#define BCE_RPM_RC_CNTL_5 0x00001928
3378#define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0)
3379#define BCE_RPM_RC_CNTL_5_B (0xfffL<<19)
3380
3381#define BCE_RPM_RC_VALUE_MASK_5 0x0000192c
3382#define BCE_RPM_RC_CNTL_6 0x00001930
3383#define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0)
3384#define BCE_RPM_RC_CNTL_6_B (0xfffL<<19)
3385
3386#define BCE_RPM_RC_VALUE_MASK_6 0x00001934
3387#define BCE_RPM_RC_CNTL_7 0x00001938
3388#define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0)
3389#define BCE_RPM_RC_CNTL_7_B (0xfffL<<19)
3390
3391#define BCE_RPM_RC_VALUE_MASK_7 0x0000193c
3392#define BCE_RPM_RC_CNTL_8 0x00001940
3393#define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0)
3394#define BCE_RPM_RC_CNTL_8_B (0xfffL<<19)
3395
3396#define BCE_RPM_RC_VALUE_MASK_8 0x00001944
3397#define BCE_RPM_RC_CNTL_9 0x00001948
3398#define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0)
3399#define BCE_RPM_RC_CNTL_9_B (0xfffL<<19)
3400
3401#define BCE_RPM_RC_VALUE_MASK_9 0x0000194c
3402#define BCE_RPM_RC_CNTL_10 0x00001950
3403#define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0)
3404#define BCE_RPM_RC_CNTL_10_B (0xfffL<<19)
3405
3406#define BCE_RPM_RC_VALUE_MASK_10 0x00001954
3407#define BCE_RPM_RC_CNTL_11 0x00001958
3408#define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0)
3409#define BCE_RPM_RC_CNTL_11_B (0xfffL<<19)
3410
3411#define BCE_RPM_RC_VALUE_MASK_11 0x0000195c
3412#define BCE_RPM_RC_CNTL_12 0x00001960
3413#define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0)
3414#define BCE_RPM_RC_CNTL_12_B (0xfffL<<19)
3415
3416#define BCE_RPM_RC_VALUE_MASK_12 0x00001964
3417#define BCE_RPM_RC_CNTL_13 0x00001968
3418#define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0)
3419#define BCE_RPM_RC_CNTL_13_B (0xfffL<<19)
3420
3421#define BCE_RPM_RC_VALUE_MASK_13 0x0000196c
3422#define BCE_RPM_RC_CNTL_14 0x00001970
3423#define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0)
3424#define BCE_RPM_RC_CNTL_14_B (0xfffL<<19)
3425
3426#define BCE_RPM_RC_VALUE_MASK_14 0x00001974
3427#define BCE_RPM_RC_CNTL_15 0x00001978
3428#define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0)
3429#define BCE_RPM_RC_CNTL_15_B (0xfffL<<19)
3430
3431#define BCE_RPM_RC_VALUE_MASK_15 0x0000197c
3432#define BCE_RPM_RC_CONFIG 0x00001980
3433#define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
3434#define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
3435
3436#define BCE_RPM_DEBUG0 0x00001984
3437#define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
3438#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
3439#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
3440#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
3441#define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
3442#define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
3443#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
3444#define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22)
3445#define BCE_RPM_DEBUG0_FM_STARTED (1L<<23)
3446#define BCE_RPM_DEBUG0_DONE (1L<<24)
3447#define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
3448#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
3449#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
3450#define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
3451#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
3452
3453#define BCE_RPM_DEBUG1 0x00001988
3454#define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
3455#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
3456#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
3457#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
3458#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
3459#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
3460#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
3461#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
3462#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
3463#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
3464#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
3465#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
3466#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
3467#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
3468#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
3469#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
3470#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
3471#define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
3472#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
3473#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
3474#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
3475#define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
3476
3477#define BCE_RPM_DEBUG2 0x0000198c
3478#define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
3479#define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16)
3480#define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
3481#define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
3482#define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
3483#define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
3484#define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
3485#define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29)
3486#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
3487#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
3488
3489#define BCE_RPM_DEBUG3 0x00001990
3490#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
3491#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
3492#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
3493#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
3494#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
3495#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
3496#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
3497#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
3498#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
3499#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
3500#define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
3501#define BCE_RPM_DEBUG3_DROP_NXT (1L<<23)
3502#define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
3503#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
3504#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
3505#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
3506#define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
3507#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
3508#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
3509#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
3510#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
3511#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
3512#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
3513#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
3514#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
3515#define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29)
3516#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
3517#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
3518#define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
3519#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
3520#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
3521#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
3522
3523#define BCE_RPM_DEBUG4 0x00001994
3524#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
3525#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
3526#define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
3527#define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
3528
3529#define BCE_RPM_DEBUG5 0x00001998
3530#define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
3531#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
3532#define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
3533#define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
3534#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
3535#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
3536#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
3537#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
3538#define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
3539#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
3540#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
3541#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
3542#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
3543#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
3544#define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
3545#define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31)
3546
3547#define BCE_RPM_DEBUG6 0x0000199c
3548#define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
3549#define BCE_RPM_DEBUG6_VEC (0xffffL<<16)
3550
3551#define BCE_RPM_DEBUG7 0x000019a0
3552#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
3553
3554#define BCE_RPM_DEBUG8 0x000019a4
3555#define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
3556#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
3557#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
3558#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
3559#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
3560#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
3561#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
3562#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
3563#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
3564#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
3565#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
3566#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
3567#define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
3568#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
3569#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
3570#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
3571#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
3572#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
3573#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
3574#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
3575#define BCE_RPM_DEBUG8_EOF_DET (1L<<12)
3576#define BCE_RPM_DEBUG8_SOF_DET (1L<<13)
3577#define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
3578#define BCE_RPM_DEBUG8_ALL_DONE (1L<<15)
3579#define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
3580#define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
3581
3582#define BCE_RPM_DEBUG9 0x000019a8
3583#define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
3584#define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
3585#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
3586#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
3587#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
3588#define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
3589#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
3590
3591#define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0
3592#define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4
3593#define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8
3594#define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc
3595#define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0
3596#define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4
3597#define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8
3598#define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc
3599#define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0
3600#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4
3601#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8
3602#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec
3603#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0
3604#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4
3605#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
3606#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
3607
3608
3609/*
d0092544
SZ
3610 * rlup_reg definition
3611 * offset: 0x2000
3612 */
3613#define BCE_RLUP_FTQ_CMD 0x000023f8
3614#define BCE_RLUP_FTQ_CTL 0x000023fc
3615#define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3616#define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3617
3618
3619/*
3620 * rv2pcsr_reg definition
3621 * offset: 0x2400
3622 */
3623#define BCE_RV2PCSR_FTQ_CMD 0x000027f8
3624#define BCE_RV2PCSR_FTQ_CTL 0x000027fc
3625#define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3626#define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3627
3628
3629/*
3630 * rdma_reg definition
3631 * offset: 0x2c00
3632 */
3633#define BCE_RDMA_FTQ_CMD 0x00002ff8
3634#define BCE_RDMA_FTQ_CTL 0x00002ffc
3635#define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3636#define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3637
3638
3639/*
3640 * timer_reg definition
3641 * offset: 0x4400
3642 */
3643#define BCE_TIMER_COMMAND 0x00004400
3644#define BCE_TIMER_COMMAND_ENABLED (1L<<0)
3645
3646#define BCE_TIMER_STATUS 0x00004404
3647#define BCE_TIMER_STATUS_CMP_FTQ_WAIT (1L<<0)
3648#define BCE_TIMER_STATUS_POLL_PASS_CNT (1L<<8)
3649#define BCE_TIMER_STATUS_TMR1_CNT (1L<<9)
3650#define BCE_TIMER_STATUS_TMR2_CNT (1L<<10)
3651#define BCE_TIMER_STATUS_TMR3_CNT (1L<<11)
3652#define BCE_TIMER_STATUS_TMR4_CNT (1L<<12)
3653#define BCE_TIMER_STATUS_TMR5_CNT (1L<<13)
3654
3655#define BCE_TIMER_25MHZ_FREE_RUNi 0x00004448
3656
3657
3658/*
3659 * tsch_reg definition
3660 * offset: 0x4c00
3661 */
3662#define BCE_TSCH_FTQ_CMD 0x00004ff8
3663#define BCE_TSCH_FTQ_CTL 0x00004ffc
3664#define BCE_TSCH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3665#define BCE_TSCH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3666
3667
3668/*
43c2aeb0
SZ
3669 * rbuf_reg definition
3670 * offset: 0x200000
3671 */
3672#define BCE_RBUF_COMMAND 0x00200000
3673#define BCE_RBUF_COMMAND_ENABLED (1L<<0)
3674#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
3675#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)
3676#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4)
3677#define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5)
3678
3679#define BCE_RBUF_STATUS1 0x00200004
3680#define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
3681
3682#define BCE_RBUF_STATUS2 0x00200008
3683#define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
3684#define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
3685
3686#define BCE_RBUF_CONFIG 0x0020000c
3687#define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
3688#define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
3689
3690#define BCE_RBUF_FW_BUF_ALLOC 0x00200010
3691#define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
3692
3693#define BCE_RBUF_FW_BUF_FREE 0x00200014
3694#define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
3695#define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
3696#define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
3697
3698#define BCE_RBUF_FW_BUF_SEL 0x00200018
3699#define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
3700#define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
3701#define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
3702
3703#define BCE_RBUF_CONFIG2 0x0020001c
3704#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
3705#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
3706
3707#define BCE_RBUF_CONFIG3 0x00200020
3708#define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
3709#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
3710
3711#define BCE_RBUF_PKT_DATA 0x00208000
3712#define BCE_RBUF_CLIST_DATA 0x00210000
3713#define BCE_RBUF_BUF_DATA 0x00220000
3714
3715
3716/*
3717 * rv2p_reg definition
3718 * offset: 0x2800
3719 */
3720#define BCE_RV2P_COMMAND 0x00002800
3721#define BCE_RV2P_COMMAND_ENABLED (1L<<0)
3722#define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
3723#define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
3724#define BCE_RV2P_COMMAND_ABORT0 (1L<<4)
3725#define BCE_RV2P_COMMAND_ABORT1 (1L<<5)
3726#define BCE_RV2P_COMMAND_ABORT2 (1L<<6)
3727#define BCE_RV2P_COMMAND_ABORT3 (1L<<7)
3728#define BCE_RV2P_COMMAND_ABORT4 (1L<<8)
3729#define BCE_RV2P_COMMAND_ABORT5 (1L<<9)
3730#define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16)
3731#define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17)
3732#define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18)
3733
3734#define BCE_RV2P_STATUS 0x00002804
3735#define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0)
3736#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
3737#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
3738#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
3739#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
3740#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
3741#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
3742
3743#define BCE_RV2P_CONFIG 0x00002808
3744#define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0)
3745#define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1)
3746#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
3747#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
3748#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
3749#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
3750#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
3751#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
3752#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
3753#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
3754#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
3755#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
3756#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
3757#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
3758#define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
3759#define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
3760#define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
3761#define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
3762#define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
3763#define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
3764#define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
3765#define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
3766#define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
3767#define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
3768#define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
3769#define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
3770#define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
3771#define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
3772
3773#define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810
3774#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
3775
3776#define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814
3777#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
3778
3779#define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818
3780#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
3781
3782#define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c
3783#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
3784
3785#define BCE_RV2P_INSTR_HIGH 0x00002830
3786#define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
3787
3788#define BCE_RV2P_INSTR_LOW 0x00002834
3789#define BCE_RV2P_PROC1_ADDR_CMD 0x00002838
3790#define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
3791#define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
3792
3793#define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c
3794#define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
3795#define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
3796
3797#define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840
3798#define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844
3799#define BCE_RV2P_GRC_PROC_DEBUG 0x00002848
3800#define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c
3801#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3802#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3803#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3804#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3805#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)