Bump .Dd for recent updates and do some mdoc cleanup.
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
011c0f93 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
0ecb11d7 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.75 2007/05/07 04:54:32 sephe Exp $
1de703da 35 *
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36 */
37
38/*
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 *
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
43 */
44
45/*
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
56 * into the driver.
57 *
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
60 *
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
64 *
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
67 *
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
72 * ring.
73 */
74
75#include <sys/param.h>
62be1357 76#include <sys/bus.h>
20c9a969 77#include <sys/endian.h>
62be1357 78#include <sys/kernel.h>
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79#include <sys/mbuf.h>
80#include <sys/malloc.h>
984263bc 81#include <sys/queue.h>
62be1357 82#include <sys/rman.h>
16dca0df 83#include <sys/serialize.h>
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84#include <sys/socket.h>
85#include <sys/sockio.h>
984263bc 86
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87#include <net/bpf.h>
88#include <net/ethernet.h>
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89#include <net/if.h>
90#include <net/if_arp.h>
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91#include <net/if_dl.h>
92#include <net/if_media.h>
984263bc 93#include <net/if_types.h>
62be1357 94#include <net/ifq_var.h>
1f2de5d4 95#include <net/vlan/if_vlan_var.h>
984263bc 96
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97#include <dev/netif/mii_layer/mii.h>
98#include <dev/netif/mii_layer/miivar.h>
1f2de5d4 99#include <dev/netif/mii_layer/brgphyreg.h>
984263bc 100
f952ab63 101#include <bus/pci/pcidevs.h>
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102#include <bus/pci/pcireg.h>
103#include <bus/pci/pcivar.h>
984263bc 104
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105#include <dev/netif/bge/if_bgereg.h>
106
107/* "device miibus" required. See GENERIC if you get errors here. */
108#include "miibus_if.h"
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109
110#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
cb623c48 111#define BGE_MIN_FRAME 60
984263bc 112
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113/*
114 * Various supported device vendors/types and their names. Note: the
115 * spec seems to indicate that the hardware still has Alteon's vendor
116 * ID burned into it, though it will always be overriden by the vendor
117 * ID in the EEPROM. Just to be safe, we cover all possibilities.
118 */
119#define BGE_DEVDESC_MAX 64 /* Maximum device description length */
120
121static struct bge_type bge_devs[] = {
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122 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
123 "3COM 3C996 Gigabit Ethernet" },
124
f952ab63 125 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
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126 "Alteon BCM5700 Gigabit Ethernet" },
127 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
128 "Alteon BCM5701 Gigabit Ethernet" },
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129
130 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
131 "Altima AC1000 Gigabit Ethernet" },
132 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
133 "Altima AC1002 Gigabit Ethernet" },
134 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
135 "Altima AC9100 Gigabit Ethernet" },
136
137 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
138 "Apple BCM5701 Gigabit Ethernet" },
139
f952ab63 140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
984263bc 141 "Broadcom BCM5700 Gigabit Ethernet" },
f952ab63 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
984263bc 143 "Broadcom BCM5701 Gigabit Ethernet" },
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144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
145 "Broadcom BCM5702 Gigabit Ethernet" },
f952ab63 146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
984263bc 147 "Broadcom BCM5702X Gigabit Ethernet" },
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148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
149 "Broadcom BCM5702 Gigabit Ethernet" },
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150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
151 "Broadcom BCM5703 Gigabit Ethernet" },
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152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
153 "Broadcom BCM5703X Gigabit Ethernet" },
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154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
155 "Broadcom BCM5703 Gigabit Ethernet" },
f952ab63 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
984263bc 157 "Broadcom BCM5704C Dual Gigabit Ethernet" },
f952ab63 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
984263bc 159 "Broadcom BCM5704S Dual Gigabit Ethernet" },
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160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
161 "Broadcom BCM5704S Dual Gigabit Ethernet" },
f952ab63 162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
7e40b8c5 163 "Broadcom BCM5705 Gigabit Ethernet" },
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164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
165 "Broadcom BCM5705F Gigabit Ethernet" },
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166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
167 "Broadcom BCM5705K Gigabit Ethernet" },
f952ab63 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
7e40b8c5 169 "Broadcom BCM5705M Gigabit Ethernet" },
9a6ee7e2 170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
7e40b8c5 171 "Broadcom BCM5705M Gigabit Ethernet" },
92decf65 172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
9a6ee7e2 173 "Broadcom BCM5714C Gigabit Ethernet" },
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174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
175 "Broadcom BCM5714S Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
177 "Broadcom BCM5715 Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
179 "Broadcom BCM5715S Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
181 "Broadcom BCM5720 Gigabit Ethernet" },
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182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
183 "Broadcom BCM5721 Gigabit Ethernet" },
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184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
185 "Broadcom BCM5722 Gigabit Ethernet" },
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186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
187 "Broadcom BCM5750 Gigabit Ethernet" },
188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
189 "Broadcom BCM5750M Gigabit Ethernet" },
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190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
191 "Broadcom BCM5751 Gigabit Ethernet" },
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192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
193 "Broadcom BCM5751F Gigabit Ethernet" },
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194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
195 "Broadcom BCM5751M Gigabit Ethernet" },
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196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
197 "Broadcom BCM5752 Gigabit Ethernet" },
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198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
199 "Broadcom BCM5752M Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
201 "Broadcom BCM5753 Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
203 "Broadcom BCM5753F Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
205 "Broadcom BCM5753M Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
207 "Broadcom BCM5754 Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
209 "Broadcom BCM5754M Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
211 "Broadcom BCM5755 Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
213 "Broadcom BCM5755M Gigabit Ethernet" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
215 "Broadcom BCM5756 Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
217 "Broadcom BCM5780 Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
219 "Broadcom BCM5780S Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
221 "Broadcom BCM5781 Gigabit Ethernet" },
f952ab63 222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
7e40b8c5 223 "Broadcom BCM5782 Gigabit Ethernet" },
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224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
225 "Broadcom BCM5786 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
227 "Broadcom BCM5787 Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
229 "Broadcom BCM5787F Gigabit Ethernet" },
230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
231 "Broadcom BCM5787M Gigabit Ethernet" },
9a6ee7e2 232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
f952ab63 233 "Broadcom BCM5788 Gigabit Ethernet" },
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234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
235 "Broadcom BCM5789 Gigabit Ethernet" },
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236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
237 "Broadcom BCM5901 Fast Ethernet" },
238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
239 "Broadcom BCM5901A2 Fast Ethernet" },
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240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
241 "Broadcom BCM5903M Fast Ethernet" },
242
f952ab63 243 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
984263bc 244 "SysKonnect Gigabit Ethernet" },
0ecb11d7 245
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246 { 0, 0, NULL }
247};
248
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249#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
250#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
251#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
252#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
253#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
254
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255static int bge_probe(device_t);
256static int bge_attach(device_t);
257static int bge_detach(device_t);
258static void bge_release_resources(struct bge_softc *);
259static void bge_txeof(struct bge_softc *);
260static void bge_rxeof(struct bge_softc *);
261
262static void bge_tick(void *);
263static void bge_stats_update(struct bge_softc *);
264static void bge_stats_update_regs(struct bge_softc *);
265static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
266
267static void bge_intr(void *);
268static void bge_start(struct ifnet *);
269static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
270static void bge_init(void *);
271static void bge_stop(struct bge_softc *);
272static void bge_watchdog(struct ifnet *);
273static void bge_shutdown(device_t);
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274static int bge_suspend(device_t);
275static int bge_resume(device_t);
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276static int bge_ifmedia_upd(struct ifnet *);
277static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
278
279static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
280static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
281
33c39a69 282static void bge_setmulti(struct bge_softc *);
6439b28a 283static void bge_setpromisc(struct bge_softc *);
33c39a69 284
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285static int bge_alloc_jumbo_mem(struct bge_softc *);
286static void bge_free_jumbo_mem(struct bge_softc *);
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287static struct bge_jslot
288 *bge_jalloc(struct bge_softc *);
289static void bge_jfree(void *);
290static void bge_jref(void *);
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291static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
292static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
293static int bge_init_rx_ring_std(struct bge_softc *);
294static void bge_free_rx_ring_std(struct bge_softc *);
295static int bge_init_rx_ring_jumbo(struct bge_softc *);
296static void bge_free_rx_ring_jumbo(struct bge_softc *);
297static void bge_free_tx_ring(struct bge_softc *);
298static int bge_init_tx_ring(struct bge_softc *);
299
300static int bge_chipinit(struct bge_softc *);
301static int bge_blockinit(struct bge_softc *);
984263bc 302
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303static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
304static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
984263bc 305#ifdef notdef
33c39a69 306static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
984263bc 307#endif
33c39a69 308static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
0ecb11d7 309static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
984263bc 310
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311static int bge_miibus_readreg(device_t, int, int);
312static int bge_miibus_writereg(device_t, int, int, int);
313static void bge_miibus_statchg(device_t);
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314static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
315static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
316static void bge_copper_link_upd(struct bge_softc *, uint32_t);
984263bc 317
33c39a69 318static void bge_reset(struct bge_softc *);
984263bc 319
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320static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
321static void bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
322 bus_size_t, int);
323static int bge_dma_alloc(struct bge_softc *);
324static void bge_dma_free(struct bge_softc *);
325static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
326 bus_dma_tag_t *, bus_dmamap_t *,
327 void **, bus_addr_t *);
328static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
329
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330/*
331 * Set following tunable to 1 for some IBM blade servers with the DNLK
332 * switch module. Auto negotiation is broken for those configurations.
333 */
334static int bge_fake_autoneg = 0;
335TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
336
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337static device_method_t bge_methods[] = {
338 /* Device interface */
339 DEVMETHOD(device_probe, bge_probe),
340 DEVMETHOD(device_attach, bge_attach),
341 DEVMETHOD(device_detach, bge_detach),
342 DEVMETHOD(device_shutdown, bge_shutdown),
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343 DEVMETHOD(device_suspend, bge_suspend),
344 DEVMETHOD(device_resume, bge_resume),
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345
346 /* bus interface */
347 DEVMETHOD(bus_print_child, bus_generic_print_child),
348 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
349
350 /* MII interface */
351 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
352 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
353 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
354
355 { 0, 0 }
356};
357
33c39a69 358static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
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359static devclass_t bge_devclass;
360
32832096 361DECLARE_DUMMY_MODULE(if_bge);
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362DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
363DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
364
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365static uint32_t
366bge_readmem_ind(struct bge_softc *sc, uint32_t off)
984263bc 367{
33c39a69 368 device_t dev = sc->bge_dev;
0ecb11d7 369 uint32_t val;
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370
371 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
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372 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
373 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
374 return (val);
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375}
376
377static void
33c39a69 378bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 379{
33c39a69 380 device_t dev = sc->bge_dev;
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381
382 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
383 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
0ecb11d7 384 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
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385}
386
387#ifdef notdef
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388static uint32_t
389bge_readreg_ind(struct bge_softc *sc, uin32_t off)
984263bc 390{
33c39a69 391 device_t dev = sc->bge_dev;
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392
393 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
394 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
395}
396#endif
397
398static void
33c39a69 399bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 400{
33c39a69 401 device_t dev = sc->bge_dev;
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402
403 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
404 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
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405}
406
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407static void
408bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
409{
410 CSR_WRITE_4(sc, off, val);
411}
412
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MD
413/*
414 * Read a byte of data stored in the EEPROM at address 'addr.' The
415 * BCM570x supports both the traditional bitbang interface and an
416 * auto access interface for reading the EEPROM. We use the auto
417 * access method.
418 */
33c39a69
JS
419static uint8_t
420bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
984263bc
MD
421{
422 int i;
33c39a69 423 uint32_t byte = 0;
984263bc
MD
424
425 /*
426 * Enable use of auto EEPROM access so we can avoid
427 * having to use the bitbang method.
428 */
429 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
430
431 /* Reset the EEPROM, load the clock period. */
432 CSR_WRITE_4(sc, BGE_EE_ADDR,
433 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
434 DELAY(20);
435
436 /* Issue the read EEPROM command. */
437 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
438
439 /* Wait for completion */
440 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
441 DELAY(10);
442 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
443 break;
444 }
445
446 if (i == BGE_TIMEOUT) {
c6fd6f3b 447 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
7b47d9c2 448 return(1);
984263bc
MD
449 }
450
451 /* Get result. */
452 byte = CSR_READ_4(sc, BGE_EE_DATA);
453
454 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
455
456 return(0);
457}
458
459/*
460 * Read a sequence of bytes from the EEPROM.
461 */
462static int
33c39a69 463bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
984263bc 464{
33c39a69
JS
465 size_t i;
466 int err;
467 uint8_t byte;
984263bc 468
33c39a69 469 for (byte = 0, err = 0, i = 0; i < len; i++) {
984263bc
MD
470 err = bge_eeprom_getbyte(sc, off + i, &byte);
471 if (err)
472 break;
473 *(dest + i) = byte;
474 }
475
476 return(err ? 1 : 0);
477}
478
479static int
33c39a69 480bge_miibus_readreg(device_t dev, int phy, int reg)
984263bc
MD
481{
482 struct bge_softc *sc;
483 struct ifnet *ifp;
33c39a69 484 uint32_t val, autopoll;
984263bc
MD
485 int i;
486
487 sc = device_get_softc(dev);
488 ifp = &sc->arpcom.ac_if;
489
7e40b8c5
HP
490 /*
491 * Broadcom's own driver always assumes the internal
492 * PHY is at GMII address 1. On some chips, the PHY responds
493 * to accesses at all addresses, which could cause us to
494 * bogusly attach the PHY 32 times at probe type. Always
495 * restricting the lookup to address 1 is simpler than
496 * trying to figure out which chips revisions should be
497 * special-cased.
498 */
984263bc 499 if (phy != 1)
7e40b8c5 500 return(0);
984263bc
MD
501
502 /* Reading with autopolling on may trigger PCI errors */
503 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
504 if (autopoll & BGE_MIMODE_AUTOPOLL) {
505 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
506 DELAY(40);
507 }
508
509 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
510 BGE_MIPHY(phy)|BGE_MIREG(reg));
511
512 for (i = 0; i < BGE_TIMEOUT; i++) {
513 val = CSR_READ_4(sc, BGE_MI_COMM);
514 if (!(val & BGE_MICOMM_BUSY))
515 break;
516 }
517
518 if (i == BGE_TIMEOUT) {
c6fd6f3b 519 if_printf(ifp, "PHY read timed out\n");
984263bc
MD
520 val = 0;
521 goto done;
522 }
523
524 val = CSR_READ_4(sc, BGE_MI_COMM);
525
526done:
527 if (autopoll & BGE_MIMODE_AUTOPOLL) {
528 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
529 DELAY(40);
530 }
531
532 if (val & BGE_MICOMM_READFAIL)
533 return(0);
534
535 return(val & 0xFFFF);
536}
537
538static int
33c39a69 539bge_miibus_writereg(device_t dev, int phy, int reg, int val)
984263bc
MD
540{
541 struct bge_softc *sc;
33c39a69 542 uint32_t autopoll;
984263bc
MD
543 int i;
544
545 sc = device_get_softc(dev);
546
547 /* Reading with autopolling on may trigger PCI errors */
548 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
549 if (autopoll & BGE_MIMODE_AUTOPOLL) {
550 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
551 DELAY(40);
552 }
553
554 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
555 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
556
557 for (i = 0; i < BGE_TIMEOUT; i++) {
558 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
559 break;
560 }
561
562 if (autopoll & BGE_MIMODE_AUTOPOLL) {
563 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
564 DELAY(40);
565 }
566
567 if (i == BGE_TIMEOUT) {
c6fd6f3b 568 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
984263bc
MD
569 return(0);
570 }
571
572 return(0);
573}
574
575static void
33c39a69 576bge_miibus_statchg(device_t dev)
984263bc
MD
577{
578 struct bge_softc *sc;
579 struct mii_data *mii;
580
581 sc = device_get_softc(dev);
582 mii = device_get_softc(sc->bge_miibus);
583
584 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
7f259627 585 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
984263bc
MD
586 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
587 } else {
588 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
589 }
590
591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
592 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
593 } else {
594 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
595 }
984263bc
MD
596}
597
984263bc
MD
598/*
599 * Memory management for jumbo frames.
600 */
984263bc 601static int
33c39a69 602bge_alloc_jumbo_mem(struct bge_softc *sc)
984263bc 603{
20c9a969 604 struct ifnet *ifp = &sc->arpcom.ac_if;
2aa9b12f 605 struct bge_jslot *entry;
20c9a969
SZ
606 uint8_t *ptr;
607 bus_addr_t paddr;
608 int i, error;
984263bc 609
20c9a969
SZ
610 /*
611 * Create tag for jumbo mbufs.
612 * This is really a bit of a kludge. We allocate a special
613 * jumbo buffer pool which (thanks to the way our DMA
614 * memory allocation works) will consist of contiguous
615 * pages. This means that even though a jumbo buffer might
616 * be larger than a page size, we don't really need to
617 * map it into more than one DMA segment. However, the
618 * default mbuf tag will result in multi-segment mappings,
619 * so we have to create a special jumbo mbuf tag that
620 * lets us get away with mapping the jumbo buffers as
621 * a single segment. I think eventually the driver should
622 * be changed so that it uses ordinary mbufs and cluster
623 * buffers, i.e. jumbo frames can span multiple DMA
624 * descriptors. But that's a project for another day.
625 */
984263bc 626
20c9a969
SZ
627 /*
628 * Create DMA stuffs for jumbo RX ring.
629 */
630 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
631 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
632 &sc->bge_cdata.bge_rx_jumbo_ring_map,
633 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
634 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
635 if (error) {
636 if_printf(ifp, "could not create jumbo RX ring\n");
637 return error;
638 }
639
640 /*
641 * Create DMA stuffs for jumbo buffer block.
642 */
643 error = bge_dma_block_alloc(sc, BGE_JMEM,
644 &sc->bge_cdata.bge_jumbo_tag,
645 &sc->bge_cdata.bge_jumbo_map,
646 (void **)&sc->bge_ldata.bge_jumbo_buf,
647 &paddr);
648 if (error) {
649 if_printf(ifp, "could not create jumbo buffer\n");
650 return error;
984263bc
MD
651 }
652
653 SLIST_INIT(&sc->bge_jfree_listhead);
984263bc
MD
654
655 /*
656 * Now divide it up into 9K pieces and save the addresses
657 * in an array. Note that we play an evil trick here by using
658 * the first few bytes in the buffer to hold the the address
659 * of the softc structure for this interface. This is because
660 * bge_jfree() needs it, but it is called by the mbuf management
661 * code which will not pass it to us explicitly.
662 */
20c9a969 663 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
2aa9b12f
JS
664 entry = &sc->bge_cdata.bge_jslots[i];
665 entry->bge_sc = sc;
666 entry->bge_buf = ptr;
20c9a969 667 entry->bge_paddr = paddr;
2aa9b12f
JS
668 entry->bge_inuse = 0;
669 entry->bge_slot = i;
670 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
20c9a969 671
2aa9b12f 672 ptr += BGE_JLEN;
20c9a969 673 paddr += BGE_JLEN;
984263bc 674 }
20c9a969 675 return 0;
984263bc
MD
676}
677
678static void
33c39a69 679bge_free_jumbo_mem(struct bge_softc *sc)
984263bc 680{
20c9a969
SZ
681 /* Destroy jumbo RX ring. */
682 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
683 sc->bge_cdata.bge_rx_jumbo_ring_map,
684 sc->bge_ldata.bge_rx_jumbo_ring);
685
686 /* Destroy jumbo buffer block. */
687 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
688 sc->bge_cdata.bge_jumbo_map,
689 sc->bge_ldata.bge_jumbo_buf);
984263bc
MD
690}
691
692/*
693 * Allocate a jumbo buffer.
694 */
2aa9b12f 695static struct bge_jslot *
33c39a69 696bge_jalloc(struct bge_softc *sc)
984263bc 697{
2aa9b12f 698 struct bge_jslot *entry;
33c39a69 699
16dca0df 700 lwkt_serialize_enter(&sc->bge_jslot_serializer);
984263bc 701 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
16dca0df
MD
702 if (entry) {
703 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
704 entry->bge_inuse = 1;
705 } else {
c6fd6f3b 706 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
984263bc 707 }
16dca0df 708 lwkt_serialize_exit(&sc->bge_jslot_serializer);
2aa9b12f 709 return(entry);
984263bc
MD
710}
711
712/*
713 * Adjust usage count on a jumbo buffer.
714 */
715static void
2aa9b12f 716bge_jref(void *arg)
984263bc 717{
2aa9b12f
JS
718 struct bge_jslot *entry = (struct bge_jslot *)arg;
719 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
720
721 if (sc == NULL)
722 panic("bge_jref: can't find softc pointer!");
723
16dca0df 724 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc
MD
725 panic("bge_jref: asked to reference buffer "
726 "that we don't manage!");
16dca0df 727 } else if (entry->bge_inuse == 0) {
984263bc 728 panic("bge_jref: buffer already free!");
16dca0df
MD
729 } else {
730 atomic_add_int(&entry->bge_inuse, 1);
731 }
984263bc
MD
732}
733
734/*
735 * Release a jumbo buffer.
736 */
737static void
2aa9b12f 738bge_jfree(void *arg)
984263bc 739{
2aa9b12f
JS
740 struct bge_jslot *entry = (struct bge_jslot *)arg;
741 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
742
743 if (sc == NULL)
744 panic("bge_jfree: can't find softc pointer!");
745
16dca0df 746 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc 747 panic("bge_jfree: asked to free buffer that we don't manage!");
16dca0df 748 } else if (entry->bge_inuse == 0) {
984263bc 749 panic("bge_jfree: buffer already free!");
16dca0df
MD
750 } else {
751 /*
752 * Possible MP race to 0, use the serializer. The atomic insn
753 * is still needed for races against bge_jref().
754 */
755 lwkt_serialize_enter(&sc->bge_jslot_serializer);
756 atomic_subtract_int(&entry->bge_inuse, 1);
757 if (entry->bge_inuse == 0) {
758 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
759 entry, jslot_link);
760 }
761 lwkt_serialize_exit(&sc->bge_jslot_serializer);
762 }
984263bc
MD
763}
764
765
766/*
767 * Intialize a standard receive ring descriptor.
768 */
769static int
33c39a69 770bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
984263bc 771{
33c39a69 772 struct mbuf *m_new = NULL;
20c9a969
SZ
773 struct bge_dmamap_arg ctx;
774 bus_dma_segment_t seg;
33c39a69 775 struct bge_rx_bd *r;
20c9a969 776 int error;
984263bc
MD
777
778 if (m == NULL) {
d5086f2b 779 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
33c39a69 780 if (m_new == NULL)
20c9a969 781 return ENOBUFS;
984263bc
MD
782 } else {
783 m_new = m;
984263bc
MD
784 m_new->m_data = m_new->m_ext.ext_buf;
785 }
20c9a969 786 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
984263bc 787
0ecb11d7 788 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
984263bc 789 m_adj(m_new, ETHER_ALIGN);
20c9a969
SZ
790
791 ctx.bge_maxsegs = 1;
792 ctx.bge_segs = &seg;
793 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
794 sc->bge_cdata.bge_rx_std_dmamap[i],
795 m_new, bge_dma_map_mbuf, &ctx,
796 BUS_DMA_NOWAIT);
797 if (error || ctx.bge_maxsegs == 0) {
798 if (m == NULL)
799 m_freem(m_new);
800 return ENOMEM;
801 }
802
984263bc 803 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
20c9a969
SZ
804
805 r = &sc->bge_ldata.bge_rx_std_ring[i];
806 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
807 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
984263bc
MD
808 r->bge_flags = BGE_RXBDFLAG_END;
809 r->bge_len = m_new->m_len;
810 r->bge_idx = i;
811
20c9a969
SZ
812 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
813 sc->bge_cdata.bge_rx_std_dmamap[i],
814 BUS_DMASYNC_PREREAD);
815 return 0;
984263bc
MD
816}
817
818/*
819 * Initialize a jumbo receive ring descriptor. This allocates
820 * a jumbo buffer from the pool managed internally by the driver.
821 */
822static int
33c39a69 823bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
984263bc
MD
824{
825 struct mbuf *m_new = NULL;
20c9a969 826 struct bge_jslot *buf;
984263bc 827 struct bge_rx_bd *r;
20c9a969 828 bus_addr_t paddr;
984263bc
MD
829
830 if (m == NULL) {
984263bc 831 /* Allocate the mbuf. */
74f1caca 832 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
33c39a69 833 if (m_new == NULL)
984263bc 834 return(ENOBUFS);
984263bc
MD
835
836 /* Allocate the jumbo buffer */
837 buf = bge_jalloc(sc);
838 if (buf == NULL) {
839 m_freem(m_new);
c6fd6f3b
JS
840 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
841 "-- packet dropped!\n");
20c9a969 842 return ENOBUFS;
984263bc
MD
843 }
844
845 /* Attach the buffer to the mbuf. */
2aa9b12f
JS
846 m_new->m_ext.ext_arg = buf;
847 m_new->m_ext.ext_buf = buf->bge_buf;
b542cd49
JS
848 m_new->m_ext.ext_free = bge_jfree;
849 m_new->m_ext.ext_ref = bge_jref;
2aa9b12f
JS
850 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
851
2aa9b12f 852 m_new->m_flags |= M_EXT;
984263bc 853 } else {
20c9a969 854 KKASSERT(m->m_flags & M_EXT);
984263bc 855 m_new = m;
20c9a969 856 buf = m_new->m_ext.ext_arg;
984263bc 857 }
20c9a969
SZ
858 m_new->m_data = m_new->m_ext.ext_buf;
859 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc 860
20c9a969 861 paddr = buf->bge_paddr;
0ecb11d7 862 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
984263bc 863 m_adj(m_new, ETHER_ALIGN);
20c9a969
SZ
864 paddr += ETHER_ALIGN;
865 }
866
984263bc 867 /* Set up the descriptor. */
984263bc 868 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
20c9a969
SZ
869
870 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
871 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
872 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
984263bc
MD
873 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
874 r->bge_len = m_new->m_len;
875 r->bge_idx = i;
876
20c9a969 877 return 0;
984263bc
MD
878}
879
880/*
881 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
882 * that's 1MB or memory, which is a lot. For now, we fill only the first
883 * 256 ring entries and hope that our CPU is fast enough to keep up with
884 * the NIC.
885 */
886static int
33c39a69 887bge_init_rx_ring_std(struct bge_softc *sc)
984263bc
MD
888{
889 int i;
890
891 for (i = 0; i < BGE_SSLOTS; i++) {
892 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
893 return(ENOBUFS);
894 };
895
20c9a969
SZ
896 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
897 sc->bge_cdata.bge_rx_std_ring_map,
898 BUS_DMASYNC_PREWRITE);
899
984263bc
MD
900 sc->bge_std = i - 1;
901 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
902
903 return(0);
904}
905
906static void
33c39a69 907bge_free_rx_ring_std(struct bge_softc *sc)
984263bc
MD
908{
909 int i;
910
911 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
912 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
20c9a969
SZ
913 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
914 sc->bge_cdata.bge_rx_std_dmamap[i]);
984263bc
MD
915 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
916 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
917 }
20c9a969 918 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
984263bc
MD
919 sizeof(struct bge_rx_bd));
920 }
984263bc
MD
921}
922
923static int
33c39a69 924bge_init_rx_ring_jumbo(struct bge_softc *sc)
984263bc
MD
925{
926 int i;
927 struct bge_rcb *rcb;
928
929 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
930 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
931 return(ENOBUFS);
932 };
933
20c9a969
SZ
934 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
935 sc->bge_cdata.bge_rx_jumbo_ring_map,
936 BUS_DMASYNC_PREWRITE);
937
984263bc
MD
938 sc->bge_jumbo = i - 1;
939
20c9a969 940 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
984263bc
MD
941 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
942 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
943
944 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
945
946 return(0);
947}
948
949static void
33c39a69 950bge_free_rx_ring_jumbo(struct bge_softc *sc)
984263bc
MD
951{
952 int i;
953
954 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
955 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
956 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
957 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
958 }
20c9a969 959 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
984263bc
MD
960 sizeof(struct bge_rx_bd));
961 }
984263bc
MD
962}
963
964static void
33c39a69 965bge_free_tx_ring(struct bge_softc *sc)
984263bc
MD
966{
967 int i;
968
984263bc
MD
969 for (i = 0; i < BGE_TX_RING_CNT; i++) {
970 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
20c9a969
SZ
971 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
972 sc->bge_cdata.bge_tx_dmamap[i]);
984263bc
MD
973 m_freem(sc->bge_cdata.bge_tx_chain[i]);
974 sc->bge_cdata.bge_tx_chain[i] = NULL;
975 }
20c9a969 976 bzero(&sc->bge_ldata.bge_tx_ring[i],
984263bc
MD
977 sizeof(struct bge_tx_bd));
978 }
984263bc
MD
979}
980
981static int
33c39a69 982bge_init_tx_ring(struct bge_softc *sc)
984263bc
MD
983{
984 sc->bge_txcnt = 0;
985 sc->bge_tx_saved_considx = 0;
94db8384
SZ
986 sc->bge_tx_prodidx = 0;
987
988 /* Initialize transmit producer index for host-memory send ring. */
989 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 990
984263bc
MD
991 /* 5700 b2 errata */
992 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
993 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
994
995 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
996 /* 5700 b2 errata */
997 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
998 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
999
1000 return(0);
1001}
1002
984263bc 1003static void
33c39a69 1004bge_setmulti(struct bge_softc *sc)
984263bc
MD
1005{
1006 struct ifnet *ifp;
1007 struct ifmultiaddr *ifma;
33c39a69 1008 uint32_t hashes[4] = { 0, 0, 0, 0 };
984263bc
MD
1009 int h, i;
1010
1011 ifp = &sc->arpcom.ac_if;
1012
1013 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1014 for (i = 0; i < 4; i++)
1015 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1016 return;
1017 }
1018
1019 /* First, zot all the existing filters. */
1020 for (i = 0; i < 4; i++)
1021 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1022
1023 /* Now program new ones. */
33c39a69 1024 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1025 if (ifma->ifma_addr->sa_family != AF_LINK)
1026 continue;
3b4ec5b8
JS
1027 h = ether_crc32_le(
1028 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1029 ETHER_ADDR_LEN) & 0x7f;
984263bc
MD
1030 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1031 }
1032
1033 for (i = 0; i < 4; i++)
1034 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
984263bc
MD
1035}
1036
1037/*
1038 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1039 * self-test results.
1040 */
1041static int
33c39a69 1042bge_chipinit(struct bge_softc *sc)
984263bc 1043{
33c39a69
JS
1044 int i;
1045 uint32_t dma_rw_ctl;
984263bc 1046
20c9a969
SZ
1047 /* Set endian type before we access any non-PCI registers. */
1048 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
984263bc
MD
1049
1050 /*
1051 * Check the 'ROM failed' bit on the RX CPU to see if
1052 * self-tests passed.
1053 */
1054 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
c6fd6f3b
JS
1055 if_printf(&sc->arpcom.ac_if,
1056 "RX CPU self-diagnostics failed!\n");
984263bc
MD
1057 return(ENODEV);
1058 }
1059
1060 /* Clear the MAC control register */
1061 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1062
1063 /*
1064 * Clear the MAC statistics block in the NIC's
1065 * internal memory.
1066 */
1067 for (i = BGE_STATS_BLOCK;
33c39a69 1068 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1069 BGE_MEMWIN_WRITE(sc, i, 0);
1070
1071 for (i = BGE_STATUS_BLOCK;
33c39a69 1072 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1073 BGE_MEMWIN_WRITE(sc, i, 0);
1074
1075 /* Set up the PCI DMA control register. */
0ecb11d7 1076 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
1077 /* PCI Express */
1078 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1079 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1080 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1081 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
984263bc 1082 /* PCI-X bus */
0ecb11d7
SZ
1083 if (BGE_IS_5714_FAMILY(sc)) {
1084 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1085 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1086 /* XXX magic values, Broadcom-supplied Linux driver */
1087 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1088 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1089 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1090 } else {
1091 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1092 }
1093 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1094 /*
1095 * The 5704 uses a different encoding of read/write
1096 * watermarks.
1097 */
984263bc
MD
1098 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1099 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1100 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1101 } else {
984263bc
MD
1102 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1103 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1104 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1105 (0x0F);
0ecb11d7 1106 }
984263bc
MD
1107
1108 /*
1109 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1110 * for hardware bugs.
1111 */
1112 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1113 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
33c39a69 1114 uint32_t tmp;
984263bc
MD
1115
1116 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1117 if (tmp == 0x6 || tmp == 0x7)
1118 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1119 }
0ecb11d7
SZ
1120 } else {
1121 /* Conventional PCI bus */
1122 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1123 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1124 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1125 (0x0F);
984263bc
MD
1126 }
1127
1128 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
7e40b8c5 1129 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
0ecb11d7 1130 sc->bge_asicrev == BGE_ASICREV_BCM5705)
984263bc
MD
1131 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1132 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1133
1134 /*
1135 * Set up general mode register.
1136 */
20c9a969 1137 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
984263bc 1138 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
cb623c48 1139 BGE_MODECTL_TX_NO_PHDR_CSUM);
984263bc
MD
1140
1141 /*
1142 * Disable memory write invalidate. Apparently it is not supported
1143 * properly by these devices.
1144 */
1145 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1146
984263bc
MD
1147 /* Set the timer prescaler (always 66Mhz) */
1148 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1149
1150 return(0);
1151}
1152
1153static int
33c39a69 1154bge_blockinit(struct bge_softc *sc)
984263bc
MD
1155{
1156 struct bge_rcb *rcb;
20c9a969
SZ
1157 bus_size_t vrcb;
1158 bge_hostaddr taddr;
0ecb11d7 1159 uint32_t val;
984263bc
MD
1160 int i;
1161
1162 /*
1163 * Initialize the memory window pointer register so that
1164 * we can access the first 32K of internal NIC RAM. This will
1165 * allow us to set up the TX send ring RCBs and the RX return
1166 * ring RCBs, plus other things which live in NIC memory.
1167 */
1168 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1169
7e40b8c5
HP
1170 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1171
0ecb11d7 1172 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5 1173 /* Configure mbuf memory pool */
0ecb11d7
SZ
1174 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1175 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1176 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1177 else
1178 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
984263bc 1179
7e40b8c5
HP
1180 /* Configure DMA resource pool */
1181 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1182 BGE_DMA_DESCRIPTORS);
1183 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1184 }
984263bc
MD
1185
1186 /* Configure mbuf pool watermarks */
0ecb11d7 1187 if (BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1188 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1189 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1190 } else {
1191 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1192 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1193 }
984263bc
MD
1194 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1195
1196 /* Configure DMA resource watermarks */
1197 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1198 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1199
1200 /* Enable buffer manager */
0ecb11d7 1201 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1202 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1203 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
984263bc 1204
7e40b8c5
HP
1205 /* Poll for buffer manager start indication */
1206 for (i = 0; i < BGE_TIMEOUT; i++) {
1207 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1208 break;
1209 DELAY(10);
1210 }
984263bc 1211
7e40b8c5 1212 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1213 if_printf(&sc->arpcom.ac_if,
1214 "buffer manager failed to start\n");
7e40b8c5
HP
1215 return(ENXIO);
1216 }
984263bc
MD
1217 }
1218
1219 /* Enable flow-through queues */
1220 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1221 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1222
1223 /* Wait until queue initialization is complete */
1224 for (i = 0; i < BGE_TIMEOUT; i++) {
1225 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1226 break;
1227 DELAY(10);
1228 }
1229
1230 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1231 if_printf(&sc->arpcom.ac_if,
1232 "flow-through queue init failed\n");
984263bc
MD
1233 return(ENXIO);
1234 }
1235
1236 /* Initialize the standard RX ring control block */
20c9a969
SZ
1237 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1238 rcb->bge_hostaddr.bge_addr_lo =
1239 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1240 rcb->bge_hostaddr.bge_addr_hi =
1241 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1242 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1243 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
0ecb11d7 1244 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
1245 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1246 else
1247 rcb->bge_maxlen_flags =
1248 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
0ecb11d7 1249 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
984263bc
MD
1250 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1251 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1252 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1253 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1254
1255 /*
1256 * Initialize the jumbo RX ring control block
1257 * We set the 'ring disabled' bit in the flags
1258 * field until we're actually ready to start
1259 * using this ring (i.e. once we set the MTU
1260 * high enough to require it).
1261 */
0ecb11d7 1262 if (BGE_IS_JUMBO_CAPABLE(sc)) {
20c9a969
SZ
1263 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1264
1265 rcb->bge_hostaddr.bge_addr_lo =
1266 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1267 rcb->bge_hostaddr.bge_addr_hi =
1268 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1269 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1270 sc->bge_cdata.bge_rx_jumbo_ring_map,
1271 BUS_DMASYNC_PREREAD);
7e40b8c5
HP
1272 rcb->bge_maxlen_flags =
1273 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1274 BGE_RCB_FLAG_RING_DISABLED);
0ecb11d7 1275 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
7e40b8c5
HP
1276 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1277 rcb->bge_hostaddr.bge_addr_hi);
1278 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1279 rcb->bge_hostaddr.bge_addr_lo);
1280 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1281 rcb->bge_maxlen_flags);
1282 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1283
1284 /* Set up dummy disabled mini ring RCB */
20c9a969 1285 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
7e40b8c5
HP
1286 rcb->bge_maxlen_flags =
1287 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1288 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1289 rcb->bge_maxlen_flags);
1290 }
984263bc
MD
1291
1292 /*
1293 * Set the BD ring replentish thresholds. The recommended
1294 * values are 1/8th the number of descriptors allocated to
1295 * each ring.
1296 */
0ecb11d7
SZ
1297 if (BGE_IS_5705_PLUS(sc))
1298 val = 8;
1299 else
1300 val = BGE_STD_RX_RING_CNT / 8;
1301 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
984263bc
MD
1302 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1303
1304 /*
1305 * Disable all unused send rings by setting the 'ring disabled'
1306 * bit in the flags field of all the TX send ring control blocks.
1307 * These are located in NIC memory.
1308 */
20c9a969 1309 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
984263bc 1310 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
20c9a969
SZ
1311 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1312 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1313 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1314 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1315 }
1316
1317 /* Configure TX RCB 0 (we use only the first ring) */
20c9a969
SZ
1318 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1319 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1320 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1321 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1322 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1323 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
0ecb11d7 1324 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1325 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1326 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1327 }
984263bc
MD
1328
1329 /* Disable all unused RX return rings */
20c9a969 1330 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
984263bc 1331 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
20c9a969
SZ
1332 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1333 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1334 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
7e40b8c5 1335 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
20c9a969
SZ
1336 BGE_RCB_FLAG_RING_DISABLED));
1337 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
984263bc 1338 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
33c39a69 1339 (i * (sizeof(uint64_t))), 0);
20c9a969 1340 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1341 }
1342
1343 /* Initialize RX ring indexes */
1344 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1345 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1346 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1347
1348 /*
1349 * Set up RX return ring 0
1350 * Note that the NIC address for RX return rings is 0x00000000.
1351 * The return rings live entirely within the host, so the
1352 * nicaddr field in the RCB isn't used.
1353 */
20c9a969
SZ
1354 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1355 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1356 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1357 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1358 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1359 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1360 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
984263bc
MD
1361
1362 /* Set random backoff seed for TX */
1363 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1364 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1365 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1366 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1367 BGE_TX_BACKOFF_SEED_MASK);
1368
1369 /* Set inter-packet gap */
1370 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1371
1372 /*
1373 * Specify which ring to use for packets that don't match
1374 * any RX rules.
1375 */
1376 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1377
1378 /*
1379 * Configure number of RX lists. One interrupt distribution
1380 * list, sixteen active lists, one bad frames class.
1381 */
1382 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1383
1384 /* Inialize RX list placement stats mask. */
1385 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1386 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1387
1388 /* Disable host coalescing until we get it set up */
1389 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1390
1391 /* Poll to make sure it's shut down. */
1392 for (i = 0; i < BGE_TIMEOUT; i++) {
1393 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1394 break;
1395 DELAY(10);
1396 }
1397
1398 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1399 if_printf(&sc->arpcom.ac_if,
1400 "host coalescing engine failed to idle\n");
984263bc
MD
1401 return(ENXIO);
1402 }
1403
1404 /* Set up host coalescing defaults */
1405 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1406 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1407 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1408 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
0ecb11d7 1409 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1410 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1411 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1412 }
984263bc
MD
1413 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1414 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
984263bc
MD
1415
1416 /* Set up address of statistics block */
0ecb11d7 1417 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1418 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1419 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
7e40b8c5 1420 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
20c9a969 1421 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
7e40b8c5
HP
1422
1423 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1424 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1425 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1426 }
984263bc
MD
1427
1428 /* Set up address of status block */
20c9a969
SZ
1429 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1430 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
984263bc 1431 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
20c9a969
SZ
1432 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1433 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1434 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
984263bc
MD
1435
1436 /* Turn on host coalescing state machine */
1437 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1438
1439 /* Turn on RX BD completion state machine and enable attentions */
1440 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1441 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1442
1443 /* Turn on RX list placement state machine */
1444 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1445
1446 /* Turn on RX list selector state machine. */
0ecb11d7 1447 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1448 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc
MD
1449
1450 /* Turn on DMA, clear stats */
1451 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1452 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1453 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1454 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
0ecb11d7
SZ
1455 ((sc->bge_flags & BGE_FLAG_TBI) ?
1456 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
984263bc
MD
1457
1458 /* Set misc. local control, enable interrupts on attentions */
1459 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1460
1461#ifdef notdef
1462 /* Assert GPIO pins for PHY reset */
1463 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1464 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1465 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1466 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1467#endif
1468
1469 /* Turn on DMA completion state machine */
0ecb11d7 1470 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1471 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
1472
1473 /* Turn on write DMA state machine */
0ecb11d7
SZ
1474 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1475 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1476 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1477 val |= (1 << 29); /* Enable host coalescing bug fix. */
1478 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
984263bc
MD
1479
1480 /* Turn on read DMA state machine */
1481 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1482 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1483
1484 /* Turn on RX data completion state machine */
1485 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1486
1487 /* Turn on RX BD initiator state machine */
1488 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1489
1490 /* Turn on RX data and RX BD initiator state machine */
1491 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1492
1493 /* Turn on Mbuf cluster free state machine */
0ecb11d7 1494 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1495 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
1496
1497 /* Turn on send BD completion state machine */
1498 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1499
1500 /* Turn on send data completion state machine */
1501 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1502
1503 /* Turn on send data initiator state machine */
1504 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1505
1506 /* Turn on send BD initiator state machine */
1507 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1508
1509 /* Turn on send BD selector state machine */
1510 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1511
1512 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1513 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1514 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1515
1516 /* ack/clear link change events */
1517 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
7e40b8c5
HP
1518 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1519 BGE_MACSTAT_LINK_CHANGED);
20c9a969 1520 CSR_WRITE_4(sc, BGE_MI_STS, 0);
984263bc
MD
1521
1522 /* Enable PHY auto polling (for MII/GMII only) */
0ecb11d7 1523 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
1524 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1525 } else {
1526 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
db861466
SZ
1527 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1528 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
984263bc
MD
1529 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1530 BGE_EVTENB_MI_INTERRUPT);
db861466 1531 }
984263bc
MD
1532 }
1533
db861466
SZ
1534 /*
1535 * Clear any pending link state attention.
1536 * Otherwise some link state change events may be lost until attention
1537 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1538 * It's not necessary on newer BCM chips - perhaps enabling link
1539 * state change attentions implies clearing pending attention.
1540 */
1541 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1542 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1543 BGE_MACSTAT_LINK_CHANGED);
1544
984263bc
MD
1545 /* Enable link state change attentions. */
1546 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1547
1548 return(0);
1549}
1550
1551/*
1552 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1553 * against our list and return its name if we find a match. Note
1554 * that since the Broadcom controller contains VPD support, we
1555 * can get the device name string from the controller itself instead
1556 * of the compiled-in string. This is a little slow, but it guarantees
1557 * we'll always announce the right product name.
1558 */
1559static int
33c39a69 1560bge_probe(device_t dev)
984263bc 1561{
984263bc 1562 struct bge_softc *sc;
33c39a69 1563 struct bge_type *t;
984263bc 1564 char *descbuf;
33c39a69
JS
1565 uint16_t product, vendor;
1566
1567 product = pci_get_device(dev);
1568 vendor = pci_get_vendor(dev);
1569
1570 for (t = bge_devs; t->bge_name != NULL; t++) {
1571 if (vendor == t->bge_vid && product == t->bge_did)
1572 break;
1573 }
984263bc 1574
33c39a69
JS
1575 if (t->bge_name == NULL)
1576 return(ENXIO);
984263bc
MD
1577
1578 sc = device_get_softc(dev);
efda3bd0 1579 descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
f8c7a42d 1580 ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
33c39a69
JS
1581 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1582 device_set_desc_copy(dev, descbuf);
1583 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
0ecb11d7 1584 sc->bge_flags |= BGE_FLAG_NO_3LED;
efda3bd0 1585 kfree(descbuf, M_TEMP);
33c39a69 1586 return(0);
984263bc
MD
1587}
1588
1589static int
33c39a69 1590bge_attach(device_t dev)
984263bc 1591{
984263bc
MD
1592 struct ifnet *ifp;
1593 struct bge_softc *sc;
33c39a69
JS
1594 uint32_t hwcfg = 0;
1595 uint32_t mac_addr = 0;
c6fd6f3b 1596 int error = 0, rid;
0a8b5977 1597 uint8_t ether_addr[ETHER_ADDR_LEN];
984263bc 1598
984263bc 1599 sc = device_get_softc(dev);
984263bc 1600 sc->bge_dev = dev;
263489fb 1601 callout_init(&sc->bge_stat_timer);
16dca0df 1602 lwkt_serialize_init(&sc->bge_jslot_serializer);
984263bc
MD
1603
1604 /*
1605 * Map control/status registers.
1606 */
cc8ddf9e 1607 pci_enable_busmaster(dev);
984263bc
MD
1608
1609 rid = BGE_PCI_BAR0;
cc8ddf9e
JS
1610 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1611 RF_ACTIVE);
984263bc
MD
1612
1613 if (sc->bge_res == NULL) {
c6fd6f3b 1614 device_printf(dev, "couldn't map memory\n");
984263bc 1615 error = ENXIO;
9a717c15 1616 return(error);
984263bc
MD
1617 }
1618
1619 sc->bge_btag = rman_get_bustag(sc->bge_res);
1620 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
984263bc 1621
9a6ee7e2
JS
1622 /* Save ASIC rev. */
1623 sc->bge_chipid =
1624 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1625 BGE_PCIMISCCTL_ASICREV;
1626 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1627 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1628
0ecb11d7
SZ
1629 /* Save chipset family. */
1630 switch (sc->bge_asicrev) {
1631 case BGE_ASICREV_BCM5700:
1632 case BGE_ASICREV_BCM5701:
1633 case BGE_ASICREV_BCM5703:
1634 case BGE_ASICREV_BCM5704:
1635 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1636 break;
1637
1638 case BGE_ASICREV_BCM5714_A0:
1639 case BGE_ASICREV_BCM5780:
1640 case BGE_ASICREV_BCM5714:
1641 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1642 /* Fall through */
1643
1644 case BGE_ASICREV_BCM5750:
1645 case BGE_ASICREV_BCM5752:
1646 case BGE_ASICREV_BCM5755:
1647 case BGE_ASICREV_BCM5787:
1648 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1649 /* Fall through */
1650
1651 case BGE_ASICREV_BCM5705:
1652 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1653 break;
1654 }
9a6ee7e2
JS
1655
1656 /*
0ecb11d7 1657 * Set various quirk flags.
9a6ee7e2 1658 */
9a6ee7e2 1659
0ecb11d7
SZ
1660 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1661 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1662 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1663 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1664 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1665 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1666 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1667
1668 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1669 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1670 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1671
1672 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1673 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1674 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1675
1676 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1677 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1678
1679 if (BGE_IS_5705_PLUS(sc)) {
1680 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1681 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1682 uint32_t product = pci_get_device(dev);
1683
1684 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1685 product != PCI_PRODUCT_BROADCOM_BCM5756)
1686 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1687 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1688 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1689 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1690 sc->bge_flags |= BGE_FLAG_BER_BUG;
9a6ee7e2
JS
1691 }
1692 }
1693
0ecb11d7
SZ
1694 /* Allocate interrupt */
1695 rid = 0;
1696
1697 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1698 RF_SHAREABLE | RF_ACTIVE);
1699
1700 if (sc->bge_irq == NULL) {
1701 device_printf(dev, "couldn't map interrupt\n");
1702 error = ENXIO;
1703 goto fail;
1704 }
1705
1706 /*
1707 * Check if this is a PCI-X or PCI Express device.
1708 */
1709 if (BGE_IS_5705_PLUS(sc)) {
1710 uint32_t reg;
1711
1712 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1713 if ((reg & 0xff) == BGE_PCIE_CAPID)
1714 sc->bge_flags |= BGE_FLAG_PCIE;
1715 } else {
1716 /*
1717 * Check if the device is in PCI-X Mode.
1718 * (This bit is not valid on PCI Express controllers.)
1719 */
1720 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1721 BGE_PCISTATE_PCI_BUSMODE) == 0)
1722 sc->bge_flags |= BGE_FLAG_PCIX;
1723 }
1724
c6fd6f3b
JS
1725 ifp = &sc->arpcom.ac_if;
1726 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
1727
1728 /* Try to reset the chip. */
1729 bge_reset(sc);
1730
1731 if (bge_chipinit(sc)) {
c6fd6f3b 1732 device_printf(dev, "chip initialization failed\n");
984263bc
MD
1733 error = ENXIO;
1734 goto fail;
1735 }
1736
1737 /*
1738 * Get station address from the EEPROM.
1739 */
1740 mac_addr = bge_readmem_ind(sc, 0x0c14);
1741 if ((mac_addr >> 16) == 0x484b) {
0a8b5977
JS
1742 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1743 ether_addr[1] = (uint8_t)mac_addr;
984263bc 1744 mac_addr = bge_readmem_ind(sc, 0x0c18);
0a8b5977
JS
1745 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1746 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1747 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1748 ether_addr[5] = (uint8_t)mac_addr;
1749 } else if (bge_read_eeprom(sc, ether_addr,
984263bc 1750 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
c6fd6f3b 1751 device_printf(dev, "failed to read station address\n");
984263bc
MD
1752 error = ENXIO;
1753 goto fail;
1754 }
1755
20c9a969 1756 /* 5705/5750 limits RX return ring to 512 entries. */
0ecb11d7 1757 if (BGE_IS_5705_PLUS(sc))
20c9a969
SZ
1758 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1759 else
1760 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
984263bc 1761
20c9a969
SZ
1762 error = bge_dma_alloc(sc);
1763 if (error)
984263bc 1764 goto fail;
984263bc
MD
1765
1766 /* Set default tuneable values. */
1767 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1768 sc->bge_rx_coal_ticks = 150;
1769 sc->bge_tx_coal_ticks = 150;
0ecb11d7
SZ
1770 sc->bge_rx_max_coal_bds = 10;
1771 sc->bge_tx_max_coal_bds = 10;
984263bc
MD
1772
1773 /* Set up ifnet structure */
984263bc 1774 ifp->if_softc = sc;
984263bc
MD
1775 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1776 ifp->if_ioctl = bge_ioctl;
984263bc
MD
1777 ifp->if_start = bge_start;
1778 ifp->if_watchdog = bge_watchdog;
1779 ifp->if_init = bge_init;
1780 ifp->if_mtu = ETHERMTU;
cb623c48 1781 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
936ff230
JS
1782 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1783 ifq_set_ready(&ifp->if_snd);
cb623c48
SZ
1784
1785 /*
1786 * 5700 B0 chips do not support checksumming correctly due
1787 * to hardware bugs.
1788 */
1789 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1790 ifp->if_capabilities |= IFCAP_HWCSUM;
1791 ifp->if_hwassist = BGE_CSUM_FEATURES;
1792 }
984263bc
MD
1793 ifp->if_capenable = ifp->if_capabilities;
1794
984263bc
MD
1795 /*
1796 * Figure out what sort of media we have by checking the
1797 * hardware config word in the first 32k of NIC internal memory,
1798 * or fall back to examining the EEPROM if necessary.
1799 * Note: on some BCM5700 cards, this value appears to be unset.
1800 * If that's the case, we have to rely on identifying the NIC
1801 * by its PCI subsystem ID, as we do below for the SysKonnect
1802 * SK-9D41.
1803 */
1804 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1805 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1806 else {
7b47d9c2
SZ
1807 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1808 sizeof(hwcfg))) {
1809 device_printf(dev, "failed to read EEPROM\n");
1810 error = ENXIO;
1811 goto fail;
1812 }
984263bc
MD
1813 hwcfg = ntohl(hwcfg);
1814 }
1815
1816 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
0ecb11d7 1817 sc->bge_flags |= BGE_FLAG_TBI;
984263bc
MD
1818
1819 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
cc8ddf9e 1820 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
0ecb11d7 1821 sc->bge_flags |= BGE_FLAG_TBI;
984263bc 1822
0ecb11d7 1823 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
1824 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1825 bge_ifmedia_upd, bge_ifmedia_sts);
1826 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1827 ifmedia_add(&sc->bge_ifmedia,
1828 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1829 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1830 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
70059b3c 1831 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
984263bc
MD
1832 } else {
1833 /*
1834 * Do transceiver setup.
1835 */
1836 if (mii_phy_probe(dev, &sc->bge_miibus,
1837 bge_ifmedia_upd, bge_ifmedia_sts)) {
c6fd6f3b 1838 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
1839 error = ENXIO;
1840 goto fail;
1841 }
1842 }
1843
1844 /*
1845 * When using the BCM5701 in PCI-X mode, data corruption has
1846 * been observed in the first few bytes of some received packets.
1847 * Aligning the packet buffer in memory eliminates the corruption.
1848 * Unfortunately, this misaligns the packet payloads. On platforms
1849 * which do not support unaligned accesses, we will realign the
1850 * payloads by copying the received packets.
1851 */
0ecb11d7
SZ
1852 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1853 (sc->bge_flags & BGE_FLAG_PCIX))
1854 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
984263bc 1855
db861466
SZ
1856 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1857 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1858 sc->bge_link_upd = bge_bcm5700_link_upd;
1859 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
0ecb11d7 1860 } else if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
1861 sc->bge_link_upd = bge_tbi_link_upd;
1862 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1863 } else {
1864 sc->bge_link_upd = bge_copper_link_upd;
1865 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1866 }
1867
984263bc
MD
1868 /*
1869 * Call MI attach routine.
1870 */
78195a76 1871 ether_ifattach(ifp, ether_addr, NULL);
984263bc 1872
78195a76
MD
1873 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1874 bge_intr, sc, &sc->bge_intrhand,
1875 ifp->if_serializer);
9a717c15
JS
1876 if (error) {
1877 ether_ifdetach(ifp);
1878 device_printf(dev, "couldn't set up irq\n");
1879 goto fail;
1880 }
9a717c15 1881 return(0);
984263bc 1882fail:
9a717c15 1883 bge_detach(dev);
984263bc
MD
1884 return(error);
1885}
1886
1887static int
33c39a69 1888bge_detach(device_t dev)
984263bc 1889{
9a717c15
JS
1890 struct bge_softc *sc = device_get_softc(dev);
1891 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1892
9a717c15 1893 if (device_is_attached(dev)) {
cdf89432 1894 lwkt_serialize_enter(ifp->if_serializer);
9a717c15
JS
1895 bge_stop(sc);
1896 bge_reset(sc);
cdf89432
SZ
1897 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1898 lwkt_serialize_exit(ifp->if_serializer);
984263bc 1899
cdf89432
SZ
1900 ether_ifdetach(ifp);
1901 }
0ecb11d7 1902 if (sc->bge_flags & BGE_FLAG_TBI)
984263bc 1903 ifmedia_removeall(&sc->bge_ifmedia);
cbf32d7e 1904 if (sc->bge_miibus)
984263bc 1905 device_delete_child(dev, sc->bge_miibus);
9a717c15 1906 bus_generic_detach(dev);
984263bc
MD
1907
1908 bge_release_resources(sc);
20c9a969 1909 bge_dma_free(sc);
9a717c15 1910
20c9a969 1911 return 0;
984263bc
MD
1912}
1913
1914static void
33c39a69 1915bge_release_resources(struct bge_softc *sc)
984263bc
MD
1916{
1917 device_t dev;
1918
1919 dev = sc->bge_dev;
1920
984263bc
MD
1921 if (sc->bge_irq != NULL)
1922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1923
1924 if (sc->bge_res != NULL)
1925 bus_release_resource(dev, SYS_RES_MEMORY,
1926 BGE_PCI_BAR0, sc->bge_res);
984263bc
MD
1927}
1928
1929static void
33c39a69 1930bge_reset(struct bge_softc *sc)
984263bc
MD
1931{
1932 device_t dev;
9a6ee7e2 1933 uint32_t cachesize, command, pcistate, reset;
0ecb11d7 1934 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
984263bc
MD
1935 int i, val = 0;
1936
1937 dev = sc->bge_dev;
1938
0ecb11d7
SZ
1939 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
1940 if (sc->bge_flags & BGE_FLAG_PCIE)
1941 write_op = bge_writemem_direct;
1942 else
1943 write_op = bge_writemem_ind;
1944 } else {
1945 write_op = bge_writereg_ind;
1946 }
1947
984263bc
MD
1948 /* Save some important PCI state. */
1949 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1950 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1951 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1952
1953 pci_write_config(dev, BGE_PCI_MISC_CTL,
1954 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
20c9a969 1955 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
984263bc 1956
0ecb11d7
SZ
1957 /* Disable fastboot on controllers that support it. */
1958 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
1959 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1960 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1961 if (bootverbose)
1962 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
1963 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
1964 }
1965
1966 /*
1967 * Write the magic number to SRAM at offset 0xB50.
1968 * When firmware finishes its initialization it will
1969 * write ~BGE_MAGIC_NUMBER to the same location.
1970 */
1971 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1972
9a6ee7e2
JS
1973 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1974
1975 /* XXX: Broadcom Linux driver. */
0ecb11d7 1976 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
1977 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
1978 CSR_WRITE_4(sc, 0x7e2c, 0x20);
1979 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1980 /* Prevent PCIE link training during global reset */
1981 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1982 reset |= (1<<29);
1983 }
1984 }
1985
0ecb11d7
SZ
1986 /*
1987 * Set GPHY Power Down Override to leave GPHY
1988 * powered up in D0 uninitialized.
1989 */
1990 if (BGE_IS_5705_PLUS(sc))
1991 reset |= 0x04000000;
1992
984263bc 1993 /* Issue global reset */
0ecb11d7 1994 write_op(sc, BGE_MISC_CFG, reset);
984263bc
MD
1995
1996 DELAY(1000);
1997
9a6ee7e2 1998 /* XXX: Broadcom Linux driver. */
0ecb11d7 1999 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
2000 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2001 uint32_t v;
2002
2003 DELAY(500000); /* wait for link training to complete */
2004 v = pci_read_config(dev, 0xc4, 4);
2005 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2006 }
0ecb11d7
SZ
2007 /*
2008 * Set PCIE max payload size to 128 bytes and
2009 * clear error status.
2010 */
9a6ee7e2
JS
2011 pci_write_config(dev, 0xd8, 0xf5000, 4);
2012 }
2013
984263bc
MD
2014 /* Reset some of the PCI state that got zapped by reset */
2015 pci_write_config(dev, BGE_PCI_MISC_CTL,
2016 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
20c9a969 2017 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
984263bc
MD
2018 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2019 pci_write_config(dev, BGE_PCI_CMD, command, 4);
0ecb11d7 2020 write_op(sc, BGE_MISC_CFG, (65 << 1));
984263bc 2021
a313b56f 2022 /* Enable memory arbiter. */
0ecb11d7
SZ
2023 if (BGE_IS_5714_FAMILY(sc)) {
2024 uint32_t val;
2025
2026 val = CSR_READ_4(sc, BGE_MARB_MODE);
2027 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2028 } else {
a313b56f 2029 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
0ecb11d7 2030 }
a313b56f 2031
984263bc 2032 /*
0ecb11d7 2033 * Poll until we see the 1's complement of the magic number.
984263bc
MD
2034 * This indicates that the firmware initialization
2035 * is complete.
2036 */
2037 for (i = 0; i < BGE_TIMEOUT; i++) {
2038 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2039 if (val == ~BGE_MAGIC_NUMBER)
2040 break;
2041 DELAY(10);
2042 }
2043
2044 if (i == BGE_TIMEOUT) {
0ecb11d7
SZ
2045 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2046 "found 0x%08x\n", val);
984263bc
MD
2047 return;
2048 }
2049
2050 /*
2051 * XXX Wait for the value of the PCISTATE register to
2052 * return to its original pre-reset state. This is a
2053 * fairly good indicator of reset completion. If we don't
2054 * wait for the reset to fully complete, trying to read
2055 * from the device's non-PCI registers may yield garbage
2056 * results.
2057 */
2058 for (i = 0; i < BGE_TIMEOUT; i++) {
2059 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2060 break;
2061 DELAY(10);
2062 }
2063
0ecb11d7
SZ
2064 if (sc->bge_flags & BGE_FLAG_PCIE) {
2065 reset = bge_readmem_ind(sc, 0x7c00);
2066 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2067 }
2068
984263bc 2069 /* Fix up byte swapping */
20c9a969 2070 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
984263bc
MD
2071 BGE_MODECTL_BYTESWAP_DATA);
2072
2073 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2074
70059b3c
JS
2075 /*
2076 * The 5704 in TBI mode apparently needs some special
2077 * adjustment to insure the SERDES drive level is set
2078 * to 1.2V.
2079 */
0ecb11d7
SZ
2080 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2081 (sc->bge_flags & BGE_FLAG_TBI)) {
70059b3c
JS
2082 uint32_t serdescfg;
2083
2084 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2085 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2086 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2087 }
2088
9a6ee7e2 2089 /* XXX: Broadcom Linux driver. */
0ecb11d7
SZ
2090 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2091 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
9a6ee7e2 2092 uint32_t v;
984263bc 2093
9a6ee7e2
JS
2094 v = CSR_READ_4(sc, 0x7c00);
2095 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2096 }
2097
2098 DELAY(10000);
984263bc
MD
2099}
2100
2101/*
2102 * Frame reception handling. This is called if there's a frame
2103 * on the receive return list.
2104 *
2105 * Note: we have to be able to handle two possibilities here:
2106 * 1) the frame is from the jumbo recieve ring
2107 * 2) the frame is from the standard receive ring
2108 */
2109
2110static void
33c39a69 2111bge_rxeof(struct bge_softc *sc)
984263bc
MD
2112{
2113 struct ifnet *ifp;
2114 int stdcnt = 0, jumbocnt = 0;
2115
449e06cc 2116 if (sc->bge_rx_saved_considx ==
20c9a969 2117 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
449e06cc
SZ
2118 return;
2119
984263bc
MD
2120 ifp = &sc->arpcom.ac_if;
2121
20c9a969
SZ
2122 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2123 sc->bge_cdata.bge_rx_return_ring_map,
2124 BUS_DMASYNC_POSTREAD);
2125 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2126 sc->bge_cdata.bge_rx_std_ring_map,
2127 BUS_DMASYNC_POSTREAD);
0ecb11d7 2128 if (BGE_IS_JUMBO_CAPABLE(sc)) {
20c9a969
SZ
2129 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2130 sc->bge_cdata.bge_rx_jumbo_ring_map,
2131 BUS_DMASYNC_POSTREAD);
2132 }
2133
2134 while (sc->bge_rx_saved_considx !=
2135 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
984263bc 2136 struct bge_rx_bd *cur_rx;
33c39a69 2137 uint32_t rxidx;
984263bc 2138 struct mbuf *m = NULL;
33c39a69 2139 uint16_t vlan_tag = 0;
984263bc
MD
2140 int have_tag = 0;
2141
2142 cur_rx =
20c9a969 2143 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
984263bc
MD
2144
2145 rxidx = cur_rx->bge_idx;
7e40b8c5 2146 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
984263bc
MD
2147
2148 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2149 have_tag = 1;
2150 vlan_tag = cur_rx->bge_vlan_tag;
2151 }
2152
2153 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2154 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2155 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2156 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2157 jumbocnt++;
2158 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2159 ifp->if_ierrors++;
2160 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2161 continue;
2162 }
2163 if (bge_newbuf_jumbo(sc,
2164 sc->bge_jumbo, NULL) == ENOBUFS) {
2165 ifp->if_ierrors++;
2166 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2167 continue;
2168 }
2169 } else {
2170 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
20c9a969
SZ
2171 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2172 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2173 BUS_DMASYNC_POSTREAD);
2174 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2175 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
984263bc
MD
2176 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2177 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2178 stdcnt++;
2179 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2180 ifp->if_ierrors++;
2181 bge_newbuf_std(sc, sc->bge_std, m);
2182 continue;
2183 }
2184 if (bge_newbuf_std(sc, sc->bge_std,
2185 NULL) == ENOBUFS) {
2186 ifp->if_ierrors++;
2187 bge_newbuf_std(sc, sc->bge_std, m);
2188 continue;
2189 }
2190 }
2191
2192 ifp->if_ipackets++;
2193#ifndef __i386__
2194 /*
2195 * The i386 allows unaligned accesses, but for other
2196 * platforms we must make sure the payload is aligned.
2197 */
0ecb11d7 2198 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
984263bc
MD
2199 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2200 cur_rx->bge_len);
2201 m->m_data += ETHER_ALIGN;
2202 }
2203#endif
160185fa 2204 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
984263bc
MD
2205 m->m_pkthdr.rcvif = ifp;
2206
cb623c48
SZ
2207 if (ifp->if_capenable & IFCAP_RXCSUM) {
2208 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2209 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2210 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2211 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2212 }
2213 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2214 m->m_pkthdr.len >= BGE_MIN_FRAME) {
984263bc
MD
2215 m->m_pkthdr.csum_data =
2216 cur_rx->bge_tcp_udp_csum;
cb623c48
SZ
2217 m->m_pkthdr.csum_flags |=
2218 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
984263bc
MD
2219 }
2220 }
984263bc
MD
2221
2222 /*
2223 * If we received a packet with a vlan tag, pass it
2224 * to vlan_input() instead of ether_input().
2225 */
2226 if (have_tag) {
3013ac0e 2227 VLAN_INPUT_TAG(m, vlan_tag);
984263bc 2228 have_tag = vlan_tag = 0;
78195a76
MD
2229 } else {
2230 ifp->if_input(ifp, m);
984263bc 2231 }
984263bc
MD
2232 }
2233
20c9a969
SZ
2234 if (stdcnt > 0) {
2235 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2236 sc->bge_cdata.bge_rx_std_ring_map,
2237 BUS_DMASYNC_PREWRITE);
2238 }
2239
0ecb11d7
SZ
2240 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2241 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2242 sc->bge_cdata.bge_rx_jumbo_ring_map,
2243 BUS_DMASYNC_PREWRITE);
20c9a969
SZ
2244 }
2245
984263bc
MD
2246 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2247 if (stdcnt)
2248 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2249 if (jumbocnt)
2250 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
2251}
2252
2253static void
33c39a69 2254bge_txeof(struct bge_softc *sc)
984263bc
MD
2255{
2256 struct bge_tx_bd *cur_tx = NULL;
2257 struct ifnet *ifp;
2258
449e06cc 2259 if (sc->bge_tx_saved_considx ==
20c9a969 2260 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
449e06cc
SZ
2261 return;
2262
984263bc
MD
2263 ifp = &sc->arpcom.ac_if;
2264
20c9a969
SZ
2265 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2266 sc->bge_cdata.bge_tx_ring_map,
2267 BUS_DMASYNC_POSTREAD);
2268
984263bc
MD
2269 /*
2270 * Go through our tx ring and free mbufs for those
2271 * frames that have been sent.
2272 */
2273 while (sc->bge_tx_saved_considx !=
20c9a969
SZ
2274 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2275 uint32_t idx = 0;
984263bc
MD
2276
2277 idx = sc->bge_tx_saved_considx;
20c9a969 2278 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
984263bc
MD
2279 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2280 ifp->if_opackets++;
2281 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
20c9a969
SZ
2282 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2283 sc->bge_cdata.bge_tx_dmamap[idx],
2284 BUS_DMASYNC_POSTWRITE);
2285 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2286 sc->bge_cdata.bge_tx_dmamap[idx]);
984263bc
MD
2287 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2288 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2289 }
2290 sc->bge_txcnt--;
2291 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
984263bc
MD
2292 }
2293
20c9a969
SZ
2294 if (cur_tx != NULL &&
2295 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2296 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
984263bc 2297 ifp->if_flags &= ~IFF_OACTIVE;
20c9a969 2298
142ca760
SZ
2299 if (sc->bge_txcnt == 0)
2300 ifp->if_timer = 0;
2301
20c9a969
SZ
2302 if (!ifq_is_empty(&ifp->if_snd))
2303 ifp->if_start(ifp);
984263bc
MD
2304}
2305
2306static void
33c39a69 2307bge_intr(void *xsc)
984263bc 2308{
bf522c7f 2309 struct bge_softc *sc = xsc;
33c39a69 2310 struct ifnet *ifp = &sc->arpcom.ac_if;
db861466 2311 uint32_t status;
0029ccf6 2312
142ca760
SZ
2313 /*
2314 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2315 * disable interrupts by writing nonzero like we used to, since with
2316 * our current organization this just gives complications and
2317 * pessimizations for re-enabling interrupts. We used to have races
2318 * instead of the necessary complications. Disabling interrupts
2319 * would just reduce the chance of a status update while we are
2320 * running (by switching to the interrupt-mode coalescence
2321 * parameters), but this chance is already very low so it is more
2322 * efficient to get another interrupt than prevent it.
2323 *
2324 * We do the ack first to ensure another interrupt if there is a
2325 * status update after the ack. We don't check for the status
2326 * changing later because it is more efficient to get another
2327 * interrupt than prevent it, not quite as above (not checking is
2328 * a smaller optimization than not toggling the interrupt enable,
2329 * since checking doesn't involve PCI accesses and toggling require
2330 * the status check). So toggling would probably be a pessimization
2331 * even with MSI. It would only be needed for using a task queue.
2332 */
2333 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2334
20c9a969
SZ
2335 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2336 sc->bge_cdata.bge_status_map,
2337 BUS_DMASYNC_POSTREAD);
2338
984263bc
MD
2339 /*
2340 * Process link state changes.
984263bc 2341 */
db861466
SZ
2342 status = CSR_READ_4(sc, BGE_MAC_STS);
2343 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2344 sc->bge_link_evt = 0;
2345 sc->bge_link_upd(sc, status);
984263bc
MD
2346 }
2347
2348 if (ifp->if_flags & IFF_RUNNING) {
2349 /* Check RX return ring producer/consumer */
2350 bge_rxeof(sc);
2351
2352 /* Check TX ring producer/consumer */
2353 bge_txeof(sc);
2354 }
984263bc
MD
2355}
2356
2357static void
33c39a69 2358bge_tick(void *xsc)
78195a76
MD
2359{
2360 struct bge_softc *sc = xsc;
2361 struct ifnet *ifp = &sc->arpcom.ac_if;
2362
2363 lwkt_serialize_enter(ifp->if_serializer);
984263bc 2364
0ecb11d7 2365 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
2366 bge_stats_update_regs(sc);
2367 else
2368 bge_stats_update(sc);
9a717c15 2369
0ecb11d7 2370 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
2371 /*
2372 * Since in TBI mode auto-polling can't be used we should poll
2373 * link status manually. Here we register pending link event
2374 * and trigger interrupt.
2375 */
2376 sc->bge_link_evt++;
2377 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3f82ed83 2378 } else if (!sc->bge_link) {
db861466 2379 mii_tick(device_get_softc(sc->bge_miibus));
984263bc
MD
2380 }
2381
db861466
SZ
2382 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2383
2384 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2385}
2386
7e40b8c5 2387static void
33c39a69 2388bge_stats_update_regs(struct bge_softc *sc)
7e40b8c5 2389{
33c39a69 2390 struct ifnet *ifp = &sc->arpcom.ac_if;
7e40b8c5 2391 struct bge_mac_stats_regs stats;
33c39a69 2392 uint32_t *s;
7e40b8c5
HP
2393 int i;
2394
33c39a69 2395 s = (uint32_t *)&stats;
7e40b8c5
HP
2396 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2397 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2398 s++;
2399 }
2400
2401 ifp->if_collisions +=
2402 (stats.dot3StatsSingleCollisionFrames +
2403 stats.dot3StatsMultipleCollisionFrames +
2404 stats.dot3StatsExcessiveCollisions +
2405 stats.dot3StatsLateCollisions) -
2406 ifp->if_collisions;
7e40b8c5
HP
2407}
2408
984263bc 2409static void
33c39a69 2410bge_stats_update(struct bge_softc *sc)
984263bc 2411{
33c39a69 2412 struct ifnet *ifp = &sc->arpcom.ac_if;
20c9a969
SZ
2413 bus_size_t stats;
2414
2415 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
984263bc 2416
20c9a969
SZ
2417#define READ_STAT(sc, stats, stat) \
2418 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
984263bc
MD
2419
2420 ifp->if_collisions +=
20c9a969
SZ
2421 (READ_STAT(sc, stats,
2422 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2423 READ_STAT(sc, stats,
2424 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2425 READ_STAT(sc, stats,
2426 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2427 READ_STAT(sc, stats,
2428 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
984263bc
MD
2429 ifp->if_collisions;
2430
20c9a969
SZ
2431#undef READ_STAT
2432
984263bc
MD
2433#ifdef notdef
2434 ifp->if_collisions +=
2435 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2436 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2437 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2438 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2439 ifp->if_collisions;
2440#endif
984263bc
MD
2441}
2442
2443/*
2444 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2445 * pointers to descriptors.
2446 */
2447static int
33c39a69 2448bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 2449{
20c9a969 2450 struct bge_tx_bd *d = NULL;
33c39a69
JS
2451 uint16_t csum_flags = 0;
2452 struct ifvlan *ifv = NULL;
20c9a969
SZ
2453 struct bge_dmamap_arg ctx;
2454 bus_dma_segment_t segs[BGE_NSEG_NEW];
2455 bus_dmamap_t map;
2456 int error, maxsegs, idx, i;
984263bc
MD
2457
2458 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2459 m_head->m_pkthdr.rcvif != NULL &&
2460 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2461 ifv = m_head->m_pkthdr.rcvif->if_softc;
2462
984263bc
MD
2463 if (m_head->m_pkthdr.csum_flags) {
2464 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2465 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2466 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2467 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2468 if (m_head->m_flags & M_LASTFRAG)
2469 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2470 else if (m_head->m_flags & M_FRAG)
2471 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2472 }
20c9a969
SZ
2473
2474 idx = *txidx;
2475 map = sc->bge_cdata.bge_tx_dmamap[idx];
2476
2477 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2478 KASSERT(maxsegs >= BGE_NSEG_SPARE,
2479 ("not enough segments %d\n", maxsegs));
2480
2481 if (maxsegs > BGE_NSEG_NEW)
2482 maxsegs = BGE_NSEG_NEW;
2483
cb623c48
SZ
2484 /*
2485 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2486 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2487 * but when such padded frames employ the bge IP/TCP checksum
2488 * offload, the hardware checksum assist gives incorrect results
2489 * (possibly from incorporating its own padding into the UDP/TCP
2490 * checksum; who knows). If we pad such runts with zeros, the
2491 * onboard checksum comes out correct. We do this by pretending
2492 * the mbuf chain has too many fragments so the coalescing code
2493 * below can assemble the packet into a single buffer that's
2494 * padded out to the mininum frame size.
2495 */
2496 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2497 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2498 error = E2BIG;
2499 } else {
2500 ctx.bge_segs = segs;
2501 ctx.bge_maxsegs = maxsegs;
2502 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2503 m_head, bge_dma_map_mbuf, &ctx,
2504 BUS_DMA_NOWAIT);
2505 }
20c9a969
SZ
2506 if (error == E2BIG || ctx.bge_maxsegs == 0) {
2507 struct mbuf *m_new;
2508
2509 m_new = m_defrag(m_head, MB_DONTWAIT);
2510 if (m_new == NULL) {
2511 if_printf(&sc->arpcom.ac_if,
2512 "could not defrag TX mbuf\n");
2513 error = ENOBUFS;
2514 goto back;
2515 } else {
2516 m_head = m_new;
2517 }
2518
cb623c48
SZ
2519 /*
2520 * Manually pad short frames, and zero the pad space
2521 * to avoid leaking data.
2522 */
2523 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2524 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2525 int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2526
2527 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2528 pad_len);
2529 m_head->m_pkthdr.len += pad_len;
2530 m_head->m_len = m_head->m_pkthdr.len;
2531 }
2532
20c9a969
SZ
2533 ctx.bge_segs = segs;
2534 ctx.bge_maxsegs = maxsegs;
2535 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2536 m_head, bge_dma_map_mbuf, &ctx,
2537 BUS_DMA_NOWAIT);
2538 if (error || ctx.bge_maxsegs == 0) {
2539 if_printf(&sc->arpcom.ac_if,
2540 "could not defrag TX mbuf\n");
2541 if (error == 0)
2542 error = E2BIG;
2543 goto back;
984263bc 2544 }
20c9a969
SZ
2545 } else if (error) {
2546 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2547 goto back;
984263bc
MD
2548 }
2549
20c9a969 2550 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
984263bc 2551
20c9a969
SZ
2552 for (i = 0; ; i++) {
2553 d = &sc->bge_ldata.bge_tx_ring[idx];
984263bc 2554
20c9a969
SZ
2555 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2556 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2557 d->bge_len = segs[i].ds_len;
2558 d->bge_flags = csum_flags;
984263bc 2559
20c9a969
SZ
2560 if (i == ctx.bge_maxsegs - 1)
2561 break;
2562 BGE_INC(idx, BGE_TX_RING_CNT);
2563 }
2564 /* Mark the last segment as end of packet... */
2565 d->bge_flags |= BGE_TXBDFLAG_END;
984263bc 2566
20c9a969
SZ
2567 /* Set vlan tag to the first segment of the packet. */
2568 d = &sc->bge_ldata.bge_tx_ring[*txidx];
2569 if (ifv != NULL) {
2570 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2571 d->bge_vlan_tag = ifv->ifv_tag;
2572 } else {
2573 d->bge_vlan_tag = 0;
2574 }
2575
2576 /*
2577 * Insure that the map for this transmission is placed at
2578 * the array index of the last descriptor in this chain.
2579 */
2580 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2581 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2582 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2583 sc->bge_txcnt += ctx.bge_maxsegs;
2584
2585 BGE_INC(idx, BGE_TX_RING_CNT);
2586 *txidx = idx;
2587back:
2588 if (error)
2589 m_freem(m_head);
2590 return error;
984263bc
MD
2591}
2592
2593/*
2594 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2595 * to the mbuf data regions directly in the transmit descriptors.
2596 */
2597static void
33c39a69 2598bge_start(struct ifnet *ifp)
984263bc 2599{
20c9a969 2600 struct bge_softc *sc = ifp->if_softc;
984263bc 2601 struct mbuf *m_head = NULL;
20c9a969 2602 uint32_t prodidx;
2f54d1d2 2603 int need_trans;
984263bc 2604
20c9a969
SZ
2605 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING ||
2606 !sc->bge_link)
984263bc
MD
2607 return;
2608
94db8384 2609 prodidx = sc->bge_tx_prodidx;
984263bc 2610
2f54d1d2 2611 need_trans = 0;
75544bcd 2612 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
936ff230 2613 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
2614 if (m_head == NULL)
2615 break;
2616
2617 /*
cb623c48
SZ
2618 * XXX
2619 * The code inside the if() block is never reached since we
2620 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2621 * requests to checksum TCP/UDP in a fragmented packet.
2622 *
984263bc
MD
2623 * XXX
2624 * safety overkill. If this is a fragmented packet chain
2625 * with delayed TCP/UDP checksums, then only encapsulate
2626 * it if we have enough descriptors to handle the entire
2627 * chain at once.
2628 * (paranoia -- may not actually be needed)
2629 */
2630 if (m_head->m_flags & M_FIRSTFRAG &&
2631 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2632 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2633 m_head->m_pkthdr.csum_data + 16) {
984263bc
MD
2634 ifp->if_flags |= IFF_OACTIVE;
2635 break;
2636 }
2637 }
2638
20c9a969
SZ
2639 /*
2640 * Sanity check: avoid coming within BGE_NSEG_RSVD
2641 * descriptors of the end of the ring. Also make
2642 * sure there are BGE_NSEG_SPARE descriptors for
2643 * jumbo buffers' defragmentation.
2644 */
2645 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2646 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2647 ifp->if_flags |= IFF_OACTIVE;
2648 break;
2649 }
2650
2651 /*
2652 * Dequeue the packet before encapsulation, since
2653 * bge_encap() may free the packet if error happens.
2654 */
2655 ifq_dequeue(&ifp->if_snd, m_head);
2656
984263bc
MD
2657 /*
2658 * Pack the data into the transmit ring. If we
2659 * don't have room, set the OACTIVE flag and wait
2660 * for the NIC to drain the ring.
2661 */
2662 if (bge_encap(sc, m_head, &prodidx)) {
984263bc
MD
2663 ifp->if_flags |= IFF_OACTIVE;
2664 break;
2665 }
2f54d1d2 2666 need_trans = 1;
984263bc 2667
7600679e 2668 BPF_MTAP(ifp, m_head);
984263bc
MD
2669 }
2670
2f54d1d2
SZ
2671 if (!need_trans)
2672 return;
2673
984263bc
MD
2674 /* Transmit */
2675 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2676 /* 5700 b2 errata */
2677 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2678 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2679
94db8384
SZ
2680 sc->bge_tx_prodidx = prodidx;
2681
984263bc
MD
2682 /*
2683 * Set a timeout in case the chip goes out to lunch.
2684 */
2685 ifp->if_timer = 5;
984263bc
MD
2686}
2687
2688static void
33c39a69 2689bge_init(void *xsc)
984263bc
MD
2690{
2691 struct bge_softc *sc = xsc;
33c39a69
JS
2692 struct ifnet *ifp = &sc->arpcom.ac_if;
2693 uint16_t *m;
984263bc 2694
aa65409c
SZ
2695 ASSERT_SERIALIZED(ifp->if_serializer);
2696
2697 if (ifp->if_flags & IFF_RUNNING)
984263bc 2698 return;
984263bc
MD
2699
2700 /* Cancel pending I/O and flush buffers. */
2701 bge_stop(sc);
2702 bge_reset(sc);
2703 bge_chipinit(sc);
2704
2705 /*
2706 * Init the various state machines, ring
2707 * control blocks and firmware.
2708 */
2709 if (bge_blockinit(sc)) {
c6fd6f3b 2710 if_printf(ifp, "initialization failure\n");
984263bc
MD
2711 return;
2712 }
2713
984263bc
MD
2714 /* Specify MTU. */
2715 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
011c0f93 2716 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
984263bc
MD
2717
2718 /* Load our MAC address. */
33c39a69 2719 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
984263bc
MD
2720 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2721 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2722
2723 /* Enable or disable promiscuous mode as needed. */
6439b28a 2724 bge_setpromisc(sc);
984263bc
MD
2725
2726 /* Program multicast filter. */
2727 bge_setmulti(sc);
2728
2729 /* Init RX ring. */
2730 bge_init_rx_ring_std(sc);
2731
7e40b8c5
HP
2732 /*
2733 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2734 * memory to insure that the chip has in fact read the first
2735 * entry of the ring.
2736 */
2737 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
33c39a69 2738 uint32_t v, i;
7e40b8c5
HP
2739 for (i = 0; i < 10; i++) {
2740 DELAY(20);
2741 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2742 if (v == (MCLBYTES - ETHER_ALIGN))
2743 break;
2744 }
2745 if (i == 10)
c6fd6f3b 2746 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
7e40b8c5
HP
2747 }
2748
984263bc
MD
2749 /* Init jumbo RX ring. */
2750 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2751 bge_init_rx_ring_jumbo(sc);
2752
2753 /* Init our RX return ring index */
2754 sc->bge_rx_saved_considx = 0;
2755
2756 /* Init TX ring. */
2757 bge_init_tx_ring(sc);
2758
2759 /* Turn on transmitter */
2760 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2761
2762 /* Turn on receiver */
2763 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2764
2765 /* Tell firmware we're alive. */
2766 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2767
2768 /* Enable host interrupts. */
2769 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2770 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2771 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2772
2773 bge_ifmedia_upd(ifp);
2774
2775 ifp->if_flags |= IFF_RUNNING;
2776 ifp->if_flags &= ~IFF_OACTIVE;
2777
263489fb 2778 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
984263bc
MD
2779}
2780
2781/*
2782 * Set media options.
2783 */
2784static int
33c39a69 2785bge_ifmedia_upd(struct ifnet *ifp)
984263bc 2786{
33c39a69 2787 struct bge_softc *sc = ifp->if_softc;
984263bc
MD
2788
2789 /* If this is a 1000baseX NIC, enable the TBI port. */
0ecb11d7 2790 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
2791 struct ifmedia *ifm = &sc->bge_ifmedia;
2792
984263bc
MD
2793 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2794 return(EINVAL);
db861466 2795
984263bc
MD
2796 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2797 case IFM_AUTO:
70059b3c
JS
2798 /*
2799 * The BCM5704 ASIC appears to have a special
2800 * mechanism for programming the autoneg
2801 * advertisement registers in TBI mode.
2802 */
5c56d5d8
SZ
2803 if (!bge_fake_autoneg &&
2804 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
70059b3c
JS
2805 uint32_t sgdig;
2806
2807 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2808 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2809 sgdig |= BGE_SGDIGCFG_AUTO |
2810 BGE_SGDIGCFG_PAUSE_CAP |
2811 BGE_SGDIGCFG_ASYM_PAUSE;
2812 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2813 sgdig | BGE_SGDIGCFG_SEND);
2814 DELAY(5);
2815 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2816 }
984263bc
MD
2817 break;
2818 case IFM_1000_SX:
2819 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2820 BGE_CLRBIT(sc, BGE_MAC_MODE,
2821 BGE_MACMODE_HALF_DUPLEX);
2822 } else {
2823 BGE_SETBIT(sc, BGE_MAC_MODE,
2824 BGE_MACMODE_HALF_DUPLEX);
2825 }
2826 break;
2827 default:
2828 return(EINVAL);
2829 }
db861466
SZ
2830 } else {
2831 struct mii_data *mii = device_get_softc(sc->bge_miibus);
984263bc 2832
db861466 2833 sc->bge_link_evt++;
3f82ed83 2834 sc->bge_link = 0;
db861466
SZ
2835 if (mii->mii_instance) {
2836 struct mii_softc *miisc;
984263bc 2837
db861466
SZ
2838 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2839 mii_phy_reset(miisc);
2840 }
2841 mii_mediachg(mii);
2842 }
984263bc
MD
2843 return(0);
2844}
2845
2846/*
2847 * Report current media status.
2848 */
2849static void
33c39a69 2850bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 2851{
33c39a69 2852 struct bge_softc *sc = ifp->if_softc;
984263bc 2853
0ecb11d7 2854 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
2855 ifmr->ifm_status = IFM_AVALID;
2856 ifmr->ifm_active = IFM_ETHER;
2857 if (CSR_READ_4(sc, BGE_MAC_STS) &
db861466 2858 BGE_MACSTAT_TBI_PCS_SYNCHED) {
984263bc 2859 ifmr->ifm_status |= IFM_ACTIVE;
db861466
SZ
2860 } else {
2861 ifmr->ifm_active |= IFM_NONE;
2862 return;
2863 }
2864
984263bc
MD
2865 ifmr->ifm_active |= IFM_1000_SX;
2866 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2867 ifmr->ifm_active |= IFM_HDX;
2868 else
2869 ifmr->ifm_active |= IFM_FDX;
db861466
SZ
2870 } else {
2871 struct mii_data *mii = device_get_softc(sc->bge_miibus);
984263bc 2872
db861466
SZ
2873 mii_pollstat(mii);
2874 ifmr->ifm_active = mii->mii_media_active;
2875 ifmr->ifm_status = mii->mii_media_status;
2876 }
984263bc
MD
2877}
2878
2879static int
33c39a69 2880bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
2881{
2882 struct bge_softc *sc = ifp->if_softc;
2883 struct ifreq *ifr = (struct ifreq *) data;
9a717c15 2884 int mask, error = 0;
984263bc
MD
2885 struct mii_data *mii;
2886
aa65409c
SZ
2887 ASSERT_SERIALIZED(ifp->if_serializer);
2888
984263bc 2889 switch(command) {
984263bc 2890 case SIOCSIFMTU:
0ecb11d7
SZ
2891 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
2892 (BGE_IS_JUMBO_CAPABLE(sc) &&
2893 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
984263bc 2894 error = EINVAL;
0ecb11d7 2895 } else if (ifp->if_mtu != ifr->ifr_mtu) {
984263bc
MD
2896 ifp->if_mtu = ifr->ifr_mtu;
2897 ifp->if_flags &= ~IFF_RUNNING;
2898 bge_init(sc);
2899 }
2900 break;
2901 case SIOCSIFFLAGS:
2902 if (ifp->if_flags & IFF_UP) {
6439b28a
SZ
2903 if (ifp->if_flags & IFF_RUNNING) {
2904 int flags = ifp->if_flags & sc->bge_if_flags;
2905
2906 /*
2907 * If only the state of the PROMISC flag
2908 * changed, then just use the 'set promisc
2909 * mode' command instead of reinitializing
2910 * the entire NIC. Doing a full re-init
2911 * means reloading the firmware and waiting
2912 * for it to start up, which may take a
2913 * second or two. Similarly for ALLMULTI.
2914 */
2915 if (flags & IFF_PROMISC)
2916 bge_setpromisc(sc);
2917 if (flags & IFF_ALLMULTI)
2918 bge_setmulti(sc);
2919 } else {
984263bc 2920 bge_init(sc);
6439b28a 2921 }
984263bc 2922 } else {
aa65409c 2923 if (ifp->if_flags & IFF_RUNNING)
984263bc 2924 bge_stop(sc);
984263bc
MD
2925 }
2926 sc->bge_if_flags = ifp->if_flags;
2927 error = 0;
2928 break;
2929 case SIOCADDMULTI:
2930 case SIOCDELMULTI:
2931 if (ifp->if_flags & IFF_RUNNING) {
2932 bge_setmulti(sc);
2933 error = 0;
2934 }
2935 break;
2936 case SIOCSIFMEDIA:
2937 case SIOCGIFMEDIA:
0ecb11d7 2938 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
2939 error = ifmedia_ioctl(ifp, ifr,
2940 &sc->bge_ifmedia, command);
2941 } else {
2942 mii = device_get_softc(sc->bge_miibus);
2943 error = ifmedia_ioctl(ifp, ifr,
2944 &mii->mii_media, command);
2945 }
2946 break;
2947 case SIOCSIFCAP:
2948 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2949 if (mask & IFCAP_HWCSUM) {
cb623c48 2950 ifp->if_capenable ^= IFCAP_HWCSUM;
984263bc 2951 if (IFCAP_HWCSUM & ifp->if_capenable)
cb623c48 2952 ifp->if_hwassist = BGE_CSUM_FEATURES;
984263bc 2953 else
cb623c48 2954 ifp->if_hwassist = 0;
984263bc
MD
2955 }
2956 error = 0;
2957 break;
2958 default:
4cde4dd5 2959 error = ether_ioctl(ifp, command, data);
984263bc
MD
2960 break;
2961 }
984263bc
MD
2962 return(error);
2963}
2964
2965static void
33c39a69 2966bge_watchdog(struct ifnet *ifp)
984263bc 2967{
33c39a69 2968 struct bge_softc *sc = ifp->if_softc;
984263bc 2969
c6fd6f3b 2970 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc
MD
2971
2972 ifp->if_flags &= ~IFF_RUNNING;
2973 bge_init(sc);
2974
2975 ifp->if_oerrors++;
2f54d1d2
SZ
2976
2977 if (!ifq_is_empty(&ifp->if_snd))
2978 ifp->if_start(ifp);
984263bc
MD
2979}
2980
2981/*
2982 * Stop the adapter and free any mbufs allocated to the
2983 * RX and TX lists.
2984 */
2985static void
33c39a69 2986bge_stop(struct bge_softc *sc)
984263bc 2987{
33c39a69 2988 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
2989 struct ifmedia_entry *ifm;
2990 struct mii_data *mii = NULL;
2991 int mtmp, itmp;
2992
aa65409c
SZ
2993 ASSERT_SERIALIZED(ifp->if_serializer);
2994
0ecb11d7 2995 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
984263bc
MD
2996 mii = device_get_softc(sc->bge_miibus);
2997
263489fb 2998 callout_stop(&sc->bge_stat_timer);
984263bc
MD
2999
3000 /*
3001 * Disable all of the receiver blocks
3002 */
3003 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3004 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3005 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
0ecb11d7 3006 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 3007 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc
MD
3008 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3009 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3010 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3011
3012 /*
3013 * Disable all of the transmit blocks
3014 */
3015 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3016 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3017 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3018 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3019 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
0ecb11d7 3020 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 3021 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
3022 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3023
3024 /*
3025 * Shut down all of the memory managers and related
3026 * state machines.
3027 */
3028 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3029 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
0ecb11d7 3030 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 3031 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
3032 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3033 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
0ecb11d7 3034 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
3035 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3036 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3037 }
984263bc
MD
3038
3039 /* Disable host interrupts. */
3040 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3041 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3042
3043 /*
3044 * Tell firmware we're shutting down.
3045 */
3046 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3047
3048 /* Free the RX lists. */
3049 bge_free_rx_ring_std(sc);
3050
3051 /* Free jumbo RX list. */
0ecb11d7 3052 if (BGE_IS_JUMBO_CAPABLE(sc))
7e40b8c5 3053 bge_free_rx_ring_jumbo(sc);
984263bc
MD
3054
3055 /* Free TX buffers. */
3056 bge_free_tx_ring(sc);
3057
3058 /*
3059 * Isolate/power down the PHY, but leave the media selection
3060 * unchanged so that things will be put back to normal when
3061 * we bring the interface back up.
3062 */
0ecb11d7 3063 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
984263bc
MD
3064 itmp = ifp->if_flags;
3065 ifp->if_flags |= IFF_UP;
3066 ifm = mii->mii_media.ifm_cur;
3067 mtmp = ifm->ifm_media;
3068 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3069 mii_mediachg(mii);
3070 ifm->ifm_media = mtmp;
3071 ifp->if_flags = itmp;
3072 }
3073
3074 sc->bge_link = 0;
3075
3076 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3077
3078 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
3079}
3080
3081/*
3082 * Stop all chip I/O so that the kernel's probe routines don't
3083 * get confused by errant DMAs when rebooting.
3084 */
3085static void
33c39a69 3086bge_shutdown(device_t dev)
984263bc 3087{
33c39a69 3088 struct bge_softc *sc = device_get_softc(dev);
aa65409c 3089 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 3090
aa65409c
SZ
3091 lwkt_serialize_enter(ifp->if_serializer);
3092 bge_stop(sc);
984263bc 3093 bge_reset(sc);
aa65409c
SZ
3094 lwkt_serialize_exit(ifp->if_serializer);
3095}
3096
3097static int
3098bge_suspend(device_t dev)
3099{
3100 struct bge_softc *sc = device_get_softc(dev);
3101 struct ifnet *ifp = &sc->arpcom.ac_if;
3102
3103 lwkt_serialize_enter(ifp->if_serializer);
3104 bge_stop(sc);
3105 lwkt_serialize_exit(ifp->if_serializer);
3106
3107 return 0;
3108}
3109
3110static int
3111bge_resume(device_t dev)
3112{
3113 struct bge_softc *sc = device_get_softc(dev);
3114 struct ifnet *ifp = &sc->arpcom.ac_if;
3115
3116 lwkt_serialize_enter(ifp->if_serializer);
3117
3118 if (ifp->if_flags & IFF_UP) {
3119 bge_init(sc);
3120
20c9a969 3121 if (!ifq_is_empty(&ifp->if_snd))
aa65409c
SZ
3122 ifp->if_start(ifp);
3123 }
3124
3125 lwkt_serialize_exit(ifp->if_serializer);
3126
3127 return 0;
984263bc 3128}
6439b28a
SZ
3129
3130static void
3131bge_setpromisc(struct bge_softc *sc)
3132{
3133 struct ifnet *ifp = &sc->arpcom.ac_if;
3134
3135 if (ifp->if_flags & IFF_PROMISC)
3136 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3137 else
3138 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3139}
20c9a969
SZ
3140
3141static void
3142bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3143{
3144 struct bge_dmamap_arg *ctx = arg;
3145
3146 if (error)
3147 return;
3148
3149 KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3150 ("only one segment is allowed\n"));
3151
3152 ctx->bge_segs[0] = *segs;
3153}
3154
3155static void
3156bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3157 bus_size_t mapsz __unused, int error)
3158{
3159 struct bge_dmamap_arg *ctx = arg;
3160 int i;
3161
3162 if (error)
3163 return;
3164
3165 if (nsegs > ctx->bge_maxsegs) {
3166 ctx->bge_maxsegs = 0;
3167 return;
3168 }
3169
3170 ctx->bge_maxsegs = nsegs;
3171 for (i = 0; i < nsegs; ++i)
3172 ctx->bge_segs[i] = segs[i];
3173}
3174
3175static void
3176bge_dma_free(struct bge_softc *sc)
3177{
3178 int i;
3179
3180 /* Destroy RX/TX mbuf DMA stuffs. */
3181 if (sc->bge_cdata.bge_mtag != NULL) {
3182 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3183 if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3184 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3185 sc->bge_cdata.bge_rx_std_dmamap[i]);
3186 }
3187 }
3188
3189 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3190 if (sc->bge_cdata.bge_tx_dmamap[i]) {
3191 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3192 sc->bge_cdata.bge_tx_dmamap[i]);
3193 }
3194 }
3195 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3196 }
3197
3198 /* Destroy standard RX ring */
3199 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3200 sc->bge_cdata.bge_rx_std_ring_map,
3201 sc->bge_ldata.bge_rx_std_ring);
3202
0ecb11d7 3203 if (BGE_IS_JUMBO_CAPABLE(sc))
20c9a969
SZ
3204 bge_free_jumbo_mem(sc);
3205
3206 /* Destroy RX return ring */
3207 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3208 sc->bge_cdata.bge_rx_return_ring_map,
3209 sc->bge_ldata.bge_rx_return_ring);
3210
3211 /* Destroy TX ring */
3212 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3213 sc->bge_cdata.bge_tx_ring_map,
3214 sc->bge_ldata.bge_tx_ring);
3215
3216 /* Destroy status block */
3217 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3218 sc->bge_cdata.bge_status_map,
3219 sc->bge_ldata.bge_status_block);
3220
3221 /* Destroy statistics block */
3222 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3223 sc->bge_cdata.bge_stats_map,
3224 sc->bge_ldata.bge_stats);
3225
3226 /* Destroy the parent tag */
3227 if (sc->bge_cdata.bge_parent_tag != NULL)
3228 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3229}
3230
3231static int
3232bge_dma_alloc(struct bge_softc *sc)
3233{
3234 struct ifnet *ifp = &sc->arpcom.ac_if;
3235 int nseg, i, error;
3236
3237 /*
3238 * Allocate the parent bus DMA tag appropriate for PCI.
3239 */
3240 error = bus_dma_tag_create(NULL, 1, 0,
3241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3242 NULL, NULL,
3243 MAXBSIZE, BGE_NSEG_NEW,
3244 BUS_SPACE_MAXSIZE_32BIT,
3245 0, &sc->bge_cdata.bge_parent_tag);
3246 if (error) {
3247 if_printf(ifp, "could not allocate parent dma tag\n");
3248 return error;
3249 }
3250
3251 /*
3252 * Create DMA tag for mbufs.
3253 */
3254 nseg = BGE_NSEG_NEW;
3255 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3256 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3257 NULL, NULL,
3258 MCLBYTES * nseg, nseg, MCLBYTES,
3259 BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3260 if (error) {
3261 if_printf(ifp, "could not allocate mbuf dma tag\n");
3262 return error;
3263 }
3264
3265 /*
3266 * Create DMA maps for TX/RX mbufs.
3267 */
3268 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3269 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3270 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3271 if (error) {
3272 int j;
3273
3274 for (j = 0; j < i; ++j) {
3275 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3276 sc->bge_cdata.bge_rx_std_dmamap[j]);
3277 }
3278 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3279 sc->bge_cdata.bge_mtag = NULL;
3280
3281 if_printf(ifp, "could not create DMA map for RX\n");
3282 return error;
3283 }
3284 }
3285
3286 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3287 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3288 &sc->bge_cdata.bge_tx_dmamap[i]);
3289 if (error) {
3290 int j;
3291
3292 for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3293 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3294 sc->bge_cdata.bge_rx_std_dmamap[j]);
3295 }
3296 for (j = 0; j < i; ++j) {
3297 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3298 sc->bge_cdata.bge_tx_dmamap[j]);
3299 }
3300 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3301 sc->bge_cdata.bge_mtag = NULL;
3302
3303 if_printf(ifp, "could not create DMA map for TX\n");
3304 return error;
3305 }
3306 }
3307
3308 /*
3309 * Create DMA stuffs for standard RX ring.
3310 */
3311 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3312 &sc->bge_cdata.bge_rx_std_ring_tag,
3313 &sc->bge_cdata.bge_rx_std_ring_map,
3314 (void **)&sc->bge_ldata.bge_rx_std_ring,
3315 &sc->bge_ldata.bge_rx_std_ring_paddr);
3316 if (error) {
3317 if_printf(ifp, "could not create std RX ring\n");
3318 return error;
3319 }
3320
3321 /*
3322 * Create jumbo buffer pool.
3323 */
0ecb11d7 3324 if (BGE_IS_JUMBO_CAPABLE(sc)) {
20c9a969
SZ
3325 error = bge_alloc_jumbo_mem(sc);
3326 if (error) {
3327 if_printf(ifp, "could not create jumbo buffer pool\n");
3328 return error;
3329 }
3330 }
3331
3332 /*
3333 * Create DMA stuffs for RX return ring.
3334 */
3335 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3336 &sc->bge_cdata.bge_rx_return_ring_tag,
3337 &sc->bge_cdata.bge_rx_return_ring_map,
3338 (void **)&sc->bge_ldata.bge_rx_return_ring,
3339 &sc->bge_ldata.bge_rx_return_ring_paddr);
3340 if (error) {
3341 if_printf(ifp, "could not create RX ret ring\n");
3342 return error;
3343 }
3344
3345 /*
3346 * Create DMA stuffs for TX ring.
3347 */
3348 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3349 &sc->bge_cdata.bge_tx_ring_tag,
3350 &sc->bge_cdata.bge_tx_ring_map,
3351 (void **)&sc->bge_ldata.bge_tx_ring,
3352 &sc->bge_ldata.bge_tx_ring_paddr);
3353 if (error) {
3354 if_printf(ifp, "could not create TX ring\n");
3355 return error;
3356 }
3357
3358 /*
3359 * Create DMA stuffs for status block.
3360 */
3361 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3362 &sc->bge_cdata.bge_status_tag,
3363 &sc->bge_cdata.bge_status_map,
3364 (void **)&sc->bge_ldata.bge_status_block,
3365 &sc->bge_ldata.bge_status_block_paddr);
3366 if (error) {
3367 if_printf(ifp, "could not create status block\n");
3368 return error;
3369 }
3370
3371 /*
3372 * Create DMA stuffs for statistics block.
3373 */
3374 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3375 &sc->bge_cdata.bge_stats_tag,
3376 &sc->bge_cdata.bge_stats_map,
3377 (void **)&sc->bge_ldata.bge_stats,
3378 &sc->bge_ldata.bge_stats_paddr);
3379 if (error) {
3380 if_printf(ifp, "could not create stats block\n");
3381 return error;
3382 }
3383 return 0;
3384}
3385
3386static int
3387bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3388 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3389{
3390 struct ifnet *ifp = &sc->arpcom.ac_if;
3391 struct bge_dmamap_arg ctx;
3392 bus_dma_segment_t seg;
3393 int error;
3394
3395 /*
3396 * Create DMA tag
3397 */
3398 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3399 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3400 NULL, NULL, size, 1, size, 0, tag);
3401 if (error) {
3402 if_printf(ifp, "could not allocate dma tag\n");
3403 return error;
3404 }
3405
3406 /*
3407 * Allocate DMA'able memory
3408 */
3409 error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3410 map);
3411 if (error) {
3412 if_printf(ifp, "could not allocate dma memory\n");
3413 bus_dma_tag_destroy(*tag);
3414 *tag = NULL;
3415 return error;
3416 }
3417
3418 /*
3419 * Load the DMA'able memory
3420 */
3421 ctx.bge_maxsegs = 1;
3422 ctx.bge_segs = &seg;
3423 error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3424 BUS_DMA_WAITOK);
3425 if (error) {
3426 if_printf(ifp, "could not load dma memory\n");
3427 bus_dmamem_free(*tag, *addr, *map);
3428 bus_dma_tag_destroy(*tag);
3429 *tag = NULL;
3430 return error;
3431 }
3432 *paddr = ctx.bge_segs[0].ds_addr;
3433
3434 return 0;
3435}
3436
3437static void
3438bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3439{
3440 if (tag != NULL) {
3441 bus_dmamap_unload(tag, map);
3442 bus_dmamem_free(tag, addr, map);
3443 bus_dma_tag_destroy(tag);
3444 }
3445}
db861466
SZ
3446
3447