i386: LINE interrupt -> LEGACY interrupt
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
CommitLineData
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
d916dbc1 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
10ff1029 46#include <sys/interrupt.h>
14bd3265 47#include <sys/rman.h>
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48#include <sys/bus.h>
49
50#include <machine/segments.h>
51#include <machine/md_var.h>
87cf6827 52#include <machine/intr_machdep.h>
0b692e79 53#include <machine/globaldata.h>
10db3cc6 54#include <machine/smp.h>
2a39d30f 55#include <machine/msi_var.h>
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56
57#include <sys/thread2.h>
5f456c40 58
7265a4fe 59#include <machine_base/icu/elcr_var.h>
9e0e3f85 60
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61#include <machine_base/icu/icu.h>
62#include <machine_base/icu/icu_ipl.h>
ed4d621d 63#include <machine_base/apic/ioapic.h>
37e7efec 64
10ff1029 65extern inthand_t
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66 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
67 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
68 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
69 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
70 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
71 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
72 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
73 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029 74
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75static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
76 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
77 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
78 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
79 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
80 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
81 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
82 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
83 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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84};
85
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86static struct icu_irqmap {
87 int im_type; /* ICU_IMT_ */
88 enum intr_trigger im_trig;
2a39d30f 89 int im_msi_base;
14bd3265 90} icu_irqmaps[MAXCPU][IDT_HWI_VECTORS];
a3dd9120 91
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92static struct lwkt_token icu_irqmap_tok =
93 LWKT_TOKEN_INITIALIZER(icu_irqmap_token);
94
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95#define ICU_IMT_UNUSED 0 /* KEEP THIS */
96#define ICU_IMT_RESERVED 1
2a32da90 97#define ICU_IMT_LEGACY 2
474ba684 98#define ICU_IMT_SYSCALL 3
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99#define ICU_IMT_SHADOW 4
100#define ICU_IMT_MSI 5
a3dd9120 101
14bd3265 102#define ICU_IMT_ISHWI(map) ((map)->im_type != ICU_IMT_RESERVED && \
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103 (map)->im_type != ICU_IMT_SYSCALL && \
104 (map)->im_type != ICU_IMT_SHADOW)
14bd3265 105
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106extern void ICU_INTREN(int);
107extern void ICU_INTRDIS(int);
108
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109extern int imcr_present;
110
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111static void icu_abi_intr_enable(int);
112static void icu_abi_intr_disable(int);
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113static void icu_abi_intr_setup(int, int);
114static void icu_abi_intr_teardown(int);
780a6eec 115static void icu_abi_intr_config(int, enum intr_trigger, enum intr_polarity);
a05c798c 116static int icu_abi_intr_cpuid(int);
780a6eec 117
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118static int icu_abi_msi_alloc(int [], int, int);
119static void icu_abi_msi_release(const int [], int, int);
120static void icu_abi_msi_map(int, uint64_t *, uint32_t *, int);
121
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122static void icu_abi_finalize(void);
123static void icu_abi_cleanup(void);
124static void icu_abi_setdefault(void);
125static void icu_abi_stabilize(void);
126static void icu_abi_initmap(void);
14bd3265 127static void icu_abi_rman_setup(struct rman *);
10db3cc6 128
30c5f287 129struct machintr_abi MachIntrABI_ICU = {
54e1df6b 130 MACHINTR_ICU,
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131 .intr_disable = icu_abi_intr_disable,
132 .intr_enable = icu_abi_intr_enable,
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133 .intr_setup = icu_abi_intr_setup,
134 .intr_teardown = icu_abi_intr_teardown,
780a6eec 135 .intr_config = icu_abi_intr_config,
a05c798c 136 .intr_cpuid = icu_abi_intr_cpuid,
35b2edcb 137
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138 .msi_alloc = icu_abi_msi_alloc,
139 .msi_release = icu_abi_msi_release,
140 .msi_map = icu_abi_msi_map,
141
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142 .finalize = icu_abi_finalize,
143 .cleanup = icu_abi_cleanup,
144 .setdefault = icu_abi_setdefault,
145 .stabilize = icu_abi_stabilize,
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146 .initmap = icu_abi_initmap,
147 .rman_setup = icu_abi_rman_setup
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148};
149
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150static int icu_abi_msi_start; /* NOTE: for testing only */
151
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152/*
153 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
154 */
37e7efec 155
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156static void
157icu_abi_intr_enable(int irq)
158{
159 const struct icu_irqmap *map;
160
161 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS,
162 ("icu enable, invalid irq %d\n", irq));
163
164 map = &icu_irqmaps[mycpuid][irq];
165 KASSERT(ICU_IMT_ISHWI(map),
166 ("icu enable, not hwi irq %d, type %d, cpu%d\n",
167 irq, map->im_type, mycpuid));
2a32da90 168 if (map->im_type != ICU_IMT_LEGACY)
d9a0e2b3 169 return;
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170
171 ICU_INTREN(irq);
172}
173
174static void
175icu_abi_intr_disable(int irq)
176{
177 const struct icu_irqmap *map;
178
179 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS,
180 ("icu disable, invalid irq %d\n", irq));
181
182 map = &icu_irqmaps[mycpuid][irq];
183 KASSERT(ICU_IMT_ISHWI(map),
184 ("icu disable, not hwi irq %d, type %d, cpu%d\n",
185 irq, map->im_type, mycpuid));
2a32da90 186 if (map->im_type != ICU_IMT_LEGACY)
d9a0e2b3 187 return;
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188
189 ICU_INTRDIS(irq);
190}
191
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192/*
193 * Called before interrupts are physically enabled
194 */
37e7efec 195static void
780a6eec 196icu_abi_stabilize(void)
37e7efec 197{
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198 int intr;
199
7bf5fa56 200 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
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201 ICU_INTRDIS(intr);
202 ICU_INTREN(ICU_IRQ_SLAVE);
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203}
204
205/*
206 * Called after interrupts physically enabled but before the
207 * critical section is released.
208 */
209static void
780a6eec 210icu_abi_cleanup(void)
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211{
212 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
213}
214
215/*
216 * Called after stablize and cleanup; critical section is not
217 * held and interrupts are not physically disabled.
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218 */
219static void
780a6eec 220icu_abi_finalize(void)
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221{
222 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
f45bfca0 223 KKASSERT(!ioapic_enable);
54e1df6b 224
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225 /*
226 * If an IMCR is present, programming bit 0 disconnects the 8259
227 * from the BSP. The 8259 may still be connected to LINT0 on the
228 * BSP's LAPIC.
229 *
230 * If we are running SMP the LAPIC is active, try to use virtual
231 * wire mode so we can use other interrupt sources within the LAPIC
232 * in addition to the 8259.
233 */
9d758cc4 234 if (imcr_present) {
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235 outb(0x22, 0x70);
236 outb(0x23, 0x01);
7bf5fa56 237 }
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238}
239
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240static void
241icu_abi_intr_setup(int intr, int flags __unused)
10ff1029 242{
d9a0e2b3 243 const struct icu_irqmap *map;
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244 u_long ef;
245
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246 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
247 ("icu setup, invalid irq %d\n", intr));
248
249 map = &icu_irqmaps[mycpuid][intr];
250 KASSERT(ICU_IMT_ISHWI(map),
251 ("icu setup, not hwi irq %d, type %d, cpu%d\n",
252 intr, map->im_type, mycpuid));
2a32da90 253 if (map->im_type != ICU_IMT_LEGACY)
d9a0e2b3 254 return;
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255
256 ef = read_eflags();
257 cpu_disable_intr();
54e1df6b 258
eaeca813 259 ICU_INTREN(intr);
54e1df6b 260
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261 write_eflags(ef);
262}
263
264static void
265icu_abi_intr_teardown(int intr)
266{
d9a0e2b3 267 const struct icu_irqmap *map;
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268 u_long ef;
269
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270 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
271 ("icu teardown, invalid irq %d\n", intr));
272
273 map = &icu_irqmaps[mycpuid][intr];
274 KASSERT(ICU_IMT_ISHWI(map),
275 ("icu teardown, not hwi irq %d, type %d, cpu%d\n",
276 intr, map->im_type, mycpuid));
2a32da90 277 if (map->im_type != ICU_IMT_LEGACY)
d9a0e2b3 278 return;
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279
280 ef = read_eflags();
281 cpu_disable_intr();
282
eaeca813 283 ICU_INTRDIS(intr);
54e1df6b 284
54e1df6b 285 write_eflags(ef);
10ff1029 286}
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287
288static void
780a6eec 289icu_abi_setdefault(void)
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290{
291 int intr;
292
293 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
294 if (intr == ICU_IRQ_SLAVE)
295 continue;
296 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
297 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
298 }
299}
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300
301static void
780a6eec 302icu_abi_initmap(void)
a3dd9120 303{
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304 int cpu;
305
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306 kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start);
307 icu_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */
308
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309 /*
310 * NOTE: ncpus is not ready yet
311 */
312 for (cpu = 0; cpu < MAXCPU; ++cpu) {
313 int i;
314
315 if (cpu != 0) {
316 for (i = 0; i < ICU_HWI_VECTORS; ++i)
317 icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED;
318 } else {
319 for (i = 0; i < ICU_HWI_VECTORS; ++i)
2a32da90 320 icu_irqmaps[cpu][i].im_type = ICU_IMT_LEGACY;
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321 icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type =
322 ICU_IMT_RESERVED;
323
324 if (elcr_found) {
325 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
326 icu_irqmaps[cpu][i].im_trig =
327 elcr_read_trigger(i);
328 }
329 } else {
330 /*
331 * NOTE: Trigger mode does not matter at all
332 */
333 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
334 icu_irqmaps[cpu][i].im_trig =
335 INTR_TRIGGER_EDGE;
336 }
337 }
338 }
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339
340 for (i = 0; i < IDT_HWI_VECTORS; ++i)
341 icu_irqmaps[cpu][i].im_msi_base = -1;
342
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343 icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type =
344 ICU_IMT_SYSCALL;
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345 }
346}
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347
348static void
780a6eec 349icu_abi_intr_config(int irq, enum intr_trigger trig,
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350 enum intr_polarity pola __unused)
351{
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352 struct icu_irqmap *map;
353
354 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
355
b2150df1 356 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS);
14bd3265 357 map = &icu_irqmaps[0][irq];
16437a92 358
2a32da90 359 KKASSERT(map->im_type == ICU_IMT_LEGACY);
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360
361 /* TODO: Check whether it is configured or not */
362
363 if (trig == map->im_trig)
364 return;
365
366 if (bootverbose) {
367 kprintf("ICU: irq %d, %s -> %s\n", irq,
368 intr_str_trigger(map->im_trig),
369 intr_str_trigger(trig));
370 }
371 map->im_trig = trig;
372
373 if (!elcr_found) {
374 if (bootverbose)
375 kprintf("ICU: no ELCR, skip irq %d config\n", irq);
376 return;
377 }
378 elcr_write_trigger(irq, map->im_trig);
d1ae7328 379}
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380
381static int
382icu_abi_intr_cpuid(int irq __unused)
383{
384 return 0;
385}
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386
387static void
388icu_abi_rman_setup(struct rman *rm)
389{
390 int start, end, i;
391
392 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
393 ("invalid rman cpuid %d", rm->rm_cpuid));
394
395 start = end = -1;
396 for (i = 0; i < IDT_HWI_VECTORS; ++i) {
397 const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i];
398
399 if (start < 0) {
400 if (ICU_IMT_ISHWI(map))
401 start = end = i;
402 } else {
403 if (ICU_IMT_ISHWI(map)) {
404 end = i;
405 } else {
406 KKASSERT(end >= 0);
407 if (bootverbose) {
408 kprintf("ICU: rman cpu%d %d - %d\n",
409 rm->rm_cpuid, start, end);
410 }
411 if (rman_manage_region(rm, start, end)) {
412 panic("rman_manage_region"
413 "(cpu%d %d - %d)", rm->rm_cpuid,
414 start, end);
415 }
416 start = end = -1;
417 }
418 }
419 }
420 if (start >= 0) {
421 KKASSERT(end >= 0);
422 if (bootverbose) {
423 kprintf("ICU: rman cpu%d %d - %d\n",
424 rm->rm_cpuid, start, end);
425 }
426 if (rman_manage_region(rm, start, end)) {
427 panic("rman_manage_region(cpu%d %d - %d)",
428 rm->rm_cpuid, start, end);
429 }
430 }
431}
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432
433static int
434icu_abi_msi_alloc(int intrs[], int count, int cpuid)
435{
436 int i, error;
437
438 KASSERT(cpuid >= 0 && cpuid < ncpus,
439 ("invalid cpuid %d", cpuid));
440
441 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
442 KASSERT((count & (count - 1)) == 0,
443 ("count %d is not power of 2\n", count));
444
445 lwkt_gettoken(&icu_irqmap_tok);
446
447 /*
448 * NOTE:
449 * Since IDT_OFFSET is 32, which is the maximum valid 'count',
450 * we do not need to find out the first properly aligned
451 * interrupt vector.
452 */
453
454 error = EMSGSIZE;
455 for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) {
456 int j;
457
458 if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED)
459 continue;
460
461 for (j = 1; j < count; ++j) {
462 if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED)
463 break;
464 }
465 if (j != count)
466 continue;
467
468 for (j = 0; j < count; ++j) {
469 int intr = i + j, cpu;
470
471 for (cpu = 0; cpu < ncpus; ++cpu) {
472 struct icu_irqmap *map;
473
474 map = &icu_irqmaps[cpu][intr];
475 KASSERT(map->im_msi_base < 0,
476 ("intr %d cpu%d, stale MSI-base %d\n",
477 intr, cpu, map->im_msi_base));
478 KASSERT(map->im_type == ICU_IMT_UNUSED,
479 ("intr %d cpu%d, already allocated\n",
480 intr, cpu));
481
482 if (cpu == cpuid) {
483 map->im_type = ICU_IMT_MSI;
484 map->im_msi_base = i;
485 } else {
486 map->im_type = ICU_IMT_SHADOW;
487 }
488 }
489
490 intrs[j] = intr;
491 msi_setup(intr);
492
493 if (bootverbose) {
494 kprintf("alloc MSI intr %d on cpu%d\n",
495 intr, cpuid);
496 }
497 }
498 error = 0;
499 break;
500 }
501
502 lwkt_reltoken(&icu_irqmap_tok);
503
504 return error;
505}
506
507static void
508icu_abi_msi_release(const int intrs[], int count, int cpuid)
509{
510 int i, msi_base = -1, intr_next = -1, mask;
511
512 KASSERT(cpuid >= 0 && cpuid < ncpus,
513 ("invalid cpuid %d", cpuid));
514
515 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
516
517 mask = count - 1;
518 KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count));
519
520 lwkt_gettoken(&icu_irqmap_tok);
521
522 for (i = 0; i < count; ++i) {
523 int intr = intrs[i], cpu;
524
525 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
526 ("invalid intr %d\n", intr));
527
528 for (cpu = 0; cpu < ncpus; ++cpu) {
529 struct icu_irqmap *map;
530
531 map = &icu_irqmaps[cpu][intr];
532
533 if (cpu == cpuid) {
534 KASSERT(map->im_type == ICU_IMT_MSI,
535 ("try release non-MSI intr %d cpu%d, "
536 "type %d\n", intr, cpu, map->im_type));
537 KASSERT(map->im_msi_base >= 0 &&
538 map->im_msi_base <= intr,
539 ("intr %d cpu%d, invalid MSI-base %d\n",
540 intr, cpu, map->im_msi_base));
541 KASSERT((map->im_msi_base & mask) == 0,
542 ("intr %d cpu%d, MSI-base %d is "
543 "not proper aligned %d\n",
544 intr, cpu, map->im_msi_base, count));
545
546 if (msi_base < 0) {
547 msi_base = map->im_msi_base;
548 } else {
549 KASSERT(map->im_msi_base == msi_base,
550 ("intr %d cpu%d, "
551 "inconsistent MSI-base, "
552 "was %d, now %d\n",
553 intr, cpu,
554 msi_base, map->im_msi_base));
555 }
556 map->im_msi_base = -1;
557 } else {
558 KASSERT(map->im_type == ICU_IMT_SHADOW,
559 ("try release non-MSIsh intr %d cpu%d, "
560 "type %d\n", intr, cpu, map->im_type));
561 KASSERT(map->im_msi_base < 0,
562 ("intr %d cpu%d, invalid MSIsh-base %d\n",
563 intr, cpu, map->im_msi_base));
564 }
565 map->im_type = ICU_IMT_UNUSED;
566 }
567
568 if (intr_next < intr)
569 intr_next = intr;
570
571 if (bootverbose)
572 kprintf("release MSI intr %d on cpu%d\n", intr, cpuid);
573 }
574
575 KKASSERT(intr_next > 0);
576 KKASSERT(msi_base >= 0);
577
578 ++intr_next;
579 if (intr_next < IDT_HWI_VECTORS) {
580 int cpu;
581
582 for (cpu = 0; cpu < ncpus; ++cpu) {
583 const struct icu_irqmap *map =
584 &icu_irqmaps[cpu][intr_next];
585
586 if (map->im_type == ICU_IMT_MSI) {
587 KASSERT(map->im_msi_base != msi_base,
588 ("more than %d MSI was allocated\n", count));
589 }
590 }
591 }
592
593 lwkt_reltoken(&icu_irqmap_tok);
594}
595
596static void
597icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
598{
599 const struct icu_irqmap *map;
600
601 KASSERT(cpuid >= 0 && cpuid < ncpus,
602 ("invalid cpuid %d", cpuid));
603
604 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
605 ("invalid intr %d\n", intr));
606
607 lwkt_gettoken(&icu_irqmap_tok);
608
609 map = &icu_irqmaps[cpuid][intr];
610 KASSERT(map->im_type == ICU_IMT_MSI,
611 ("try map non-MSI intr %d, type %d\n", intr, map->im_type));
612 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
613 ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base));
614
615 msi_map(map->im_msi_base, addr, data, cpuid);
616
617 if (bootverbose)
618 kprintf("map MSI intr %d on cpu%d\n", intr, cpuid);
619
620 lwkt_reltoken(&icu_irqmap_tok);
621}