pci/amd64: Duplicate pci/i386 to pci/amd64.
[dragonfly.git] / sys / bus / pci / amd64 / pci_cfgreg.c
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1/*-
2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2004, Scott Long <scottl@kfreebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: src/sys/i386/pci/pci_cfgreg.c,v 1.124.2.2.6.1 2009/04/15 03:14:26 kensmith Exp $
30 */
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35#include <sys/lock.h>
36#include <sys/malloc.h>
37#include <sys/thread2.h>
38#include <sys/spinlock.h>
39#include <sys/spinlock2.h>
40#include <sys/queue.h>
41#include <bus/pci/pcivar.h>
42#include <bus/pci/pcireg.h>
43#include "pci_cfgreg.h"
44#include <machine/pc/bios.h>
45#ifdef APIC_IO
46#include <machine/smp.h>
47#endif
48
49#include <vm/vm.h>
50#include <vm/vm_param.h>
51#include <vm/vm_kern.h>
52#include <vm/vm_extern.h>
53#include <vm/pmap.h>
54#include <machine/pmap.h>
55
56#if defined(__DragonFly__)
57#define mtx_init(a, b, c, d) spin_init(a)
58#define mtx_lock_spin(a) spin_lock_wr(a)
59#define mtx_unlock_spin(a) spin_unlock_wr(a)
60#endif
61
62#define PRVERB(a) do { \
63 if (bootverbose) \
64 kprintf a ; \
65} while(0)
66
67#define PCIE_CACHE 8
68struct pcie_cfg_elem {
69 TAILQ_ENTRY(pcie_cfg_elem) elem;
70 vm_offset_t vapage;
71 vm_paddr_t papage;
72};
73
74enum {
75 CFGMECH_NONE = 0,
76 CFGMECH_1,
77 CFGMECH_2,
78 CFGMECH_PCIE,
79};
80
81static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
82static uint32_t pciebar;
83static int cfgmech;
84static int devmax;
85#if defined(__DragonFly__)
86static struct spinlock pcicfg_mtx;
87#else
88static struct mtx pcicfg_mtx;
89#endif
90
91static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
92static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
93static int pcireg_cfgopen(void);
94
95static int pciereg_cfgopen(void);
96static int pciereg_cfgread(int bus, int slot, int func, int reg,
97 int bytes);
98static void pciereg_cfgwrite(int bus, int slot, int func, int reg,
99 int data, int bytes);
100
101/*
102 * Some BIOS writers seem to want to ignore the spec and put
103 * 0 in the intline rather than 255 to indicate none. Some use
104 * numbers in the range 128-254 to indicate something strange and
105 * apparently undocumented anywhere. Assume these are completely bogus
106 * and map them to 255, which means "none".
107 */
108static __inline int
109pci_i386_map_intline(int line)
110{
111 if (line == 0 || line >= 128)
112 return (PCI_INVALID_IRQ);
113 return (line);
114}
115
116#ifdef notyet
117
118static u_int16_t
119pcibios_get_version(void)
120{
121 struct bios_regs args;
122
123 if (PCIbios.ventry == 0) {
124 PRVERB(("pcibios: No call entry point\n"));
125 return (0);
126 }
127 args.eax = PCIBIOS_BIOS_PRESENT;
128 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
129 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
130 return (0);
131 }
132 if (args.edx != 0x20494350) {
133 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
134 return (0);
135 }
136 return (args.ebx & 0xffff);
137}
138
139#endif
140
141/*
142 * Initialise access to PCI configuration space
143 */
144int
145pci_cfgregopen(void)
146{
147 static int opened = 0;
148#ifdef notyet
149 u_int16_t vid, did;
150 u_int16_t v;
151#endif
152
153 if (opened)
154 return(1);
155
156 if (pcireg_cfgopen() == 0)
157 return(0);
158
159#ifdef notyet
160 v = pcibios_get_version();
161 if (v > 0)
162 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
163 v & 0xff));
164 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
165 opened = 1;
166
167 /* $PIR requires PCI BIOS 2.10 or greater. */
168 if (v >= 0x0210)
169 pci_pir_open();
170
171 /*
172 * Grope around in the PCI config space to see if this is a
173 * chipset that is capable of doing memory-mapped config cycles.
174 * This also implies that it can do PCIe extended config cycles.
175 */
176
177 /* Check for supported chipsets */
178 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
179 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
180 if (vid == 0x8086) {
181 if (did == 0x3590 || did == 0x3592) {
182 /* Intel 7520 or 7320 */
183 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
184 pciereg_cfgopen();
185 } else if (did == 0x2580 || did == 0x2584) {
186 /* Intel 915 or 925 */
187 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
188 pciereg_cfgopen();
189 }
190 }
191#else
192 opened = 1;
193#endif
194 return(1);
195}
196
197/*
198 * Read configuration space register
199 */
200u_int32_t
201pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
202{
203 uint32_t line;
204#ifdef APIC_IO
205 uint32_t pin;
206
207 /*
208 * If we are using the APIC, the contents of the intline
209 * register will probably be wrong (since they are set up for
210 * use with the PIC. Rather than rewrite these registers
211 * (maybe that would be smarter) we trap attempts to read them
212 * and translate to our private vector numbers.
213 */
214 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
215
216 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
217 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
218
219 if (pin != 0) {
220 int airq;
221
222 airq = pci_apic_irq(bus, slot, pin);
223 if (airq >= 0) {
224 /* PCI specific entry found in MP table */
225 if (airq != line)
226 undirect_pci_irq(line);
227 return (airq);
228 } else {
229 /*
230 * PCI interrupts might be redirected to the
231 * ISA bus according to some MP tables. Use the
232 * same methods as used by the ISA devices
233 * devices to find the proper IOAPIC int pin.
234 */
235 airq = isa_apic_irq(line);
236 if ((airq >= 0) && (airq != line)) {
237 /* XXX: undirect_pci_irq() ? */
238 undirect_isa_irq(line);
239 return (airq);
240 }
241 }
242 }
243 return (line);
244 }
245#else
246 /*
247 * Some BIOS writers seem to want to ignore the spec and put
248 * 0 in the intline rather than 255 to indicate none. The rest of
249 * the code uses 255 as an invalid IRQ.
250 */
251 if (reg == PCIR_INTLINE && bytes == 1) {
252 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
253 return (pci_i386_map_intline(line));
254 }
255#endif /* APIC_IO */
256 return (pcireg_cfgread(bus, slot, func, reg, bytes));
257}
258
259/*
260 * Write configuration space register
261 */
262void
263pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
264{
265
266 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
267}
268
269/*
270 * Configuration space access using direct register operations
271 */
272
273/* enable configuration space accesses and return data port address */
274static int
275pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
276{
277 int dataport = 0;
278
279#ifdef XBOX
280 if (arch_i386_is_xbox) {
281 /*
282 * The Xbox MCPX chipset is a derivative of the nForce 1
283 * chipset. It almost has the same bus layout; some devices
284 * cannot be used, because they have been removed.
285 */
286
287 /*
288 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
289 * the nForce chipset, but on the Xbox, using them will lockup
290 * the chipset.
291 */
292 if (bus == 0 && slot == 0 && (func == 1 || func == 2))
293 return dataport;
294
295 /*
296 * Bus 1 only contains a VGA controller at 01:00.0. When you try
297 * to probe beyond that device, you only get garbage, which
298 * could cause lockups.
299 */
300 if (bus == 1 && (slot != 0 || func != 0))
301 return dataport;
302
303 /*
304 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
305 * doesn't have one. Probing it can cause lockups.
306 */
307 if (bus >= 2)
308 return dataport;
309 }
310#endif
311
312 if (bus <= PCI_BUSMAX
313 && slot < devmax
314 && func <= PCI_FUNCMAX
315 && reg <= PCI_REGMAX
316 && bytes != 3
317 && (unsigned) bytes <= 4
318 && (reg & (bytes - 1)) == 0) {
319 switch (cfgmech) {
320 case CFGMECH_1:
321 outl(CONF1_ADDR_PORT, (1 << 31)
322 | (bus << 16) | (slot << 11)
323 | (func << 8) | (reg & ~0x03));
324 dataport = CONF1_DATA_PORT + (reg & 0x03);
325 break;
326 case CFGMECH_2:
327 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
328 outb(CONF2_FORWARD_PORT, bus);
329 dataport = 0xc000 | (slot << 8) | reg;
330 break;
331 }
332 }
333 return (dataport);
334}
335
336/* disable configuration space accesses */
337static void
338pci_cfgdisable(void)
339{
340 switch (cfgmech) {
341 case CFGMECH_1:
342 /*
343 * Do nothing for the config mechanism 1 case.
344 * Writing a 0 to the address port can apparently
345 * confuse some bridges and cause spurious
346 * access failures.
347 */
348 break;
349 case CFGMECH_2:
350 outb(CONF2_ENABLE_PORT, 0);
351 break;
352 }
353}
354
355static int
356pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
357{
358 int data = -1;
359 int port;
360
361 if (cfgmech == CFGMECH_PCIE) {
362 data = pciereg_cfgread(bus, slot, func, reg, bytes);
363 return (data);
364 }
365
366 mtx_lock_spin(&pcicfg_mtx);
367 port = pci_cfgenable(bus, slot, func, reg, bytes);
368 if (port != 0) {
369 switch (bytes) {
370 case 1:
371 data = inb(port);
372 break;
373 case 2:
374 data = inw(port);
375 break;
376 case 4:
377 data = inl(port);
378 break;
379 }
380 pci_cfgdisable();
381 }
382 mtx_unlock_spin(&pcicfg_mtx);
383 return (data);
384}
385
386static void
387pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
388{
389 int port;
390
391 if (cfgmech == CFGMECH_PCIE) {
392 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
393 return;
394 }
395
396 mtx_lock_spin(&pcicfg_mtx);
397 port = pci_cfgenable(bus, slot, func, reg, bytes);
398 if (port != 0) {
399 switch (bytes) {
400 case 1:
401 outb(port, data);
402 break;
403 case 2:
404 outw(port, data);
405 break;
406 case 4:
407 outl(port, data);
408 break;
409 }
410 pci_cfgdisable();
411 }
412 mtx_unlock_spin(&pcicfg_mtx);
413}
414
415/* check whether the configuration mechanism has been correctly identified */
416static int
417pci_cfgcheck(int maxdev)
418{
419 uint32_t id, class;
420 uint8_t header;
421 uint8_t device;
422 int port;
423
424 if (bootverbose)
425 kprintf("pci_cfgcheck:\tdevice ");
426
427 for (device = 0; device < maxdev; device++) {
428 if (bootverbose)
429 kprintf("%d ", device);
430
431 port = pci_cfgenable(0, device, 0, 0, 4);
432 id = inl(port);
433 if (id == 0 || id == 0xffffffff)
434 continue;
435
436 port = pci_cfgenable(0, device, 0, 8, 4);
437 class = inl(port) >> 8;
438 if (bootverbose)
439 kprintf("[class=%06x] ", class);
440 if (class == 0 || (class & 0xf870ff) != 0)
441 continue;
442
443 port = pci_cfgenable(0, device, 0, 14, 1);
444 header = inb(port);
445 if (bootverbose)
446 kprintf("[hdr=%02x] ", header);
447 if ((header & 0x7e) != 0)
448 continue;
449
450 if (bootverbose)
451 kprintf("is there (id=%08x)\n", id);
452
453 pci_cfgdisable();
454 return (1);
455 }
456 if (bootverbose)
457 kprintf("-- nothing found\n");
458
459 pci_cfgdisable();
460 return (0);
461}
462
463static int
464pcireg_cfgopen(void)
465{
466 uint32_t mode1res, oldval1;
467 uint8_t mode2res, oldval2;
468
469 /* Check for type #1 first. */
470 oldval1 = inl(CONF1_ADDR_PORT);
471
472 if (bootverbose) {
473 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
474 oldval1);
475 }
476
477 cfgmech = CFGMECH_1;
478 devmax = 32;
479
480 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
481 DELAY(1);
482 mode1res = inl(CONF1_ADDR_PORT);
483 outl(CONF1_ADDR_PORT, oldval1);
484
485 if (bootverbose)
486 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
487 CONF1_ENABLE_CHK);
488
489 if (mode1res) {
490 if (pci_cfgcheck(32))
491 return (cfgmech);
492 }
493
494 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
495 mode1res = inl(CONF1_ADDR_PORT);
496 outl(CONF1_ADDR_PORT, oldval1);
497
498 if (bootverbose)
499 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
500 CONF1_ENABLE_CHK1);
501
502 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
503 if (pci_cfgcheck(32))
504 return (cfgmech);
505 }
506
507 /* Type #1 didn't work, so try type #2. */
508 oldval2 = inb(CONF2_ENABLE_PORT);
509
510 if (bootverbose) {
511 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
512 oldval2);
513 }
514
515 if ((oldval2 & 0xf0) == 0) {
516
517 cfgmech = CFGMECH_2;
518 devmax = 16;
519
520 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
521 mode2res = inb(CONF2_ENABLE_PORT);
522 outb(CONF2_ENABLE_PORT, oldval2);
523
524 if (bootverbose)
525 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
526 mode2res, CONF2_ENABLE_CHK);
527
528 if (mode2res == CONF2_ENABLE_RES) {
529 if (bootverbose)
530 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
531
532 if (pci_cfgcheck(16))
533 return (cfgmech);
534 }
535 }
536
537 /* Nothing worked, so punt. */
538 cfgmech = CFGMECH_NONE;
539 devmax = 0;
540 return (cfgmech);
541}
542
543static int
544pciereg_cfgopen(void)
545{
546#ifdef PCIE_CFG_MECH
547 struct pcie_cfg_list *pcielist;
548 struct pcie_cfg_elem *pcie_array, *elem;
549#ifdef SMP
550 struct pcpu *pc;
551#endif
552 vm_offset_t va;
553 int i;
554
555 if (bootverbose)
556 kprintf("Setting up PCIe mappings for BAR 0x%x\n", pciebar);
557
558#ifdef SMP
559 SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
560#endif
561 {
562
563 pcie_array = kmalloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
564 M_DEVBUF, M_NOWAIT);
565 if (pcie_array == NULL)
566 return (0);
567
568 va = kmem_alloc_nofault(&kernel_map, PCIE_CACHE * PAGE_SIZE);
569 if (va == 0) {
570 kfree(pcie_array, M_DEVBUF);
571 return (0);
572 }
573
574#ifdef SMP
575 pcielist = &pcie_list[pc->pc_cpuid];
576#else
577 pcielist = &pcie_list[0];
578#endif
579 TAILQ_INIT(pcielist);
580 for (i = 0; i < PCIE_CACHE; i++) {
581 elem = &pcie_array[i];
582 elem->vapage = va + (i * PAGE_SIZE);
583 elem->papage = 0;
584 TAILQ_INSERT_HEAD(pcielist, elem, elem);
585 }
586 }
587
588
589 cfgmech = CFGMECH_PCIE;
590 devmax = 32;
591 return (1);
592#else /* !PCIE_CFG_MECH */
593 return (0);
594#endif /* PCIE_CFG_MECH */
595}
596
597#define PCIE_PADDR(bar, reg, bus, slot, func) \
598 ((bar) | \
599 (((bus) & 0xff) << 20) | \
600 (((slot) & 0x1f) << 15) | \
601 (((func) & 0x7) << 12) | \
602 ((reg) & 0xfff))
603
604/*
605 * Find an element in the cache that matches the physical page desired, or
606 * create a new mapping from the least recently used element.
607 * A very simple LRU algorithm is used here, does it need to be more
608 * efficient?
609 */
610static __inline struct pcie_cfg_elem *
611pciereg_findelem(vm_paddr_t papage)
612{
613 struct pcie_cfg_list *pcielist;
614 struct pcie_cfg_elem *elem;
615 pcielist = &pcie_list[mycpuid];
616 TAILQ_FOREACH(elem, pcielist, elem) {
617 if (elem->papage == papage)
618 break;
619 }
620
621 if (elem == NULL) {
622 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
623 if (elem->papage != 0) {
624 pmap_kremove(elem->vapage);
625 cpu_invlpg(&elem->vapage);
626 }
627 pmap_kenter(elem->vapage, papage);
628 elem->papage = papage;
629 }
630
631 if (elem != TAILQ_FIRST(pcielist)) {
632 TAILQ_REMOVE(pcielist, elem, elem);
633 TAILQ_INSERT_HEAD(pcielist, elem, elem);
634 }
635 return (elem);
636}
637
638static int
639pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
640{
641 struct pcie_cfg_elem *elem;
642 volatile vm_offset_t va;
643 vm_paddr_t pa, papage;
644 int data;
645
646 crit_enter();
647 pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
648 papage = pa & ~PAGE_MASK;
649 elem = pciereg_findelem(papage);
650 va = elem->vapage | (pa & PAGE_MASK);
651
652 switch (bytes) {
653 case 4:
654 data = *(volatile uint32_t *)(va);
655 break;
656 case 2:
657 data = *(volatile uint16_t *)(va);
658 break;
659 case 1:
660 data = *(volatile uint8_t *)(va);
661 break;
662 default:
663 panic("pciereg_cfgread: invalid width");
664 }
665
666 crit_exit();
667 return (data);
668}
669
670static void
671pciereg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
672{
673 struct pcie_cfg_elem *elem;
674 volatile vm_offset_t va;
675 vm_paddr_t pa, papage;
676
677 crit_enter();
678 pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
679 papage = pa & ~PAGE_MASK;
680 elem = pciereg_findelem(papage);
681 va = elem->vapage | (pa & PAGE_MASK);
682
683 switch (bytes) {
684 case 4:
685 *(volatile uint32_t *)(va) = data;
686 break;
687 case 2:
688 *(volatile uint16_t *)(va) = data;
689 break;
690 case 1:
691 *(volatile uint8_t *)(va) = data;
692 break;
693 default:
694 panic("pciereg_cfgwrite: invalid width");
695 }
696
697 crit_exit();
698}