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em(4)/emx(4): Update to Intel's 7.1.7
[dragonfly.git] / sys / dev / netif / em / if_em.c
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78195a76 1/*
78195a76
MD		 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
9c80d176 4 * Copyright (c) 2001-2008, Intel Corporation
78195a76
MD		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9c80d176 9 *
78195a76
MD		 10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
9c80d176 12 *
78195a76
MD		 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
9c80d176 16 *
78195a76
MD		 17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
9c80d176 20 *
78195a76
MD		 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
9c80d176 35 *
78195a76
MD		 36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
9c80d176 38 *
78195a76
MD		 39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
9c80d176 42 *
78195a76
MD		 43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
9c80d176 52 *
78195a76
MD		 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
9c80d176 65 *
78195a76
MD		 66 */
67/*
68 * SERIALIZATION API RULES:
69 *
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
9c80d176 72 * driver.
78195a76
MD		 73 *
74 * - ifmedia entry points will be serialized by the ifmedia code using the
75 * ifnet serializer.
76 *
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
79 *
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
82 *
83 * - The device driver typically holds the serializer at the time it wishes
9c80d176
SZ		 84 * to call if_input.
85 *
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
78195a76
MD		 90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
2b71c8f1
SZ		 95
96#include "opt_polling.h"
87307ba1
SZ		 97
98#include <sys/param.h>
99#include <sys/bus.h>
100#include <sys/endian.h>
9db4b353 101#include <sys/interrupt.h>
87307ba1
SZ		 102#include <sys/kernel.h>
103#include <sys/ktr.h>
104#include <sys/malloc.h>
105#include <sys/mbuf.h>
9c80d176 106#include <sys/proc.h>
87307ba1
SZ		 107#include <sys/rman.h>
108#include <sys/serialize.h>
109#include <sys/socket.h>
110#include <sys/sockio.h>
111#include <sys/sysctl.h>
9c80d176 112#include <sys/systm.h>
87307ba1
SZ		 113
114#include <net/bpf.h>
115#include <net/ethernet.h>
116#include <net/if.h>
117#include <net/if_arp.h>
118#include <net/if_dl.h>
119#include <net/if_media.h>
87307ba1
SZ		 120#include <net/ifq_var.h>
121#include <net/vlan/if_vlan_var.h>
b637f170 122#include <net/vlan/if_vlan_ether.h>
87307ba1 123
87307ba1 124#include <netinet/in_systm.h>
9c80d176 125#include <netinet/in.h>
87307ba1
SZ		 126#include <netinet/ip.h>
127#include <netinet/tcp.h>
128#include <netinet/udp.h>
984263bc 129
9c80d176
SZ		 130#include <bus/pci/pcivar.h>
131#include <bus/pci/pcireg.h>
984263bc 132
9c80d176
SZ		 133#include <dev/netif/ig_hal/e1000_api.h>
134#include <dev/netif/ig_hal/e1000_82571.h>
135#include <dev/netif/em/if_em.h>
984263bc 136
9c80d176 137#define EM_NAME "Intel(R) PRO/1000 Network Connection "
2d0e5700 138#define EM_VER " 7.1.7"
9c80d176 139
96ced48a
SZ		 140#define _EM_DEVICE(id, ret) \
141 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
142#define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
143#define EM_DEVICE(id) _EM_DEVICE(id, 0)
144#define EM_DEVICE_NULL { 0, 0, 0, NULL }
9c80d176
SZ		 145
146static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM),
148 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP),
150 EM_DEVICE(82540EP_LOM),
151 EM_DEVICE(82540EP_LP),
152
153 EM_DEVICE(82541EI),
154 EM_DEVICE(82541ER),
155 EM_DEVICE(82541ER_LOM),
156 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI),
158 EM_DEVICE(82541GI_LF),
159 EM_DEVICE(82541GI_MOBILE),
160
161 EM_DEVICE(82542),
162
163 EM_DEVICE(82543GC_FIBER),
164 EM_DEVICE(82543GC_COPPER),
165
166 EM_DEVICE(82544EI_COPPER),
167 EM_DEVICE(82544EI_FIBER),
168 EM_DEVICE(82544GC_COPPER),
169 EM_DEVICE(82544GC_LOM),
170
171 EM_DEVICE(82545EM_COPPER),
172 EM_DEVICE(82545EM_FIBER),
173 EM_DEVICE(82545GM_COPPER),
174 EM_DEVICE(82545GM_FIBER),
175 EM_DEVICE(82545GM_SERDES),
176
177 EM_DEVICE(82546EB_COPPER),
178 EM_DEVICE(82546EB_FIBER),
179 EM_DEVICE(82546EB_QUAD_COPPER),
180 EM_DEVICE(82546GB_COPPER),
181 EM_DEVICE(82546GB_FIBER),
182 EM_DEVICE(82546GB_SERDES),
183 EM_DEVICE(82546GB_PCIE),
184 EM_DEVICE(82546GB_QUAD_COPPER),
185 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
186
187 EM_DEVICE(82547EI),
188 EM_DEVICE(82547EI_MOBILE),
189 EM_DEVICE(82547GI),
190
96ced48a
SZ		 191 EM_EMX_DEVICE(82571EB_COPPER),
192 EM_EMX_DEVICE(82571EB_FIBER),
193 EM_EMX_DEVICE(82571EB_SERDES),
194 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
195 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
96ced48a
SZ		 198 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
199 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
200 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201
202 EM_EMX_DEVICE(82572EI_COPPER),
203 EM_EMX_DEVICE(82572EI_FIBER),
204 EM_EMX_DEVICE(82572EI_SERDES),
205 EM_EMX_DEVICE(82572EI),
206
207 EM_EMX_DEVICE(82573E),
208 EM_EMX_DEVICE(82573E_IAMT),
209 EM_EMX_DEVICE(82573L),
210
2d0e5700
SZ		 211 EM_DEVICE(82583V),
212
96ced48a
SZ		 213 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
215 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
216 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
9c80d176
SZ		 217
218 EM_DEVICE(ICH8_IGP_M_AMT),
219 EM_DEVICE(ICH8_IGP_AMT),
220 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE),
222 EM_DEVICE(ICH8_IFE_GT),
223 EM_DEVICE(ICH8_IFE_G),
224 EM_DEVICE(ICH8_IGP_M),
2d0e5700 225 EM_DEVICE(ICH8_82567V_3),
9c80d176
SZ		 226
227 EM_DEVICE(ICH9_IGP_M_AMT),
228 EM_DEVICE(ICH9_IGP_AMT),
229 EM_DEVICE(ICH9_IGP_C),
230 EM_DEVICE(ICH9_IGP_M),
231 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE),
233 EM_DEVICE(ICH9_IFE_GT),
234 EM_DEVICE(ICH9_IFE_G),
235 EM_DEVICE(ICH9_BM),
236
96ced48a 237 EM_EMX_DEVICE(82574L),
2d0e5700 238 EM_EMX_DEVICE(82574LA),
9c80d176
SZ		 239
240 EM_DEVICE(ICH10_R_BM_LM),
241 EM_DEVICE(ICH10_R_BM_LF),
242 EM_DEVICE(ICH10_R_BM_V),
243 EM_DEVICE(ICH10_D_BM_LM),
244 EM_DEVICE(ICH10_D_BM_LF),
2d0e5700
SZ		 245 EM_DEVICE(ICH10_D_BM_V),
246
247 EM_DEVICE(PCH_M_HV_LM),
248 EM_DEVICE(PCH_M_HV_LC),
249 EM_DEVICE(PCH_D_HV_DM),
250 EM_DEVICE(PCH_D_HV_DC),
251
252 EM_DEVICE(PCH2_LV_LM),
253 EM_DEVICE(PCH2_LV_V),
984263bc 254
f647ad3d 255 /* required last entry */
9c80d176 256 EM_DEVICE_NULL
984263bc
MD		 257};
258
f647ad3d
JS		 259static int em_probe(device_t);
260static int em_attach(device_t);
261static int em_detach(device_t);
262static int em_shutdown(device_t);
87307ba1
SZ		 263static int em_suspend(device_t);
264static int em_resume(device_t);
9c80d176
SZ		 265
266static void em_init(void *);
267static void em_stop(struct adapter *);
f647ad3d 268static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
9c80d176
SZ		 269static void em_start(struct ifnet *);
270#ifdef DEVICE_POLLING
271static void em_poll(struct ifnet *, enum poll_cmd, int);
272#endif
f647ad3d 273static void em_watchdog(struct ifnet *);
f647ad3d
JS		 274static void em_media_status(struct ifnet *, struct ifmediareq *);
275static int em_media_change(struct ifnet *);
9c80d176
SZ		 276static void em_timer(void *);
277
278static void em_intr(void *);
279static void em_rxeof(struct adapter *, int);
280static void em_txeof(struct adapter *);
9f60d74b 281static void em_tx_collect(struct adapter *);
9c80d176 282static void em_tx_purge(struct adapter *);
f647ad3d
JS		 283static void em_enable_intr(struct adapter *);
284static void em_disable_intr(struct adapter *);
9c80d176
SZ		 285
286static int em_dma_malloc(struct adapter *, bus_size_t,
287 struct em_dma_alloc *);
288static void em_dma_free(struct adapter *, struct em_dma_alloc *);
289static void em_init_tx_ring(struct adapter *);
290static int em_init_rx_ring(struct adapter *);
291static int em_create_tx_ring(struct adapter *);
292static int em_create_rx_ring(struct adapter *);
293static void em_destroy_tx_ring(struct adapter *, int);
294static void em_destroy_rx_ring(struct adapter *, int);
295static int em_newbuf(struct adapter *, int, int);
296static int em_encap(struct adapter *, struct mbuf **);
297static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
298 struct mbuf *);
002b3a05 299static int em_txcsum_pullup(struct adapter *, struct mbuf **);
9f60d74b 300static int em_txcsum(struct adapter *, struct mbuf *,
9c80d176
SZ		 301 uint32_t *, uint32_t *);
302
303static int em_get_hw_info(struct adapter *);
304static int em_is_valid_eaddr(const uint8_t *);
305static int em_alloc_pci_res(struct adapter *);
306static void em_free_pci_res(struct adapter *);
2d0e5700 307static int em_reset(struct adapter *);
9c80d176
SZ		 308static void em_setup_ifp(struct adapter *);
309static void em_init_tx_unit(struct adapter *);
310static void em_init_rx_unit(struct adapter *);
311static void em_update_stats(struct adapter *);
f647ad3d
JS		 312static void em_set_promisc(struct adapter *);
313static void em_disable_promisc(struct adapter *);
314static void em_set_multi(struct adapter *);
87307ba1 315static void em_update_link_status(struct adapter *);
f647ad3d 316static void em_smartspeed(struct adapter *);
2d0e5700 317static void em_set_itr(struct adapter *, uint32_t);
9c80d176
SZ		 318
319/* Hardware workarounds */
f647ad3d
JS		 320static int em_82547_fifo_workaround(struct adapter *, int);
321static void em_82547_update_fifo_head(struct adapter *, int);
322static int em_82547_tx_fifo_reset(struct adapter *);
1eca7b82
SZ		 323static void em_82547_move_tail(void *);
324static void em_82547_move_tail_serialized(struct adapter *);
9c80d176
SZ		 325static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
326
f647ad3d 327static void em_print_debug_info(struct adapter *);
9c80d176
SZ		 328static void em_print_nvm_info(struct adapter *);
329static void em_print_hw_stats(struct adapter *);
330
f647ad3d
JS		 331static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
332static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
d0870c72 333static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
9f60d74b 334static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
9c80d176 335static void em_add_sysctl(struct adapter *adapter);
984263bc 336
9c80d176
SZ		 337/* Management and WOL Support */
338static void em_get_mgmt(struct adapter *);
339static void em_rel_mgmt(struct adapter *);
340static void em_get_hw_control(struct adapter *);
341static void em_rel_hw_control(struct adapter *);
342static void em_enable_wol(device_t);
984263bc
MD		 343
344static device_method_t em_methods[] = {
345 /* Device interface */
9c80d176
SZ		 346 DEVMETHOD(device_probe, em_probe),
347 DEVMETHOD(device_attach, em_attach),
348 DEVMETHOD(device_detach, em_detach),
349 DEVMETHOD(device_shutdown, em_shutdown),
350 DEVMETHOD(device_suspend, em_suspend),
351 DEVMETHOD(device_resume, em_resume),
352 { 0, 0 }
984263bc
MD		 353};
354
355static driver_t em_driver = {
9c80d176
SZ		 356 "em",
357 em_methods,
358 sizeof(struct adapter),
984263bc
MD		 359};
360
361static devclass_t em_devclass;
32832096
MD		 362
363DECLARE_DUMMY_MODULE(if_em);
9c80d176 364MODULE_DEPEND(em, ig_hal, 1, 1, 1);
aa2b9d05 365DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
984263bc 366
91e8debf
SZ		 367/*
368 * Tunables
369 */
9c80d176
SZ		 370static int em_int_throttle_ceil = EM_DEFAULT_ITR;
371static int em_rxd = EM_DEFAULT_RXD;
372static int em_txd = EM_DEFAULT_TXD;
373static int em_smart_pwr_down = FALSE;
0d366ee7 374
9c80d176
SZ		 375/* Controls whether promiscuous also shows bad packets */
376static int em_debug_sbp = FALSE;
0d366ee7 377
05580856
SZ		 378static int em_82573_workaround = TRUE;
379
d0870c72 380TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
1eca7b82
SZ		 381TUNABLE_INT("hw.em.rxd", &em_rxd);
382TUNABLE_INT("hw.em.txd", &em_txd);
383TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
9c80d176 384TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
05580856 385TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
9c80d176
SZ		 386
387/* Global used in WOL setup with multiport cards */
388static int em_global_quad_port_a = 0;
389
390/* Set this to one to display debug statistics */
391static int em_display_debug_stats = 0;
0d366ee7 392
07855a48
MD		 393#if !defined(KTR_IF_EM)
394#define KTR_IF_EM KTR_ALL
395#endif
396KTR_INFO_MASTER(if_em);
397KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0);
398KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0);
07855a48
MD		 399KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0);
400KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0);
401KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0);
402#define logif(name) KTR_LOG(if_em_ ## name)
403
984263bc
MD		 404static int
405em_probe(device_t dev)
406{
9c80d176
SZ		 407 const struct em_vendor_info *ent;
408 uint16_t vid, did;
984263bc 409
9c80d176
SZ		 410 vid = pci_get_vendor(dev);
411 did = pci_get_device(dev);
984263bc 412
9c80d176
SZ		 413 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
414 if (vid == ent->vendor_id && did == ent->device_id) {
415 device_set_desc(dev, ent->desc);
dbcd0c9b 416 device_set_async_attach(dev, TRUE);
96ced48a 417 return (ent->ret);
984263bc 418 }
984263bc 419 }
87307ba1 420 return (ENXIO);
984263bc
MD		 421}
422
984263bc
MD		 423static int
424em_attach(device_t dev)
425{
9c80d176
SZ		 426 struct adapter *adapter = device_get_softc(dev);
427 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d
JS		 428 int tsize, rsize;
429 int error = 0;
2d0e5700 430 uint16_t eeprom_data, device_id, apme_mask;
984263bc 431
9c80d176 432 adapter->dev = adapter->osdep.dev = dev;
f647ad3d 433
af82d4bb
JS		 434 callout_init(&adapter->timer);
435 callout_init(&adapter->tx_fifo_timer);
436
9c80d176
SZ		 437 /* Determine hardware and mac info */
438 error = em_get_hw_info(adapter);
439 if (error) {
440 device_printf(dev, "Identify hardware failed\n");
441 goto fail;
f647ad3d
JS		 442 }
443
9c80d176
SZ		 444 /* Setup PCI resources */
445 error = em_alloc_pci_res(adapter);
446 if (error) {
447 device_printf(dev, "Allocation of PCI resources failed\n");
448 goto fail;
449 }
984263bc 450
9c80d176
SZ		 451 /*
452 * For ICH8 and family we need to map the flash memory,
453 * and this must happen after the MAC is identified.
454 */
455 if (adapter->hw.mac.type == e1000_ich8lan ||
2d0e5700 456 adapter->hw.mac.type == e1000_ich9lan ||
9c80d176 457 adapter->hw.mac.type == e1000_ich10lan ||
2d0e5700
SZ		 458 adapter->hw.mac.type == e1000_pchlan ||
459 adapter->hw.mac.type == e1000_pch2lan) {
9c80d176
SZ		 460 adapter->flash_rid = EM_BAR_FLASH;
461
462 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
463 &adapter->flash_rid, RF_ACTIVE);
464 if (adapter->flash == NULL) {
465 device_printf(dev, "Mapping of Flash failed\n");
466 error = ENXIO;
467 goto fail;
468 }
469 adapter->osdep.flash_bus_space_tag =
470 rman_get_bustag(adapter->flash);
471 adapter->osdep.flash_bus_space_handle =
472 rman_get_bushandle(adapter->flash);
984263bc 473
9c80d176
SZ		 474 /*
475 * This is used in the shared code
476 * XXX this goof is actually not used.
477 */
478 adapter->hw.flash_address = (uint8_t *)adapter->flash;
479 }
0d366ee7 480
9c80d176
SZ		 481 /* Do Shared Code initialization */
482 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
483 device_printf(dev, "Setup of Shared code failed\n");
484 error = ENXIO;
485 goto fail;
f647ad3d 486 }
7ea52455 487
9c80d176
SZ		 488 e1000_get_bus_info(&adapter->hw);
489
1eca7b82 490 /*
9c80d176 491 * Validate number of transmit and receive descriptors. It
1eca7b82 492 * must not exceed hardware maximum, and must be multiple
9c80d176 493 * of E1000_DBA_ALIGN.
1eca7b82 494 */
9c80d176
SZ		 495 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
496 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
497 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
498 em_txd < EM_MIN_TXD) {
1eca7b82 499 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
9c80d176 500 EM_DEFAULT_TXD, em_txd);
1eca7b82
SZ		 501 adapter->num_tx_desc = EM_DEFAULT_TXD;
502 } else {
503 adapter->num_tx_desc = em_txd;
504 }
9c80d176
SZ		 505 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
506 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
507 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
508 em_rxd < EM_MIN_RXD) {
1eca7b82 509 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
9c80d176 510 EM_DEFAULT_RXD, em_rxd);
1eca7b82
SZ		 511 adapter->num_rx_desc = EM_DEFAULT_RXD;
512 } else {
513 adapter->num_rx_desc = em_rxd;
514 }
515
9c80d176
SZ		 516 adapter->hw.mac.autoneg = DO_AUTO_NEG;
517 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
518 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
519 adapter->rx_buffer_len = MCLBYTES;
e94c2bf4 520
9c80d176
SZ		 521 /*
522 * Interrupt throttle rate
523 */
524 if (em_int_throttle_ceil == 0) {
525 adapter->int_throttle_ceil = 0;
526 } else {
527 int throttle = em_int_throttle_ceil;
f647ad3d 528
9c80d176
SZ		 529 if (throttle < 0)
530 throttle = EM_DEFAULT_ITR;
0d366ee7 531
9c80d176
SZ		 532 /* Recalculate the tunable value to get the exact frequency. */
533 throttle = 1000000000 / 256 / throttle;
664c7645
SZ		 534
535 /* Upper 16bits of ITR is reserved and should be zero */
536 if (throttle & 0xffff0000)
537 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
538
9c80d176
SZ		 539 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
540 }
984263bc 541
9c80d176
SZ		 542 e1000_init_script_state_82541(&adapter->hw, TRUE);
543 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
544
545 /* Copper options */
546 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
547 adapter->hw.phy.mdix = AUTO_ALL_MODES;
548 adapter->hw.phy.disable_polarity_correction = FALSE;
549 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
550 }
551
552 /* Set the frame limits assuming standard ethernet sized frames. */
553 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
554 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
984263bc 555
9c80d176
SZ		 556 /* This controls when hardware reports transmit completion status. */
557 adapter->hw.mac.report_tx_early = 1;
984263bc 558
87307ba1 559 /*
9c80d176 560 * Create top level busdma tag
984263bc 561 */
9c80d176
SZ		 562 error = bus_dma_tag_create(NULL, 1, 0,
563 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
564 NULL, NULL,
565 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
566 0, &adapter->parent_dtag);
567 if (error) {
568 device_printf(dev, "could not create top level DMA tag\n");
af82d4bb 569 goto fail;
9c80d176 570 }
af82d4bb 571
9c80d176
SZ		 572 /*
573 * Allocate Transmit Descriptor ring
574 */
575 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
1eca7b82 576 EM_DBA_ALIGN);
87307ba1
SZ		 577 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
578 if (error) {
9c80d176 579 device_printf(dev, "Unable to allocate tx_desc memory\n");
af82d4bb 580 goto fail;
984263bc 581 }
9c80d176 582 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
984263bc 583
9c80d176
SZ		 584 /*
585 * Allocate Receive Descriptor ring
586 */
587 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
1eca7b82 588 EM_DBA_ALIGN);
87307ba1
SZ		 589 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
590 if (error) {
9ccd8c1f 591 device_printf(dev, "Unable to allocate rx_desc memory\n");
af82d4bb 592 goto fail;
984263bc 593 }
9c80d176
SZ		 594 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
595
2d0e5700
SZ		 596 /* Allocate multicast array memory. */
597 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
598 M_DEVBUF, M_WAITOK);
599
600 /* Indicate SOL/IDER usage */
601 if (e1000_check_reset_block(&adapter->hw)) {
602 device_printf(dev,
603 "PHY reset is blocked due to SOL/IDER session.\n");
604 }
605
606 /*
607 * Start from a known state, this is important in reading the
608 * nvm and mac from that.
609 */
610 e1000_reset_hw(&adapter->hw);
611
9c80d176
SZ		 612 /* Make sure we have a good EEPROM before we read from it */
613 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
614 /*
615 * Some PCI-E parts fail the first check due to
616 * the link being in sleep state, call it again,
617 * if it fails a second time its a real issue.
618 */
619 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
620 device_printf(dev,
621 "The EEPROM Checksum Is Not Valid\n");
622 error = EIO;
623 goto fail;
624 }
625 }
984263bc 626
984263bc 627 /* Copy the permanent MAC address out of the EEPROM */
9c80d176
SZ		 628 if (e1000_read_mac_addr(&adapter->hw) < 0) {
629 device_printf(dev, "EEPROM read error while reading MAC"
630 " address\n");
984263bc 631 error = EIO;
af82d4bb 632 goto fail;
984263bc 633 }
9c80d176 634 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
87307ba1 635 device_printf(dev, "Invalid MAC address\n");
984263bc 636 error = EIO;
af82d4bb 637 goto fail;
984263bc
MD		 638 }
639
9c80d176
SZ		 640 /* Allocate transmit descriptors and buffers */
641 error = em_create_tx_ring(adapter);
642 if (error) {
643 device_printf(dev, "Could not setup transmit structures\n");
644 goto fail;
645 }
646
647 /* Allocate receive descriptors and buffers */
648 error = em_create_rx_ring(adapter);
649 if (error) {
650 device_printf(dev, "Could not setup receive structures\n");
651 goto fail;
652 }
653
654 /* Manually turn off all interrupts */
655 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
656
9c80d176
SZ		 657 /* Determine if we have to control management hardware */
658 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
659
660 /*
661 * Setup Wake-on-Lan
662 */
2d0e5700
SZ		 663 apme_mask = EM_EEPROM_APME;
664 eeprom_data = 0;
9c80d176
SZ		 665 switch (adapter->hw.mac.type) {
666 case e1000_82542:
667 case e1000_82543:
668 break;
669
2d0e5700
SZ		 670 case e1000_82573:
671 case e1000_82583:
672 adapter->has_amt = 1;
673 /* FALL THROUGH */
674
9c80d176
SZ		 675 case e1000_82546:
676 case e1000_82546_rev_3:
677 case e1000_82571:
2d0e5700 678 case e1000_82572:
9c80d176
SZ		 679 case e1000_80003es2lan:
680 if (adapter->hw.bus.func == 1) {
681 e1000_read_nvm(&adapter->hw,
682 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
683 } else {
684 e1000_read_nvm(&adapter->hw,
685 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
686 }
2d0e5700
SZ		 687 break;
688
689 case e1000_ich8lan:
690 case e1000_ich9lan:
691 case e1000_ich10lan:
692 case e1000_pchlan:
693 case e1000_pch2lan:
694 apme_mask = E1000_WUC_APME;
695 adapter->has_amt = TRUE;
696 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
9c80d176
SZ		 697 break;
698
699 default:
2d0e5700
SZ		 700 e1000_read_nvm(&adapter->hw,
701 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9c80d176
SZ		 702 break;
703 }
2d0e5700
SZ		 704 if (eeprom_data & apme_mask)
705 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
706
9c80d176
SZ		 707 /*
708 * We have the eeprom settings, now apply the special cases
709 * where the eeprom may be wrong or the board won't support
710 * wake on lan on a particular port
711 */
712 device_id = pci_get_device(dev);
713 switch (device_id) {
714 case E1000_DEV_ID_82546GB_PCIE:
715 adapter->wol = 0;
716 break;
717
718 case E1000_DEV_ID_82546EB_FIBER:
719 case E1000_DEV_ID_82546GB_FIBER:
720 case E1000_DEV_ID_82571EB_FIBER:
721 /*
722 * Wake events only supported on port A for dual fiber
723 * regardless of eeprom setting
724 */
725 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
726 E1000_STATUS_FUNC_1)
727 adapter->wol = 0;
728 break;
729
730 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
731 case E1000_DEV_ID_82571EB_QUAD_COPPER:
732 case E1000_DEV_ID_82571EB_QUAD_FIBER:
733 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
734 /* if quad port adapter, disable WoL on all but port A */
735 if (em_global_quad_port_a != 0)
736 adapter->wol = 0;
737 /* Reset for multiple quad port adapters */
738 if (++em_global_quad_port_a == 4)
739 em_global_quad_port_a = 0;
740 break;
741 }
742
743 /* XXX disable wol */
744 adapter->wol = 0;
745
2d0e5700
SZ		 746 /* Setup OS specific network interface */
747 em_setup_ifp(adapter);
748
749 /* Add sysctl tree, must after em_setup_ifp() */
750 em_add_sysctl(adapter);
751
752 /* Reset the hardware */
753 error = em_reset(adapter);
754 if (error) {
755 device_printf(dev, "Unable to reset the hardware\n");
756 goto fail;
757 }
758
759 /* Initialize statistics */
760 em_update_stats(adapter);
761
762 adapter->hw.mac.get_link_status = 1;
763 em_update_link_status(adapter);
764
9c80d176
SZ		 765 /* Do we need workaround for 82544 PCI-X adapter? */
766 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
767 adapter->hw.mac.type == e1000_82544)
f647ad3d 768 adapter->pcix_82544 = TRUE;
87307ba1 769 else
f647ad3d 770 adapter->pcix_82544 = FALSE;
af82d4bb 771
9c80d176
SZ		 772 if (adapter->pcix_82544) {
773 /*
774 * 82544 on PCI-X may split one TX segment
775 * into two TX descs, so we double its number
776 * of spare TX desc here.
777 */
778 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
779 } else {
780 adapter->spare_tx_desc = EM_TX_SPARE;
781 }
782
9f60d74b
SZ		 783 /*
784 * Keep following relationship between spare_tx_desc, oact_tx_desc
785 * and tx_int_nsegs:
786 * (spare_tx_desc + EM_TX_RESERVED) <=
787 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
788 */
789 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
790 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
791 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
792 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
793 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
794
795 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
796 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
797 adapter->tx_int_nsegs = adapter->oact_tx_desc;
798
2d0e5700
SZ		 799 /* Non-AMT based hardware can now take control from firmware */
800 if (adapter->has_manage && !adapter->has_amt &&
801 adapter->hw.mac.type >= e1000_82571)
802 em_get_hw_control(adapter);
803
9c80d176
SZ		 804 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
805 em_intr, adapter, &adapter->intr_tag,
806 ifp->if_serializer);
af82d4bb 807 if (error) {
9c80d176
SZ		 808 device_printf(dev, "Failed to register interrupt handler");
809 ether_ifdetach(&adapter->arpcom.ac_if);
af82d4bb
JS		 810 goto fail;
811 }
812
9c80d176 813 ifp->if_cpuid = ithread_cpuid(rman_get_start(adapter->intr_res));
9db4b353 814 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
9c80d176 815 return (0);
af82d4bb
JS		 816fail:
817 em_detach(dev);
9c80d176 818 return (error);
984263bc
MD		 819}
820
984263bc
MD		 821static int
822em_detach(device_t dev)
823{
78195a76 824 struct adapter *adapter = device_get_softc(dev);
984263bc 825
af82d4bb 826 if (device_is_attached(dev)) {
9c80d176 827 struct ifnet *ifp = &adapter->arpcom.ac_if;
cdf89432
SZ		 828
829 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 830
af82d4bb 831 em_stop(adapter);
9c80d176
SZ		 832
833 e1000_phy_hw_reset(&adapter->hw);
834
835 em_rel_mgmt(adapter);
2d0e5700 836 em_rel_hw_control(adapter);
9c80d176
SZ		 837
838 if (adapter->wol) {
839 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
840 E1000_WUC_PME_EN);
841 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
842 em_enable_wol(dev);
843 }
844
845 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
846
cdf89432
SZ		 847 lwkt_serialize_exit(ifp->if_serializer);
848
849 ether_ifdetach(ifp);
2d0e5700
SZ		 850 } else {
851 em_rel_hw_control(adapter);
7ea52455 852 }
cdf89432
SZ		 853 bus_generic_detach(dev);
854
9c80d176
SZ		 855 em_free_pci_res(adapter);
856
857 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
858 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
af82d4bb 859
984263bc 860 /* Free Transmit Descriptor ring */
9c80d176 861 if (adapter->tx_desc_base)
9ccd8c1f 862 em_dma_free(adapter, &adapter->txdma);
984263bc 863
984263bc 864 /* Free Receive Descriptor ring */
9c80d176 865 if (adapter->rx_desc_base)
9ccd8c1f 866 em_dma_free(adapter, &adapter->rxdma);
9c80d176
SZ		 867
868 /* Free top level busdma tag */
869 if (adapter->parent_dtag != NULL)
870 bus_dma_tag_destroy(adapter->parent_dtag);
984263bc 871
1eca7b82 872 /* Free sysctl tree */
9c80d176 873 if (adapter->sysctl_tree != NULL)
1eca7b82 874 sysctl_ctx_free(&adapter->sysctl_ctx);
984263bc 875
87307ba1 876 return (0);
984263bc
MD		 877}
878
984263bc
MD		 879static int
880em_shutdown(device_t dev)
881{
9c80d176 882 return em_suspend(dev);
87307ba1
SZ		 883}
884
87307ba1
SZ		 885static int
886em_suspend(device_t dev)
887{
888 struct adapter *adapter = device_get_softc(dev);
9c80d176 889 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ		 890
891 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 892
87307ba1 893 em_stop(adapter);
9c80d176
SZ		 894
895 em_rel_mgmt(adapter);
2d0e5700 896 em_rel_hw_control(adapter);
9c80d176 897
2d0e5700 898 if (adapter->wol) {
9c80d176
SZ		 899 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
900 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
901 em_enable_wol(dev);
2d0e5700 902 }
9c80d176 903
87307ba1 904 lwkt_serialize_exit(ifp->if_serializer);
9c80d176
SZ		 905
906 return bus_generic_suspend(dev);
87307ba1
SZ		 907}
908
909static int
910em_resume(device_t dev)
911{
912 struct adapter *adapter = device_get_softc(dev);
9c80d176 913 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ		 914
915 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 916
87307ba1 917 em_init(adapter);
9c80d176 918 em_get_mgmt(adapter);
9db4b353 919 if_devstart(ifp);
9c80d176 920
87307ba1
SZ		 921 lwkt_serialize_exit(ifp->if_serializer);
922
923 return bus_generic_resume(dev);
984263bc
MD		 924}
925
984263bc
MD		 926static void
927em_start(struct ifnet *ifp)
928{
f647ad3d 929 struct adapter *adapter = ifp->if_softc;
9c80d176 930 struct mbuf *m_head;
984263bc 931
1eca7b82 932 ASSERT_SERIALIZED(ifp->if_serializer);
78195a76 933
87307ba1
SZ		 934 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
935 return;
9c80d176 936
9db4b353
SZ		 937 if (!adapter->link_active) {
938 ifq_purge(&ifp->if_snd);
f647ad3d 939 return;
9db4b353 940 }
9c80d176 941
e26dc3e9 942 while (!ifq_is_empty(&ifp->if_snd)) {
9f60d74b
SZ		 943 /* Now do we at least have a minimal? */
944 if (EM_IS_OACTIVE(adapter)) {
945 em_tx_collect(adapter);
9c80d176 946 if (EM_IS_OACTIVE(adapter)) {
9c80d176 947 ifp->if_flags |= IFF_OACTIVE;
9f60d74b 948 adapter->no_tx_desc_avail1++;
9c80d176
SZ		 949 break;
950 }
951 }
952
953 logif(pkt_txqueue);
9db4b353 954 m_head = ifq_dequeue(&ifp->if_snd, NULL);
f647ad3d
JS		 955 if (m_head == NULL)
956 break;
984263bc 957
9c80d176 958 if (em_encap(adapter, &m_head)) {
002b3a05 959 ifp->if_oerrors++;
9f60d74b
SZ		 960 em_tx_collect(adapter);
961 continue;
f647ad3d 962 }
984263bc
MD		 963
964 /* Send a copy of the frame to the BPF listener */
b637f170 965 ETHER_BPF_MTAP(ifp, m_head);
87307ba1
SZ		 966
967 /* Set timeout in case hardware has problems transmitting. */
968 ifp->if_timer = EM_TX_TIMEOUT;
f647ad3d 969 }
984263bc
MD		 970}
971
984263bc 972static int
bd4539cc 973em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 974{
f647ad3d 975 struct adapter *adapter = ifp->if_softc;
9c80d176 976 struct ifreq *ifr = (struct ifreq *)data;
1eca7b82 977 uint16_t eeprom_data = 0;
9c80d176
SZ		 978 int max_frame_size, mask, reinit;
979 int error = 0;
0d366ee7 980
9c80d176 981 ASSERT_SERIALIZED(ifp->if_serializer);
0d366ee7 982
984263bc 983 switch (command) {
984263bc 984 case SIOCSIFMTU:
9c80d176
SZ		 985 switch (adapter->hw.mac.type) {
986 case e1000_82573:
1eca7b82
SZ		 987 /*
988 * 82573 only supports jumbo frames
989 * if ASPM is disabled.
990 */
9c80d176
SZ		 991 e1000_read_nvm(&adapter->hw,
992 NVM_INIT_3GIO_3, 1, &eeprom_data);
993 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1eca7b82
SZ		 994 max_frame_size = ETHER_MAX_LEN;
995 break;
996 }
9c80d176
SZ		 997 /* FALL THROUGH */
998
999 /* Limit Jumbo Frame size */
1000 case e1000_82571:
1001 case e1000_82572:
1002 case e1000_ich9lan:
1003 case e1000_ich10lan:
2d0e5700 1004 case e1000_pch2lan:
9c80d176
SZ		 1005 case e1000_82574:
1006 case e1000_80003es2lan:
1eca7b82 1007 max_frame_size = 9234;
7ea52455 1008 break;
9c80d176 1009
2d0e5700
SZ		 1010 case e1000_pchlan:
1011 max_frame_size = 4096;
1012 break;
1013
9c80d176
SZ		 1014 /* Adapters that do not support jumbo frames */
1015 case e1000_82542:
2d0e5700 1016 case e1000_82583:
9c80d176 1017 case e1000_ich8lan:
7ea52455
SZ		 1018 max_frame_size = ETHER_MAX_LEN;
1019 break;
9c80d176 1020
7ea52455
SZ		 1021 default:
1022 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1023 break;
1024 }
9c80d176
SZ		 1025 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1026 ETHER_CRC_LEN) {
984263bc 1027 error = EINVAL;
9c80d176 1028 break;
984263bc 1029 }
9c80d176
SZ		 1030
1031 ifp->if_mtu = ifr->ifr_mtu;
1032 adapter->max_frame_size =
1033 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1034
1035 if (ifp->if_flags & IFF_RUNNING)
1036 em_init(adapter);
984263bc 1037 break;
9c80d176 1038
984263bc 1039 case SIOCSIFFLAGS:
984263bc 1040 if (ifp->if_flags & IFF_UP) {
9c80d176
SZ		 1041 if ((ifp->if_flags & IFF_RUNNING)) {
1042 if ((ifp->if_flags ^ adapter->if_flags) &
1043 (IFF_PROMISC | IFF_ALLMULTI)) {
1044 em_disable_promisc(adapter);
1045 em_set_promisc(adapter);
1046 }
1047 } else {
78195a76 1048 em_init(adapter);
87307ba1 1049 }
9c80d176
SZ		 1050 } else if (ifp->if_flags & IFF_RUNNING) {
1051 em_stop(adapter);
984263bc 1052 }
87307ba1 1053 adapter->if_flags = ifp->if_flags;
984263bc 1054 break;
9c80d176 1055
984263bc
MD		 1056 case SIOCADDMULTI:
1057 case SIOCDELMULTI:
984263bc
MD		 1058 if (ifp->if_flags & IFF_RUNNING) {
1059 em_disable_intr(adapter);
1060 em_set_multi(adapter);
9c80d176
SZ		 1061 if (adapter->hw.mac.type == e1000_82542 &&
1062 adapter->hw.revision_id == E1000_REVISION_2)
1063 em_init_rx_unit(adapter);
1eca7b82 1064#ifdef DEVICE_POLLING
9c80d176 1065 if (!(ifp->if_flags & IFF_POLLING))
1eca7b82 1066#endif
9c80d176 1067 em_enable_intr(adapter);
984263bc
MD		 1068 }
1069 break;
9c80d176 1070
984263bc 1071 case SIOCSIFMEDIA:
87307ba1 1072 /* Check SOL/IDER usage */
9c80d176
SZ		 1073 if (e1000_check_reset_block(&adapter->hw)) {
1074 device_printf(adapter->dev, "Media change is"
1075 " blocked due to SOL/IDER session.\n");
87307ba1
SZ		 1076 break;
1077 }
9c80d176
SZ		 1078 /* FALL THROUGH */
1079
984263bc 1080 case SIOCGIFMEDIA:
984263bc
MD		 1081 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1082 break;
9c80d176 1083
984263bc 1084 case SIOCSIFCAP:
9c80d176 1085 reinit = 0;
984263bc
MD		 1086 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1087 if (mask & IFCAP_HWCSUM) {
9c80d176 1088 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
1eca7b82 1089 reinit = 1;
984263bc 1090 }
1eca7b82
SZ		 1091 if (mask & IFCAP_VLAN_HWTAGGING) {
1092 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1093 reinit = 1;
1094 }
9c80d176 1095 if (reinit && (ifp->if_flags & IFF_RUNNING))
1eca7b82 1096 em_init(adapter);
984263bc 1097 break;
9c80d176 1098
984263bc 1099 default:
1eca7b82
SZ		 1100 error = ether_ioctl(ifp, command, data);
1101 break;
984263bc 1102 }
87307ba1 1103 return (error);
984263bc
MD		 1104}
1105
984263bc
MD		 1106static void
1107em_watchdog(struct ifnet *ifp)
1108{
1eca7b82 1109 struct adapter *adapter = ifp->if_softc;
984263bc 1110
9c80d176
SZ		 1111 ASSERT_SERIALIZED(ifp->if_serializer);
1112
1113 /*
1114 * The timer is set to 5 every time start queues a packet.
1115 * Then txeof keeps resetting it as long as it cleans at
1116 * least one descriptor.
1117 * Finally, anytime all descriptors are clean the timer is
1118 * set to 0.
1119 */
1120
9f60d74b
SZ		 1121 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1122 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1123 /*
1124 * If we reach here, all TX jobs are completed and
1125 * the TX engine should have been idled for some time.
1126 * We don't need to call if_devstart() here.
1127 */
1128 ifp->if_flags &= ~IFF_OACTIVE;
1129 ifp->if_timer = 0;
1130 return;
1131 }
1132
1eca7b82
SZ		 1133 /*
1134 * If we are in this routine because of pause frames, then
984263bc
MD		 1135 * don't reset the hardware.
1136 */
9c80d176
SZ		 1137 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1138 E1000_STATUS_TXOFF) {
984263bc
MD		 1139 ifp->if_timer = EM_TX_TIMEOUT;
1140 return;
1141 }
1142
9c80d176 1143 if (e1000_check_for_link(&adapter->hw) == 0)
f647ad3d 1144 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc 1145
9c80d176
SZ		 1146 ifp->if_oerrors++;
1147 adapter->watchdog_events++;
1148
984263bc
MD		 1149 em_init(adapter);
1150
9c80d176
SZ		 1151 if (!ifq_is_empty(&ifp->if_snd))
1152 if_devstart(ifp);
984263bc
MD		 1153}
1154
984263bc 1155static void
9c80d176 1156em_init(void *xsc)
984263bc 1157{
9c80d176
SZ		 1158 struct adapter *adapter = xsc;
1159 struct ifnet *ifp = &adapter->arpcom.ac_if;
1160 device_t dev = adapter->dev;
eac00e59 1161 uint32_t pba;
984263bc 1162
87307ba1
SZ		 1163 ASSERT_SERIALIZED(ifp->if_serializer);
1164
984263bc
MD		 1165 em_stop(adapter);
1166
eac00e59
SZ		 1167 /*
1168 * Packet Buffer Allocation (PBA)
1169 * Writing PBA sets the receive portion of the buffer
1170 * the remainder is used for the transmit buffer.
1eca7b82
SZ		 1171 *
1172 * Devices before the 82547 had a Packet Buffer of 64K.
1173 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1174 * After the 82547 the buffer was reduced to 40K.
1175 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1176 * Note: default does not leave enough room for Jumbo Frame >10k.
eac00e59 1177 */
9c80d176
SZ		 1178 switch (adapter->hw.mac.type) {
1179 case e1000_82547:
1180 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1181 if (adapter->max_frame_size > 8192)
eac00e59 1182 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
7ea52455
SZ		 1183 else
1184 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
eac00e59
SZ		 1185 adapter->tx_fifo_head = 0;
1186 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1187 adapter->tx_fifo_size =
9c80d176 1188 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
7ea52455 1189 break;
9c80d176 1190
87307ba1 1191 /* Total Packet Buffer on these is 48K */
9c80d176
SZ		 1192 case e1000_82571:
1193 case e1000_82572:
1194 case e1000_80003es2lan:
7ea52455
SZ		 1195 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1196 break;
9c80d176
SZ		 1197
1198 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
7ea52455
SZ		 1199 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1200 break;
9c80d176
SZ		 1201
1202 case e1000_82574:
2d0e5700 1203 case e1000_82583:
9c80d176 1204 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1eca7b82 1205 break;
9c80d176 1206
2d0e5700
SZ		 1207 case e1000_ich8lan:
1208 pba = E1000_PBA_8K;
1209 break;
1210
9c80d176
SZ		 1211 case e1000_ich9lan:
1212 case e1000_ich10lan:
1213#define E1000_PBA_10K 0x000A
b0ff1d56
MS		 1214 pba = E1000_PBA_10K;
1215 break;
9c80d176 1216
2d0e5700
SZ		 1217 case e1000_pchlan:
1218 case e1000_pch2lan:
1219 pba = E1000_PBA_26K;
9c80d176
SZ		 1220 break;
1221
7ea52455
SZ		 1222 default:
1223 /* Devices before 82547 had a Packet Buffer of 64K. */
9c80d176 1224 if (adapter->max_frame_size > 8192)
7ea52455
SZ		 1225 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1226 else
1227 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
eac00e59 1228 }
9c80d176 1229 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
a4a205fa 1230
0d366ee7 1231 /* Get the latest mac address, User can use a LAA */
9c80d176
SZ		 1232 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1233
1234 /* Put the address into the Receive Address Array */
1235 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1236
1237 /*
1238 * With the 82571 adapter, RAR[0] may be overwritten
1239 * when the other port is reset, we make a duplicate
1240 * in RAR[14] for that eventuality, this assures
1241 * the interface continues to function.
1242 */
1243 if (adapter->hw.mac.type == e1000_82571) {
1244 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1245 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1246 E1000_RAR_ENTRIES - 1);
1247 }
0d366ee7 1248
2d0e5700
SZ		 1249 /* Reset the hardware */
1250 if (em_reset(adapter)) {
1251 device_printf(dev, "Unable to reset the hardware\n");
9c80d176 1252 /* XXX em_stop()? */
984263bc
MD		 1253 return;
1254 }
87307ba1 1255 em_update_link_status(adapter);
984263bc 1256
9c80d176
SZ		 1257 /* Setup VLAN support, basic and offload if available */
1258 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
984263bc 1259
9c80d176
SZ		 1260 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1261 uint32_t ctrl;
1262
1263 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1264 ctrl |= E1000_CTRL_VME;
1265 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
87307ba1
SZ		 1266 }
1267
9c80d176
SZ		 1268 /* Set hardware offload abilities */
1269 if (ifp->if_capenable & IFCAP_TXCSUM)
1270 ifp->if_hwassist = EM_CSUM_FEATURES;
1271 else
1272 ifp->if_hwassist = 0;
1273
1274 /* Configure for OS presence */
1275 em_get_mgmt(adapter);
1276
984263bc 1277 /* Prepare transmit descriptors and buffers */
9c80d176
SZ		 1278 em_init_tx_ring(adapter);
1279 em_init_tx_unit(adapter);
984263bc
MD		 1280
1281 /* Setup Multicast table */
1282 em_set_multi(adapter);
1283
1284 /* Prepare receive descriptors and buffers */
9c80d176
SZ		 1285 if (em_init_rx_ring(adapter)) {
1286 device_printf(dev, "Could not setup receive structures\n");
984263bc 1287 em_stop(adapter);
984263bc
MD		 1288 return;
1289 }
9c80d176 1290 em_init_rx_unit(adapter);
7ea52455 1291
87307ba1 1292 /* Don't lose promiscuous settings */
0d366ee7 1293 em_set_promisc(adapter);
984263bc 1294
984263bc
MD		 1295 ifp->if_flags |= IFF_RUNNING;
1296 ifp->if_flags &= ~IFF_OACTIVE;
1297
9c80d176
SZ		 1298 callout_reset(&adapter->timer, hz, em_timer, adapter);
1299 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1300
1301 /* MSI/X configuration for 82574 */
1302 if (adapter->hw.mac.type == e1000_82574) {
1303 int tmp;
1304
1305 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1306 tmp |= E1000_CTRL_EXT_PBA_CLR;
1307 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1308 /*
2d0e5700 1309 * XXX MSIX
9c80d176
SZ		 1310 * Set the IVAR - interrupt vector routing.
1311 * Each nibble represents a vector, high bit
1312 * is enable, other 3 bits are the MSIX table
1313 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1314 * Link (other) to 2, hence the magic number.
1315 */
1316 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1317 }
1eca7b82
SZ		 1318
1319#ifdef DEVICE_POLLING
9c80d176
SZ		 1320 /*
1321 * Only enable interrupts if we are not polling, make sure
1322 * they are off otherwise.
1323 */
1eca7b82
SZ		 1324 if (ifp->if_flags & IFF_POLLING)
1325 em_disable_intr(adapter);
1326 else
9c80d176
SZ		 1327#endif /* DEVICE_POLLING */
1328 em_enable_intr(adapter);
0d366ee7 1329
2d0e5700
SZ		 1330 /* AMT based hardware can now take control from firmware */
1331 if (adapter->has_manage && adapter->has_amt &&
1332 adapter->hw.mac.type >= e1000_82571)
1333 em_get_hw_control(adapter);
1334
0d366ee7 1335 /* Don't reset the phy next time init gets called */
9c80d176 1336 adapter->hw.phy.reset_disable = TRUE;
984263bc
MD		 1337}
1338
984263bc 1339#ifdef DEVICE_POLLING
f647ad3d
JS		 1340
1341static void
984263bc
MD		 1342em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1343{
f647ad3d
JS		 1344 struct adapter *adapter = ifp->if_softc;
1345 uint32_t reg_icr;
984263bc 1346
78195a76
MD		 1347 ASSERT_SERIALIZED(ifp->if_serializer);
1348
9c80d176 1349 switch (cmd) {
9c095379
MD		 1350 case POLL_REGISTER:
1351 em_disable_intr(adapter);
1352 break;
9c80d176 1353
9c095379 1354 case POLL_DEREGISTER:
f647ad3d 1355 em_enable_intr(adapter);
9c095379 1356 break;
9c80d176 1357
9c095379 1358 case POLL_AND_CHECK_STATUS:
9c80d176 1359 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
f647ad3d 1360 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
9ccd8c1f 1361 callout_stop(&adapter->timer);
9c80d176 1362 adapter->hw.mac.get_link_status = 1;
87307ba1 1363 em_update_link_status(adapter);
9c80d176 1364 callout_reset(&adapter->timer, hz, em_timer, adapter);
f647ad3d 1365 }
9c80d176 1366 /* FALL THROUGH */
9c095379
MD		 1367 case POLL_ONLY:
1368 if (ifp->if_flags & IFF_RUNNING) {
87307ba1
SZ		 1369 em_rxeof(adapter, count);
1370 em_txeof(adapter);
1eca7b82 1371
9c095379 1372 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1373 if_devstart(ifp);
9c095379
MD		 1374 }
1375 break;
f647ad3d 1376 }
984263bc 1377}
9c095379 1378
984263bc
MD		 1379#endif /* DEVICE_POLLING */
1380
984263bc 1381static void
9c80d176 1382em_intr(void *xsc)
984263bc 1383{
9c80d176
SZ		 1384 struct adapter *adapter = xsc;
1385 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1386 uint32_t reg_icr;
984263bc 1387
07855a48 1388 logif(intr_beg);
78195a76
MD		 1389 ASSERT_SERIALIZED(ifp->if_serializer);
1390
9c80d176
SZ		 1391 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1392
1393 if ((adapter->hw.mac.type >= e1000_82571 &&
1eca7b82
SZ		 1394 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1395 reg_icr == 0) {
07855a48 1396 logif(intr_end);
984263bc 1397 return;
07855a48 1398 }
984263bc 1399
87307ba1 1400 /*
9c80d176
SZ		 1401 * XXX: some laptops trigger several spurious interrupts
1402 * on em(4) when in the resume cycle. The ICR register
1403 * reports all-ones value in this case. Processing such
1404 * interrupts would lead to a freeze. I don't know why.
87307ba1
SZ		 1405 */
1406 if (reg_icr == 0xffffffff) {
1407 logif(intr_end);
1408 return;
984263bc
MD		 1409 }
1410
79938e61 1411 if (ifp->if_flags & IFF_RUNNING) {
9f60d74b 1412 if (reg_icr &
6643d744 1413 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
9f60d74b 1414 em_rxeof(adapter, -1);
6643d744 1415 if (reg_icr & E1000_ICR_TXDW) {
9f60d74b
SZ		 1416 em_txeof(adapter);
1417 if (!ifq_is_empty(&ifp->if_snd))
1418 if_devstart(ifp);
1419 }
f647ad3d 1420 }
984263bc 1421
87307ba1
SZ		 1422 /* Link status change */
1423 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1424 callout_stop(&adapter->timer);
9c80d176 1425 adapter->hw.mac.get_link_status = 1;
87307ba1 1426 em_update_link_status(adapter);
9c80d176
SZ		 1427
1428 /* Deal with TX cruft when link lost */
1429 em_tx_purge(adapter);
1430
1431 callout_reset(&adapter->timer, hz, em_timer, adapter);
87307ba1
SZ		 1432 }
1433
1434 if (reg_icr & E1000_ICR_RXO)
1435 adapter->rx_overruns++;
1436
07855a48 1437 logif(intr_end);
984263bc
MD		 1438}
1439
984263bc
MD		 1440static void
1441em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1442{
87307ba1 1443 struct adapter *adapter = ifp->if_softc;
1eca7b82 1444 u_char fiber_type = IFM_1000_SX;
984263bc 1445
78195a76
MD		 1446 ASSERT_SERIALIZED(ifp->if_serializer);
1447
87307ba1 1448 em_update_link_status(adapter);
984263bc
MD		 1449
1450 ifmr->ifm_status = IFM_AVALID;
1451 ifmr->ifm_active = IFM_ETHER;
1452
1453 if (!adapter->link_active)
1454 return;
1455
1456 ifmr->ifm_status |= IFM_ACTIVE;
1457
9c80d176
SZ		 1458 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1459 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1460 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ		 1461 fiber_type = IFM_1000_LX;
1462 ifmr->ifm_active |= fiber_type | IFM_FDX;
984263bc
MD		 1463 } else {
1464 switch (adapter->link_speed) {
1465 case 10:
1466 ifmr->ifm_active |= IFM_10_T;
1467 break;
1468 case 100:
1469 ifmr->ifm_active |= IFM_100_TX;
1470 break;
9c80d176 1471
984263bc 1472 case 1000:
7f259627 1473 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD		 1474 break;
1475 }
1476 if (adapter->link_duplex == FULL_DUPLEX)
1477 ifmr->ifm_active |= IFM_FDX;
1478 else
1479 ifmr->ifm_active |= IFM_HDX;
1480 }
984263bc
MD		 1481}
1482
984263bc
MD		 1483static int
1484em_media_change(struct ifnet *ifp)
1485{
87307ba1
SZ		 1486 struct adapter *adapter = ifp->if_softc;
1487 struct ifmedia *ifm = &adapter->media;
984263bc 1488
78195a76 1489 ASSERT_SERIALIZED(ifp->if_serializer);
9c095379 1490
87307ba1
SZ		 1491 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1492 return (EINVAL);
1493
984263bc
MD		 1494 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1495 case IFM_AUTO:
9c80d176
SZ		 1496 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1497 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
984263bc 1498 break;
9c80d176 1499
1eca7b82 1500 case IFM_1000_LX:
984263bc 1501 case IFM_1000_SX:
7f259627 1502 case IFM_1000_T:
9c80d176
SZ		 1503 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1504 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
984263bc 1505 break;
9c80d176 1506
984263bc 1507 case IFM_100_TX:
9c80d176
SZ		 1508 adapter->hw.mac.autoneg = FALSE;
1509 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1510 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1511 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
984263bc 1512 else
9c80d176 1513 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
984263bc 1514 break;
9c80d176 1515
984263bc 1516 case IFM_10_T:
9c80d176
SZ		 1517 adapter->hw.mac.autoneg = FALSE;
1518 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1519 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1520 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
984263bc 1521 else
9c80d176 1522 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
984263bc 1523 break;
9c80d176 1524
984263bc 1525 default:
f647ad3d 1526 if_printf(ifp, "Unsupported media type\n");
9c80d176 1527 break;
984263bc 1528 }
9c80d176 1529
f647ad3d 1530 /*
9c80d176 1531 * As the speed/duplex settings my have changed we need to
f647ad3d
JS		 1532 * reset the PHY.
1533 */
9c80d176 1534 adapter->hw.phy.reset_disable = FALSE;
984263bc 1535
78195a76 1536 em_init(adapter);
984263bc 1537
9c80d176 1538 return (0);
9ccd8c1f
JS		 1539}
1540
984263bc 1541static int
9c80d176 1542em_encap(struct adapter *adapter, struct mbuf **m_headp)
9ccd8c1f 1543{
9c80d176 1544 bus_dma_segment_t segs[EM_MAX_SCATTER];
1eca7b82 1545 bus_dmamap_t map;
9c80d176
SZ		 1546 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1547 struct e1000_tx_desc *ctxd = NULL;
002b3a05 1548 struct mbuf *m_head = *m_headp;
9f60d74b 1549 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
9c80d176 1550 int maxsegs, nsegs, i, j, first, last = 0, error;
984263bc 1551
3752657e 1552 if (m_head->m_len < EM_TXCSUM_MINHL &&
002b3a05
SZ		 1553 (m_head->m_flags & EM_CSUM_FEATURES)) {
1554 /*
1555 * Make sure that ethernet header and ip.ip_hl are in
1556 * contiguous memory, since if TXCSUM is enabled, later
1557 * TX context descriptor's setup need to access ip.ip_hl.
1558 */
1559 error = em_txcsum_pullup(adapter, m_headp);
1560 if (error) {
1561 KKASSERT(*m_headp == NULL);
1562 return error;
1563 }
1564 m_head = *m_headp;
1565 }
1566
9c80d176
SZ		 1567 txd_upper = txd_lower = 0;
1568 txd_used = 0;
87307ba1
SZ		 1569
1570 /*
9c80d176
SZ		 1571 * Capture the first descriptor index, this descriptor
1572 * will have the index of the EOP which is the only one
1573 * that now gets a DONE bit writeback.
87307ba1 1574 */
9c80d176
SZ		 1575 first = adapter->next_avail_tx_desc;
1576 tx_buffer = &adapter->tx_buffer_area[first];
1577 tx_buffer_mapped = tx_buffer;
1578 map = tx_buffer->map;
87307ba1 1579
9c80d176
SZ		 1580 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1581 KASSERT(maxsegs >= adapter->spare_tx_desc,
1582 ("not enough spare TX desc\n"));
1583 if (adapter->pcix_82544) {
1584 /* Half it; see the comment in em_attach() */
1585 maxsegs >>= 1;
9ccd8c1f 1586 }
9c80d176
SZ		 1587 if (maxsegs > EM_MAX_SCATTER)
1588 maxsegs = EM_MAX_SCATTER;
984263bc 1589
9c80d176
SZ		 1590 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1591 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1592 if (error) {
1593 if (error == ENOBUFS)
1594 adapter->mbuf_alloc_failed++;
1595 else
1596 adapter->no_tx_dma_setup++;
984263bc 1597
9c80d176
SZ		 1598 m_freem(*m_headp);
1599 *m_headp = NULL;
1600 return error;
7ea52455 1601 }
9c80d176 1602 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
984263bc 1603
9c80d176 1604 m_head = *m_headp;
9f60d74b 1605 adapter->tx_nsegs += nsegs;
9c80d176 1606
002b3a05 1607 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
9c80d176 1608 /* TX csum offloading will consume one TX desc */
9f60d74b
SZ		 1609 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1610 &txd_upper, &txd_lower);
9c80d176 1611 }
984263bc 1612 i = adapter->next_avail_tx_desc;
87307ba1
SZ		 1613
1614 /* Set up our transmit descriptors */
9c80d176 1615 for (j = 0; j < nsegs; j++) {
9ccd8c1f
JS		 1616 /* If adapter is 82544 and on PCIX bus */
1617 if(adapter->pcix_82544) {
87307ba1
SZ		 1618 DESC_ARRAY desc_array;
1619 uint32_t array_elements, counter;
1620
9c80d176 1621 /*
f647ad3d
JS		 1622 * Check the Address and Length combination and
1623 * split the data accordingly
9ccd8c1f 1624 */
9c80d176
SZ		 1625 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1626 segs[j].ds_len, &desc_array);
9ccd8c1f 1627 for (counter = 0; counter < array_elements; counter++) {
9c80d176
SZ		 1628 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1629
9ccd8c1f 1630 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176
SZ		 1631 ctxd = &adapter->tx_desc_base[i];
1632
1633 ctxd->buffer_addr = htole64(
1634 desc_array.descriptor[counter].address);
1635 ctxd->lower.data = htole32(
2af74b85 1636 E1000_TXD_CMD_IFCS | txd_lower |
9c80d176
SZ		 1637 desc_array.descriptor[counter].length);
1638 ctxd->upper.data = htole32(txd_upper);
87307ba1
SZ		 1639
1640 last = i;
9ccd8c1f
JS		 1641 if (++i == adapter->num_tx_desc)
1642 i = 0;
1643
9ccd8c1f 1644 txd_used++;
9c80d176 1645 }
9ccd8c1f 1646 } else {
0d366ee7 1647 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176 1648 ctxd = &adapter->tx_desc_base[i];
9ccd8c1f 1649
9c80d176 1650 ctxd->buffer_addr = htole64(segs[j].ds_addr);
2af74b85 1651 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
9c80d176
SZ		 1652 txd_lower | segs[j].ds_len);
1653 ctxd->upper.data = htole32(txd_upper);
984263bc 1654
87307ba1 1655 last = i;
0d366ee7
MD		 1656 if (++i == adapter->num_tx_desc)
1657 i = 0;
0d366ee7 1658 }
984263bc 1659 }
9ccd8c1f 1660
984263bc 1661 adapter->next_avail_tx_desc = i;
9c80d176
SZ		 1662 if (adapter->pcix_82544) {
1663 KKASSERT(adapter->num_tx_desc_avail > txd_used);
9ccd8c1f 1664 adapter->num_tx_desc_avail -= txd_used;
9c80d176
SZ		 1665 } else {
1666 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1667 adapter->num_tx_desc_avail -= nsegs;
1668 }
984263bc 1669
9c80d176 1670 /* Handle VLAN tag */
83790f85 1671 if (m_head->m_flags & M_VLANTAG) {
9c80d176
SZ		 1672 /* Set the vlan id. */
1673 ctxd->upper.fields.special =
1674 htole16(m_head->m_pkthdr.ether_vlantag);
9ccd8c1f 1675
f647ad3d 1676 /* Tell hardware to add tag */
9c80d176 1677 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
f647ad3d 1678 }
984263bc
MD		 1679
1680 tx_buffer->m_head = m_head;
9c80d176 1681 tx_buffer_mapped->map = tx_buffer->map;
1eca7b82 1682 tx_buffer->map = map;
9ccd8c1f 1683
9f60d74b
SZ		 1684 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1685 adapter->tx_nsegs = 0;
4e4e8481
SZ		 1686
1687 /*
1688 * Report Status (RS) is turned on
1689 * every tx_int_nsegs descriptors.
1690 */
9f60d74b
SZ		 1691 cmd = E1000_TXD_CMD_RS;
1692
b4b0a2b4
SZ		 1693 /*
1694 * Keep track of the descriptor, which will
1695 * be written back by hardware.
1696 */
9f60d74b
SZ		 1697 adapter->tx_dd[adapter->tx_dd_tail] = last;
1698 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1699 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1700 }
1701
9ccd8c1f 1702 /*
984263bc 1703 * Last Descriptor of Packet needs End Of Packet (EOP)
87307ba1 1704 */
9f60d74b 1705 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
87307ba1
SZ		 1706
1707 /*
9c80d176 1708 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
984263bc
MD		 1709 * that this frame is available to transmit.
1710 */
9c80d176 1711 if (adapter->hw.mac.type == e1000_82547 &&
984263bc 1712 adapter->link_duplex == HALF_DUPLEX) {
cfefda96 1713 em_82547_move_tail_serialized(adapter);
9ccd8c1f 1714 } else {
9c80d176
SZ		 1715 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1716 if (adapter->hw.mac.type == e1000_82547) {
cfefda96 1717 em_82547_update_fifo_head(adapter,
9c80d176 1718 m_head->m_pkthdr.len);
984263bc
MD		 1719 }
1720 }
87307ba1 1721 return (0);
984263bc
MD		 1722}
1723
9c80d176 1724/*
984263bc 1725 * 82547 workaround to avoid controller hang in half-duplex environment.
87307ba1 1726 * The workaround is to avoid queuing a large packet that would span
9c80d176
SZ		 1727 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1728 * in this case. We do that only when FIFO is quiescent.
1729 */
9c095379 1730static void
1eca7b82 1731em_82547_move_tail_serialized(struct adapter *adapter)
9c095379 1732{
9c80d176
SZ		 1733 struct e1000_tx_desc *tx_desc;
1734 uint16_t hw_tdt, sw_tdt, length = 0;
1735 bool eop = 0;
984263bc 1736
9c80d176
SZ		 1737 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1738
1739 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
984263bc 1740 sw_tdt = adapter->next_avail_tx_desc;
f647ad3d 1741
984263bc
MD		 1742 while (hw_tdt != sw_tdt) {
1743 tx_desc = &adapter->tx_desc_base[hw_tdt];
1744 length += tx_desc->lower.flags.length;
1745 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
87307ba1 1746 if (++hw_tdt == adapter->num_tx_desc)
984263bc
MD		 1747 hw_tdt = 0;
1748
87307ba1 1749 if (eop) {
984263bc 1750 if (em_82547_fifo_workaround(adapter, length)) {
eac00e59 1751 adapter->tx_fifo_wrk_cnt++;
9ccd8c1f
JS		 1752 callout_reset(&adapter->tx_fifo_timer, 1,
1753 em_82547_move_tail, adapter);
1754 break;
984263bc 1755 }
9c80d176 1756 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
9ccd8c1f
JS		 1757 em_82547_update_fifo_head(adapter, length);
1758 length = 0;
984263bc 1759 }
9c80d176
SZ		 1760 }
1761}
1762
1763static void
1764em_82547_move_tail(void *xsc)
1765{
1766 struct adapter *adapter = xsc;
1767 struct ifnet *ifp = &adapter->arpcom.ac_if;
1768
1769 lwkt_serialize_enter(ifp->if_serializer);
1770 em_82547_move_tail_serialized(adapter);
1771 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD		 1772}
1773
1774static int
1775em_82547_fifo_workaround(struct adapter *adapter, int len)
1776{
1777 int fifo_space, fifo_pkt_len;
1778
1eca7b82 1779 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
984263bc
MD		 1780
1781 if (adapter->link_duplex == HALF_DUPLEX) {
eac00e59 1782 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
984263bc
MD		 1783
1784 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
f647ad3d 1785 if (em_82547_tx_fifo_reset(adapter))
87307ba1 1786 return (0);
f647ad3d 1787 else
87307ba1 1788 return (1);
984263bc
MD		 1789 }
1790 }
87307ba1 1791 return (0);
984263bc
MD		 1792}
1793
1794static void
1795em_82547_update_fifo_head(struct adapter *adapter, int len)
1796{
1eca7b82 1797 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
f647ad3d 1798
984263bc
MD		 1799 /* tx_fifo_head is always 16 byte aligned */
1800 adapter->tx_fifo_head += fifo_pkt_len;
eac00e59
SZ		 1801 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1802 adapter->tx_fifo_head -= adapter->tx_fifo_size;
984263bc
MD		 1803}
1804
984263bc
MD		 1805static int
1806em_82547_tx_fifo_reset(struct adapter *adapter)
7ea52455 1807{
984263bc
MD		 1808 uint32_t tctl;
1809
9c80d176
SZ		 1810 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1811 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1812 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1813 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1814 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1815 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1816 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
984263bc 1817 /* Disable TX unit */
9c80d176
SZ		 1818 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1819 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1820 tctl & ~E1000_TCTL_EN);
984263bc
MD		 1821
1822 /* Reset FIFO pointers */
9c80d176
SZ		 1823 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1824 adapter->tx_head_addr);
1825 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1826 adapter->tx_head_addr);
1827 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1828 adapter->tx_head_addr);
1829 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1830 adapter->tx_head_addr);
984263bc
MD		 1831
1832 /* Re-enable TX unit */
9c80d176 1833 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD		 1834 E1000_WRITE_FLUSH(&adapter->hw);
1835
1836 adapter->tx_fifo_head = 0;
eac00e59 1837 adapter->tx_fifo_reset_cnt++;
984263bc 1838
87307ba1 1839 return (TRUE);
eac00e59 1840 } else {
87307ba1 1841 return (FALSE);
984263bc
MD		 1842 }
1843}
1844
1845static void
f647ad3d 1846em_set_promisc(struct adapter *adapter)
984263bc 1847{
9c80d176 1848 struct ifnet *ifp = &adapter->arpcom.ac_if;
1eca7b82 1849 uint32_t reg_rctl;
984263bc 1850
9c80d176 1851 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc
MD		 1852
1853 if (ifp->if_flags & IFF_PROMISC) {
1854 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
9c80d176
SZ		 1855 /* Turn this on if you want to see bad packets */
1856 if (em_debug_sbp)
1857 reg_rctl |= E1000_RCTL_SBP;
1858 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD		 1859 } else if (ifp->if_flags & IFF_ALLMULTI) {
1860 reg_rctl |= E1000_RCTL_MPE;
1861 reg_rctl &= ~E1000_RCTL_UPE;
9c80d176 1862 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc 1863 }
984263bc
MD		 1864}
1865
1866static void
f647ad3d 1867em_disable_promisc(struct adapter *adapter)
984263bc 1868{
f647ad3d 1869 uint32_t reg_rctl;
984263bc 1870
9c80d176 1871 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc 1872
9c80d176
SZ		 1873 reg_rctl &= ~E1000_RCTL_UPE;
1874 reg_rctl &= ~E1000_RCTL_MPE;
1875 reg_rctl &= ~E1000_RCTL_SBP;
1876 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD		 1877}
1878
984263bc 1879static void
f647ad3d 1880em_set_multi(struct adapter *adapter)
984263bc 1881{
9c80d176 1882 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1883 struct ifmultiaddr *ifma;
9c80d176 1884 uint32_t reg_rctl = 0;
2d0e5700 1885 uint8_t *mta;
f647ad3d 1886 int mcnt = 0;
f647ad3d 1887
2d0e5700
SZ		 1888 mta = adapter->mta;
1889 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1890
9c80d176
SZ		 1891 if (adapter->hw.mac.type == e1000_82542 &&
1892 adapter->hw.revision_id == E1000_REVISION_2) {
1893 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1894 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1895 e1000_pci_clear_mwi(&adapter->hw);
f647ad3d 1896 reg_rctl |= E1000_RCTL_RST;
9c80d176 1897 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d
JS		 1898 msec_delay(5);
1899 }
984263bc 1900
441d34b2 1901 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
f647ad3d
JS		 1902 if (ifma->ifma_addr->sa_family != AF_LINK)
1903 continue;
1904
1905 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1906 break;
984263bc 1907
f647ad3d 1908 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
9c80d176 1909 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
f647ad3d
JS		 1910 mcnt++;
1911 }
1912
1913 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
9c80d176 1914 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1915 reg_rctl |= E1000_RCTL_MPE;
9c80d176 1916 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
7ea52455 1917 } else {
6a5a645e 1918 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
7ea52455 1919 }
f647ad3d 1920
9c80d176
SZ		 1921 if (adapter->hw.mac.type == e1000_82542 &&
1922 adapter->hw.revision_id == E1000_REVISION_2) {
1923 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1924 reg_rctl &= ~E1000_RCTL_RST;
9c80d176 1925 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d 1926 msec_delay(5);
9c80d176
SZ		 1927 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1928 e1000_pci_set_mwi(&adapter->hw);
f647ad3d
JS		 1929 }
1930}
984263bc 1931
9c80d176
SZ		 1932/*
1933 * This routine checks for link status and updates statistics.
1934 */
984263bc 1935static void
9c80d176 1936em_timer(void *xsc)
984263bc 1937{
9c80d176
SZ		 1938 struct adapter *adapter = xsc;
1939 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 1940
78195a76 1941 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1942
87307ba1 1943 em_update_link_status(adapter);
9c80d176
SZ		 1944 em_update_stats(adapter);
1945
1946 /* Reset LAA into RAR[0] on 82571 */
1947 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1948 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1949
1950 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
984263bc 1951 em_print_hw_stats(adapter);
9c80d176 1952
984263bc
MD		 1953 em_smartspeed(adapter);
1954
9c80d176 1955 callout_reset(&adapter->timer, hz, em_timer, adapter);
984263bc 1956
78195a76 1957 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD		 1958}
1959
1960static void
87307ba1 1961em_update_link_status(struct adapter *adapter)
984263bc 1962{
9c80d176
SZ		 1963 struct e1000_hw *hw = &adapter->hw;
1964 struct ifnet *ifp = &adapter->arpcom.ac_if;
1965 device_t dev = adapter->dev;
1966 uint32_t link_check = 0;
1967
1968 /* Get the cached link value or read phy for real */
1969 switch (hw->phy.media_type) {
1970 case e1000_media_type_copper:
1971 if (hw->mac.get_link_status) {
1972 /* Do the work to read phy */
1973 e1000_check_for_link(hw);
1974 link_check = !hw->mac.get_link_status;
1975 if (link_check) /* ESB2 fix */
1976 e1000_cfg_on_link_up(hw);
1977 } else {
1978 link_check = TRUE;
984263bc 1979 }
9c80d176
SZ		 1980 break;
1981
1982 case e1000_media_type_fiber:
1983 e1000_check_for_link(hw);
1984 link_check =
1985 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1986 break;
1987
1988 case e1000_media_type_internal_serdes:
1989 e1000_check_for_link(hw);
1990 link_check = adapter->hw.mac.serdes_has_link;
1991 break;
1992
1993 case e1000_media_type_unknown:
1994 default:
1995 break;
1996 }
1997
1998 /* Now check for a transition */
1999 if (link_check && adapter->link_active == 0) {
2000 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2001 &adapter->link_duplex);
cb5a6be6
SZ		 2002
2003 /*
2004 * Check if we should enable/disable SPEED_MODE bit on
2005 * 82571/82572
2006 */
2d0e5700
SZ		 2007 if (adapter->link_speed != SPEED_1000 &&
2008 (hw->mac.type == e1000_82571 ||
2009 hw->mac.type == e1000_82572)) {
9c80d176
SZ		 2010 int tarc0;
2011
2012 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 2013 tarc0 &= ~SPEED_MODE_BIT;
9c80d176 2014 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
984263bc 2015 }
9c80d176
SZ		 2016 if (bootverbose) {
2017 device_printf(dev, "Link is up %d Mbps %s\n",
2018 adapter->link_speed,
2019 ((adapter->link_duplex == FULL_DUPLEX) ?
2020 "Full Duplex" : "Half Duplex"));
2021 }
2022 adapter->link_active = 1;
2023 adapter->smartspeed = 0;
2024 ifp->if_baudrate = adapter->link_speed * 1000000;
2025 ifp->if_link_state = LINK_STATE_UP;
2026 if_link_state_change(ifp);
2027 } else if (!link_check && adapter->link_active == 1) {
2028 ifp->if_baudrate = adapter->link_speed = 0;
2029 adapter->link_duplex = 0;
2030 if (bootverbose)
2031 device_printf(dev, "Link is Down\n");
2032 adapter->link_active = 0;
2033#if 0
2034 /* Link down, disable watchdog */
2035 if->if_timer = 0;
2036#endif
2037 ifp->if_link_state = LINK_STATE_DOWN;
2038 if_link_state_change(ifp);
984263bc 2039 }
984263bc
MD		 2040}
2041
984263bc 2042static void
9c80d176 2043em_stop(struct adapter *adapter)
984263bc 2044{
9c80d176
SZ		 2045 struct ifnet *ifp = &adapter->arpcom.ac_if;
2046 int i;
984263bc 2047
1eca7b82
SZ		 2048 ASSERT_SERIALIZED(ifp->if_serializer);
2049
984263bc 2050 em_disable_intr(adapter);
9c80d176 2051
9ccd8c1f
JS		 2052 callout_stop(&adapter->timer);
2053 callout_stop(&adapter->tx_fifo_timer);
984263bc 2054
984263bc 2055 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
af82d4bb 2056 ifp->if_timer = 0;
9c80d176
SZ		 2057
2058 e1000_reset_hw(&adapter->hw);
2059 if (adapter->hw.mac.type >= e1000_82544)
2060 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2061
2062 for (i = 0; i < adapter->num_tx_desc; i++) {
2063 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2064
2065 if (tx_buffer->m_head != NULL) {
2066 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2067 m_freem(tx_buffer->m_head);
2068 tx_buffer->m_head = NULL;
2069 }
9c80d176
SZ		 2070 }
2071
2072 for (i = 0; i < adapter->num_rx_desc; i++) {
2073 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2074
2075 if (rx_buffer->m_head != NULL) {
2076 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2077 m_freem(rx_buffer->m_head);
2078 rx_buffer->m_head = NULL;
2079 }
2080 }
c9ff32cc
SZ		 2081
2082 if (adapter->fmp != NULL)
2083 m_freem(adapter->fmp);
2084 adapter->fmp = NULL;
2085 adapter->lmp = NULL;
51e6819f
SZ		 2086
2087 adapter->csum_flags = 0;
2088 adapter->csum_ehlen = 0;
2089 adapter->csum_iphlen = 0;
9f60d74b
SZ		 2090
2091 adapter->tx_dd_head = 0;
2092 adapter->tx_dd_tail = 0;
2093 adapter->tx_nsegs = 0;
984263bc
MD		 2094}
2095
9c80d176
SZ		 2096static int
2097em_get_hw_info(struct adapter *adapter)
984263bc
MD		 2098{
2099 device_t dev = adapter->dev;
2100
984263bc
MD		 2101 /* Save off the information about this board */
2102 adapter->hw.vendor_id = pci_get_vendor(dev);
2103 adapter->hw.device_id = pci_get_device(dev);
f647ad3d
JS		 2104 adapter->hw.revision_id = pci_get_revid(dev);
2105 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
9c80d176 2106 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
984263bc 2107
9c80d176
SZ		 2108 /* Do Shared Code Init and Setup */
2109 if (e1000_set_mac_type(&adapter->hw))
2110 return ENXIO;
2111 return 0;
984263bc
MD		 2112}
2113
1eca7b82 2114static int
9c80d176 2115em_alloc_pci_res(struct adapter *adapter)
1eca7b82 2116{
9c80d176 2117 device_t dev = adapter->dev;
a483bd34 2118 int val, rid;
9c80d176
SZ		 2119
2120 /* Enable bus mastering */
2121 pci_enable_busmaster(dev);
1eca7b82 2122
9c80d176
SZ		 2123 adapter->memory_rid = EM_BAR_MEM;
2124 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2125 &adapter->memory_rid, RF_ACTIVE);
2126 if (adapter->memory == NULL) {
1eca7b82 2127 device_printf(dev, "Unable to allocate bus resource: memory\n");
9c80d176 2128 return (ENXIO);
1eca7b82
SZ		 2129 }
2130 adapter->osdep.mem_bus_space_tag =
9c80d176 2131 rman_get_bustag(adapter->memory);
1eca7b82 2132 adapter->osdep.mem_bus_space_handle =
9c80d176
SZ		 2133 rman_get_bushandle(adapter->memory);
2134
2135 /* XXX This is quite goofy, it is not actually used */
1eca7b82
SZ		 2136 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2137
9c80d176
SZ		 2138 /* Only older adapters use IO mapping */
2139 if (adapter->hw.mac.type > e1000_82543 &&
2140 adapter->hw.mac.type < e1000_82571) {
1eca7b82 2141 /* Figure our where our IO BAR is ? */
9c80d176 2142 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
1eca7b82 2143 val = pci_read_config(dev, rid, 4);
87307ba1 2144 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1eca7b82
SZ		 2145 adapter->io_rid = rid;
2146 break;
2147 }
2148 rid += 4;
87307ba1
SZ		 2149 /* check for 64bit BAR */
2150 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2151 rid += 4;
1eca7b82 2152 }
9c80d176 2153 if (rid >= PCIR_CARDBUSCIS) {
87307ba1
SZ		 2154 device_printf(dev, "Unable to locate IO BAR\n");
2155 return (ENXIO);
9c80d176
SZ		 2156 }
2157 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2158 &adapter->io_rid, RF_ACTIVE);
2159 if (adapter->ioport == NULL) {
1eca7b82 2160 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ		 2161 "ioport\n");
2162 return (ENXIO);
1eca7b82 2163 }
87307ba1
SZ		 2164 adapter->hw.io_base = 0;
2165 adapter->osdep.io_bus_space_tag =
9c80d176 2166 rman_get_bustag(adapter->ioport);
87307ba1 2167 adapter->osdep.io_bus_space_handle =
9c80d176 2168 rman_get_bushandle(adapter->ioport);
1eca7b82
SZ		 2169 }
2170
9c80d176
SZ		 2171 adapter->intr_rid = 0;
2172 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
2173 &adapter->intr_rid,
2174 RF_SHAREABLE | RF_ACTIVE);
2175 if (adapter->intr_res == NULL) {
1eca7b82 2176 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ		 2177 "interrupt\n");
2178 return (ENXIO);
1eca7b82
SZ		 2179 }
2180
9c80d176 2181 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1eca7b82 2182 adapter->hw.back = &adapter->osdep;
a483bd34 2183 return (0);
1eca7b82
SZ		 2184}
2185
2186static void
9c80d176 2187em_free_pci_res(struct adapter *adapter)
1eca7b82 2188{
9c80d176 2189 device_t dev = adapter->dev;
1eca7b82 2190
9c80d176
SZ		 2191 if (adapter->intr_res != NULL) {
2192 bus_release_resource(dev, SYS_RES_IRQ,
2193 adapter->intr_rid, adapter->intr_res);
1eca7b82 2194 }
9c80d176
SZ		 2195
2196 if (adapter->memory != NULL) {
2197 bus_release_resource(dev, SYS_RES_MEMORY,
2198 adapter->memory_rid, adapter->memory);
1eca7b82
SZ		 2199 }
2200
9c80d176
SZ		 2201 if (adapter->flash != NULL) {
2202 bus_release_resource(dev, SYS_RES_MEMORY,
2203 adapter->flash_rid, adapter->flash);
1eca7b82
SZ		 2204 }
2205
9c80d176
SZ		 2206 if (adapter->ioport != NULL) {
2207 bus_release_resource(dev, SYS_RES_IOPORT,
2208 adapter->io_rid, adapter->ioport);
1eca7b82
SZ		 2209 }
2210}
2211
984263bc 2212static int
2d0e5700 2213em_reset(struct adapter *adapter)
984263bc 2214{
9c80d176
SZ		 2215 device_t dev = adapter->dev;
2216 uint16_t rx_buffer_size;
7ea52455 2217
984263bc
MD		 2218 /* When hardware is reset, fifo_head is also reset */
2219 adapter->tx_fifo_head = 0;
2220
87307ba1 2221 /* Set up smart power down as default off on newer adapters. */
1eca7b82 2222 if (!em_smart_pwr_down &&
9c80d176
SZ		 2223 (adapter->hw.mac.type == e1000_82571 ||
2224 adapter->hw.mac.type == e1000_82572)) {
1eca7b82
SZ		 2225 uint16_t phy_tmp = 0;
2226
87307ba1 2227 /* Speed up time to link by disabling smart power down. */
9c80d176
SZ		 2228 e1000_read_phy_reg(&adapter->hw,
2229 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1eca7b82 2230 phy_tmp &= ~IGP02E1000_PM_SPD;
9c80d176
SZ		 2231 e1000_write_phy_reg(&adapter->hw,
2232 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1eca7b82
SZ		 2233 }
2234
7ea52455 2235 /*
87307ba1
SZ		 2236 * These parameters control the automatic generation (Tx) and
2237 * response (Rx) to Ethernet PAUSE frames.
7ea52455
SZ		 2238 * - High water mark should allow for at least two frames to be
2239 * received after sending an XOFF.
2240 * - Low water mark works best when it is very near the high water mark.
2241 * This allows the receiver to restart by sending XON when it has
9c80d176
SZ		 2242 * drained a bit. Here we use an arbitary value of 1500 which will
2243 * restart after one full frame is pulled from the buffer. There
7ea52455
SZ		 2244 * could be several smaller frames in the buffer and if so they will
2245 * not trigger the XON until their total number reduces the buffer
2246 * by 1500.
2247 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2248 */
9c80d176
SZ		 2249 rx_buffer_size =
2250 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
7ea52455 2251
9c80d176
SZ		 2252 adapter->hw.fc.high_water = rx_buffer_size -
2253 roundup2(adapter->max_frame_size, 1024);
2254 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2255
2256 if (adapter->hw.mac.type == e1000_80003es2lan)
2257 adapter->hw.fc.pause_time = 0xFFFF;
1eca7b82 2258 else
9c80d176 2259 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2d0e5700 2260
9c80d176 2261 adapter->hw.fc.send_xon = TRUE;
2d0e5700 2262
9c80d176 2263 adapter->hw.fc.requested_mode = e1000_fc_full;
7ea52455 2264
2d0e5700
SZ		 2265 /* Workaround: no TX flow ctrl for PCH */
2266 if (adapter->hw.mac.type == e1000_pchlan)
2267 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2268
2269 /* Override - settings for PCH2LAN, ya its magic :) */
2270 if (adapter->hw.mac.type == e1000_pch2lan) {
2271 adapter->hw.fc.high_water = 0x5C20;
2272 adapter->hw.fc.low_water = 0x5048;
2273 adapter->hw.fc.pause_time = 0x0650;
2274 adapter->hw.fc.refresh_time = 0x0400;
2275
2276 /* Jumbos need adjusted PBA */
2277 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2278 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2279 else
2280 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2281 }
2282
2283 /* Issue a global reset */
2284 e1000_reset_hw(&adapter->hw);
2285 if (adapter->hw.mac.type >= e1000_82544)
2286 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2287
9c80d176
SZ		 2288 if (e1000_init_hw(&adapter->hw) < 0) {
2289 device_printf(dev, "Hardware Initialization Failed\n");
87307ba1 2290 return (EIO);
984263bc
MD		 2291 }
2292
2d0e5700
SZ		 2293 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2294 e1000_get_phy_info(&adapter->hw);
9c80d176 2295 e1000_check_for_link(&adapter->hw);
984263bc 2296
87307ba1 2297 return (0);
984263bc
MD		 2298}
2299
984263bc 2300static void
9c80d176 2301em_setup_ifp(struct adapter *adapter)
984263bc 2302{
9c80d176 2303 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2304
9c80d176
SZ		 2305 if_initname(ifp, device_get_name(adapter->dev),
2306 device_get_unit(adapter->dev));
984263bc
MD		 2307 ifp->if_softc = adapter;
2308 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c80d176 2309 ifp->if_init = em_init;
984263bc
MD		 2310 ifp->if_ioctl = em_ioctl;
2311 ifp->if_start = em_start;
9c095379
MD		 2312#ifdef DEVICE_POLLING
2313 ifp->if_poll = em_poll;
2314#endif
984263bc 2315 ifp->if_watchdog = em_watchdog;
e26dc3e9 2316 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
19b1d5b8 2317 ifq_set_ready(&ifp->if_snd);
984263bc 2318
9c80d176 2319 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
984263bc 2320
9c80d176
SZ		 2321 if (adapter->hw.mac.type >= e1000_82543)
2322 ifp->if_capabilities = IFCAP_HWCSUM;
e095c7aa 2323
9c80d176
SZ		 2324 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2325 ifp->if_capenable = ifp->if_capabilities;
984263bc 2326
9c80d176
SZ		 2327 if (ifp->if_capenable & IFCAP_TXCSUM)
2328 ifp->if_hwassist = EM_CSUM_FEATURES;
21fa6062 2329
f647ad3d
JS		 2330 /*
2331 * Tell the upper layer(s) we support long frames.
2332 */
2333 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
984263bc 2334
87307ba1 2335 /*
984263bc
MD		 2336 * Specify the media types supported by this adapter and register
2337 * callbacks to update media and link information
2338 */
9c80d176
SZ		 2339 ifmedia_init(&adapter->media, IFM_IMASK,
2340 em_media_change, em_media_status);
2341 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2342 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2343 u_char fiber_type = IFM_1000_SX; /* default type */
2344
2345 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ		 2346 fiber_type = IFM_1000_LX;
2347 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
984263bc 2348 0, NULL);
87307ba1 2349 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
984263bc
MD		 2350 } else {
2351 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
87307ba1 2352 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
984263bc 2353 0, NULL);
87307ba1 2354 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
984263bc 2355 0, NULL);
87307ba1 2356 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
984263bc 2357 0, NULL);
9c80d176
SZ		 2358 if (adapter->hw.phy.type != e1000_phy_ife) {
2359 ifmedia_add(&adapter->media,
2360 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2361 ifmedia_add(&adapter->media,
2362 IFM_ETHER | IFM_1000_T, 0, NULL);
2363 }
984263bc
MD		 2364 }
2365 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2366 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
984263bc
MD		 2367}
2368
9c80d176
SZ		 2369
2370/*
2371 * Workaround for SmartSpeed on 82541 and 82547 controllers
2372 */
984263bc
MD		 2373static void
2374em_smartspeed(struct adapter *adapter)
2375{
f647ad3d
JS		 2376 uint16_t phy_tmp;
2377
9c80d176
SZ		 2378 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2379 adapter->hw.mac.autoneg == 0 ||
2380 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
984263bc
MD		 2381 return;
2382
f647ad3d
JS		 2383 if (adapter->smartspeed == 0) {
2384 /*
2385 * If Master/Slave config fault is asserted twice,
9c80d176 2386 * we assume back-to-back
f647ad3d 2387 */
9c80d176 2388 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d
JS		 2389 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2390 return;
9c80d176 2391 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d 2392 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
9c80d176
SZ		 2393 e1000_read_phy_reg(&adapter->hw,
2394 PHY_1000T_CTRL, &phy_tmp);
f647ad3d
JS		 2395 if (phy_tmp & CR_1000T_MS_ENABLE) {
2396 phy_tmp &= ~CR_1000T_MS_ENABLE;
9c80d176
SZ		 2397 e1000_write_phy_reg(&adapter->hw,
2398 PHY_1000T_CTRL, phy_tmp);
f647ad3d 2399 adapter->smartspeed++;
9c80d176
SZ		 2400 if (adapter->hw.mac.autoneg &&
2401 !e1000_phy_setup_autoneg(&adapter->hw) &&
2402 !e1000_read_phy_reg(&adapter->hw,
2403 PHY_CONTROL, &phy_tmp)) {
2404 phy_tmp |= MII_CR_AUTO_NEG_EN |
2405 MII_CR_RESTART_AUTO_NEG;
2406 e1000_write_phy_reg(&adapter->hw,
2407 PHY_CONTROL, phy_tmp);
f647ad3d
JS		 2408 }
2409 }
2410 }
87307ba1 2411 return;
f647ad3d
JS		 2412 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2413 /* If still no link, perhaps using 2/3 pair cable */
9c80d176 2414 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
f647ad3d 2415 phy_tmp |= CR_1000T_MS_ENABLE;
9c80d176
SZ		 2416 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2417 if (adapter->hw.mac.autoneg &&
2418 !e1000_phy_setup_autoneg(&adapter->hw) &&
2419 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2420 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2421 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
f647ad3d
JS		 2422 }
2423 }
9c80d176 2424
f647ad3d
JS		 2425 /* Restart process after EM_SMARTSPEED_MAX iterations */
2426 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2427 adapter->smartspeed = 0;
984263bc
MD		 2428}
2429
9ccd8c1f
JS		 2430static int
2431em_dma_malloc(struct adapter *adapter, bus_size_t size,
87307ba1 2432 struct em_dma_alloc *dma)
9ccd8c1f 2433{
9c80d176
SZ		 2434 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2435 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2436 &dma->dma_tag, &dma->dma_map,
2437 &dma->dma_paddr);
2438 if (dma->dma_vaddr == NULL)
2439 return ENOMEM;
2440 else
2441 return 0;
9ccd8c1f
JS		 2442}
2443
2444static void
2445em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2446{
9c80d176
SZ		 2447 if (dma->dma_tag == NULL)
2448 return;
2449 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2450 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2451 bus_dma_tag_destroy(dma->dma_tag);
984263bc
MD		 2452}
2453
984263bc 2454static int
9c80d176 2455em_create_tx_ring(struct adapter *adapter)
984263bc 2456{
9c80d176 2457 device_t dev = adapter->dev;
1eca7b82 2458 struct em_buffer *tx_buffer;
1eca7b82
SZ		 2459 int error, i;
2460
87307ba1
SZ		 2461 adapter->tx_buffer_area =
2462 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2463 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 2464
9c80d176
SZ		 2465 /*
2466 * Create DMA tags for tx buffers
2467 */
2468 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2469 1, 0, /* alignment, bounds */
2470 BUS_SPACE_MAXADDR, /* lowaddr */
2471 BUS_SPACE_MAXADDR, /* highaddr */
2472 NULL, NULL, /* filter, filterarg */
2473 EM_TSO_SIZE, /* maxsize */
2474 EM_MAX_SCATTER, /* nsegments */
2475 EM_MAX_SEGSIZE, /* maxsegsize */
2476 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2477 BUS_DMA_ONEBPAGE, /* flags */
2478 &adapter->txtag);
2479 if (error) {
2480 device_printf(dev, "Unable to allocate TX DMA tag\n");
2481 kfree(adapter->tx_buffer_area, M_DEVBUF);
2482 adapter->tx_buffer_area = NULL;
2483 return error;
2484 }
2485
2486 /*
2487 * Create DMA maps for tx buffers
2488 */
1eca7b82 2489 for (i = 0; i < adapter->num_tx_desc; i++) {
9c80d176
SZ		 2490 tx_buffer = &adapter->tx_buffer_area[i];
2491
2492 error = bus_dmamap_create(adapter->txtag,
2493 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2494 &tx_buffer->map);
1eca7b82 2495 if (error) {
9c80d176
SZ		 2496 device_printf(dev, "Unable to create TX DMA map\n");
2497 em_destroy_tx_ring(adapter, i);
2498 return error;
1eca7b82 2499 }
1eca7b82 2500 }
9c80d176
SZ		 2501 return (0);
2502}
9ccd8c1f 2503
9c80d176
SZ		 2504static void
2505em_init_tx_ring(struct adapter *adapter)
2506{
2507 /* Clear the old ring contents */
2508 bzero(adapter->tx_desc_base,
2509 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2510
2511 /* Reset state */
87307ba1
SZ		 2512 adapter->next_avail_tx_desc = 0;
2513 adapter->next_tx_to_clean = 0;
984263bc 2514 adapter->num_tx_desc_avail = adapter->num_tx_desc;
984263bc
MD		 2515}
2516
984263bc 2517static void
9c80d176 2518em_init_tx_unit(struct adapter *adapter)
984263bc 2519{
9c80d176 2520 uint32_t tctl, tarc, tipg = 0;
9ccd8c1f
JS		 2521 uint64_t bus_addr;
2522
984263bc 2523 /* Setup the Base and Length of the Tx Descriptor Ring */
9ccd8c1f 2524 bus_addr = adapter->txdma.dma_paddr;
9c80d176
SZ		 2525 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2526 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2527 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2528 (uint32_t)(bus_addr >> 32));
2529 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2530 (uint32_t)bus_addr);
984263bc 2531 /* Setup the HW Tx Head and Tail descriptor pointers */
9c80d176
SZ		 2532 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2533 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
984263bc 2534
984263bc 2535 /* Set the default values for the Tx Inter Packet Gap timer */
9c80d176
SZ		 2536 switch (adapter->hw.mac.type) {
2537 case e1000_82542:
2538 tipg = DEFAULT_82542_TIPG_IPGT;
2539 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2540 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
984263bc 2541 break;
9c80d176
SZ		 2542
2543 case e1000_80003es2lan:
2544 tipg = DEFAULT_82543_TIPG_IPGR1;
2545 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2546 E1000_TIPG_IPGR2_SHIFT;
1eca7b82 2547 break;
9c80d176 2548
984263bc 2549 default:
9c80d176
SZ		 2550 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2551 adapter->hw.phy.media_type ==
2552 e1000_media_type_internal_serdes)
2553 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
984263bc 2554 else
9c80d176
SZ		 2555 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2556 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2557 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2558 break;
2559 }
2560
2561 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
91e8debf
SZ		 2562
2563 /* NOTE: 0 is not allowed for TIDV */
2564 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2565 if(adapter->hw.mac.type >= e1000_82540)
2566 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
984263bc 2567
9c80d176
SZ		 2568 if (adapter->hw.mac.type == e1000_82571 ||
2569 adapter->hw.mac.type == e1000_82572) {
2570 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2571 tarc |= SPEED_MODE_BIT;
2572 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2573 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2574 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2575 tarc |= 1;
2576 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2577 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2578 tarc |= 1;
2579 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
1eca7b82
SZ		 2580 }
2581
984263bc 2582 /* Program the Transmit Control Register */
9c80d176
SZ		 2583 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2584 tctl &= ~E1000_TCTL_CT;
2585 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2586 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2587
2588 if (adapter->hw.mac.type >= e1000_82571)
2589 tctl |= E1000_TCTL_MULR;
1eca7b82 2590
87307ba1 2591 /* This write will effectively turn on the transmit unit. */
9c80d176 2592 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD		 2593}
2594
984263bc 2595static void
9c80d176 2596em_destroy_tx_ring(struct adapter *adapter, int ndesc)
984263bc 2597{
f647ad3d
JS		 2598 struct em_buffer *tx_buffer;
2599 int i;
984263bc 2600
9c80d176
SZ		 2601 if (adapter->tx_buffer_area == NULL)
2602 return;
984263bc 2603
9c80d176
SZ		 2604 for (i = 0; i < ndesc; i++) {
2605 tx_buffer = &adapter->tx_buffer_area[i];
1eca7b82 2606
9c80d176
SZ		 2607 KKASSERT(tx_buffer->m_head == NULL);
2608 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
9ccd8c1f 2609 }
9c80d176
SZ		 2610 bus_dma_tag_destroy(adapter->txtag);
2611
2612 kfree(adapter->tx_buffer_area, M_DEVBUF);
2613 adapter->tx_buffer_area = NULL;
984263bc
MD		 2614}
2615
9c80d176
SZ		 2616/*
2617 * The offload context needs to be set when we transfer the first
2618 * packet of a particular protocol (TCP/UDP). This routine has been
002b3a05 2619 * enhanced to deal with inserted VLAN headers.
51e6819f
SZ		 2620 *
2621 * If the new packet's ether header length, ip header length and
2622 * csum offloading type are same as the previous packet, we should
2623 * avoid allocating a new csum context descriptor; mainly to take
2624 * advantage of the pipeline effect of the TX data read request.
9f60d74b
SZ		 2625 *
2626 * This function returns number of TX descrptors allocated for
2627 * csum context.
9c80d176 2628 */
9f60d74b 2629static int
9c80d176
SZ		 2630em_txcsum(struct adapter *adapter, struct mbuf *mp,
2631 uint32_t *txd_upper, uint32_t *txd_lower)
984263bc 2632{
9c80d176 2633 struct e1000_context_desc *TXD;
984263bc 2634 struct em_buffer *tx_buffer;
9c80d176 2635 struct ether_vlan_header *eh;
51e6819f
SZ		 2636 struct ip *ip;
2637 int curr_txd, ehdrlen, csum_flags;
9c80d176
SZ		 2638 uint32_t cmd, hdr_len, ip_hlen;
2639 uint16_t etype;
9c80d176 2640
9c80d176
SZ		 2641 /*
2642 * Determine where frame payload starts.
2643 * Jump over vlan headers if already present,
2644 * helpful for QinQ too.
2645 */
252dfd0d
SZ		 2646 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2647 ("em_txcsum_pullup is not called (eh)?\n"));
9c80d176
SZ		 2648 eh = mtod(mp, struct ether_vlan_header *);
2649 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
252dfd0d
SZ		 2650 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2651 ("em_txcsum_pullup is not called (evh)?\n"));
9c80d176
SZ		 2652 etype = ntohs(eh->evl_proto);
2653 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
984263bc 2654 } else {
9c80d176
SZ		 2655 etype = ntohs(eh->evl_encap_proto);
2656 ehdrlen = ETHER_HDR_LEN;
984263bc
MD		 2657 }
2658
1eca7b82 2659 /*
002b3a05 2660 * We only support TCP/UDP for IPv4 for the moment.
9c80d176 2661 * TODO: Support SCTP too when it hits the tree.
984263bc 2662 */
51e6819f 2663 if (etype != ETHERTYPE_IP)
9f60d74b 2664 return 0;
002b3a05 2665
51e6819f 2666 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE,
252dfd0d 2667 ("em_txcsum_pullup is not called (eh+ip_vhl)?\n"));
9c80d176 2668
51e6819f
SZ		 2669 /* NOTE: We could only safely access ip.ip_vhl part */
2670 ip = (struct ip *)(mp->m_data + ehdrlen);
2671 ip_hlen = ip->ip_hl << 2;
984263bc 2672
51e6819f
SZ		 2673 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2674
2675 if (adapter->csum_ehlen == ehdrlen &&
2676 adapter->csum_iphlen == ip_hlen &&
2677 adapter->csum_flags == csum_flags) {
2678 /*
2679 * Same csum offload context as the previous packets;
2680 * just return.
2681 */
2682 *txd_upper = adapter->csum_txd_upper;
2683 *txd_lower = adapter->csum_txd_lower;
9f60d74b 2684 return 0;
984263bc
MD		 2685 }
2686
51e6819f
SZ		 2687 /*
2688 * Setup a new csum offload context.
2689 */
2690
2691 curr_txd = adapter->next_avail_tx_desc;
2692 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2693 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2694
2695 cmd = 0;
2696
2697 /* Setup of IP header checksum. */
2698 if (csum_flags & CSUM_IP) {
2699 /*
2700 * Start offset for header checksum calculation.
2701 * End offset for header checksum calculation.
2702 * Offset of place to put the checksum.
2703 */
2704 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2705 TXD->lower_setup.ip_fields.ipcse =
2706 htole16(ehdrlen + ip_hlen - 1);
2707 TXD->lower_setup.ip_fields.ipcso =
2708 ehdrlen + offsetof(struct ip, ip_sum);
2709 cmd |= E1000_TXD_CMD_IP;
2710 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2711 }
2712 hdr_len = ehdrlen + ip_hlen;
2713
2714 if (csum_flags & CSUM_TCP) {
002b3a05
SZ		 2715 /*
2716 * Start offset for payload checksum calculation.
2717 * End offset for payload checksum calculation.
2718 * Offset of place to put the checksum.
2719 */
2720 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2721 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2722 TXD->upper_setup.tcp_fields.tucso =
2723 hdr_len + offsetof(struct tcphdr, th_sum);
2724 cmd |= E1000_TXD_CMD_TCP;
2725 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
51e6819f 2726 } else if (csum_flags & CSUM_UDP) {
002b3a05
SZ		 2727 /*
2728 * Start offset for header checksum calculation.
2729 * End offset for header checksum calculation.
2730 * Offset of place to put the checksum.
2731 */
2732 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2733 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2734 TXD->upper_setup.tcp_fields.tucso =
2735 hdr_len + offsetof(struct udphdr, uh_sum);
2736 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
9c80d176
SZ		 2737 }
2738
2739 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2740 E1000_TXD_DTYP_D; /* Data descr */
51e6819f
SZ		 2741
2742 /* Save the information for this csum offloading context */
2743 adapter->csum_ehlen = ehdrlen;
2744 adapter->csum_iphlen = ip_hlen;
2745 adapter->csum_flags = csum_flags;
2746 adapter->csum_txd_upper = *txd_upper;
2747 adapter->csum_txd_lower = *txd_lower;
2748
9c80d176
SZ		 2749 TXD->tcp_seg_setup.data = htole32(0);
2750 TXD->cmd_and_length =
2af74b85 2751 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
984263bc
MD		 2752
2753 if (++curr_txd == adapter->num_tx_desc)
2754 curr_txd = 0;
2755
9c80d176 2756 KKASSERT(adapter->num_tx_desc_avail > 0);
984263bc 2757 adapter->num_tx_desc_avail--;
9c80d176 2758
984263bc 2759 adapter->next_avail_tx_desc = curr_txd;
9f60d74b 2760 return 1;
984263bc
MD		 2761}
2762
002b3a05
SZ		 2763static int
2764em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0)
2765{
2766 struct mbuf *m = *m0;
2767 struct ether_header *eh;
2768 int len;
2769
2770 adapter->tx_csum_try_pullup++;
2771
2772 len = ETHER_HDR_LEN + EM_IPVHL_SIZE;
2773
2774 if (__predict_false(!M_WRITABLE(m))) {
2775 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2776 adapter->tx_csum_drop1++;
2777 m_freem(m);
2778 *m0 = NULL;
2779 return ENOBUFS;
2780 }
2781 eh = mtod(m, struct ether_header *);
2782
2783 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2784 len += EVL_ENCAPLEN;
2785
3752657e 2786 if (m->m_len < len) {
002b3a05
SZ		 2787 adapter->tx_csum_drop2++;
2788 m_freem(m);
2789 *m0 = NULL;
2790 return ENOBUFS;
2791 }
2792 return 0;
2793 }
2794
2795 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2796 adapter->tx_csum_pullup1++;
2797 m = m_pullup(m, ETHER_HDR_LEN);
2798 if (m == NULL) {
2799 adapter->tx_csum_pullup1_failed++;
2800 *m0 = NULL;
2801 return ENOBUFS;
2802 }
2803 *m0 = m;
2804 }
2805 eh = mtod(m, struct ether_header *);
2806
2807 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2808 len += EVL_ENCAPLEN;
2809
3752657e 2810 if (m->m_len < len) {
002b3a05
SZ		 2811 adapter->tx_csum_pullup2++;
2812 m = m_pullup(m, len);
2813 if (m == NULL) {
2814 adapter->tx_csum_pullup2_failed++;
2815 *m0 = NULL;
2816 return ENOBUFS;
2817 }
2818 *m0 = m;
2819 }
2820 return 0;
2821}
2822
984263bc 2823static void
87307ba1 2824em_txeof(struct adapter *adapter)
984263bc 2825{
9c80d176 2826 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ		 2827 struct em_buffer *tx_buffer;
2828 int first, num_avail;
2829
2830 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2831 return;
984263bc 2832
f647ad3d
JS		 2833 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2834 return;
984263bc 2835
9c80d176 2836 num_avail = adapter->num_tx_desc_avail;
87307ba1 2837 first = adapter->next_tx_to_clean;
9c80d176 2838
9f60d74b 2839 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
4e499730 2840 struct e1000_tx_desc *tx_desc;
9f60d74b 2841 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
984263bc 2842
9f60d74b 2843 tx_desc = &adapter->tx_desc_base[dd_idx];
9f60d74b
SZ		 2844 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2845 EM_INC_TXDD_IDX(adapter->tx_dd_head);
984263bc 2846
9f60d74b
SZ		 2847 if (++dd_idx == adapter->num_tx_desc)
2848 dd_idx = 0;
9c80d176 2849
9f60d74b 2850 while (first != dd_idx) {
edbfa193
SZ		 2851 logif(pkt_txclean);
2852
9f60d74b
SZ		 2853 num_avail++;
2854
4e499730 2855 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ		 2856 if (tx_buffer->m_head) {
2857 ifp->if_opackets++;
2858 bus_dmamap_unload(adapter->txtag,
2859 tx_buffer->map);
2860 m_freem(tx_buffer->m_head);
2861 tx_buffer->m_head = NULL;
2862 }
2863
2864 if (++first == adapter->num_tx_desc)
2865 first = 0;
2866 }
87307ba1
SZ		 2867 } else {
2868 break;
2869 }
f647ad3d 2870 }
9f60d74b
SZ		 2871 adapter->next_tx_to_clean = first;
2872 adapter->num_tx_desc_avail = num_avail;
2873
2874 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2875 adapter->tx_dd_head = 0;
2876 adapter->tx_dd_tail = 0;
2877 }
2878
2879 if (!EM_IS_OACTIVE(adapter)) {
2880 ifp->if_flags &= ~IFF_OACTIVE;
2881
2882 /* All clean, turn off the timer */
2883 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2884 ifp->if_timer = 0;
2885 }
2886}
2887
2888static void
2889em_tx_collect(struct adapter *adapter)
2890{
2891 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ		 2892 struct em_buffer *tx_buffer;
2893 int tdh, first, num_avail, dd_idx = -1;
2894
2895 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2896 return;
2897
2898 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2899 if (tdh == adapter->next_tx_to_clean)
2900 return;
2901
2902 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2903 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2904
2905 num_avail = adapter->num_tx_desc_avail;
2906 first = adapter->next_tx_to_clean;
2907
2908 while (first != tdh) {
edbfa193
SZ		 2909 logif(pkt_txclean);
2910
9f60d74b
SZ		 2911 num_avail++;
2912
4e499730 2913 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ		 2914 if (tx_buffer->m_head) {
2915 ifp->if_opackets++;
2916 bus_dmamap_unload(adapter->txtag,
2917 tx_buffer->map);
2918 m_freem(tx_buffer->m_head);
2919 tx_buffer->m_head = NULL;
2920 }
2921
2922 if (first == dd_idx) {
2923 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2924 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2925 adapter->tx_dd_head = 0;
2926 adapter->tx_dd_tail = 0;
2927 dd_idx = -1;
2928 } else {
2929 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2930 }
2931 }
2932
2933 if (++first == adapter->num_tx_desc)
2934 first = 0;
2935 }
2936 adapter->next_tx_to_clean = first;
9c80d176 2937 adapter->num_tx_desc_avail = num_avail;
984263bc 2938
9f60d74b 2939 if (!EM_IS_OACTIVE(adapter)) {
9c80d176 2940 ifp->if_flags &= ~IFF_OACTIVE;
afa68aa1 2941
9c80d176
SZ		 2942 /* All clean, turn off the timer */
2943 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2944 ifp->if_timer = 0;
2945 }
2946}
984263bc 2947
9c80d176
SZ		 2948/*
2949 * When Link is lost sometimes there is work still in the TX ring
2950 * which will result in a watchdog, rather than allow that do an
2951 * attempted cleanup and then reinit here. Note that this has been
2952 * seens mostly with fiber adapters.
2953 */
2954static void
2955em_tx_purge(struct adapter *adapter)
2956{
2957 struct ifnet *ifp = &adapter->arpcom.ac_if;
2958
2959 if (!adapter->link_active && ifp->if_timer) {
9f60d74b 2960 em_tx_collect(adapter);
9c80d176
SZ		 2961 if (ifp->if_timer) {
2962 if_printf(ifp, "Link lost, TX pending, reinit\n");
f647ad3d 2963 ifp->if_timer = 0;
9c80d176
SZ		 2964 em_init(adapter);
2965 }
f647ad3d 2966 }
984263bc
MD		 2967}
2968
984263bc 2969static int
9c80d176 2970em_newbuf(struct adapter *adapter, int i, int init)
984263bc 2971{
9c80d176
SZ		 2972 struct mbuf *m;
2973 bus_dma_segment_t seg;
2974 bus_dmamap_t map;
9ccd8c1f 2975 struct em_buffer *rx_buffer;
9c80d176
SZ		 2976 int error, nseg;
2977
2978 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2979 if (m == NULL) {
2980 adapter->mbuf_cluster_failed++;
2981 if (init) {
2982 if_printf(&adapter->arpcom.ac_if,
2983 "Unable to allocate RX mbuf\n");
984263bc 2984 }
9c80d176 2985 return (ENOBUFS);
984263bc 2986 }
9c80d176 2987 m->m_len = m->m_pkthdr.len = MCLBYTES;
87307ba1 2988
9c80d176
SZ		 2989 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2990 m_adj(m, ETHER_ALIGN);
9ccd8c1f 2991
9c80d176
SZ		 2992 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
2993 adapter->rx_sparemap, m,
2994 &seg, 1, &nseg, BUS_DMA_NOWAIT);
9ccd8c1f 2995 if (error) {
9c80d176
SZ		 2996 m_freem(m);
2997 if (init) {
2998 if_printf(&adapter->arpcom.ac_if,
2999 "Unable to load RX mbuf\n");
3000 }
87307ba1 3001 return (error);
9ccd8c1f 3002 }
984263bc 3003
9c80d176
SZ		 3004 rx_buffer = &adapter->rx_buffer_area[i];
3005 if (rx_buffer->m_head != NULL)
3006 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3007
3008 map = rx_buffer->map;
3009 rx_buffer->map = adapter->rx_sparemap;
3010 adapter->rx_sparemap = map;
3011
3012 rx_buffer->m_head = m;
3013
3014 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
87307ba1 3015 return (0);
984263bc
MD		 3016}
3017
984263bc 3018static int
9c80d176 3019em_create_rx_ring(struct adapter *adapter)
984263bc 3020{
9c80d176 3021 device_t dev = adapter->dev;
9ccd8c1f 3022 struct em_buffer *rx_buffer;
9c80d176
SZ		 3023 int i, error;
3024
3025 adapter->rx_buffer_area =
3026 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3027 M_DEVBUF, M_WAITOK | M_ZERO);
9ccd8c1f 3028
9c80d176
SZ		 3029 /*
3030 * Create DMA tag for rx buffers
3031 */
3032 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3033 1, 0, /* alignment, bounds */
3034 BUS_SPACE_MAXADDR, /* lowaddr */
3035 BUS_SPACE_MAXADDR, /* highaddr */
3036 NULL, NULL, /* filter, filterarg */
3037 MCLBYTES, /* maxsize */
3038 1, /* nsegments */
3039 MCLBYTES, /* maxsegsize */
3040 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3041 &adapter->rxtag);
87307ba1 3042 if (error) {
9c80d176
SZ		 3043 device_printf(dev, "Unable to allocate RX DMA tag\n");
3044 kfree(adapter->rx_buffer_area, M_DEVBUF);
3045 adapter->rx_buffer_area = NULL;
3046 return error;
3047 }
3048
3049 /*
3050 * Create spare DMA map for rx buffers
3051 */
3052 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3053 &adapter->rx_sparemap);
3054 if (error) {
3055 device_printf(dev, "Unable to create spare RX DMA map\n");
3056 bus_dma_tag_destroy(adapter->rxtag);
3057 kfree(adapter->rx_buffer_area, M_DEVBUF);
3058 adapter->rx_buffer_area = NULL;
3059 return error;
9ccd8c1f 3060 }
9c80d176
SZ		 3061
3062 /*
3063 * Create DMA maps for rx buffers
3064 */
3065 for (i = 0; i < adapter->num_rx_desc; i++) {
3066 rx_buffer = &adapter->rx_buffer_area[i];
3067
3068 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
9ccd8c1f 3069 &rx_buffer->map);
87307ba1 3070 if (error) {
9c80d176
SZ		 3071 device_printf(dev, "Unable to create RX DMA map\n");
3072 em_destroy_rx_ring(adapter, i);
3073 return error;
9ccd8c1f 3074 }
984263bc 3075 }
87307ba1 3076 return (0);
984263bc
MD		 3077}
3078
984263bc 3079static int
9c80d176 3080em_init_rx_ring(struct adapter *adapter)
984263bc 3081{
9c80d176 3082 int i, error;
984263bc 3083
9c80d176 3084 /* Reset descriptor ring */
87307ba1 3085 bzero(adapter->rx_desc_base,
9c80d176 3086 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
87307ba1 3087
9c80d176
SZ		 3088 /* Allocate new ones. */
3089 for (i = 0; i < adapter->num_rx_desc; i++) {
3090 error = em_newbuf(adapter, i, 1);
3091 if (error)
3092 return (error);
3093 }
984263bc
MD		 3094
3095 /* Setup our descriptor pointers */
f647ad3d 3096 adapter->next_rx_desc_to_check = 0;
87307ba1
SZ		 3097
3098 return (0);
984263bc
MD		 3099}
3100
984263bc 3101static void
9c80d176 3102em_init_rx_unit(struct adapter *adapter)
984263bc 3103{
9c80d176 3104 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 3105 uint64_t bus_addr;
2d0e5700 3106 uint32_t rctl;
984263bc 3107
87307ba1
SZ		 3108 /*
3109 * Make sure receives are disabled while setting
3110 * up the descriptor ring
3111 */
9c80d176
SZ		 3112 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3113 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
984263bc 3114
9c80d176 3115 if (adapter->hw.mac.type >= e1000_82540) {
2d0e5700
SZ		 3116 uint32_t itr;
3117
9c80d176
SZ		 3118 /*
3119 * Set the interrupt throttling rate. Value is calculated
3120 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3121 */
2d0e5700
SZ		 3122 if (adapter->int_throttle_ceil)
3123 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3124 else
3125 itr = 0;
3126 em_set_itr(adapter, itr);
f647ad3d 3127 }
984263bc 3128
9c80d176
SZ		 3129 /* Disable accelerated ackknowledge */
3130 if (adapter->hw.mac.type == e1000_82574) {
3131 E1000_WRITE_REG(&adapter->hw,
3132 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3133 }
3134
2d0e5700
SZ		 3135 /* Receive Checksum Offload for TCP and UDP */
3136 if (ifp->if_capenable & IFCAP_RXCSUM) {
3137 uint32_t rxcsum;
3138
3139 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3140 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3141 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3142 }
3143
3144 /*
3145 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3146 * long latencies are observed, like Lenovo X60. This
3147 * change eliminates the problem, but since having positive
3148 * values in RDTR is a known source of problems on other
3149 * platforms another solution is being sought.
3150 */
3151 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3152 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3153 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3154 }
3155
3156 /*
3157 * Setup the Base and Length of the Rx Descriptor Ring
3158 */
9ccd8c1f 3159 bus_addr = adapter->rxdma.dma_paddr;
9c80d176
SZ		 3160 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3161 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3162 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3163 (uint32_t)(bus_addr >> 32));
3164 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3165 (uint32_t)bus_addr);
984263bc 3166
2d0e5700
SZ		 3167 /*
3168 * Setup the HW Rx Head and Tail Descriptor Pointers
3169 */
3170 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3171 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3172
3173 /* Set early receive threshold on appropriate hw */
3174 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3175 (adapter->hw.mac.type == e1000_pch2lan) ||
3176 (adapter->hw.mac.type == e1000_ich10lan)) &&
3177 (ifp->if_mtu > ETHERMTU)) {
3178 uint32_t rxdctl;
3179
3180 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3181 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3182 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13));
3183 }
3184
3185 if (adapter->hw.mac.type == e1000_pch2lan) {
3186 if (ifp->if_mtu > ETHERMTU)
3187 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE);
3188 else
3189 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE);
3190 }
3191
984263bc 3192 /* Setup the Receive Control Register */
9c80d176
SZ		 3193 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3194 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3195 E1000_RCTL_RDMTS_HALF |
3196 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
984263bc 3197
9c80d176
SZ		 3198 /* Make sure VLAN Filters are off */
3199 rctl &= ~E1000_RCTL_VFE;
3200
3201 if (e1000_tbi_sbp_enabled_82543(&adapter->hw))
3202 rctl |= E1000_RCTL_SBP;
3203 else
3204 rctl &= ~E1000_RCTL_SBP;
984263bc 3205
984263bc
MD		 3206 switch (adapter->rx_buffer_len) {
3207 default:
9c80d176
SZ		 3208 case 2048:
3209 rctl |= E1000_RCTL_SZ_2048;
3210 break;
3211
3212 case 4096:
3213 rctl |= E1000_RCTL_SZ_4096 |
3214 E1000_RCTL_BSEX | E1000_RCTL_LPE;
984263bc 3215 break;
9c80d176
SZ		 3216
3217 case 8192:
3218 rctl |= E1000_RCTL_SZ_8192 |
3219 E1000_RCTL_BSEX | E1000_RCTL_LPE;
984263bc 3220 break;
9c80d176
SZ		 3221
3222 case 16384:
3223 rctl |= E1000_RCTL_SZ_16384 |
3224 E1000_RCTL_BSEX | E1000_RCTL_LPE;
984263bc
MD		 3225 break;
3226 }
3227
3228 if (ifp->if_mtu > ETHERMTU)
9c80d176
SZ		 3229 rctl |= E1000_RCTL_LPE;
3230 else
3231 rctl &= ~E1000_RCTL_LPE;
984263bc 3232
6b96e920
SZ		 3233 /* Enable Receives */
3234 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
984263bc
MD		 3235}
3236
984263bc 3237static void
9c80d176 3238em_destroy_rx_ring(struct adapter *adapter, int ndesc)
984263bc 3239{
f647ad3d
JS		 3240 struct em_buffer *rx_buffer;
3241 int i;
984263bc 3242
9c80d176
SZ		 3243 if (adapter->rx_buffer_area == NULL)
3244 return;
984263bc 3245
9c80d176
SZ		 3246 for (i = 0; i < ndesc; i++) {
3247 rx_buffer = &adapter->rx_buffer_area[i];
3248
3249 KKASSERT(rx_buffer->m_head == NULL);
3250 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
9ccd8c1f 3251 }
9c80d176
SZ		 3252 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap);