em(4)/emx(4): Update to Intel's 7.1.7
[dragonfly.git] / sys / dev / netif / em / if_em.h
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1/*
2 * Copyright (c) 2001-2008, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
984263bc 31
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32#ifndef _IF_EM_H_
33#define _IF_EM_H_
984263bc 34
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35/* Tunables */
36
37/*
1eca7b82 38 * EM_TXD: Maximum number of Transmit Descriptors
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39 * Valid Range: 256 for 82542 and 82543-based adapters
40 * 256-4096 for others
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41 * Default Value: 256
42 * This value is the number of transmit descriptors allocated by the driver.
43 * Increasing this value allows the driver to queue more transmits. Each
44 * descriptor is 16 bytes.
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45 * Since TDLEN should be multiple of 128bytes, the number of transmit
46 * desscriptors should meet the following condition.
9c80d176 47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
984263bc 48 */
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49#define EM_MIN_TXD 256
50#define EM_MAX_TXD_82543 EM_MIN_TXD
9c80d176 51#define EM_MAX_TXD 4096
9f60d74b 52#define EM_DEFAULT_TXD EM_MIN_TXD
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53
54/*
1eca7b82 55 * EM_RXD - Maximum number of receive Descriptors
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56 * Valid Range: 256 for 82542 and 82543-based adapters
57 * 256-4096 for others
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58 * Default Value: 256
59 * This value is the number of receive descriptors allocated by the driver.
60 * Increasing this value allows the driver to buffer more incoming packets.
61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
62 * descriptor. The maximum MTU size is 16110.
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63 * Since TDLEN should be multiple of 128bytes, the number of transmit
64 * desscriptors should meet the following condition.
9c80d176 65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
984263bc 66 */
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67#define EM_MIN_RXD 256
68#define EM_MAX_RXD_82543 EM_MIN_RXD
9c80d176 69#define EM_MAX_RXD 4096
9f60d74b 70#define EM_DEFAULT_RXD EM_MIN_RXD
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71
72/*
9ccd8c1f 73 * EM_TIDV - Transmit Interrupt Delay Value
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74 * Valid Range: 0-65535 (0=off)
75 * Default Value: 64
76 * This value delays the generation of transmit interrupts in units of
77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
78 * efficiency if properly tuned for specific network traffic. If the
79 * system is reporting dropped transmits, this value may be set too high
80 * causing the driver to run out of available transmit descriptors.
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81 *
82 * NOTE:
83 * It is not used. In DragonFly the TX interrupt moderation is done by
84 * conditionally setting RS bit in TX descriptors. See the description
85 * in struct adapter.
984263bc 86 */
9c80d176 87#define EM_TIDV 64
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88
89/*
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90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
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92 * Valid Range: 0-65535 (0=off)
93 * Default Value: 64
94 * This value, in units of 1.024 microseconds, limits the delay in which a
0d366ee7 95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
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96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
0d366ee7 98 * along with EM_TIDV, may improve traffic throughput in specific
984263bc 99 * network conditions.
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100 *
101 * NOTE:
102 * It is not used. In DragonFly the TX interrupt moderation is done by
103 * conditionally setting RS bit in TX descriptors. See the description
104 * in struct adapter.
984263bc 105 */
9c80d176 106#define EM_TADV 64
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107
108/*
2cc36323 109 * Receive Interrupt Delay Timer (Packet Timer)
984263bc 110 *
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111 * NOTE:
112 * RDTR and RADV are deprecated; use ITR instead. They are only used to
113 * workaround hardware bug on certain 82573 based NICs.
984263bc 114 */
2cc36323 115#define EM_RDTR_82573 32
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116
117/*
0d366ee7 118 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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119 *
120 * NOTE:
121 * RDTR and RADV are deprecated; use ITR instead. They are only used to
122 * workaround hardware bug on certain 82573 based NICs.
984263bc 123 */
2cc36323 124#define EM_RADV_82573 64
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125
126/*
127 * This parameter controls the duration of transmit watchdog timer.
128 */
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129#define EM_TX_TIMEOUT 5
130
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131/* One for TX csum offloading desc, the other 2 are reserved */
132#define EM_TX_RESERVED 3
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133
134/* Large enough for 16K jumbo frame */
135#define EM_TX_SPARE 8
136
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137#define EM_TX_OACTIVE_MAX 64
138
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139/* Interrupt throttle rate */
140#define EM_DEFAULT_ITR 10000
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141
142/*
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143 * This parameter controls whether or not autonegotation is enabled.
144 * 0 - Disable autonegotiation
145 * 1 - Enable autonegotiation
146 */
9c80d176 147#define DO_AUTO_NEG 1
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148
149/*
150 * This parameter control whether or not the driver will wait for
151 * autonegotiation to complete.
152 * 1 - Wait for autonegotiation to complete
153 * 0 - Don't wait for autonegotiation to complete
154 */
9c80d176 155#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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156
157/* Tunables -- End */
158
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159#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
160 ADVERTISE_10_FULL | \
161 ADVERTISE_100_HALF | \
162 ADVERTISE_100_FULL | \
163 ADVERTISE_1000_FULL)
984263bc 164
9c80d176 165#define AUTO_ALL_MODES 0
984263bc 166
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167/* PHY master/slave setting */
168#define EM_MASTER_SLAVE e1000_ms_hw_default
984263bc 169
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170/*
171 * Micellaneous constants
172 */
173#define EM_VENDOR_ID 0x8086
87307ba1 174
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175#define EM_BAR_MEM PCIR_BAR(0)
176#define EM_BAR_FLASH PCIR_BAR(1)
177
178#define EM_JUMBO_PBA 0x00000028
179#define EM_DEFAULT_PBA 0x00000030
180#define EM_SMARTSPEED_DOWNSHIFT 3
181#define EM_SMARTSPEED_MAX 15
182#define EM_MAX_INTR 10
183
184#define MAX_NUM_MULTICAST_ADDRESSES 128
185#define PCI_ANY_ID (~0U)
186#define EM_FC_PAUSE_TIME 1000
187#define EM_EEPROM_APME 0x400;
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188
189/*
190 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
191 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
192 * also optimize cache line size effect. H/W supports up to cache line size 128.
193 */
194#define EM_DBA_ALIGN 128
195
9c80d176 196#define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
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197
198/* PCI Config defines */
199#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
200#define EM_BAR_TYPE_MASK 0x00000001
201#define EM_BAR_TYPE_MMEM 0x00000000
202#define EM_BAR_TYPE_IO 0x00000001
203#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
204#define EM_BAR_MEM_TYPE_MASK 0x00000006
205#define EM_BAR_MEM_TYPE_32BIT 0x00000000
206#define EM_BAR_MEM_TYPE_64BIT 0x00000004
207
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208#define EM_MAX_SCATTER 64
209#define EM_TSO_SIZE (65535 + \
210 sizeof(struct ether_vlan_header))
211#define EM_MAX_SEGSIZE 4096
212#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
213#define ETH_ZLEN 60
214
215#define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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216#define EM_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
217#define EM_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
218 EM_IPVHL_SIZE)
9c80d176 219
87307ba1 220/*
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221 * 82574 has a nonstandard address for EIAC
222 * and since its only used in MSIX, and in
223 * the em driver only 82574 uses MSIX we can
224 * solve it just using this define.
87307ba1 225 */
9c80d176 226#define EM_EIAC 0x000DC
984263bc 227
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228/* Used in for 82547 10Mb Half workaround */
229#define EM_PBA_BYTES_SHIFT 0xA
230#define EM_TX_HEAD_ADDR_SHIFT 7
231#define EM_PBA_TX_MASK 0xFFFF0000
232#define EM_FIFO_HDR 0x10
233#define EM_82547_PKT_THRESH 0x3e0
984263bc 234
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235/*
236 * Bus dma allocation structure used by
f7b52b45 237 * em_dma_malloc and em_dma_free.
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238 */
239struct em_dma_alloc {
240 bus_addr_t dma_paddr;
9c80d176 241 void *dma_vaddr;
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242 bus_dma_tag_t dma_tag;
243 bus_dmamap_t dma_map;
9ccd8c1f 244};
984263bc 245
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246/* Our adapter structure */
247struct adapter {
248 struct arpcom arpcom;
249 struct e1000_hw hw;
984263bc 250
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251 /* DragonFly operating-system-specific structures. */
252 struct e1000_osdep osdep;
253 device_t dev;
0d366ee7 254
9c80d176 255 bus_dma_tag_t parent_dtag;
0d366ee7 256
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257 struct resource *memory;
258 int memory_rid;
259 struct resource *flash;
260 int flash_rid;
9ccd8c1f 261
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262 struct resource *ioport;
263 int io_rid;
264
265 struct resource *intr_res;
266 void *intr_tag;
267 int intr_rid;
268
269 struct ifmedia media;
270 struct callout timer;
271 struct callout tx_fifo_timer;
272 int if_flags;
273 int max_frame_size;
274 int min_frame_size;
275
276 /* Management and WOL features */
277 int wol;
278 int has_manage;
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279 int has_amt;
280 int control_hw;
281
282 /* Multicast array memory */
283 uint8_t *mta;
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284
285 /* Info about the board itself */
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286 uint8_t link_active;
287 uint16_t link_speed;
288 uint16_t link_duplex;
289 uint32_t smartspeed;
9c80d176 290 int int_throttle_ceil;
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291
292 /*
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293 * Transmit definitions
294 *
295 * We have an array of num_tx_desc descriptors (handled
296 * by the controller) paired with an array of tx_buffers
297 * (at tx_buffer_area).
298 * The index of the next available descriptor is next_avail_tx_desc.
299 * The number of remaining tx_desc is num_tx_desc_avail.
300 */
9ccd8c1f 301 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
9c80d176 302 struct e1000_tx_desc *tx_desc_base;
9f60d74b 303 struct em_buffer *tx_buffer_area;
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304 uint32_t next_avail_tx_desc;
305 uint32_t next_tx_to_clean;
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306 int num_tx_desc_avail;
307 int num_tx_desc;
9ccd8c1f 308 bus_dma_tag_t txtag; /* dma tag for tx */
9c80d176 309 int spare_tx_desc;
9f60d74b 310 int oact_tx_desc;
984263bc 311
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312 /* Saved csum offloading context information */
313 int csum_flags;
314 int csum_ehlen;
315 int csum_iphlen;
316 uint32_t csum_txd_upper;
317 uint32_t csum_txd_lower;
318
319 /*
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320 * Variables used to reduce TX interrupt rate and
321 * number of device's TX ring write requests.
322 *
323 * tx_nsegs:
324 * Number of TX descriptors setup so far.
325 *
326 * tx_int_nsegs:
327 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
328 * in the last TX descriptor of the packet, and
329 * tx_nsegs will be reset to 0. So TX interrupt and
330 * TX ring write request should be generated roughly
331 * every tx_int_nsegs TX descriptors.
332 *
333 * tx_dd[]:
334 * Index of the TX descriptors which have RS bit set,
335 * i.e. DD bit will be set on this TX descriptor after
336 * the data of the TX descriptor are transfered to
337 * hardware's internal packet buffer. Only the TX
338 * descriptors listed in tx_dd[] will be checked upon
339 * TX interrupt. This array is used as circular ring.
340 *
341 * tx_dd_tail, tx_dd_head:
342 * Tail and head index of valid elements in tx_dd[].
343 * tx_dd_tail == tx_dd_head means there is no valid
344 * elements in tx_dd[]. tx_dd_tail points to the position
345 * which is one beyond the last valid element in tx_dd[].
346 * tx_dd_head points to the first valid element in
347 * tx_dd[].
348 */
349 int tx_int_nsegs;
350 int tx_nsegs;
351 int tx_dd_tail;
352 int tx_dd_head;
353#define EM_TXDD_MAX 64
af2ee69f 354#define EM_TXDD_SAFE 48 /* must be less than EM_TXDD_MAX */
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355 int tx_dd[EM_TXDD_MAX];
356
357 /*
984263bc 358 * Receive definitions
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359 *
360 * we have an array of num_rx_desc rx_desc (handled by the
361 * controller), and paired with an array of rx_buffers
362 * (at rx_buffer_area).
363 * The next pair to check on receive is at offset next_rx_desc_to_check
364 */
9ccd8c1f 365 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
9c80d176 366 struct e1000_rx_desc *rx_desc_base;
87307ba1 367 uint32_t next_rx_desc_to_check;
87307ba1 368 uint32_t rx_buffer_len;
9c80d176 369 int num_rx_desc;
87307ba1 370 struct em_buffer *rx_buffer_area;
9ccd8c1f 371 bus_dma_tag_t rxtag;
9c80d176 372 bus_dmamap_t rx_sparemap;
984263bc 373
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374 /*
375 * First/last mbuf pointers, for
376 * collecting multisegment RX packets.
377 */
378 struct mbuf *fmp;
379 struct mbuf *lmp;
984263bc 380
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381 /* Misc stats maintained by the driver */
382 unsigned long dropped_pkts;
383 unsigned long mbuf_alloc_failed;
384 unsigned long mbuf_cluster_failed;
385 unsigned long no_tx_desc_avail1;
386 unsigned long no_tx_desc_avail2;
387 unsigned long no_tx_map_avail;
388 unsigned long no_tx_dma_setup;
389 unsigned long watchdog_events;
390 unsigned long rx_overruns;
391 unsigned long rx_irq;
392 unsigned long tx_irq;
393 unsigned long link_irq;
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394 unsigned long tx_csum_try_pullup;
395 unsigned long tx_csum_pullup1;
396 unsigned long tx_csum_pullup1_failed;
397 unsigned long tx_csum_pullup2;
398 unsigned long tx_csum_pullup2_failed;
399 unsigned long tx_csum_drop1;
400 unsigned long tx_csum_drop2;
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401
402 /* sysctl tree glue */
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403 struct sysctl_ctx_list sysctl_ctx;
404 struct sysctl_oid *sysctl_tree;
984263bc 405
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406 /* 82547 workaround */
407 uint32_t tx_fifo_size;
408 uint32_t tx_fifo_head;
409 uint32_t tx_fifo_head_addr;
410 uint64_t tx_fifo_reset_cnt;
411 uint64_t tx_fifo_wrk_cnt;
412 uint32_t tx_head_addr;
413
414 /* For 82544 PCIX Workaround */
415 boolean_t pcix_82544;
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416
417 struct e1000_hw_stats stats;
418};
419
420struct em_vendor_info {
421 uint16_t vendor_id;
422 uint16_t device_id;
96ced48a 423 int ret;
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424 const char *desc;
425};
426
427struct em_buffer {
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428 struct mbuf *m_head;
429 bus_dmamap_t map; /* bus_dma map for packet */
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430};
431
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432/* For 82544 PCIX Workaround */
433typedef struct _ADDRESS_LENGTH_PAIR {
434 uint64_t address;
435 uint32_t length;
436} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
437
438typedef struct _DESCRIPTOR_PAIR {
439 ADDRESS_LENGTH_PAIR descriptor[4];
440 uint32_t elements;
441} DESC_ARRAY, *PDESC_ARRAY;
442
443#define EM_IS_OACTIVE(adapter) \
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444 ((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc)
445
446#define EM_INC_TXDD_IDX(idx) \
447do { \
448 if (++(idx) == EM_TXDD_MAX) \
449 (idx) = 0; \
450} while (0)
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451
452#endif /* _IF_EM_H_ */