em(4)/emx(4): Update to Intel's 7.1.7
[dragonfly.git] / sys / dev / netif / ig_hal / e1000_nvm.c
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1/******************************************************************************
2
6a5a645e 3 Copyright (c) 2001-2009, Intel Corporation
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4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
6a5a645e 33/*$FreeBSD: $*/
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34
35#include "e1000_api.h"
36
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37#ifdef NO_82542_SUPPORT
38static void e1000_stop_nvm(struct e1000_hw *hw);
39#endif
40static void e1000_reload_nvm_generic(struct e1000_hw *hw);
41
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42/**
43 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
44 * @hw: pointer to the HW structure
45 *
46 * Setups up the function pointers to no-op functions
47 **/
48void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
49{
50 struct e1000_nvm_info *nvm = &hw->nvm;
51 DEBUGFUNC("e1000_init_nvm_ops_generic");
52
53 /* Initialize function pointers */
54 nvm->ops.init_params = e1000_null_ops_generic;
55 nvm->ops.acquire = e1000_null_ops_generic;
56 nvm->ops.read = e1000_null_read_nvm;
57 nvm->ops.release = e1000_null_nvm_generic;
58 nvm->ops.reload = e1000_reload_nvm_generic;
59 nvm->ops.update = e1000_null_ops_generic;
60 nvm->ops.valid_led_default = e1000_null_led_default;
61 nvm->ops.validate = e1000_null_ops_generic;
62 nvm->ops.write = e1000_null_write_nvm;
63}
64
65/**
66 * e1000_null_nvm_read - No-op function, return 0
67 * @hw: pointer to the HW structure
68 **/
69s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
70{
71 DEBUGFUNC("e1000_null_read_nvm");
72 return E1000_SUCCESS;
73}
74
75/**
76 * e1000_null_nvm_generic - No-op function, return void
77 * @hw: pointer to the HW structure
78 **/
79void e1000_null_nvm_generic(struct e1000_hw *hw)
80{
81 DEBUGFUNC("e1000_null_nvm_generic");
82 return;
83}
84
85/**
86 * e1000_null_led_default - No-op function, return 0
87 * @hw: pointer to the HW structure
88 **/
89s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
90{
91 DEBUGFUNC("e1000_null_led_default");
92 return E1000_SUCCESS;
93}
94
95/**
96 * e1000_null_write_nvm - No-op function, return 0
97 * @hw: pointer to the HW structure
98 **/
99s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
100{
101 DEBUGFUNC("e1000_null_write_nvm");
102 return E1000_SUCCESS;
103}
104
105/**
106 * e1000_raise_eec_clk - Raise EEPROM clock
107 * @hw: pointer to the HW structure
108 * @eecd: pointer to the EEPROM
109 *
110 * Enable/Raise the EEPROM clock bit.
111 **/
112static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
113{
114 *eecd = *eecd | E1000_EECD_SK;
115 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
116 E1000_WRITE_FLUSH(hw);
117 usec_delay(hw->nvm.delay_usec);
118}
119
120/**
121 * e1000_lower_eec_clk - Lower EEPROM clock
122 * @hw: pointer to the HW structure
123 * @eecd: pointer to the EEPROM
124 *
125 * Clear/Lower the EEPROM clock bit.
126 **/
127static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
128{
129 *eecd = *eecd & ~E1000_EECD_SK;
130 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
131 E1000_WRITE_FLUSH(hw);
132 usec_delay(hw->nvm.delay_usec);
133}
134
135/**
136 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
137 * @hw: pointer to the HW structure
138 * @data: data to send to the EEPROM
139 * @count: number of bits to shift out
140 *
141 * We need to shift 'count' bits out to the EEPROM. So, the value in the
142 * "data" parameter will be shifted out to the EEPROM one bit at a time.
143 * In order to do this, "data" must be broken down into bits.
144 **/
145static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
146{
147 struct e1000_nvm_info *nvm = &hw->nvm;
148 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
149 u32 mask;
150
151 DEBUGFUNC("e1000_shift_out_eec_bits");
152
153 mask = 0x01 << (count - 1);
154 if (nvm->type == e1000_nvm_eeprom_microwire)
155 eecd &= ~E1000_EECD_DO;
156 else
157 if (nvm->type == e1000_nvm_eeprom_spi)
158 eecd |= E1000_EECD_DO;
159
160 do {
161 eecd &= ~E1000_EECD_DI;
162
163 if (data & mask)
164 eecd |= E1000_EECD_DI;
165
166 E1000_WRITE_REG(hw, E1000_EECD, eecd);
167 E1000_WRITE_FLUSH(hw);
168
169 usec_delay(nvm->delay_usec);
170
171 e1000_raise_eec_clk(hw, &eecd);
172 e1000_lower_eec_clk(hw, &eecd);
173
174 mask >>= 1;
175 } while (mask);
176
177 eecd &= ~E1000_EECD_DI;
178 E1000_WRITE_REG(hw, E1000_EECD, eecd);
179}
180
181/**
182 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
183 * @hw: pointer to the HW structure
184 * @count: number of bits to shift in
185 *
186 * In order to read a register from the EEPROM, we need to shift 'count' bits
187 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
188 * the EEPROM (setting the SK bit), and then reading the value of the data out
189 * "DO" bit. During this "shifting in" process the data in "DI" bit should
190 * always be clear.
191 **/
192static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
193{
194 u32 eecd;
195 u32 i;
196 u16 data;
197
198 DEBUGFUNC("e1000_shift_in_eec_bits");
199
200 eecd = E1000_READ_REG(hw, E1000_EECD);
201
202 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
203 data = 0;
204
205 for (i = 0; i < count; i++) {
206 data <<= 1;
207 e1000_raise_eec_clk(hw, &eecd);
208
209 eecd = E1000_READ_REG(hw, E1000_EECD);
210
211 eecd &= ~E1000_EECD_DI;
212 if (eecd & E1000_EECD_DO)
213 data |= 1;
214
215 e1000_lower_eec_clk(hw, &eecd);
216 }
217
218 return data;
219}
220
221/**
222 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
223 * @hw: pointer to the HW structure
224 * @ee_reg: EEPROM flag for polling
225 *
226 * Polls the EEPROM status bit for either read or write completion based
227 * upon the value of 'ee_reg'.
228 **/
229s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
230{
231 u32 attempts = 100000;
232 u32 i, reg = 0;
233 s32 ret_val = -E1000_ERR_NVM;
234
235 DEBUGFUNC("e1000_poll_eerd_eewr_done");
236
237 for (i = 0; i < attempts; i++) {
238 if (ee_reg == E1000_NVM_POLL_READ)
239 reg = E1000_READ_REG(hw, E1000_EERD);
240 else
241 reg = E1000_READ_REG(hw, E1000_EEWR);
242
243 if (reg & E1000_NVM_RW_REG_DONE) {
244 ret_val = E1000_SUCCESS;
245 break;
246 }
247
248 usec_delay(5);
249 }
250
251 return ret_val;
252}
253
254/**
255 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
256 * @hw: pointer to the HW structure
257 *
258 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
259 * Return successful if access grant bit set, else clear the request for
260 * EEPROM access and return -E1000_ERR_NVM (-1).
261 **/
262s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
263{
264 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
265 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
266 s32 ret_val = E1000_SUCCESS;
267
268 DEBUGFUNC("e1000_acquire_nvm_generic");
269
270 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
271 eecd = E1000_READ_REG(hw, E1000_EECD);
272
273 while (timeout) {
274 if (eecd & E1000_EECD_GNT)
275 break;
276 usec_delay(5);
277 eecd = E1000_READ_REG(hw, E1000_EECD);
278 timeout--;
279 }
280
281 if (!timeout) {
282 eecd &= ~E1000_EECD_REQ;
283 E1000_WRITE_REG(hw, E1000_EECD, eecd);
284 DEBUGOUT("Could not acquire NVM grant\n");
285 ret_val = -E1000_ERR_NVM;
286 }
287
288 return ret_val;
289}
290
291/**
292 * e1000_standby_nvm - Return EEPROM to standby state
293 * @hw: pointer to the HW structure
294 *
295 * Return the EEPROM to a standby state.
296 **/
297static void e1000_standby_nvm(struct e1000_hw *hw)
298{
299 struct e1000_nvm_info *nvm = &hw->nvm;
300 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
301
302 DEBUGFUNC("e1000_standby_nvm");
303
304 if (nvm->type == e1000_nvm_eeprom_microwire) {
305 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
306 E1000_WRITE_REG(hw, E1000_EECD, eecd);
307 E1000_WRITE_FLUSH(hw);
308 usec_delay(nvm->delay_usec);
309
310 e1000_raise_eec_clk(hw, &eecd);
311
312 /* Select EEPROM */
313 eecd |= E1000_EECD_CS;
314 E1000_WRITE_REG(hw, E1000_EECD, eecd);
315 E1000_WRITE_FLUSH(hw);
316 usec_delay(nvm->delay_usec);
317
318 e1000_lower_eec_clk(hw, &eecd);
319 } else
320 if (nvm->type == e1000_nvm_eeprom_spi) {
321 /* Toggle CS to flush commands */
322 eecd |= E1000_EECD_CS;
323 E1000_WRITE_REG(hw, E1000_EECD, eecd);
324 E1000_WRITE_FLUSH(hw);
325 usec_delay(nvm->delay_usec);
326 eecd &= ~E1000_EECD_CS;
327 E1000_WRITE_REG(hw, E1000_EECD, eecd);
328 E1000_WRITE_FLUSH(hw);
329 usec_delay(nvm->delay_usec);
330 }
331}
332
333/**
334 * e1000_stop_nvm - Terminate EEPROM command
335 * @hw: pointer to the HW structure
336 *
337 * Terminates the current command by inverting the EEPROM's chip select pin.
338 **/
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339#ifdef NO_82542_SUPPORT
340static void e1000_stop_nvm(struct e1000_hw *hw)
341#else
9c80d176 342void e1000_stop_nvm(struct e1000_hw *hw)
6a5a645e 343#endif
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344{
345 u32 eecd;
346
347 DEBUGFUNC("e1000_stop_nvm");
348
349 eecd = E1000_READ_REG(hw, E1000_EECD);
350 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
351 /* Pull CS high */
352 eecd |= E1000_EECD_CS;
353 e1000_lower_eec_clk(hw, &eecd);
354 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
355 /* CS on Microwire is active-high */
356 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
357 E1000_WRITE_REG(hw, E1000_EECD, eecd);
358 e1000_raise_eec_clk(hw, &eecd);
359 e1000_lower_eec_clk(hw, &eecd);
360 }
361}
362
363/**
364 * e1000_release_nvm_generic - Release exclusive access to EEPROM
365 * @hw: pointer to the HW structure
366 *
367 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
368 **/
369void e1000_release_nvm_generic(struct e1000_hw *hw)
370{
371 u32 eecd;
372
373 DEBUGFUNC("e1000_release_nvm_generic");
374
375 e1000_stop_nvm(hw);
376
377 eecd = E1000_READ_REG(hw, E1000_EECD);
378 eecd &= ~E1000_EECD_REQ;
379 E1000_WRITE_REG(hw, E1000_EECD, eecd);
380}
381
382/**
383 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
384 * @hw: pointer to the HW structure
385 *
386 * Setups the EEPROM for reading and writing.
387 **/
388static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
389{
390 struct e1000_nvm_info *nvm = &hw->nvm;
391 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
392 s32 ret_val = E1000_SUCCESS;
393 u16 timeout = 0;
394 u8 spi_stat_reg;
395
396 DEBUGFUNC("e1000_ready_nvm_eeprom");
397
398 if (nvm->type == e1000_nvm_eeprom_microwire) {
399 /* Clear SK and DI */
400 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
401 E1000_WRITE_REG(hw, E1000_EECD, eecd);
402 /* Set CS */
403 eecd |= E1000_EECD_CS;
404 E1000_WRITE_REG(hw, E1000_EECD, eecd);
405 } else
406 if (nvm->type == e1000_nvm_eeprom_spi) {
407 /* Clear SK and CS */
408 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
409 E1000_WRITE_REG(hw, E1000_EECD, eecd);
410 usec_delay(1);
411 timeout = NVM_MAX_RETRY_SPI;
412
413 /*
414 * Read "Status Register" repeatedly until the LSB is cleared.
415 * The EEPROM will signal that the command has been completed
416 * by clearing bit 0 of the internal status register. If it's
417 * not cleared within 'timeout', then error out.
418 */
419 while (timeout) {
420 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
421 hw->nvm.opcode_bits);
422 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
423 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
424 break;
425
426 usec_delay(5);
427 e1000_standby_nvm(hw);
428 timeout--;
429 }
430
431 if (!timeout) {
432 DEBUGOUT("SPI NVM Status error\n");
433 ret_val = -E1000_ERR_NVM;
434 goto out;
435 }
436 }
437
438out:
439 return ret_val;
440}
441
442/**
443 * e1000_read_nvm_spi - Read EEPROM's using SPI
444 * @hw: pointer to the HW structure
445 * @offset: offset of word in the EEPROM to read
446 * @words: number of words to read
447 * @data: word read from the EEPROM
448 *
449 * Reads a 16 bit word from the EEPROM.
450 **/
451s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
452{
453 struct e1000_nvm_info *nvm = &hw->nvm;
454 u32 i = 0;
455 s32 ret_val;
456 u16 word_in;
457 u8 read_opcode = NVM_READ_OPCODE_SPI;
458
459 DEBUGFUNC("e1000_read_nvm_spi");
460
461 /*
462 * A check for invalid values: offset too large, too many words,
463 * and not enough words.
464 */
465 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
466 (words == 0)) {
467 DEBUGOUT("nvm parameter(s) out of bounds\n");
468 ret_val = -E1000_ERR_NVM;
469 goto out;
470 }
471
472 ret_val = nvm->ops.acquire(hw);
473 if (ret_val)
474 goto out;
475
476 ret_val = e1000_ready_nvm_eeprom(hw);
477 if (ret_val)
478 goto release;
479
480 e1000_standby_nvm(hw);
481
482 if ((nvm->address_bits == 8) && (offset >= 128))
483 read_opcode |= NVM_A8_OPCODE_SPI;
484
485 /* Send the READ command (opcode + addr) */
486 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
487 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
488
489 /*
490 * Read the data. SPI NVMs increment the address with each byte
491 * read and will roll over if reading beyond the end. This allows
492 * us to read the whole NVM from any offset
493 */
494 for (i = 0; i < words; i++) {
495 word_in = e1000_shift_in_eec_bits(hw, 16);
496 data[i] = (word_in >> 8) | (word_in << 8);
497 }
498
499release:
500 nvm->ops.release(hw);
501
502out:
503 return ret_val;
504}
505
506/**
507 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
508 * @hw: pointer to the HW structure
509 * @offset: offset of word in the EEPROM to read
510 * @words: number of words to read
511 * @data: word read from the EEPROM
512 *
513 * Reads a 16 bit word from the EEPROM.
514 **/
515s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
516 u16 *data)
517{
518 struct e1000_nvm_info *nvm = &hw->nvm;
519 u32 i = 0;
520 s32 ret_val;
521 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
522
523 DEBUGFUNC("e1000_read_nvm_microwire");
524
525 /*
526 * A check for invalid values: offset too large, too many words,
527 * and not enough words.
528 */
529 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
530 (words == 0)) {
531 DEBUGOUT("nvm parameter(s) out of bounds\n");
532 ret_val = -E1000_ERR_NVM;
533 goto out;
534 }
535
536 ret_val = nvm->ops.acquire(hw);
537 if (ret_val)
538 goto out;
539
540 ret_val = e1000_ready_nvm_eeprom(hw);
541 if (ret_val)
542 goto release;
543
544 for (i = 0; i < words; i++) {
545 /* Send the READ command (opcode + addr) */
546 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
547 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
548 nvm->address_bits);
549
550 /*
551 * Read the data. For microwire, each word requires the
552 * overhead of setup and tear-down.
553 */
554 data[i] = e1000_shift_in_eec_bits(hw, 16);
555 e1000_standby_nvm(hw);
556 }
557
558release:
559 nvm->ops.release(hw);
560
561out:
562 return ret_val;
563}
564
565/**
566 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
567 * @hw: pointer to the HW structure
568 * @offset: offset of word in the EEPROM to read
569 * @words: number of words to read
570 * @data: word read from the EEPROM
571 *
572 * Reads a 16 bit word from the EEPROM using the EERD register.
573 **/
574s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
575{
576 struct e1000_nvm_info *nvm = &hw->nvm;
577 u32 i, eerd = 0;
578 s32 ret_val = E1000_SUCCESS;
579
580 DEBUGFUNC("e1000_read_nvm_eerd");
581
582 /*
583 * A check for invalid values: offset too large, too many words,
584 * too many words for the offset, and not enough words.
585 */
586 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
587 (words == 0)) {
588 DEBUGOUT("nvm parameter(s) out of bounds\n");
589 ret_val = -E1000_ERR_NVM;
590 goto out;
591 }
592
593 for (i = 0; i < words; i++) {
594 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
595 E1000_NVM_RW_REG_START;
596
597 E1000_WRITE_REG(hw, E1000_EERD, eerd);
598 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
599 if (ret_val)
600 break;
601
602 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
603 E1000_NVM_RW_REG_DATA);
604 }
605
606out:
607 return ret_val;
608}
609
610/**
611 * e1000_write_nvm_spi - Write to EEPROM using SPI
612 * @hw: pointer to the HW structure
613 * @offset: offset within the EEPROM to be written to
614 * @words: number of words to write
615 * @data: 16 bit word(s) to be written to the EEPROM
616 *
617 * Writes data to EEPROM at offset using SPI interface.
618 *
619 * If e1000_update_nvm_checksum is not called after this function , the
620 * EEPROM will most likely contain an invalid checksum.
621 **/
622s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
623{
624 struct e1000_nvm_info *nvm = &hw->nvm;
625 s32 ret_val;
626 u16 widx = 0;
627
628 DEBUGFUNC("e1000_write_nvm_spi");
629
630 /*
631 * A check for invalid values: offset too large, too many words,
632 * and not enough words.
633 */
634 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
635 (words == 0)) {
636 DEBUGOUT("nvm parameter(s) out of bounds\n");
637 ret_val = -E1000_ERR_NVM;
638 goto out;
639 }
640
641 ret_val = nvm->ops.acquire(hw);
642 if (ret_val)
643 goto out;
644
645 while (widx < words) {
646 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
647
648 ret_val = e1000_ready_nvm_eeprom(hw);
649 if (ret_val)
650 goto release;
651
652 e1000_standby_nvm(hw);
653
654 /* Send the WRITE ENABLE command (8 bit opcode) */
655 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
656 nvm->opcode_bits);
657
658 e1000_standby_nvm(hw);
659
660 /*
661 * Some SPI eeproms use the 8th address bit embedded in the
662 * opcode
663 */
664 if ((nvm->address_bits == 8) && (offset >= 128))
665 write_opcode |= NVM_A8_OPCODE_SPI;
666
667 /* Send the Write command (8-bit opcode + addr) */
668 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
669 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
670 nvm->address_bits);
671
672 /* Loop to allow for up to whole page write of eeprom */
673 while (widx < words) {
674 u16 word_out = data[widx];
675 word_out = (word_out >> 8) | (word_out << 8);
676 e1000_shift_out_eec_bits(hw, word_out, 16);
677 widx++;
678
679 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
680 e1000_standby_nvm(hw);
681 break;
682 }
683 }
684 }
685
686 msec_delay(10);
687release:
688 nvm->ops.release(hw);
689
690out:
691 return ret_val;
692}
693
694/**
695 * e1000_write_nvm_microwire - Writes EEPROM using microwire
696 * @hw: pointer to the HW structure
697 * @offset: offset within the EEPROM to be written to
698 * @words: number of words to write
699 * @data: 16 bit word(s) to be written to the EEPROM
700 *
701 * Writes data to EEPROM at offset using microwire interface.
702 *
703 * If e1000_update_nvm_checksum is not called after this function , the
704 * EEPROM will most likely contain an invalid checksum.
705 **/
706s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
707 u16 *data)
708{
709 struct e1000_nvm_info *nvm = &hw->nvm;
710 s32 ret_val;
711 u32 eecd;
712 u16 words_written = 0;
713 u16 widx = 0;
714
715 DEBUGFUNC("e1000_write_nvm_microwire");
716
717 /*
718 * A check for invalid values: offset too large, too many words,
719 * and not enough words.
720 */
721 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
722 (words == 0)) {
723 DEBUGOUT("nvm parameter(s) out of bounds\n");
724 ret_val = -E1000_ERR_NVM;
725 goto out;
726 }
727
728 ret_val = nvm->ops.acquire(hw);
729 if (ret_val)
730 goto out;
731
732 ret_val = e1000_ready_nvm_eeprom(hw);
733 if (ret_val)
734 goto release;
735
736 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
737 (u16)(nvm->opcode_bits + 2));
738
739 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
740
741 e1000_standby_nvm(hw);
742
743 while (words_written < words) {
744 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
745 nvm->opcode_bits);
746
747 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
748 nvm->address_bits);
749
750 e1000_shift_out_eec_bits(hw, data[words_written], 16);
751
752 e1000_standby_nvm(hw);
753
754 for (widx = 0; widx < 200; widx++) {
755 eecd = E1000_READ_REG(hw, E1000_EECD);
756 if (eecd & E1000_EECD_DO)
757 break;
758 usec_delay(50);
759 }
760
761 if (widx == 200) {
762 DEBUGOUT("NVM Write did not complete\n");
763 ret_val = -E1000_ERR_NVM;
764 goto release;
765 }
766
767 e1000_standby_nvm(hw);
768
769 words_written++;
770 }
771
772 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
773 (u16)(nvm->opcode_bits + 2));
774
775 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
776
777release:
778 nvm->ops.release(hw);
779
780out:
781 return ret_val;
782}
783
784/**
6a5a645e
SZ
785 * e1000_read_pba_string_generic - Read device part number
786 * @hw: pointer to the HW structure
787 * @pba_num: pointer to device part number
788 * @pba_num_size: size of part number buffer
789 *
790 * Reads the product board assembly (PBA) number from the EEPROM and stores
791 * the value in pba_num.
792 **/
793s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
794 u32 pba_num_size)
795{
796 s32 ret_val;
797 u16 nvm_data;
798 u16 pba_ptr;
799 u16 offset;
800 u16 length;
801
802 DEBUGFUNC("e1000_read_pba_string_generic");
803
804 if (pba_num == NULL) {
805 DEBUGOUT("PBA string buffer was null\n");
806 ret_val = E1000_ERR_INVALID_ARGUMENT;
807 goto out;
808 }
809
810 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
811 if (ret_val) {
812 DEBUGOUT("NVM Read Error\n");
813 goto out;
814 }
815
816 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
817 if (ret_val) {
818 DEBUGOUT("NVM Read Error\n");
819 goto out;
820 }
821
822 /*
823 * if nvm_data is not ptr guard the PBA must be in legacy format which
824 * means pba_ptr is actually our second data word for the PBA number
825 * and we can decode it into an ascii string
826 */
827 if (nvm_data != NVM_PBA_PTR_GUARD) {
828 DEBUGOUT("NVM PBA number is not stored as string\n");
829
830 /* we will need 11 characters to store the PBA */
831 if (pba_num_size < 11) {
832 DEBUGOUT("PBA string buffer too small\n");
833 return E1000_ERR_NO_SPACE;
834 }
835
836 /* extract hex string from data and pba_ptr */
837 pba_num[0] = (nvm_data >> 12) & 0xF;
838 pba_num[1] = (nvm_data >> 8) & 0xF;
839 pba_num[2] = (nvm_data >> 4) & 0xF;
840 pba_num[3] = nvm_data & 0xF;
841 pba_num[4] = (pba_ptr >> 12) & 0xF;
842 pba_num[5] = (pba_ptr >> 8) & 0xF;
843 pba_num[6] = '-';
844 pba_num[7] = 0;
845 pba_num[8] = (pba_ptr >> 4) & 0xF;
846 pba_num[9] = pba_ptr & 0xF;
847
848 /* put a null character on the end of our string */
849 pba_num[10] = '\0';
850
851 /* switch all the data but the '-' to hex char */
852 for (offset = 0; offset < 10; offset++) {
853 if (pba_num[offset] < 0xA)
854 pba_num[offset] += '0';
855 else if (pba_num[offset] < 0x10)
856 pba_num[offset] += 'A' - 0xA;
857 }
858
859 goto out;
860 }
861
862 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
863 if (ret_val) {
864 DEBUGOUT("NVM Read Error\n");
865 goto out;
866 }
867
868 if (length == 0xFFFF || length == 0) {
869 DEBUGOUT("NVM PBA number section invalid length\n");
870 ret_val = E1000_ERR_NVM_PBA_SECTION;
871 goto out;
872 }
873 /* check if pba_num buffer is big enough */
874 if (pba_num_size < (((u32)length * 2) - 1)) {
875 DEBUGOUT("PBA string buffer too small\n");
876 ret_val = E1000_ERR_NO_SPACE;
877 goto out;
878 }
879
880 /* trim pba length from start of string */
881 pba_ptr++;
882 length--;
883
884 for (offset = 0; offset < length; offset++) {
885 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
886 if (ret_val) {
887 DEBUGOUT("NVM Read Error\n");
888 goto out;
889 }
890 pba_num[offset * 2] = (u8)(nvm_data >> 8);
891 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
892 }
893 pba_num[offset * 2] = '\0';
894
895out:
896 return ret_val;
897}
898
899/**
900 * e1000_read_pba_length_generic - Read device part number length
901 * @hw: pointer to the HW structure
902 * @pba_num_size: size of part number buffer
903 *
904 * Reads the product board assembly (PBA) number length from the EEPROM and
905 * stores the value in pba_num_size.
906 **/
907s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
908{
909 s32 ret_val;
910 u16 nvm_data;
911 u16 pba_ptr;
912 u16 length;
913
914 DEBUGFUNC("e1000_read_pba_length_generic");
915
916 if (pba_num_size == NULL) {
917 DEBUGOUT("PBA buffer size was null\n");
918 ret_val = E1000_ERR_INVALID_ARGUMENT;
919 goto out;
920 }
921
922 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
923 if (ret_val) {
924 DEBUGOUT("NVM Read Error\n");
925 goto out;
926 }
927
928 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
929 if (ret_val) {
930 DEBUGOUT("NVM Read Error\n");
931 goto out;
932 }
933
934 /* if data is not ptr guard the PBA must be in legacy format */
935 if (nvm_data != NVM_PBA_PTR_GUARD) {
936 *pba_num_size = 11;
937 goto out;
938 }
939
940 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
941 if (ret_val) {
942 DEBUGOUT("NVM Read Error\n");
943 goto out;
944 }
945
946 if (length == 0xFFFF || length == 0) {
947 DEBUGOUT("NVM PBA number section invalid length\n");
948 ret_val = E1000_ERR_NVM_PBA_SECTION;
949 goto out;
950 }
951
952 /*
953 * Convert from length in u16 values to u8 chars, add 1 for NULL,
954 * and subtract 2 because length field is included in length.
955 */
956 *pba_num_size = ((u32)length * 2) - 1;
957
958out:
959 return ret_val;
960}
961
962/**
9c80d176
SZ
963 * e1000_read_pba_num_generic - Read device part number
964 * @hw: pointer to the HW structure
965 * @pba_num: pointer to device part number
966 *
967 * Reads the product board assembly (PBA) number from the EEPROM and stores
968 * the value in pba_num.
969 **/
970s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
971{
972 s32 ret_val;
973 u16 nvm_data;
974
975 DEBUGFUNC("e1000_read_pba_num_generic");
976
977 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
978 if (ret_val) {
979 DEBUGOUT("NVM Read Error\n");
980 goto out;
6a5a645e
SZ
981 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
982 DEBUGOUT("NVM Not Supported\n");
983 ret_val = E1000_NOT_IMPLEMENTED;
984 goto out;
9c80d176
SZ
985 }
986 *pba_num = (u32)(nvm_data << 16);
987
988 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
989 if (ret_val) {
990 DEBUGOUT("NVM Read Error\n");
991 goto out;
992 }
993 *pba_num |= nvm_data;
994
995out:
996 return ret_val;
997}
998
999/**
1000 * e1000_read_mac_addr_generic - Read device MAC address
1001 * @hw: pointer to the HW structure
1002 *
1003 * Reads the device MAC address from the EEPROM and stores the value.
1004 * Since devices with two ports use the same EEPROM, we increment the
1005 * last bit in the MAC address for the second port.
1006 **/
1007s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1008{
6a5a645e
SZ
1009 u32 rar_high;
1010 u32 rar_low;
1011 u16 i;
1012
1013 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1014 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1015
1016 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1017 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1018
1019 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1020 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1021
1022 for (i = 0; i < ETH_ADDR_LEN; i++)
1023 hw->mac.addr[i] = hw->mac.perm_addr[i];
1024
1025 return E1000_SUCCESS;
9c80d176
SZ
1026}
1027
1028/**
1029 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1030 * @hw: pointer to the HW structure
1031 *
1032 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1033 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1034 **/
1035s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1036{
1037 s32 ret_val = E1000_SUCCESS;
1038 u16 checksum = 0;
1039 u16 i, nvm_data;
1040
1041 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1042
1043 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1044 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1045 if (ret_val) {
1046 DEBUGOUT("NVM Read Error\n");
1047 goto out;
1048 }
1049 checksum += nvm_data;
1050 }
1051
1052 if (checksum != (u16) NVM_SUM) {
1053 DEBUGOUT("NVM Checksum Invalid\n");
1054 ret_val = -E1000_ERR_NVM;
1055 goto out;
1056 }
1057
1058out:
1059 return ret_val;
1060}
1061
1062/**
1063 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1064 * @hw: pointer to the HW structure
1065 *
1066 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1067 * up to the checksum. Then calculates the EEPROM checksum and writes the
1068 * value to the EEPROM.
1069 **/
1070s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1071{
6a5a645e 1072 s32 ret_val;
9c80d176
SZ
1073 u16 checksum = 0;
1074 u16 i, nvm_data;
1075
1076 DEBUGFUNC("e1000_update_nvm_checksum");
1077
1078 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1079 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1080 if (ret_val) {
1081 DEBUGOUT("NVM Read Error while updating checksum.\n");
1082 goto out;
1083 }
1084 checksum += nvm_data;
1085 }
1086 checksum = (u16) NVM_SUM - checksum;
1087 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1088 if (ret_val)
1089 DEBUGOUT("NVM Write Error while updating checksum.\n");
1090
1091out:
1092 return ret_val;
1093}
1094
1095/**
1096 * e1000_reload_nvm_generic - Reloads EEPROM
1097 * @hw: pointer to the HW structure
1098 *
1099 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1100 * extended control register.
1101 **/
6a5a645e 1102static void e1000_reload_nvm_generic(struct e1000_hw *hw)
9c80d176
SZ
1103{
1104 u32 ctrl_ext;
1105
1106 DEBUGFUNC("e1000_reload_nvm_generic");
1107
1108 usec_delay(10);
1109 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1110 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1111 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1112 E1000_WRITE_FLUSH(hw);
1113}
1114